The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rlreg.h

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    1 /*
    2  * Copyright (c) 1997, 1998-2003
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/5.2/sys/pci/if_rlreg.h 122689 2003-11-14 19:00:32Z sam $
   33  */
   34 
   35 /*
   36  * RealTek 8129/8139 register offsets
   37  */
   38 #define RL_IDR0         0x0000          /* ID register 0 (station addr) */
   39 #define RL_IDR1         0x0001          /* Must use 32-bit accesses (?) */
   40 #define RL_IDR2         0x0002
   41 #define RL_IDR3         0x0003
   42 #define RL_IDR4         0x0004
   43 #define RL_IDR5         0x0005
   44                                         /* 0006-0007 reserved */
   45 #define RL_MAR0         0x0008          /* Multicast hash table */
   46 #define RL_MAR1         0x0009
   47 #define RL_MAR2         0x000A
   48 #define RL_MAR3         0x000B
   49 #define RL_MAR4         0x000C
   50 #define RL_MAR5         0x000D
   51 #define RL_MAR6         0x000E
   52 #define RL_MAR7         0x000F
   53 
   54 #define RL_TXSTAT0      0x0010          /* status of TX descriptor 0 */
   55 #define RL_TXSTAT1      0x0014          /* status of TX descriptor 1 */
   56 #define RL_TXSTAT2      0x0018          /* status of TX descriptor 2 */
   57 #define RL_TXSTAT3      0x001C          /* status of TX descriptor 3 */
   58 
   59 #define RL_TXADDR0      0x0020          /* address of TX descriptor 0 */
   60 #define RL_TXADDR1      0x0024          /* address of TX descriptor 1 */
   61 #define RL_TXADDR2      0x0028          /* address of TX descriptor 2 */
   62 #define RL_TXADDR3      0x002C          /* address of TX descriptor 3 */
   63 
   64 #define RL_RXADDR               0x0030  /* RX ring start address */
   65 #define RL_RX_EARLY_BYTES       0x0034  /* RX early byte count */
   66 #define RL_RX_EARLY_STAT        0x0036  /* RX early status */
   67 #define RL_COMMAND      0x0037          /* command register */
   68 #define RL_CURRXADDR    0x0038          /* current address of packet read */
   69 #define RL_CURRXBUF     0x003A          /* current RX buffer address */
   70 #define RL_IMR          0x003C          /* interrupt mask register */
   71 #define RL_ISR          0x003E          /* interrupt status register */
   72 #define RL_TXCFG        0x0040          /* transmit config */
   73 #define RL_RXCFG        0x0044          /* receive config */
   74 #define RL_TIMERCNT     0x0048          /* timer count register */
   75 #define RL_MISSEDPKT    0x004C          /* missed packet counter */
   76 #define RL_EECMD        0x0050          /* EEPROM command register */
   77 #define RL_CFG0         0x0051          /* config register #0 */
   78 #define RL_CFG1         0x0052          /* config register #1 */
   79                                         /* 0053-0057 reserved */   
   80 #define RL_MEDIASTAT    0x0058          /* media status register (8139) */
   81                                         /* 0059-005A reserved */
   82 #define RL_MII          0x005A          /* 8129 chip only */
   83 #define RL_HALTCLK      0x005B
   84 #define RL_MULTIINTR    0x005C          /* multiple interrupt */
   85 #define RL_PCIREV       0x005E          /* PCI revision value */
   86                                         /* 005F reserved */
   87 #define RL_TXSTAT_ALL   0x0060          /* TX status of all descriptors */
   88 
   89 /* Direct PHY access registers only available on 8139 */
   90 #define RL_BMCR         0x0062          /* PHY basic mode control */
   91 #define RL_BMSR         0x0064          /* PHY basic mode status */
   92 #define RL_ANAR         0x0066          /* PHY autoneg advert */
   93 #define RL_LPAR         0x0068          /* PHY link partner ability */
   94 #define RL_ANER         0x006A          /* PHY autoneg expansion */
   95 
   96 #define RL_DISCCNT      0x006C          /* disconnect counter */
   97 #define RL_FALSECAR     0x006E          /* false carrier counter */
   98 #define RL_NWAYTST      0x0070          /* NWAY test register */
   99 #define RL_RX_ER        0x0072          /* RX_ER counter */
  100 #define RL_CSCFG        0x0074          /* CS configuration register */
  101 
  102 /*
  103  * When operating in special C+ mode, some of the registers in an
  104  * 8139C+ chip have different definitions. These are also used for
  105  * the 8169 gigE chip.
  106  */
  107 #define RL_DUMPSTATS_LO         0x0010  /* counter dump command register */
  108 #define RL_DUMPSTATS_HI         0x0014  /* counter dump command register */
  109 #define RL_TXLIST_ADDR_LO       0x0020  /* 64 bits, 256 byte alignment */
  110 #define RL_TXLIST_ADDR_HI       0x0024  /* 64 bits, 256 byte alignment */
  111 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028  /* 64 bits, 256 byte alignment */
  112 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C  /* 64 bits, 256 byte alignment */
  113 #define RL_CFG2                 0x0053
  114 #define RL_TIMERINT             0x0054  /* interrupt on timer expire */
  115 #define RL_TXSTART              0x00D9  /* 8 bits */
  116 #define RL_CPLUS_CMD            0x00E0  /* 16 bits */
  117 #define RL_RXLIST_ADDR_LO       0x00E4  /* 64 bits, 256 byte alignment */
  118 #define RL_RXLIST_ADDR_HI       0x00E8  /* 64 bits, 256 byte alignment */
  119 #define RL_EARLY_TX_THRESH      0x00EC  /* 8 bits */
  120 
  121 /*
  122  * Registers specific to the 8169 gigE chip
  123  */
  124 #define RL_TIMERINT_8169        0x0058  /* different offset than 8139 */
  125 #define RL_PHYAR                0x0060
  126 #define RL_TBICSR               0x0064
  127 #define RL_TBI_ANAR             0x0068
  128 #define RL_TBI_LPAR             0x006A
  129 #define RL_GMEDIASTAT           0x006C  /* 8 bits */
  130 #define RL_MAXRXPKTLEN          0x00DA  /* 16 bits, chip multiplies by 8 */
  131 #define RL_GTXSTART             0x0038  /* 16 bits */
  132 
  133 /*
  134  * TX config register bits
  135  */
  136 #define RL_TXCFG_CLRABRT        0x00000001      /* retransmit aborted pkt */
  137 #define RL_TXCFG_MAXDMA         0x00000700      /* max DMA burst size */
  138 #define RL_TXCFG_CRCAPPEND      0x00010000      /* CRC append (0 = yes) */
  139 #define RL_TXCFG_LOOPBKTST      0x00060000      /* loopback test */
  140 #define RL_TXCFG_IFG2           0x00080000      /* 8169 only */
  141 #define RL_TXCFG_IFG            0x03000000      /* interframe gap */
  142 #define RL_TXCFG_HWREV          0x7CC00000
  143 
  144 #define RL_LOOPTEST_OFF         0x00000000
  145 #define RL_LOOPTEST_ON          0x00020000
  146 #define RL_LOOPTEST_ON_CPLUS    0x00060000
  147 
  148 #define RL_HWREV_8169           0x00000000
  149 #define RL_HWREV_8169S          0x04000000
  150 #define RL_HWREV_8110S          0x00800000
  151 #define RL_HWREV_8139           0x60000000
  152 #define RL_HWREV_8139A          0x70000000
  153 #define RL_HWREV_8139AG         0x70800000
  154 #define RL_HWREV_8139B          0x78000000
  155 #define RL_HWREV_8130           0x7C000000
  156 #define RL_HWREV_8139C          0x74000000
  157 #define RL_HWREV_8139D          0x74400000
  158 #define RL_HWREV_8139CPLUS      0x74800000
  159 #define RL_HWREV_8101           0x74c00000
  160 #define RL_HWREV_8100           0x78800000
  161 
  162 #define RL_TXDMA_16BYTES        0x00000000
  163 #define RL_TXDMA_32BYTES        0x00000100
  164 #define RL_TXDMA_64BYTES        0x00000200
  165 #define RL_TXDMA_128BYTES       0x00000300
  166 #define RL_TXDMA_256BYTES       0x00000400
  167 #define RL_TXDMA_512BYTES       0x00000500
  168 #define RL_TXDMA_1024BYTES      0x00000600
  169 #define RL_TXDMA_2048BYTES      0x00000700
  170 
  171 /*
  172  * Transmit descriptor status register bits.
  173  */
  174 #define RL_TXSTAT_LENMASK       0x00001FFF
  175 #define RL_TXSTAT_OWN           0x00002000
  176 #define RL_TXSTAT_TX_UNDERRUN   0x00004000
  177 #define RL_TXSTAT_TX_OK         0x00008000
  178 #define RL_TXSTAT_EARLY_THRESH  0x003F0000
  179 #define RL_TXSTAT_COLLCNT       0x0F000000
  180 #define RL_TXSTAT_CARR_HBEAT    0x10000000
  181 #define RL_TXSTAT_OUTOFWIN      0x20000000
  182 #define RL_TXSTAT_TXABRT        0x40000000
  183 #define RL_TXSTAT_CARRLOSS      0x80000000
  184 
  185 /*
  186  * Interrupt status register bits.
  187  */
  188 #define RL_ISR_RX_OK            0x0001
  189 #define RL_ISR_RX_ERR           0x0002
  190 #define RL_ISR_TX_OK            0x0004
  191 #define RL_ISR_TX_ERR           0x0008
  192 #define RL_ISR_RX_OVERRUN       0x0010
  193 #define RL_ISR_PKT_UNDERRUN     0x0020
  194 #define RL_ISR_LINKCHG          0x0020  /* 8169 only */
  195 #define RL_ISR_FIFO_OFLOW       0x0040  /* 8139 only */
  196 #define RL_ISR_TX_DESC_UNAVAIL  0x0080  /* C+ only */
  197 #define RL_ISR_SWI              0x0100  /* C+ only */
  198 #define RL_ISR_CABLE_LEN_CHGD   0x2000
  199 #define RL_ISR_PCS_TIMEOUT      0x4000  /* 8129 only */
  200 #define RL_ISR_TIMEOUT_EXPIRED  0x4000
  201 #define RL_ISR_SYSTEM_ERR       0x8000
  202 
  203 #define RL_INTRS        \
  204         (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|         \
  205         RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
  206         RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
  207 
  208 #define RL_INTRS_CPLUS  \
  209         (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|                      \
  210         RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
  211         RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
  212 
  213 /*
  214  * Media status register. (8139 only)
  215  */
  216 #define RL_MEDIASTAT_RXPAUSE    0x01
  217 #define RL_MEDIASTAT_TXPAUSE    0x02
  218 #define RL_MEDIASTAT_LINK       0x04
  219 #define RL_MEDIASTAT_SPEED10    0x08
  220 #define RL_MEDIASTAT_RXFLOWCTL  0x40    /* duplex mode */
  221 #define RL_MEDIASTAT_TXFLOWCTL  0x80    /* duplex mode */
  222 
  223 /*
  224  * Receive config register.
  225  */
  226 #define RL_RXCFG_RX_ALLPHYS     0x00000001      /* accept all nodes */
  227 #define RL_RXCFG_RX_INDIV       0x00000002      /* match filter */
  228 #define RL_RXCFG_RX_MULTI       0x00000004      /* accept all multicast */
  229 #define RL_RXCFG_RX_BROAD       0x00000008      /* accept all broadcast */
  230 #define RL_RXCFG_RX_RUNT        0x00000010
  231 #define RL_RXCFG_RX_ERRPKT      0x00000020
  232 #define RL_RXCFG_WRAP           0x00000080
  233 #define RL_RXCFG_MAXDMA         0x00000700
  234 #define RL_RXCFG_BUFSZ          0x00001800
  235 #define RL_RXCFG_FIFOTHRESH     0x0000E000
  236 #define RL_RXCFG_EARLYTHRESH    0x07000000
  237 
  238 #define RL_RXDMA_16BYTES        0x00000000
  239 #define RL_RXDMA_32BYTES        0x00000100
  240 #define RL_RXDMA_64BYTES        0x00000200
  241 #define RL_RXDMA_128BYTES       0x00000300
  242 #define RL_RXDMA_256BYTES       0x00000400
  243 #define RL_RXDMA_512BYTES       0x00000500
  244 #define RL_RXDMA_1024BYTES      0x00000600
  245 #define RL_RXDMA_UNLIMITED      0x00000700
  246 
  247 #define RL_RXBUF_8              0x00000000
  248 #define RL_RXBUF_16             0x00000800
  249 #define RL_RXBUF_32             0x00001000
  250 #define RL_RXBUF_64             0x00001800
  251 
  252 #define RL_RXFIFO_16BYTES       0x00000000
  253 #define RL_RXFIFO_32BYTES       0x00002000
  254 #define RL_RXFIFO_64BYTES       0x00004000
  255 #define RL_RXFIFO_128BYTES      0x00006000
  256 #define RL_RXFIFO_256BYTES      0x00008000
  257 #define RL_RXFIFO_512BYTES      0x0000A000
  258 #define RL_RXFIFO_1024BYTES     0x0000C000
  259 #define RL_RXFIFO_NOTHRESH      0x0000E000
  260 
  261 /*
  262  * Bits in RX status header (included with RX'ed packet
  263  * in ring buffer).
  264  */
  265 #define RL_RXSTAT_RXOK          0x00000001
  266 #define RL_RXSTAT_ALIGNERR      0x00000002
  267 #define RL_RXSTAT_CRCERR        0x00000004
  268 #define RL_RXSTAT_GIANT         0x00000008
  269 #define RL_RXSTAT_RUNT          0x00000010
  270 #define RL_RXSTAT_BADSYM        0x00000020
  271 #define RL_RXSTAT_BROAD         0x00002000
  272 #define RL_RXSTAT_INDIV         0x00004000
  273 #define RL_RXSTAT_MULTI         0x00008000
  274 #define RL_RXSTAT_LENMASK       0xFFFF0000
  275 
  276 #define RL_RXSTAT_UNFINISHED    0xFFF0          /* DMA still in progress */
  277 /*
  278  * Command register.
  279  */
  280 #define RL_CMD_EMPTY_RXBUF      0x0001
  281 #define RL_CMD_TX_ENB           0x0004
  282 #define RL_CMD_RX_ENB           0x0008
  283 #define RL_CMD_RESET            0x0010
  284 
  285 /*
  286  * EEPROM control register
  287  */
  288 #define RL_EE_DATAOUT           0x01    /* Data out */
  289 #define RL_EE_DATAIN            0x02    /* Data in */
  290 #define RL_EE_CLK               0x04    /* clock */
  291 #define RL_EE_SEL               0x08    /* chip select */
  292 #define RL_EE_MODE              (0x40|0x80)
  293 
  294 #define RL_EEMODE_OFF           0x00
  295 #define RL_EEMODE_AUTOLOAD      0x40
  296 #define RL_EEMODE_PROGRAM       0x80
  297 #define RL_EEMODE_WRITECFG      (0x80|0x40)
  298 
  299 /* 9346 EEPROM commands */
  300 #define RL_EECMD_WRITE          0x140
  301 #define RL_EECMD_READ_6BIT      0x180
  302 #define RL_EECMD_READ_8BIT      0x600
  303 #define RL_EECMD_ERASE          0x1c0
  304 
  305 #define RL_EE_ID                0x00
  306 #define RL_EE_PCI_VID           0x01
  307 #define RL_EE_PCI_DID           0x02
  308 /* Location of station address inside EEPROM */
  309 #define RL_EE_EADDR             0x07
  310 
  311 /*
  312  * MII register (8129 only)
  313  */
  314 #define RL_MII_CLK              0x01
  315 #define RL_MII_DATAIN           0x02
  316 #define RL_MII_DATAOUT          0x04
  317 #define RL_MII_DIR              0x80    /* 0 == input, 1 == output */
  318 
  319 /*
  320  * Config 0 register
  321  */
  322 #define RL_CFG0_ROM0            0x01
  323 #define RL_CFG0_ROM1            0x02
  324 #define RL_CFG0_ROM2            0x04
  325 #define RL_CFG0_PL0             0x08
  326 #define RL_CFG0_PL1             0x10
  327 #define RL_CFG0_10MBPS          0x20    /* 10 Mbps internal mode */
  328 #define RL_CFG0_PCS             0x40
  329 #define RL_CFG0_SCR             0x80
  330 
  331 /*
  332  * Config 1 register
  333  */
  334 #define RL_CFG1_PWRDWN          0x01
  335 #define RL_CFG1_SLEEP           0x02
  336 #define RL_CFG1_IOMAP           0x04
  337 #define RL_CFG1_MEMMAP          0x08
  338 #define RL_CFG1_RSVD            0x10
  339 #define RL_CFG1_DRVLOAD         0x20
  340 #define RL_CFG1_LED0            0x40
  341 #define RL_CFG1_FULLDUPLEX      0x40    /* 8129 only */
  342 #define RL_CFG1_LED1            0x80
  343 
  344 /*
  345  * 8139C+ register definitions
  346  */
  347 
  348 /* RL_DUMPSTATS_LO register */
  349 
  350 #define RL_DUMPSTATS_START      0x00000008
  351 
  352 /* Transmit start register */
  353 
  354 #define RL_TXSTART_SWI          0x01    /* generate TX interrupt */
  355 #define RL_TXSTART_START        0x40    /* start normal queue transmit */
  356 #define RL_TXSTART_HPRIO_START  0x80    /* start hi prio queue transmit */
  357 
  358 /*
  359  * Config 2 register, 8139C+/8169/8169S/8110S only
  360  */
  361 #define RL_CFG2_BUSFREQ         0x07
  362 #define RL_CFG2_BUSWIDTH        0x08
  363 #define RL_CFG2_AUXPWRSTS       0x10
  364 
  365 #define RL_BUSFREQ_33MHZ        0x00
  366 #define RL_BUSFREQ_66MHZ        0x01
  367                                         
  368 #define RL_BUSWIDTH_32BITS      0x00
  369 #define RL_BUSWIDTH_64BITS      0x08
  370 
  371 /* C+ mode command register */
  372 
  373 #define RL_CPLUSCMD_TXENB       0x0001  /* enable C+ transmit mode */
  374 #define RL_CPLUSCMD_RXENB       0x0002  /* enable C+ receive mode */
  375 #define RL_CPLUSCMD_PCI_MRW     0x0008  /* enable PCI multi-read/write */
  376 #define RL_CPLUSCMD_PCI_DAC     0x0010  /* PCI dual-address cycle only */
  377 #define RL_CPLUSCMD_RXCSUM_ENB  0x0020  /* enable RX checksum offload */
  378 #define RL_CPLUSCMD_VLANSTRIP   0x0040  /* enable VLAN tag stripping */
  379 
  380 /* C+ early transmit threshold */
  381 
  382 #define RL_EARLYTXTHRESH_CNT    0x003F  /* byte count times 8 */ 
  383 
  384 /*
  385  * Gigabit PHY access register (8169 only)
  386  */
  387 
  388 #define RL_PHYAR_PHYDATA        0x0000FFFF
  389 #define RL_PHYAR_PHYREG         0x001F0000
  390 #define RL_PHYAR_BUSY           0x80000000
  391 
  392 /*
  393  * Gigabit media status (8169 only)
  394  */
  395 #define RL_GMEDIASTAT_FDX       0x01    /* full duplex */
  396 #define RL_GMEDIASTAT_LINK      0x02    /* link up */
  397 #define RL_GMEDIASTAT_10MBPS    0x04    /* 10mps link */
  398 #define RL_GMEDIASTAT_100MBPS   0x08    /* 100mbps link */
  399 #define RL_GMEDIASTAT_1000MBPS  0x10    /* gigE link */
  400 #define RL_GMEDIASTAT_RXFLOW    0x20    /* RX flow control on */
  401 #define RL_GMEDIASTAT_TXFLOW    0x40    /* TX flow control on */
  402 #define RL_GMEDIASTAT_TBI       0x80    /* TBI enabled */
  403 
  404 /*
  405  * The RealTek doesn't use a fragment-based descriptor mechanism.
  406  * Instead, there are only four register sets, each or which represents
  407  * one 'descriptor.' Basically, each TX descriptor is just a contiguous
  408  * packet buffer (32-bit aligned!) and we place the buffer addresses in
  409  * the registers so the chip knows where they are.
  410  *
  411  * We can sort of kludge together the same kind of buffer management
  412  * used in previous drivers, but we have to do buffer copies almost all
  413  * the time, so it doesn't really buy us much.
  414  *
  415  * For reception, there's just one large buffer where the chip stores
  416  * all received packets.
  417  */
  418 
  419 #define RL_RX_BUF_SZ            RL_RXBUF_64
  420 #define RL_RXBUFLEN             (1 << ((RL_RX_BUF_SZ >> 11) + 13))
  421 #define RL_TX_LIST_CNT          4
  422 #define RL_MIN_FRAMELEN         60
  423 #define RL_TXTHRESH(x)          ((x) << 11)
  424 #define RL_TX_THRESH_INIT       96
  425 #define RL_RX_FIFOTHRESH        RL_RXFIFO_NOTHRESH
  426 #define RL_RX_MAXDMA            RL_RXDMA_UNLIMITED
  427 #define RL_TX_MAXDMA            RL_TXDMA_2048BYTES
  428 
  429 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
  430 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
  431 
  432 #define RL_ETHER_ALIGN  2
  433 
  434 struct rl_chain_data {
  435         u_int16_t               cur_rx;
  436         caddr_t                 rl_rx_buf;
  437         caddr_t                 rl_rx_buf_ptr;
  438         bus_dmamap_t            rl_rx_dmamap;
  439 
  440         struct mbuf             *rl_tx_chain[RL_TX_LIST_CNT];
  441         bus_dmamap_t            rl_tx_dmamap[RL_TX_LIST_CNT];
  442         u_int8_t                last_tx;
  443         u_int8_t                cur_tx;
  444 };
  445 
  446 #define RL_INC(x)               (x = (x + 1) % RL_TX_LIST_CNT)
  447 #define RL_CUR_TXADDR(x)        ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
  448 #define RL_CUR_TXSTAT(x)        ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
  449 #define RL_CUR_TXMBUF(x)        (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
  450 #define RL_CUR_DMAMAP(x)        (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
  451 #define RL_LAST_TXADDR(x)       ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
  452 #define RL_LAST_TXSTAT(x)       ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
  453 #define RL_LAST_TXMBUF(x)       (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
  454 #define RL_LAST_DMAMAP(x)       (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
  455 
  456 struct rl_type {
  457         u_int16_t               rl_vid;
  458         u_int16_t               rl_did;
  459         int                     rl_basetype;
  460         char                    *rl_name;
  461 };
  462 
  463 struct rl_hwrev {
  464         u_int32_t               rl_rev;
  465         int                     rl_type;
  466         char                    *rl_desc;
  467 };
  468 
  469 struct rl_mii_frame {
  470         u_int8_t                mii_stdelim;
  471         u_int8_t                mii_opcode;
  472         u_int8_t                mii_phyaddr;
  473         u_int8_t                mii_regaddr;
  474         u_int8_t                mii_turnaround;
  475         u_int16_t               mii_data;
  476 };
  477 
  478 /*
  479  * MII constants
  480  */
  481 #define RL_MII_STARTDELIM       0x01
  482 #define RL_MII_READOP           0x02
  483 #define RL_MII_WRITEOP          0x01
  484 #define RL_MII_TURNAROUND       0x02
  485 
  486 #define RL_8129                 1
  487 #define RL_8139                 2
  488 #define RL_8139CPLUS            3
  489 #define RL_8169                 4
  490 
  491 #define RL_ISCPLUS(x)           ((x)->rl_type == RL_8139CPLUS ||        \
  492                                  (x)->rl_type == RL_8169)
  493 
  494 /*
  495  * The 8139C+ and 8160 gigE chips support descriptor-based TX
  496  * and RX. In fact, they even support TCP large send. Descriptors
  497  * must be allocated in contiguous blocks that are aligned on a
  498  * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
  499  */
  500 
  501 /*
  502  * RX/TX descriptor definition. When large send mode is enabled, the
  503  * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
  504  * the checksum offload bits are disabled. The structure layout is
  505  * the same for RX and TX descriptors
  506  */
  507 
  508 struct rl_desc {
  509         u_int32_t               rl_cmdstat;
  510         u_int32_t               rl_vlanctl;
  511         u_int32_t               rl_bufaddr_lo;
  512         u_int32_t               rl_bufaddr_hi;
  513 };
  514 
  515 #define RL_TDESC_CMD_FRAGLEN    0x0000FFFF
  516 #define RL_TDESC_CMD_TCPCSUM    0x00010000      /* TCP checksum enable */
  517 #define RL_TDESC_CMD_UDPCSUM    0x00020000      /* UDP checksum enable */
  518 #define RL_TDESC_CMD_IPCSUM     0x00040000      /* IP header checksum enable */
  519 #define RL_TDESC_CMD_MSSVAL     0x07FF0000      /* Large send MSS value */
  520 #define RL_TDESC_CMD_LGSEND     0x08000000      /* TCP large send enb */
  521 #define RL_TDESC_CMD_EOF        0x10000000      /* end of frame marker */
  522 #define RL_TDESC_CMD_SOF        0x20000000      /* start of frame marker */
  523 #define RL_TDESC_CMD_EOR        0x40000000      /* end of ring marker */
  524 #define RL_TDESC_CMD_OWN        0x80000000      /* chip owns descriptor */
  525 
  526 #define RL_TDESC_VLANCTL_TAG    0x00020000      /* Insert VLAN tag */
  527 #define RL_TDESC_VLANCTL_DATA   0x0000FFFF      /* TAG data */
  528 
  529 /*
  530  * Error bits are valid only on the last descriptor of a frame
  531  * (i.e. RL_TDESC_CMD_EOF == 1)
  532  */
  533 
  534 #define RL_TDESC_STAT_COLCNT    0x000F0000      /* collision count */
  535 #define RL_TDESC_STAT_EXCESSCOL 0x00100000      /* excessive collisions */
  536 #define RL_TDESC_STAT_LINKFAIL  0x00200000      /* link faulure */
  537 #define RL_TDESC_STAT_OWINCOL   0x00400000      /* out-of-window collision */
  538 #define RL_TDESC_STAT_TXERRSUM  0x00800000      /* transmit error summary */
  539 #define RL_TDESC_STAT_UNDERRUN  0x02000000      /* TX underrun occured */
  540 #define RL_TDESC_STAT_OWN       0x80000000
  541 
  542 /*
  543  * RX descriptor cmd/vlan definitions
  544  */
  545 
  546 #define RL_RDESC_CMD_EOR        0x40000000
  547 #define RL_RDESC_CMD_OWN        0x80000000
  548 #define RL_RDESC_CMD_BUFLEN     0x00001FFF
  549 
  550 #define RL_RDESC_STAT_OWN       0x80000000
  551 #define RL_RDESC_STAT_EOR       0x40000000
  552 #define RL_RDESC_STAT_SOF       0x20000000
  553 #define RL_RDESC_STAT_EOF       0x10000000
  554 #define RL_RDESC_STAT_FRALIGN   0x08000000      /* frame alignment error */
  555 #define RL_RDESC_STAT_MCAST     0x04000000      /* multicast pkt received */
  556 #define RL_RDESC_STAT_UCAST     0x02000000      /* unicast pkt received */
  557 #define RL_RDESC_STAT_BCAST     0x01000000      /* broadcast pkt received */
  558 #define RL_RDESC_STAT_BUFOFLOW  0x00800000      /* out of buffer space */
  559 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000      /* FIFO overrun */
  560 #define RL_RDESC_STAT_GIANT     0x00200000      /* pkt > 4096 bytes */
  561 #define RL_RDESC_STAT_RXERRSUM  0x00100000      /* RX error summary */
  562 #define RL_RDESC_STAT_RUNT      0x00080000      /* runt packet received */
  563 #define RL_RDESC_STAT_CRCERR    0x00040000      /* CRC error */
  564 #define RL_RDESC_STAT_PROTOID   0x00030000      /* Protocol type */
  565 #define RL_RDESC_STAT_IPSUMBAD  0x00008000      /* IP header checksum bad */
  566 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000      /* UDP checksum bad */
  567 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000      /* TCP checksum bad */
  568 #define RL_RDESC_STAT_FRAGLEN   0x00001FFF      /* RX'ed frame/frag len */
  569 #define RL_RDESC_STAT_GFRAGLEN  0x00003FFF      /* RX'ed frame/frag len */
  570 
  571 #define RL_RDESC_VLANCTL_TAG    0x00010000      /* VLAN tag available
  572                                                    (rl_vlandata valid)*/
  573 #define RL_RDESC_VLANCTL_DATA   0x0000FFFF      /* TAG data */
  574 
  575 #define RL_PROTOID_NONIP        0x00000000
  576 #define RL_PROTOID_TCPIP        0x00010000
  577 #define RL_PROTOID_UDPIP        0x00020000
  578 #define RL_PROTOID_IP           0x00030000
  579 #define RL_TCPPKT(x)            (((x) & RL_RDESC_STAT_PROTOID) == \
  580                                  RL_PROTOID_TCPIP)
  581 #define RL_UDPPKT(x)            (((x) & RL_RDESC_STAT_PROTOID) == \
  582                                  RL_PROTOID_UDPIP)
  583 
  584 /*
  585  * Statistics counter structure (8139C+ and 8169 only)
  586  */
  587 struct rl_stats {
  588         u_int32_t               rl_tx_pkts_lo;
  589         u_int32_t               rl_tx_pkts_hi;
  590         u_int32_t               rl_tx_errs_lo;
  591         u_int32_t               rl_tx_errs_hi;
  592         u_int32_t               rl_tx_errs;
  593         u_int16_t               rl_missed_pkts;
  594         u_int16_t               rl_rx_framealign_errs;
  595         u_int32_t               rl_tx_onecoll;
  596         u_int32_t               rl_tx_multicolls;
  597         u_int32_t               rl_rx_ucasts_hi;
  598         u_int32_t               rl_rx_ucasts_lo;
  599         u_int32_t               rl_rx_bcasts_lo;
  600         u_int32_t               rl_rx_bcasts_hi;
  601         u_int32_t               rl_rx_mcasts;
  602         u_int16_t               rl_tx_aborts;
  603         u_int16_t               rl_rx_underruns;
  604 };
  605 
  606 #define RL_RX_DESC_CNT          64
  607 #define RL_TX_DESC_CNT          64
  608 #define RL_RX_LIST_SZ           (RL_RX_DESC_CNT * sizeof(struct rl_desc))
  609 #define RL_TX_LIST_SZ           (RL_TX_DESC_CNT * sizeof(struct rl_desc))
  610 #define RL_RING_ALIGN           256
  611 #define RL_IFQ_MAXLEN           512
  612 #define RL_DESC_INC(x)          (x = (x + 1) % RL_TX_DESC_CNT)
  613 #define RL_OWN(x)               (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
  614 #define RL_RXBYTES(x)           (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
  615 #define RL_PKTSZ(x)             ((x)/* >> 3*/)
  616 
  617 #define RL_ADDR_LO(y)   ((u_int64_t) (y) & 0xFFFFFFFF)
  618 #define RL_ADDR_HI(y)   ((u_int64_t) (y) >> 32)
  619 
  620 #define RL_JUMBO_FRAMELEN       9018
  621 #define RL_JUMBO_MTU            (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
  622 
  623 struct rl_softc;
  624 
  625 struct rl_dmaload_arg {
  626         struct rl_softc         *sc;
  627         int                     rl_idx;
  628         int                     rl_maxsegs;
  629         u_int32_t               rl_flags;
  630         struct rl_desc          *rl_ring;
  631 };
  632 
  633 struct rl_list_data {
  634         struct mbuf             *rl_tx_mbuf[RL_TX_DESC_CNT];
  635         struct mbuf             *rl_rx_mbuf[RL_TX_DESC_CNT];
  636         int                     rl_tx_prodidx;
  637         int                     rl_rx_prodidx;
  638         int                     rl_tx_considx;
  639         int                     rl_tx_free;
  640         bus_dmamap_t            rl_tx_dmamap[RL_TX_DESC_CNT];
  641         bus_dmamap_t            rl_rx_dmamap[RL_RX_DESC_CNT];
  642         bus_dma_tag_t           rl_mtag;        /* mbuf mapping tag */
  643         bus_dma_tag_t           rl_stag;        /* stats mapping tag */
  644         bus_dmamap_t            rl_smap;        /* stats map */
  645         struct rl_stats         *rl_stats;
  646         bus_addr_t              rl_stats_addr;
  647         bus_dma_tag_t           rl_rx_list_tag;
  648         bus_dmamap_t            rl_rx_list_map;
  649         struct rl_desc          *rl_rx_list;
  650         bus_addr_t              rl_rx_list_addr;
  651         bus_dma_tag_t           rl_tx_list_tag;
  652         bus_dmamap_t            rl_tx_list_map;
  653         struct rl_desc          *rl_tx_list;
  654         bus_addr_t              rl_tx_list_addr;
  655 };
  656 
  657 struct rl_softc {
  658         struct arpcom           arpcom;         /* interface info */
  659         bus_space_handle_t      rl_bhandle;     /* bus space handle */
  660         bus_space_tag_t         rl_btag;        /* bus space tag */
  661         struct resource         *rl_res;
  662         struct resource         *rl_irq;
  663         void                    *rl_intrhand;
  664         device_t                rl_miibus;
  665         bus_dma_tag_t           rl_parent_tag;
  666         bus_dma_tag_t           rl_tag;
  667         u_int8_t                rl_unit;        /* interface number */
  668         u_int8_t                rl_type;
  669         int                     rl_eecmd_read;
  670         u_int8_t                rl_stats_no_timeout;
  671         int                     rl_txthresh;
  672         struct rl_chain_data    rl_cdata;
  673         struct rl_list_data     rl_ldata;
  674         struct callout_handle   rl_stat_ch;
  675         struct mtx              rl_mtx;
  676         struct mbuf             *rl_head;
  677         struct mbuf             *rl_tail;
  678         u_int32_t               rl_hwrev;
  679         u_int32_t               rl_rxlenmask;
  680         int                     rl_testmode;
  681         int                     suspended;      /* 0 = normal  1 = suspended */
  682 #ifdef DEVICE_POLLING
  683         int                     rxcycles;
  684 #endif
  685 
  686         u_int32_t               saved_maps[5];  /* pci data */
  687         u_int32_t               saved_biosaddr;
  688         u_int8_t                saved_intline;
  689         u_int8_t                saved_cachelnsz;
  690         u_int8_t                saved_lattimer;
  691 };
  692 
  693 #define RL_LOCK(_sc)            mtx_lock(&(_sc)->rl_mtx)
  694 #define RL_UNLOCK(_sc)          mtx_unlock(&(_sc)->rl_mtx)
  695 #define RL_LOCK_ASSERT(_sc)     mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
  696 
  697 /*
  698  * register space access macros
  699  */
  700 #define CSR_WRITE_STREAM_4(sc, reg, val)        \
  701         bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
  702 #define CSR_WRITE_4(sc, reg, val)       \
  703         bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
  704 #define CSR_WRITE_2(sc, reg, val)       \
  705         bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
  706 #define CSR_WRITE_1(sc, reg, val)       \
  707         bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
  708 
  709 #define CSR_READ_4(sc, reg)             \
  710         bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
  711 #define CSR_READ_2(sc, reg)             \
  712         bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
  713 #define CSR_READ_1(sc, reg)             \
  714         bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
  715 
  716 #define RL_TIMEOUT              1000
  717 
  718 /*
  719  * General constants that are fun to know.
  720  *
  721  * RealTek PCI vendor ID
  722  */
  723 #define RT_VENDORID                             0x10EC
  724 
  725 /*
  726  * RealTek chip device IDs.
  727  */
  728 #define RT_DEVICEID_8129                        0x8129
  729 #define RT_DEVICEID_8138                        0x8138
  730 #define RT_DEVICEID_8139                        0x8139
  731 #define RT_DEVICEID_8169                        0x8169
  732 #define RT_DEVICEID_8100                        0x8100
  733 
  734 #define RT_REVID_8139CPLUS                      0x20
  735 
  736 /*
  737  * Accton PCI vendor ID
  738  */
  739 #define ACCTON_VENDORID                         0x1113
  740 
  741 /*
  742  * Accton MPX 5030/5038 device ID.
  743  */
  744 #define ACCTON_DEVICEID_5030                    0x1211
  745 
  746 /*
  747  * Nortel PCI vendor ID
  748  */
  749 #define NORTEL_VENDORID                         0x126C
  750 
  751 /*
  752  * Delta Electronics Vendor ID.
  753  */
  754 #define DELTA_VENDORID                          0x1500
  755 
  756 /*
  757  * Delta device IDs.
  758  */
  759 #define DELTA_DEVICEID_8139                     0x1360
  760 
  761 /*
  762  * Addtron vendor ID.
  763  */
  764 #define ADDTRON_VENDORID                        0x4033
  765 
  766 /*
  767  * Addtron device IDs.
  768  */
  769 #define ADDTRON_DEVICEID_8139                   0x1360
  770 
  771 /*
  772  * D-Link vendor ID.
  773  */
  774 #define DLINK_VENDORID                          0x1186
  775 
  776 /*
  777  * D-Link DFE-530TX+ device ID
  778  */
  779 #define DLINK_DEVICEID_530TXPLUS                0x1300
  780 
  781 /*
  782  * D-Link DFE-690TXD device ID
  783  */
  784 #define DLINK_DEVICEID_690TXD                   0x1340
  785 
  786 /*
  787  * Corega K.K vendor ID
  788  */
  789 #define COREGA_VENDORID                         0x1259
  790 
  791 /*
  792  * Corega FEther CB-TXD device ID
  793  */
  794 #define COREGA_DEVICEID_FETHERCBTXD                     0xa117
  795 
  796 /*
  797  * Corega FEtherII CB-TXD device ID
  798  */
  799 #define COREGA_DEVICEID_FETHERIICBTXD                   0xa11e
  800 
  801 /*
  802  * Peppercon vendor ID
  803  */
  804 #define PEPPERCON_VENDORID                      0x1743
  805 
  806 /*
  807  * Peppercon ROL-F device ID
  808  */
  809 #define PEPPERCON_DEVICEID_ROLF                 0x8139
  810 
  811 /*
  812  * Planex Communications, Inc. vendor ID
  813  */
  814 #define PLANEX_VENDORID                         0x14ea
  815 
  816 /*
  817  * Planex FNW-3800-TX device ID
  818  */
  819 #define PLANEX_DEVICEID_FNW3800TX               0xab07
  820 
  821 /*
  822  * LevelOne vendor ID
  823  */
  824 #define LEVEL1_VENDORID                         0x018A
  825 
  826 /*
  827  * LevelOne FPC-0106TX devide ID
  828  */
  829 #define LEVEL1_DEVICEID_FPC0106TX               0x0106
  830 
  831 /*
  832  * Compaq vendor ID
  833  */
  834 #define CP_VENDORID                             0x021B
  835 
  836 /*
  837  * Edimax vendor ID
  838  */
  839 #define EDIMAX_VENDORID                         0x13D1
  840 
  841 /*
  842  * Edimax EP-4103DL cardbus device ID
  843  */
  844 #define EDIMAX_DEVICEID_EP4103DL                0xAB06
  845 
  846 /*
  847  * PCI low memory base and low I/O base register, and
  848  * other PCI registers.
  849  */
  850 
  851 #define RL_PCI_VENDOR_ID        0x00
  852 #define RL_PCI_DEVICE_ID        0x02
  853 #define RL_PCI_COMMAND          0x04
  854 #define RL_PCI_STATUS           0x06
  855 #define RL_PCI_CLASSCODE        0x09
  856 #define RL_PCI_LATENCY_TIMER    0x0D
  857 #define RL_PCI_HEADER_TYPE      0x0E
  858 #define RL_PCI_LOIO             0x10
  859 #define RL_PCI_LOMEM            0x14
  860 #define RL_PCI_BIOSROM          0x30
  861 #define RL_PCI_INTLINE          0x3C
  862 #define RL_PCI_INTPIN           0x3D
  863 #define RL_PCI_MINGNT           0x3E
  864 #define RL_PCI_MINLAT           0x0F
  865 #define RL_PCI_RESETOPT         0x48
  866 #define RL_PCI_EEPROM_DATA      0x4C
  867 
  868 #define RL_PCI_CAPID            0x50 /* 8 bits */
  869 #define RL_PCI_NEXTPTR          0x51 /* 8 bits */
  870 #define RL_PCI_PWRMGMTCAP       0x52 /* 16 bits */
  871 #define RL_PCI_PWRMGMTCTRL      0x54 /* 16 bits */
  872 
  873 #define RL_PSTATE_MASK          0x0003
  874 #define RL_PSTATE_D0            0x0000
  875 #define RL_PSTATE_D1            0x0002
  876 #define RL_PSTATE_D2            0x0002
  877 #define RL_PSTATE_D3            0x0003
  878 #define RL_PME_EN               0x0010
  879 #define RL_PME_STATUS           0x8000

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