The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rlreg.h

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    1 /*-
    2  * Copyright (c) 1997, 1998-2003
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD$
   33  */
   34 
   35 /*
   36  * RealTek 8129/8139 register offsets
   37  */
   38 #define RL_IDR0         0x0000          /* ID register 0 (station addr) */
   39 #define RL_IDR1         0x0001          /* Must use 32-bit accesses (?) */
   40 #define RL_IDR2         0x0002
   41 #define RL_IDR3         0x0003
   42 #define RL_IDR4         0x0004
   43 #define RL_IDR5         0x0005
   44                                         /* 0006-0007 reserved */
   45 #define RL_MAR0         0x0008          /* Multicast hash table */
   46 #define RL_MAR1         0x0009
   47 #define RL_MAR2         0x000A
   48 #define RL_MAR3         0x000B
   49 #define RL_MAR4         0x000C
   50 #define RL_MAR5         0x000D
   51 #define RL_MAR6         0x000E
   52 #define RL_MAR7         0x000F
   53 
   54 #define RL_TXSTAT0      0x0010          /* status of TX descriptor 0 */
   55 #define RL_TXSTAT1      0x0014          /* status of TX descriptor 1 */
   56 #define RL_TXSTAT2      0x0018          /* status of TX descriptor 2 */
   57 #define RL_TXSTAT3      0x001C          /* status of TX descriptor 3 */
   58 
   59 #define RL_TXADDR0      0x0020          /* address of TX descriptor 0 */
   60 #define RL_TXADDR1      0x0024          /* address of TX descriptor 1 */
   61 #define RL_TXADDR2      0x0028          /* address of TX descriptor 2 */
   62 #define RL_TXADDR3      0x002C          /* address of TX descriptor 3 */
   63 
   64 #define RL_RXADDR               0x0030  /* RX ring start address */
   65 #define RL_RX_EARLY_BYTES       0x0034  /* RX early byte count */
   66 #define RL_RX_EARLY_STAT        0x0036  /* RX early status */
   67 #define RL_COMMAND      0x0037          /* command register */
   68 #define RL_CURRXADDR    0x0038          /* current address of packet read */
   69 #define RL_CURRXBUF     0x003A          /* current RX buffer address */
   70 #define RL_IMR          0x003C          /* interrupt mask register */
   71 #define RL_ISR          0x003E          /* interrupt status register */
   72 #define RL_TXCFG        0x0040          /* transmit config */
   73 #define RL_RXCFG        0x0044          /* receive config */
   74 #define RL_TIMERCNT     0x0048          /* timer count register */
   75 #define RL_MISSEDPKT    0x004C          /* missed packet counter */
   76 #define RL_EECMD        0x0050          /* EEPROM command register */
   77 #define RL_CFG0         0x0051          /* config register #0 */
   78 #define RL_CFG1         0x0052          /* config register #1 */
   79 #define RL_CFG2         0x0053          /* config register #2 */
   80 #define RL_CFG3         0x0054          /* config register #3 */
   81 #define RL_CFG4         0x0055          /* config register #4 */
   82 #define RL_CFG5         0x0056          /* config register #5 */
   83                                         /* 0057 reserved */
   84 #define RL_MEDIASTAT    0x0058          /* media status register (8139) */
   85                                         /* 0059-005A reserved */
   86 #define RL_MII          0x005A          /* 8129 chip only */
   87 #define RL_HALTCLK      0x005B
   88 #define RL_MULTIINTR    0x005C          /* multiple interrupt */
   89 #define RL_PCIREV       0x005E          /* PCI revision value */
   90                                         /* 005F reserved */
   91 #define RL_TXSTAT_ALL   0x0060          /* TX status of all descriptors */
   92 
   93 /* Direct PHY access registers only available on 8139 */
   94 #define RL_BMCR         0x0062          /* PHY basic mode control */
   95 #define RL_BMSR         0x0064          /* PHY basic mode status */
   96 #define RL_ANAR         0x0066          /* PHY autoneg advert */
   97 #define RL_LPAR         0x0068          /* PHY link partner ability */
   98 #define RL_ANER         0x006A          /* PHY autoneg expansion */
   99 
  100 #define RL_DISCCNT      0x006C          /* disconnect counter */
  101 #define RL_FALSECAR     0x006E          /* false carrier counter */
  102 #define RL_NWAYTST      0x0070          /* NWAY test register */
  103 #define RL_RX_ER        0x0072          /* RX_ER counter */
  104 #define RL_CSCFG        0x0074          /* CS configuration register */
  105 
  106 /*
  107  * When operating in special C+ mode, some of the registers in an
  108  * 8139C+ chip have different definitions. These are also used for
  109  * the 8169 gigE chip.
  110  */
  111 #define RL_DUMPSTATS_LO         0x0010  /* counter dump command register */
  112 #define RL_DUMPSTATS_HI         0x0014  /* counter dump command register */
  113 #define RL_TXLIST_ADDR_LO       0x0020  /* 64 bits, 256 byte alignment */
  114 #define RL_TXLIST_ADDR_HI       0x0024  /* 64 bits, 256 byte alignment */
  115 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028  /* 64 bits, 256 byte alignment */
  116 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C  /* 64 bits, 256 byte alignment */
  117 #define RL_CFG2                 0x0053
  118 #define RL_TIMERINT             0x0054  /* interrupt on timer expire */
  119 #define RL_TXSTART              0x00D9  /* 8 bits */
  120 #define RL_CPLUS_CMD            0x00E0  /* 16 bits */
  121 #define RL_RXLIST_ADDR_LO       0x00E4  /* 64 bits, 256 byte alignment */
  122 #define RL_RXLIST_ADDR_HI       0x00E8  /* 64 bits, 256 byte alignment */
  123 #define RL_EARLY_TX_THRESH      0x00EC  /* 8 bits */
  124 
  125 /*
  126  * Registers specific to the 8169 gigE chip
  127  */
  128 #define RL_TIMERINT_8169        0x0058  /* different offset than 8139 */
  129 #define RL_PHYAR                0x0060
  130 #define RL_TBICSR               0x0064
  131 #define RL_TBI_ANAR             0x0068
  132 #define RL_TBI_LPAR             0x006A
  133 #define RL_GMEDIASTAT           0x006C  /* 8 bits */
  134 #define RL_MAXRXPKTLEN          0x00DA  /* 16 bits, chip multiplies by 8 */
  135 #define RL_GTXSTART             0x0038  /* 8 bits */
  136 
  137 /*
  138  * TX config register bits
  139  */
  140 #define RL_TXCFG_CLRABRT        0x00000001      /* retransmit aborted pkt */
  141 #define RL_TXCFG_MAXDMA         0x00000700      /* max DMA burst size */
  142 #define RL_TXCFG_CRCAPPEND      0x00010000      /* CRC append (0 = yes) */
  143 #define RL_TXCFG_LOOPBKTST      0x00060000      /* loopback test */
  144 #define RL_TXCFG_IFG2           0x00080000      /* 8169 only */
  145 #define RL_TXCFG_IFG            0x03000000      /* interframe gap */
  146 #define RL_TXCFG_HWREV          0x7CC00000
  147 
  148 #define RL_LOOPTEST_OFF         0x00000000
  149 #define RL_LOOPTEST_ON          0x00020000
  150 #define RL_LOOPTEST_ON_CPLUS    0x00060000
  151 
  152 /* Known revision codes. */
  153 
  154 #define RL_HWREV_8169           0x00000000
  155 #define RL_HWREV_8110S          0x00800000
  156 #define RL_HWREV_8169S          0x04000000
  157 #define RL_HWREV_8169_8110SB    0x10000000
  158 #define RL_HWREV_8169_8110SC    0x18000000
  159 #define RL_HWREV_8102EL         0x24800000
  160 #define RL_HWREV_8168D          0x28000000
  161 #define RL_HWREV_8168_SPIN1     0x30000000
  162 #define RL_HWREV_8100E          0x30800000
  163 #define RL_HWREV_8101E          0x34000000
  164 #define RL_HWREV_8102E          0x34800000
  165 #define RL_HWREV_8168_SPIN2     0x38000000
  166 #define RL_HWREV_8168_SPIN3     0x38400000
  167 #define RL_HWREV_8168C          0x3C000000
  168 #define RL_HWREV_8168C_SPIN2    0x3C400000
  169 #define RL_HWREV_8168CP         0x3C800000
  170 #define RL_HWREV_8139           0x60000000
  171 #define RL_HWREV_8139A          0x70000000
  172 #define RL_HWREV_8139AG         0x70800000
  173 #define RL_HWREV_8139B          0x78000000
  174 #define RL_HWREV_8130           0x7C000000
  175 #define RL_HWREV_8139C          0x74000000
  176 #define RL_HWREV_8139D          0x74400000
  177 #define RL_HWREV_8139CPLUS      0x74800000
  178 #define RL_HWREV_8101           0x74c00000
  179 #define RL_HWREV_8100           0x78800000
  180 #define RL_HWREV_8169_8110SBL   0x7CC00000
  181 
  182 #define RL_TXDMA_16BYTES        0x00000000
  183 #define RL_TXDMA_32BYTES        0x00000100
  184 #define RL_TXDMA_64BYTES        0x00000200
  185 #define RL_TXDMA_128BYTES       0x00000300
  186 #define RL_TXDMA_256BYTES       0x00000400
  187 #define RL_TXDMA_512BYTES       0x00000500
  188 #define RL_TXDMA_1024BYTES      0x00000600
  189 #define RL_TXDMA_2048BYTES      0x00000700
  190 
  191 /*
  192  * Transmit descriptor status register bits.
  193  */
  194 #define RL_TXSTAT_LENMASK       0x00001FFF
  195 #define RL_TXSTAT_OWN           0x00002000
  196 #define RL_TXSTAT_TX_UNDERRUN   0x00004000
  197 #define RL_TXSTAT_TX_OK         0x00008000
  198 #define RL_TXSTAT_EARLY_THRESH  0x003F0000
  199 #define RL_TXSTAT_COLLCNT       0x0F000000
  200 #define RL_TXSTAT_CARR_HBEAT    0x10000000
  201 #define RL_TXSTAT_OUTOFWIN      0x20000000
  202 #define RL_TXSTAT_TXABRT        0x40000000
  203 #define RL_TXSTAT_CARRLOSS      0x80000000
  204 
  205 /*
  206  * Interrupt status register bits.
  207  */
  208 #define RL_ISR_RX_OK            0x0001
  209 #define RL_ISR_RX_ERR           0x0002
  210 #define RL_ISR_TX_OK            0x0004
  211 #define RL_ISR_TX_ERR           0x0008
  212 #define RL_ISR_RX_OVERRUN       0x0010
  213 #define RL_ISR_PKT_UNDERRUN     0x0020
  214 #define RL_ISR_LINKCHG          0x0020  /* 8169 only */
  215 #define RL_ISR_FIFO_OFLOW       0x0040  /* 8139 only */
  216 #define RL_ISR_TX_DESC_UNAVAIL  0x0080  /* C+ only */
  217 #define RL_ISR_SWI              0x0100  /* C+ only */
  218 #define RL_ISR_CABLE_LEN_CHGD   0x2000
  219 #define RL_ISR_PCS_TIMEOUT      0x4000  /* 8129 only */
  220 #define RL_ISR_TIMEOUT_EXPIRED  0x4000
  221 #define RL_ISR_SYSTEM_ERR       0x8000
  222 
  223 #define RL_INTRS        \
  224         (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|         \
  225         RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
  226         RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
  227 
  228 #ifdef RE_TX_MODERATION
  229 #define RL_INTRS_CPLUS  \
  230         (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|                      \
  231         RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
  232         RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
  233 #else
  234 #define RL_INTRS_CPLUS  \
  235         (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK|         \
  236         RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
  237         RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
  238 #endif
  239 
  240 /*
  241  * Media status register. (8139 only)
  242  */
  243 #define RL_MEDIASTAT_RXPAUSE    0x01
  244 #define RL_MEDIASTAT_TXPAUSE    0x02
  245 #define RL_MEDIASTAT_LINK       0x04
  246 #define RL_MEDIASTAT_SPEED10    0x08
  247 #define RL_MEDIASTAT_RXFLOWCTL  0x40    /* duplex mode */
  248 #define RL_MEDIASTAT_TXFLOWCTL  0x80    /* duplex mode */
  249 
  250 /*
  251  * Receive config register.
  252  */
  253 #define RL_RXCFG_RX_ALLPHYS     0x00000001      /* accept all nodes */
  254 #define RL_RXCFG_RX_INDIV       0x00000002      /* match filter */
  255 #define RL_RXCFG_RX_MULTI       0x00000004      /* accept all multicast */
  256 #define RL_RXCFG_RX_BROAD       0x00000008      /* accept all broadcast */
  257 #define RL_RXCFG_RX_RUNT        0x00000010
  258 #define RL_RXCFG_RX_ERRPKT      0x00000020
  259 #define RL_RXCFG_WRAP           0x00000080
  260 #define RL_RXCFG_MAXDMA         0x00000700
  261 #define RL_RXCFG_BUFSZ          0x00001800
  262 #define RL_RXCFG_FIFOTHRESH     0x0000E000
  263 #define RL_RXCFG_EARLYTHRESH    0x07000000
  264 
  265 #define RL_RXDMA_16BYTES        0x00000000
  266 #define RL_RXDMA_32BYTES        0x00000100
  267 #define RL_RXDMA_64BYTES        0x00000200
  268 #define RL_RXDMA_128BYTES       0x00000300
  269 #define RL_RXDMA_256BYTES       0x00000400
  270 #define RL_RXDMA_512BYTES       0x00000500
  271 #define RL_RXDMA_1024BYTES      0x00000600
  272 #define RL_RXDMA_UNLIMITED      0x00000700
  273 
  274 #define RL_RXBUF_8              0x00000000
  275 #define RL_RXBUF_16             0x00000800
  276 #define RL_RXBUF_32             0x00001000
  277 #define RL_RXBUF_64             0x00001800
  278 
  279 #define RL_RXFIFO_16BYTES       0x00000000
  280 #define RL_RXFIFO_32BYTES       0x00002000
  281 #define RL_RXFIFO_64BYTES       0x00004000
  282 #define RL_RXFIFO_128BYTES      0x00006000
  283 #define RL_RXFIFO_256BYTES      0x00008000
  284 #define RL_RXFIFO_512BYTES      0x0000A000
  285 #define RL_RXFIFO_1024BYTES     0x0000C000
  286 #define RL_RXFIFO_NOTHRESH      0x0000E000
  287 
  288 /*
  289  * Bits in RX status header (included with RX'ed packet
  290  * in ring buffer).
  291  */
  292 #define RL_RXSTAT_RXOK          0x00000001
  293 #define RL_RXSTAT_ALIGNERR      0x00000002
  294 #define RL_RXSTAT_CRCERR        0x00000004
  295 #define RL_RXSTAT_GIANT         0x00000008
  296 #define RL_RXSTAT_RUNT          0x00000010
  297 #define RL_RXSTAT_BADSYM        0x00000020
  298 #define RL_RXSTAT_BROAD         0x00002000
  299 #define RL_RXSTAT_INDIV         0x00004000
  300 #define RL_RXSTAT_MULTI         0x00008000
  301 #define RL_RXSTAT_LENMASK       0xFFFF0000
  302 
  303 #define RL_RXSTAT_UNFINISHED    0xFFF0          /* DMA still in progress */
  304 /*
  305  * Command register.
  306  */
  307 #define RL_CMD_EMPTY_RXBUF      0x0001
  308 #define RL_CMD_TX_ENB           0x0004
  309 #define RL_CMD_RX_ENB           0x0008
  310 #define RL_CMD_RESET            0x0010
  311 
  312 /*
  313  * EEPROM control register
  314  */
  315 #define RL_EE_DATAOUT           0x01    /* Data out */
  316 #define RL_EE_DATAIN            0x02    /* Data in */
  317 #define RL_EE_CLK               0x04    /* clock */
  318 #define RL_EE_SEL               0x08    /* chip select */
  319 #define RL_EE_MODE              (0x40|0x80)
  320 
  321 #define RL_EEMODE_OFF           0x00
  322 #define RL_EEMODE_AUTOLOAD      0x40
  323 #define RL_EEMODE_PROGRAM       0x80
  324 #define RL_EEMODE_WRITECFG      (0x80|0x40)
  325 
  326 /* 9346 EEPROM commands */
  327 #define RL_9346_ADDR_LEN        6       /* 93C46 1K: 128x16 */
  328 #define RL_9356_ADDR_LEN        8       /* 93C56 2K: 256x16 */
  329 
  330 #define RL_9346_WRITE          0x5
  331 #define RL_9346_READ           0x6
  332 #define RL_9346_ERASE          0x7
  333 #define RL_9346_EWEN           0x4
  334 #define RL_9346_EWEN_ADDR      0x30
  335 #define RL_9456_EWDS           0x4
  336 #define RL_9346_EWDS_ADDR      0x00
  337 
  338 #define RL_EECMD_WRITE          0x140
  339 #define RL_EECMD_READ_6BIT      0x180
  340 #define RL_EECMD_READ_8BIT      0x600
  341 #define RL_EECMD_ERASE          0x1c0
  342 
  343 #define RL_EE_ID                0x00
  344 #define RL_EE_PCI_VID           0x01
  345 #define RL_EE_PCI_DID           0x02
  346 /* Location of station address inside EEPROM */
  347 #define RL_EE_EADDR             0x07
  348 
  349 /*
  350  * MII register (8129 only)
  351  */
  352 #define RL_MII_CLK              0x01
  353 #define RL_MII_DATAIN           0x02
  354 #define RL_MII_DATAOUT          0x04
  355 #define RL_MII_DIR              0x80    /* 0 == input, 1 == output */
  356 
  357 /*
  358  * Config 0 register
  359  */
  360 #define RL_CFG0_ROM0            0x01
  361 #define RL_CFG0_ROM1            0x02
  362 #define RL_CFG0_ROM2            0x04
  363 #define RL_CFG0_PL0             0x08
  364 #define RL_CFG0_PL1             0x10
  365 #define RL_CFG0_10MBPS          0x20    /* 10 Mbps internal mode */
  366 #define RL_CFG0_PCS             0x40
  367 #define RL_CFG0_SCR             0x80
  368 
  369 /*
  370  * Config 1 register
  371  */
  372 #define RL_CFG1_PWRDWN          0x01
  373 #define RL_CFG1_PME             0x01    
  374 #define RL_CFG1_SLEEP           0x02
  375 #define RL_CFG1_VPDEN           0x02
  376 #define RL_CFG1_IOMAP           0x04
  377 #define RL_CFG1_MEMMAP          0x08
  378 #define RL_CFG1_RSVD            0x10
  379 #define RL_CFG1_LWACT           0x10
  380 #define RL_CFG1_DRVLOAD         0x20
  381 #define RL_CFG1_LED0            0x40
  382 #define RL_CFG1_FULLDUPLEX      0x40    /* 8129 only */
  383 #define RL_CFG1_LED1            0x80
  384 
  385 /*
  386  * Config 2 register
  387  */
  388 #define RL_CFG2_PCI33MHZ        0x00
  389 #define RL_CFG2_PCI66MHZ        0x01
  390 #define RL_CFG2_PCI64BIT        0x08
  391 #define RL_CFG2_AUXPWR          0x10
  392 #define RL_CFG2_MSI             0x20
  393 
  394 /*
  395  * Config 3 register
  396  */
  397 #define RL_CFG3_GRANTSEL        0x80
  398 #define RL_CFG3_WOL_MAGIC       0x20
  399 #define RL_CFG3_WOL_LINK        0x10
  400 #define RL_CFG3_FAST_B2B        0x01
  401 
  402 /*
  403  * Config 4 register
  404  */
  405 #define RL_CFG4_LWPTN           0x04
  406 #define RL_CFG4_LWPME           0x10
  407 
  408 /*
  409  * Config 5 register
  410  */
  411 #define RL_CFG5_WOL_BCAST       0x40
  412 #define RL_CFG5_WOL_MCAST       0x20
  413 #define RL_CFG5_WOL_UCAST       0x10
  414 #define RL_CFG5_WOL_LANWAKE     0x02
  415 #define RL_CFG5_PME_STS         0x01
  416 
  417 /*
  418  * 8139C+ register definitions
  419  */
  420 
  421 /* RL_DUMPSTATS_LO register */
  422 
  423 #define RL_DUMPSTATS_START      0x00000008
  424 
  425 /* Transmit start register */
  426 
  427 #define RL_TXSTART_SWI          0x01    /* generate TX interrupt */
  428 #define RL_TXSTART_START        0x40    /* start normal queue transmit */
  429 #define RL_TXSTART_HPRIO_START  0x80    /* start hi prio queue transmit */
  430 
  431 /*
  432  * Config 2 register, 8139C+/8169/8169S/8110S only
  433  */
  434 #define RL_CFG2_BUSFREQ         0x07
  435 #define RL_CFG2_BUSWIDTH        0x08
  436 #define RL_CFG2_AUXPWRSTS       0x10
  437 
  438 #define RL_BUSFREQ_33MHZ        0x00
  439 #define RL_BUSFREQ_66MHZ        0x01
  440                                         
  441 #define RL_BUSWIDTH_32BITS      0x00
  442 #define RL_BUSWIDTH_64BITS      0x08
  443 
  444 /* C+ mode command register */
  445 
  446 #define RL_CPLUSCMD_TXENB       0x0001  /* enable C+ transmit mode */
  447 #define RL_CPLUSCMD_RXENB       0x0002  /* enable C+ receive mode */
  448 #define RL_CPLUSCMD_PCI_MRW     0x0008  /* enable PCI multi-read/write */
  449 #define RL_CPLUSCMD_PCI_DAC     0x0010  /* PCI dual-address cycle only */
  450 #define RL_CPLUSCMD_RXCSUM_ENB  0x0020  /* enable RX checksum offload */
  451 #define RL_CPLUSCMD_VLANSTRIP   0x0040  /* enable VLAN tag stripping */
  452 #define RL_CPLUSCMD_MACSTAT_DIS 0x0080  /* 8168B/C/CP */
  453 #define RL_CPLUSCMD_ASF         0x0100  /* 8168C/CP */
  454 #define RL_CPLUSCMD_DBG_SEL     0x0200  /* 8168C/CP */
  455 #define RL_CPLUSCMD_FORCE_TXFC  0x0400  /* 8168C/CP */
  456 #define RL_CPLUSCMD_FORCE_RXFC  0x0800  /* 8168C/CP */
  457 #define RL_CPLUSCMD_FORCE_HDPX  0x1000  /* 8168C/CP */
  458 #define RL_CPLUSCMD_NORMAL_MODE 0x2000  /* 8168C/CP */
  459 #define RL_CPLUSCMD_DBG_ENB     0x4000  /* 8168C/CP */
  460 #define RL_CPLUSCMD_BIST_ENB    0x8000  /* 8168C/CP */
  461 
  462 /* C+ early transmit threshold */
  463 
  464 #define RL_EARLYTXTHRESH_CNT    0x003F  /* byte count times 8 */ 
  465 
  466 /*
  467  * Gigabit PHY access register (8169 only)
  468  */
  469 
  470 #define RL_PHYAR_PHYDATA        0x0000FFFF
  471 #define RL_PHYAR_PHYREG         0x001F0000
  472 #define RL_PHYAR_BUSY           0x80000000
  473 
  474 /*
  475  * Gigabit media status (8169 only)
  476  */
  477 #define RL_GMEDIASTAT_FDX       0x01    /* full duplex */
  478 #define RL_GMEDIASTAT_LINK      0x02    /* link up */
  479 #define RL_GMEDIASTAT_10MBPS    0x04    /* 10mps link */
  480 #define RL_GMEDIASTAT_100MBPS   0x08    /* 100mbps link */
  481 #define RL_GMEDIASTAT_1000MBPS  0x10    /* gigE link */
  482 #define RL_GMEDIASTAT_RXFLOW    0x20    /* RX flow control on */
  483 #define RL_GMEDIASTAT_TXFLOW    0x40    /* TX flow control on */
  484 #define RL_GMEDIASTAT_TBI       0x80    /* TBI enabled */
  485 
  486 /*
  487  * The RealTek doesn't use a fragment-based descriptor mechanism.
  488  * Instead, there are only four register sets, each or which represents
  489  * one 'descriptor.' Basically, each TX descriptor is just a contiguous
  490  * packet buffer (32-bit aligned!) and we place the buffer addresses in
  491  * the registers so the chip knows where they are.
  492  *
  493  * We can sort of kludge together the same kind of buffer management
  494  * used in previous drivers, but we have to do buffer copies almost all
  495  * the time, so it doesn't really buy us much.
  496  *
  497  * For reception, there's just one large buffer where the chip stores
  498  * all received packets.
  499  */
  500 
  501 #define RL_RX_BUF_SZ            RL_RXBUF_64
  502 #define RL_RXBUFLEN             (1 << ((RL_RX_BUF_SZ >> 11) + 13))
  503 #define RL_TX_LIST_CNT          4
  504 #define RL_MIN_FRAMELEN         60
  505 #define RL_TXTHRESH(x)          ((x) << 11)
  506 #define RL_TX_THRESH_INIT       96
  507 #define RL_RX_FIFOTHRESH        RL_RXFIFO_NOTHRESH
  508 #define RL_RX_MAXDMA            RL_RXDMA_UNLIMITED
  509 #define RL_TX_MAXDMA            RL_TXDMA_2048BYTES
  510 
  511 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
  512 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
  513 
  514 #define RL_ETHER_ALIGN  2
  515 
  516 /*
  517  * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
  518  */
  519 #define RL_IP4CSUMTX_MINLEN     28
  520 #define RL_IP4CSUMTX_PADLEN     (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
  521 
  522 struct rl_chain_data {
  523         uint16_t                cur_rx;
  524         uint8_t                 *rl_rx_buf;
  525         uint8_t                 *rl_rx_buf_ptr;
  526         bus_dmamap_t            rl_rx_dmamap;
  527 
  528         struct mbuf             *rl_tx_chain[RL_TX_LIST_CNT];
  529         bus_dmamap_t            rl_tx_dmamap[RL_TX_LIST_CNT];
  530         uint8_t                 last_tx;
  531         uint8_t                 cur_tx;
  532 };
  533 
  534 #define RL_INC(x)               (x = (x + 1) % RL_TX_LIST_CNT)
  535 #define RL_CUR_TXADDR(x)        ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
  536 #define RL_CUR_TXSTAT(x)        ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
  537 #define RL_CUR_TXMBUF(x)        (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
  538 #define RL_CUR_DMAMAP(x)        (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
  539 #define RL_LAST_TXADDR(x)       ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
  540 #define RL_LAST_TXSTAT(x)       ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
  541 #define RL_LAST_TXMBUF(x)       (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
  542 #define RL_LAST_DMAMAP(x)       (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
  543 
  544 struct rl_type {
  545         uint16_t                rl_vid;
  546         uint16_t                rl_did;
  547         int                     rl_basetype;
  548         char                    *rl_name;
  549 };
  550 
  551 struct rl_hwrev {
  552         uint32_t                rl_rev;
  553         int                     rl_type;
  554         char                    *rl_desc;
  555 };
  556 
  557 struct rl_mii_frame {
  558         uint8_t         mii_stdelim;
  559         uint8_t         mii_opcode;
  560         uint8_t         mii_phyaddr;
  561         uint8_t         mii_regaddr;
  562         uint8_t         mii_turnaround;
  563         uint16_t        mii_data;
  564 };
  565 
  566 /*
  567  * MII constants
  568  */
  569 #define RL_MII_STARTDELIM       0x01
  570 #define RL_MII_READOP           0x02
  571 #define RL_MII_WRITEOP          0x01
  572 #define RL_MII_TURNAROUND       0x02
  573 
  574 #define RL_8129                 1
  575 #define RL_8139                 2
  576 #define RL_8139CPLUS            3
  577 #define RL_8169                 4
  578 
  579 #define RL_ISCPLUS(x)           ((x)->rl_type == RL_8139CPLUS ||        \
  580                                  (x)->rl_type == RL_8169)
  581 
  582 /*
  583  * The 8139C+ and 8160 gigE chips support descriptor-based TX
  584  * and RX. In fact, they even support TCP large send. Descriptors
  585  * must be allocated in contiguous blocks that are aligned on a
  586  * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
  587  */
  588 
  589 /*
  590  * RX/TX descriptor definition. When large send mode is enabled, the
  591  * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
  592  * the checksum offload bits are disabled. The structure layout is
  593  * the same for RX and TX descriptors
  594  */
  595 
  596 struct rl_desc {
  597         uint32_t                rl_cmdstat;
  598         uint32_t                rl_vlanctl;
  599         uint32_t                rl_bufaddr_lo;
  600         uint32_t                rl_bufaddr_hi;
  601 };
  602 
  603 #define RL_TDESC_CMD_FRAGLEN    0x0000FFFF
  604 #define RL_TDESC_CMD_TCPCSUM    0x00010000      /* TCP checksum enable */
  605 #define RL_TDESC_CMD_UDPCSUM    0x00020000      /* UDP checksum enable */
  606 #define RL_TDESC_CMD_IPCSUM     0x00040000      /* IP header checksum enable */
  607 #define RL_TDESC_CMD_MSSVAL     0x07FF0000      /* Large send MSS value */
  608 #define RL_TDESC_CMD_MSSVAL_SHIFT       16      /* Large send MSS value shift */
  609 #define RL_TDESC_CMD_LGSEND     0x08000000      /* TCP large send enb */
  610 #define RL_TDESC_CMD_EOF        0x10000000      /* end of frame marker */
  611 #define RL_TDESC_CMD_SOF        0x20000000      /* start of frame marker */
  612 #define RL_TDESC_CMD_EOR        0x40000000      /* end of ring marker */
  613 #define RL_TDESC_CMD_OWN        0x80000000      /* chip owns descriptor */
  614 
  615 #define RL_TDESC_VLANCTL_TAG    0x00020000      /* Insert VLAN tag */
  616 #define RL_TDESC_VLANCTL_DATA   0x0000FFFF      /* TAG data */
  617 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
  618 #define RL_TDESC_CMD_UDPCSUMV2  0x80000000
  619 #define RL_TDESC_CMD_TCPCSUMV2  0x40000000      
  620 #define RL_TDESC_CMD_IPCSUMV2   0x20000000      
  621 
  622 /*
  623  * Error bits are valid only on the last descriptor of a frame
  624  * (i.e. RL_TDESC_CMD_EOF == 1)
  625  */
  626 
  627 #define RL_TDESC_STAT_COLCNT    0x000F0000      /* collision count */
  628 #define RL_TDESC_STAT_EXCESSCOL 0x00100000      /* excessive collisions */
  629 #define RL_TDESC_STAT_LINKFAIL  0x00200000      /* link faulure */
  630 #define RL_TDESC_STAT_OWINCOL   0x00400000      /* out-of-window collision */
  631 #define RL_TDESC_STAT_TXERRSUM  0x00800000      /* transmit error summary */
  632 #define RL_TDESC_STAT_UNDERRUN  0x02000000      /* TX underrun occured */
  633 #define RL_TDESC_STAT_OWN       0x80000000
  634 
  635 /*
  636  * RX descriptor cmd/vlan definitions
  637  */
  638 
  639 #define RL_RDESC_CMD_EOR        0x40000000
  640 #define RL_RDESC_CMD_OWN        0x80000000
  641 #define RL_RDESC_CMD_BUFLEN     0x00001FFF
  642 
  643 #define RL_RDESC_STAT_OWN       0x80000000
  644 #define RL_RDESC_STAT_EOR       0x40000000
  645 #define RL_RDESC_STAT_SOF       0x20000000
  646 #define RL_RDESC_STAT_EOF       0x10000000
  647 #define RL_RDESC_STAT_FRALIGN   0x08000000      /* frame alignment error */
  648 #define RL_RDESC_STAT_MCAST     0x04000000      /* multicast pkt received */
  649 #define RL_RDESC_STAT_UCAST     0x02000000      /* unicast pkt received */
  650 #define RL_RDESC_STAT_BCAST     0x01000000      /* broadcast pkt received */
  651 #define RL_RDESC_STAT_BUFOFLOW  0x00800000      /* out of buffer space */
  652 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000      /* FIFO overrun */
  653 #define RL_RDESC_STAT_GIANT     0x00200000      /* pkt > 4096 bytes */
  654 #define RL_RDESC_STAT_RXERRSUM  0x00100000      /* RX error summary */
  655 #define RL_RDESC_STAT_RUNT      0x00080000      /* runt packet received */
  656 #define RL_RDESC_STAT_CRCERR    0x00040000      /* CRC error */
  657 #define RL_RDESC_STAT_PROTOID   0x00030000      /* Protocol type */
  658 #define RL_RDESC_STAT_UDP       0x00020000      /* UDP, 8168C/CP, 8111C/CP */
  659 #define RL_RDESC_STAT_TCP       0x00010000      /* TCP, 8168C/CP, 8111C/CP */
  660 #define RL_RDESC_STAT_IPSUMBAD  0x00008000      /* IP header checksum bad */
  661 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000      /* UDP checksum bad */
  662 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000      /* TCP checksum bad */
  663 #define RL_RDESC_STAT_FRAGLEN   0x00001FFF      /* RX'ed frame/frag len */
  664 #define RL_RDESC_STAT_GFRAGLEN  0x00003FFF      /* RX'ed frame/frag len */
  665 #define RL_RDESC_STAT_ERRS      (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
  666                                  RL_RDESC_STAT_CRCERR)
  667 
  668 #define RL_RDESC_VLANCTL_TAG    0x00010000      /* VLAN tag available
  669                                                    (rl_vlandata valid)*/
  670 #define RL_RDESC_VLANCTL_DATA   0x0000FFFF      /* TAG data */
  671 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
  672 #define RL_RDESC_IPV6           0x80000000
  673 #define RL_RDESC_IPV4           0x40000000
  674 
  675 #define RL_PROTOID_NONIP        0x00000000
  676 #define RL_PROTOID_TCPIP        0x00010000
  677 #define RL_PROTOID_UDPIP        0x00020000
  678 #define RL_PROTOID_IP           0x00030000
  679 #define RL_TCPPKT(x)            (((x) & RL_RDESC_STAT_PROTOID) == \
  680                                  RL_PROTOID_TCPIP)
  681 #define RL_UDPPKT(x)            (((x) & RL_RDESC_STAT_PROTOID) == \
  682                                  RL_PROTOID_UDPIP)
  683 
  684 /*
  685  * Statistics counter structure (8139C+ and 8169 only)
  686  */
  687 struct rl_stats {
  688         uint32_t                rl_tx_pkts_lo;
  689         uint32_t                rl_tx_pkts_hi;
  690         uint32_t                rl_tx_errs_lo;
  691         uint32_t                rl_tx_errs_hi;
  692         uint32_t                rl_tx_errs;
  693         uint16_t                rl_missed_pkts;
  694         uint16_t                rl_rx_framealign_errs;
  695         uint32_t                rl_tx_onecoll;
  696         uint32_t                rl_tx_multicolls;
  697         uint32_t                rl_rx_ucasts_hi;
  698         uint32_t                rl_rx_ucasts_lo;
  699         uint32_t                rl_rx_bcasts_lo;
  700         uint32_t                rl_rx_bcasts_hi;
  701         uint32_t                rl_rx_mcasts;
  702         uint16_t                rl_tx_aborts;
  703         uint16_t                rl_rx_underruns;
  704 };
  705 
  706 /*
  707  * Rx/Tx descriptor parameters (8139C+ and 8169 only)
  708  *
  709  * 8139C+
  710  *  Number of descriptors supported : up to 64
  711  *  Descriptor alignment : 256 bytes
  712  *  Tx buffer : At least 4 bytes in length.
  713  *  Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
  714  *  
  715  * 8169
  716  *  Number of descriptors supported : up to 1024
  717  *  Descriptor alignment : 256 bytes
  718  *  Tx buffer : At least 4 bytes in length.
  719  *  Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
  720  */
  721 #ifndef __NO_STRICT_ALIGNMENT
  722 #define RE_FIXUP_RX     1
  723 #endif
  724 
  725 #define RL_8169_TX_DESC_CNT     256
  726 #define RL_8169_RX_DESC_CNT     256
  727 #define RL_8139_TX_DESC_CNT     64
  728 #define RL_8139_RX_DESC_CNT     64
  729 #define RL_TX_DESC_CNT          RL_8169_TX_DESC_CNT
  730 #define RL_RX_DESC_CNT          RL_8169_RX_DESC_CNT
  731 #define RL_NTXSEGS              32
  732 
  733 #define RL_RING_ALIGN           256
  734 #define RL_IFQ_MAXLEN           512
  735 #define RL_TX_DESC_NXT(sc,x)    ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
  736 #define RL_TX_DESC_PRV(sc,x)    ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
  737 #define RL_RX_DESC_NXT(sc,x)    ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
  738 #define RL_OWN(x)               (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
  739 #define RL_RXBYTES(x)           (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
  740 #define RL_PKTSZ(x)             ((x)/* >> 3*/)
  741 #ifdef RE_FIXUP_RX
  742 #define RE_ETHER_ALIGN  sizeof(uint64_t)
  743 #define RE_RX_DESC_BUFLEN       (MCLBYTES - RE_ETHER_ALIGN)
  744 #else
  745 #define RE_ETHER_ALIGN  0
  746 #define RE_RX_DESC_BUFLEN       MCLBYTES
  747 #endif
  748 
  749 #define RL_MSI_MESSAGES 2
  750 
  751 #define RL_ADDR_LO(y)           ((uint64_t) (y) & 0xFFFFFFFF)
  752 #define RL_ADDR_HI(y)           ((uint64_t) (y) >> 32)
  753 
  754 /*
  755  * The number of bits reserved for MSS in RealTek controllers is
  756  * 11bits. This limits the maximum interface MTU size in TSO case
  757  * as upper stack should not generate TCP segments with MSS greater
  758  * than the limit.
  759  */
  760 #define RL_TSO_MTU              (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
  761 
  762 /* see comment in dev/re/if_re.c */
  763 #define RL_JUMBO_FRAMELEN       7440
  764 #define RL_JUMBO_MTU            (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
  765 #define RL_MAX_FRAMELEN         \
  766         (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
  767 
  768 struct rl_txdesc {
  769         struct mbuf             *tx_m;
  770         bus_dmamap_t            tx_dmamap;
  771 };
  772 
  773 struct rl_rxdesc {
  774         struct mbuf             *rx_m;
  775         bus_dmamap_t            rx_dmamap;
  776         bus_size_t              rx_size;
  777 };
  778 
  779 struct rl_list_data {
  780         struct rl_txdesc        rl_tx_desc[RL_TX_DESC_CNT];
  781         struct rl_rxdesc        rl_rx_desc[RL_RX_DESC_CNT];
  782         int                     rl_tx_desc_cnt;
  783         int                     rl_rx_desc_cnt;
  784         int                     rl_tx_prodidx;
  785         int                     rl_rx_prodidx;
  786         int                     rl_tx_considx;
  787         int                     rl_tx_free;
  788         bus_dma_tag_t           rl_tx_mtag;     /* mbuf TX mapping tag */
  789         bus_dma_tag_t           rl_rx_mtag;     /* mbuf RX mapping tag */
  790         bus_dmamap_t            rl_rx_sparemap;
  791         bus_dma_tag_t           rl_stag;        /* stats mapping tag */
  792         bus_dmamap_t            rl_smap;        /* stats map */
  793         struct rl_stats         *rl_stats;
  794         bus_addr_t              rl_stats_addr;
  795         bus_dma_tag_t           rl_rx_list_tag;
  796         bus_dmamap_t            rl_rx_list_map;
  797         struct rl_desc          *rl_rx_list;
  798         bus_addr_t              rl_rx_list_addr;
  799         bus_dma_tag_t           rl_tx_list_tag;
  800         bus_dmamap_t            rl_tx_list_map;
  801         struct rl_desc          *rl_tx_list;
  802         bus_addr_t              rl_tx_list_addr;
  803 };
  804 
  805 struct rl_softc {
  806         struct ifnet            *rl_ifp;        /* interface info */
  807         bus_space_handle_t      rl_bhandle;     /* bus space handle */
  808         bus_space_tag_t         rl_btag;        /* bus space tag */
  809         device_t                rl_dev;
  810         struct resource         *rl_res;
  811         int                     rl_res_id;
  812         int                     rl_res_type;
  813         struct resource         *rl_irq[RL_MSI_MESSAGES];
  814         void                    *rl_intrhand[RL_MSI_MESSAGES];
  815         device_t                rl_miibus;
  816         bus_dma_tag_t           rl_parent_tag;
  817         bus_dma_tag_t           rl_tag;
  818         uint8_t                 rl_type;
  819         int                     rl_eecmd_read;
  820         int                     rl_eewidth;
  821         uint8_t                 rl_stats_no_timeout;
  822         int                     rl_txthresh;
  823         struct rl_chain_data    rl_cdata;
  824         struct rl_list_data     rl_ldata;
  825         struct callout          rl_stat_callout;
  826         int                     rl_watchdog_timer;
  827         struct mtx              rl_mtx;
  828         struct mbuf             *rl_head;
  829         struct mbuf             *rl_tail;
  830         uint32_t                rl_hwrev;
  831         uint32_t                rl_rxlenmask;
  832         int                     rl_testmode;
  833         int                     rl_if_flags;
  834         int                     suspended;      /* 0 = normal  1 = suspended */
  835 #ifdef DEVICE_POLLING
  836         int                     rxcycles;
  837 #endif
  838 
  839         struct task             rl_txtask;
  840         struct task             rl_inttask;
  841 
  842         int                     rl_txstart;
  843         uint32_t                rl_flags;
  844 #define RL_FLAG_MSI             0x0001
  845 #define RL_FLAG_INVMAR          0x0004
  846 #define RL_FLAG_PHYWAKE         0x0008
  847 #define RL_FLAG_NOJUMBO         0x0010
  848 #define RL_FLAG_PAR             0x0020
  849 #define RL_FLAG_DESCV2          0x0040
  850 #define RL_FLAG_MACSTAT         0x0080
  851 #define RL_FLAG_LINK            0x8000
  852 };
  853 
  854 #define RL_LOCK(_sc)            mtx_lock(&(_sc)->rl_mtx)
  855 #define RL_UNLOCK(_sc)          mtx_unlock(&(_sc)->rl_mtx)
  856 #define RL_LOCK_ASSERT(_sc)     mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
  857 
  858 /*
  859  * register space access macros
  860  */
  861 #define CSR_WRITE_STREAM_4(sc, reg, val)        \
  862         bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
  863 #define CSR_WRITE_4(sc, reg, val)       \
  864         bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
  865 #define CSR_WRITE_2(sc, reg, val)       \
  866         bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
  867 #define CSR_WRITE_1(sc, reg, val)       \
  868         bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
  869 
  870 #define CSR_READ_4(sc, reg)             \
  871         bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
  872 #define CSR_READ_2(sc, reg)             \
  873         bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
  874 #define CSR_READ_1(sc, reg)             \
  875         bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
  876 
  877 #define CSR_SETBIT_1(sc, offset, val)           \
  878         CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
  879 
  880 #define CSR_CLRBIT_1(sc, offset, val)           \
  881         CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
  882 
  883 #define CSR_SETBIT_2(sc, offset, val)           \
  884         CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
  885 
  886 #define CSR_CLRBIT_2(sc, offset, val)           \
  887         CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
  888 
  889 #define CSR_SETBIT_4(sc, offset, val)           \
  890         CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
  891 
  892 #define CSR_CLRBIT_4(sc, offset, val)           \
  893         CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
  894 
  895 #define RL_TIMEOUT              1000
  896 
  897 /*
  898  * General constants that are fun to know.
  899  *
  900  * RealTek PCI vendor ID
  901  */
  902 #define RT_VENDORID                             0x10EC
  903 
  904 /*
  905  * RealTek chip device IDs.
  906  */
  907 #define RT_DEVICEID_8139D                       0x8039
  908 #define RT_DEVICEID_8129                        0x8129
  909 #define RT_DEVICEID_8101E                       0x8136
  910 #define RT_DEVICEID_8138                        0x8138
  911 #define RT_DEVICEID_8139                        0x8139
  912 #define RT_DEVICEID_8169SC                      0x8167
  913 #define RT_DEVICEID_8168                        0x8168
  914 #define RT_DEVICEID_8169                        0x8169
  915 #define RT_DEVICEID_8100                        0x8100
  916 
  917 #define RT_REVID_8139CPLUS                      0x20
  918 
  919 /*
  920  * Accton PCI vendor ID
  921  */
  922 #define ACCTON_VENDORID                         0x1113
  923 
  924 /*
  925  * Accton MPX 5030/5038 device ID.
  926  */
  927 #define ACCTON_DEVICEID_5030                    0x1211
  928 
  929 /*
  930  * Nortel PCI vendor ID
  931  */
  932 #define NORTEL_VENDORID                         0x126C
  933 
  934 /*
  935  * Delta Electronics Vendor ID.
  936  */
  937 #define DELTA_VENDORID                          0x1500
  938 
  939 /*
  940  * Delta device IDs.
  941  */
  942 #define DELTA_DEVICEID_8139                     0x1360
  943 
  944 /*
  945  * Addtron vendor ID.
  946  */
  947 #define ADDTRON_VENDORID                        0x4033
  948 
  949 /*
  950  * Addtron device IDs.
  951  */
  952 #define ADDTRON_DEVICEID_8139                   0x1360
  953 
  954 /*
  955  * D-Link vendor ID.
  956  */
  957 #define DLINK_VENDORID                          0x1186
  958 
  959 /*
  960  * D-Link DFE-530TX+ device ID
  961  */
  962 #define DLINK_DEVICEID_530TXPLUS                0x1300
  963 
  964 /*
  965  * D-Link DFE-5280T device ID
  966  */
  967 #define DLINK_DEVICEID_528T                     0x4300
  968 
  969 /*
  970  * D-Link DFE-690TXD device ID
  971  */
  972 #define DLINK_DEVICEID_690TXD                   0x1340
  973 
  974 /*
  975  * Corega K.K vendor ID
  976  */
  977 #define COREGA_VENDORID                         0x1259
  978 
  979 /*
  980  * Corega FEther CB-TXD device ID
  981  */
  982 #define COREGA_DEVICEID_FETHERCBTXD             0xa117
  983 
  984 /*
  985  * Corega FEtherII CB-TXD device ID
  986  */
  987 #define COREGA_DEVICEID_FETHERIICBTXD           0xa11e
  988 
  989 /*
  990  * Corega CG-LAPCIGT device ID
  991  */
  992 #define COREGA_DEVICEID_CGLAPCIGT               0xc107
  993 
  994 /*
  995  * Linksys vendor ID
  996  */
  997 #define LINKSYS_VENDORID                        0x1737
  998 
  999 /*
 1000  * Linksys EG1032 device ID
 1001  */
 1002 #define LINKSYS_DEVICEID_EG1032                 0x1032
 1003 
 1004 /*
 1005  * Linksys EG1032 rev 3 sub-device ID
 1006  */
 1007 #define LINKSYS_SUBDEVICE_EG1032_REV3           0x0024
 1008 
 1009 /*
 1010  * Peppercon vendor ID
 1011  */
 1012 #define PEPPERCON_VENDORID                      0x1743
 1013 
 1014 /*
 1015  * Peppercon ROL-F device ID
 1016  */
 1017 #define PEPPERCON_DEVICEID_ROLF                 0x8139
 1018 
 1019 /*
 1020  * Planex Communications, Inc. vendor ID
 1021  */
 1022 #define PLANEX_VENDORID                         0x14ea
 1023 
 1024 /*
 1025  * Planex FNW-3603-TX device ID
 1026  */
 1027 #define PLANEX_DEVICEID_FNW3603TX               0xab06
 1028 
 1029 /*
 1030  * Planex FNW-3800-TX device ID
 1031  */
 1032 #define PLANEX_DEVICEID_FNW3800TX               0xab07
 1033 
 1034 /*
 1035  * LevelOne vendor ID
 1036  */
 1037 #define LEVEL1_VENDORID                         0x018A
 1038 
 1039 /*
 1040  * LevelOne FPC-0106TX devide ID
 1041  */
 1042 #define LEVEL1_DEVICEID_FPC0106TX               0x0106
 1043 
 1044 /*
 1045  * Compaq vendor ID
 1046  */
 1047 #define CP_VENDORID                             0x021B
 1048 
 1049 /*
 1050  * Edimax vendor ID
 1051  */
 1052 #define EDIMAX_VENDORID                         0x13D1
 1053 
 1054 /*
 1055  * Edimax EP-4103DL cardbus device ID
 1056  */
 1057 #define EDIMAX_DEVICEID_EP4103DL                0xAB06
 1058 
 1059 /* US Robotics vendor ID */
 1060 
 1061 #define USR_VENDORID            0x16EC
 1062 
 1063 /* US Robotics 997902 device ID */
 1064 
 1065 #define USR_DEVICEID_997902     0x0116
 1066 
 1067 /*
 1068  * PCI low memory base and low I/O base register, and
 1069  * other PCI registers.
 1070  */
 1071 
 1072 #define RL_PCI_VENDOR_ID        0x00
 1073 #define RL_PCI_DEVICE_ID        0x02
 1074 #define RL_PCI_COMMAND          0x04
 1075 #define RL_PCI_STATUS           0x06
 1076 #define RL_PCI_CLASSCODE        0x09
 1077 #define RL_PCI_LATENCY_TIMER    0x0D
 1078 #define RL_PCI_HEADER_TYPE      0x0E
 1079 #define RL_PCI_LOIO             0x10
 1080 #define RL_PCI_LOMEM            0x14
 1081 #define RL_PCI_BIOSROM          0x30
 1082 #define RL_PCI_INTLINE          0x3C
 1083 #define RL_PCI_INTPIN           0x3D
 1084 #define RL_PCI_MINGNT           0x3E
 1085 #define RL_PCI_MINLAT           0x0F
 1086 #define RL_PCI_RESETOPT         0x48
 1087 #define RL_PCI_EEPROM_DATA      0x4C
 1088 
 1089 #define RL_PCI_CAPID            0x50 /* 8 bits */
 1090 #define RL_PCI_NEXTPTR          0x51 /* 8 bits */
 1091 #define RL_PCI_PWRMGMTCAP       0x52 /* 16 bits */
 1092 #define RL_PCI_PWRMGMTCTRL      0x54 /* 16 bits */
 1093 
 1094 #define RL_PSTATE_MASK          0x0003
 1095 #define RL_PSTATE_D0            0x0000
 1096 #define RL_PSTATE_D1            0x0002
 1097 #define RL_PSTATE_D2            0x0002
 1098 #define RL_PSTATE_D3            0x0003
 1099 #define RL_PME_EN               0x0010
 1100 #define RL_PME_STATUS           0x8000

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