The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rlreg.h

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    1 /*-
    2  * Copyright (c) 1997, 1998-2003
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/8.1/sys/pci/if_rlreg.h 206579 2010-04-14 01:22:33Z yongari $
   33  */
   34 
   35 /*
   36  * RealTek 8129/8139 register offsets
   37  */
   38 #define RL_IDR0         0x0000          /* ID register 0 (station addr) */
   39 #define RL_IDR1         0x0001          /* Must use 32-bit accesses (?) */
   40 #define RL_IDR2         0x0002
   41 #define RL_IDR3         0x0003
   42 #define RL_IDR4         0x0004
   43 #define RL_IDR5         0x0005
   44                                         /* 0006-0007 reserved */
   45 #define RL_MAR0         0x0008          /* Multicast hash table */
   46 #define RL_MAR1         0x0009
   47 #define RL_MAR2         0x000A
   48 #define RL_MAR3         0x000B
   49 #define RL_MAR4         0x000C
   50 #define RL_MAR5         0x000D
   51 #define RL_MAR6         0x000E
   52 #define RL_MAR7         0x000F
   53 
   54 #define RL_TXSTAT0      0x0010          /* status of TX descriptor 0 */
   55 #define RL_TXSTAT1      0x0014          /* status of TX descriptor 1 */
   56 #define RL_TXSTAT2      0x0018          /* status of TX descriptor 2 */
   57 #define RL_TXSTAT3      0x001C          /* status of TX descriptor 3 */
   58 
   59 #define RL_TXADDR0      0x0020          /* address of TX descriptor 0 */
   60 #define RL_TXADDR1      0x0024          /* address of TX descriptor 1 */
   61 #define RL_TXADDR2      0x0028          /* address of TX descriptor 2 */
   62 #define RL_TXADDR3      0x002C          /* address of TX descriptor 3 */
   63 
   64 #define RL_RXADDR               0x0030  /* RX ring start address */
   65 #define RL_RX_EARLY_BYTES       0x0034  /* RX early byte count */
   66 #define RL_RX_EARLY_STAT        0x0036  /* RX early status */
   67 #define RL_COMMAND      0x0037          /* command register */
   68 #define RL_CURRXADDR    0x0038          /* current address of packet read */
   69 #define RL_CURRXBUF     0x003A          /* current RX buffer address */
   70 #define RL_IMR          0x003C          /* interrupt mask register */
   71 #define RL_ISR          0x003E          /* interrupt status register */
   72 #define RL_TXCFG        0x0040          /* transmit config */
   73 #define RL_RXCFG        0x0044          /* receive config */
   74 #define RL_TIMERCNT     0x0048          /* timer count register */
   75 #define RL_MISSEDPKT    0x004C          /* missed packet counter */
   76 #define RL_EECMD        0x0050          /* EEPROM command register */
   77 #define RL_CFG0         0x0051          /* config register #0 */
   78 #define RL_CFG1         0x0052          /* config register #1 */
   79 #define RL_CFG2         0x0053          /* config register #2 */
   80 #define RL_CFG3         0x0054          /* config register #3 */
   81 #define RL_CFG4         0x0055          /* config register #4 */
   82 #define RL_CFG5         0x0056          /* config register #5 */
   83                                         /* 0057 reserved */
   84 #define RL_MEDIASTAT    0x0058          /* media status register (8139) */
   85                                         /* 0059-005A reserved */
   86 #define RL_MII          0x005A          /* 8129 chip only */
   87 #define RL_HALTCLK      0x005B
   88 #define RL_MULTIINTR    0x005C          /* multiple interrupt */
   89 #define RL_PCIREV       0x005E          /* PCI revision value */
   90                                         /* 005F reserved */
   91 #define RL_TXSTAT_ALL   0x0060          /* TX status of all descriptors */
   92 
   93 /* Direct PHY access registers only available on 8139 */
   94 #define RL_BMCR         0x0062          /* PHY basic mode control */
   95 #define RL_BMSR         0x0064          /* PHY basic mode status */
   96 #define RL_ANAR         0x0066          /* PHY autoneg advert */
   97 #define RL_LPAR         0x0068          /* PHY link partner ability */
   98 #define RL_ANER         0x006A          /* PHY autoneg expansion */
   99 
  100 #define RL_DISCCNT      0x006C          /* disconnect counter */
  101 #define RL_FALSECAR     0x006E          /* false carrier counter */
  102 #define RL_NWAYTST      0x0070          /* NWAY test register */
  103 #define RL_RX_ER        0x0072          /* RX_ER counter */
  104 #define RL_CSCFG        0x0074          /* CS configuration register */
  105 
  106 /*
  107  * When operating in special C+ mode, some of the registers in an
  108  * 8139C+ chip have different definitions. These are also used for
  109  * the 8169 gigE chip.
  110  */
  111 #define RL_DUMPSTATS_LO         0x0010  /* counter dump command register */
  112 #define RL_DUMPSTATS_HI         0x0014  /* counter dump command register */
  113 #define RL_TXLIST_ADDR_LO       0x0020  /* 64 bits, 256 byte alignment */
  114 #define RL_TXLIST_ADDR_HI       0x0024  /* 64 bits, 256 byte alignment */
  115 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028  /* 64 bits, 256 byte alignment */
  116 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C  /* 64 bits, 256 byte alignment */
  117 #define RL_CFG2                 0x0053
  118 #define RL_TIMERINT             0x0054  /* interrupt on timer expire */
  119 #define RL_TXSTART              0x00D9  /* 8 bits */
  120 #define RL_CPLUS_CMD            0x00E0  /* 16 bits */
  121 #define RL_RXLIST_ADDR_LO       0x00E4  /* 64 bits, 256 byte alignment */
  122 #define RL_RXLIST_ADDR_HI       0x00E8  /* 64 bits, 256 byte alignment */
  123 #define RL_EARLY_TX_THRESH      0x00EC  /* 8 bits */
  124 
  125 /*
  126  * Registers specific to the 8169 gigE chip
  127  */
  128 #define RL_TIMERINT_8169        0x0058  /* different offset than 8139 */
  129 #define RL_PHYAR                0x0060
  130 #define RL_TBICSR               0x0064
  131 #define RL_TBI_ANAR             0x0068
  132 #define RL_TBI_LPAR             0x006A
  133 #define RL_GMEDIASTAT           0x006C  /* 8 bits */
  134 #define RL_MACDBG               0x006D  /* 8 bits, 8168C SPIN2 only */
  135 #define RL_GPIO                 0x006E  /* 8 bits, 8168C SPIN2 only */
  136 #define RL_PMCH                 0x006F  /* 8 bits */
  137 #define RL_MAXRXPKTLEN          0x00DA  /* 16 bits, chip multiplies by 8 */
  138 #define RL_GTXSTART             0x0038  /* 8 bits */
  139 
  140 /*
  141  * TX config register bits
  142  */
  143 #define RL_TXCFG_CLRABRT        0x00000001      /* retransmit aborted pkt */
  144 #define RL_TXCFG_MAXDMA         0x00000700      /* max DMA burst size */
  145 #define RL_TXCFG_CRCAPPEND      0x00010000      /* CRC append (0 = yes) */
  146 #define RL_TXCFG_LOOPBKTST      0x00060000      /* loopback test */
  147 #define RL_TXCFG_IFG2           0x00080000      /* 8169 only */
  148 #define RL_TXCFG_IFG            0x03000000      /* interframe gap */
  149 #define RL_TXCFG_HWREV          0x7CC00000
  150 
  151 #define RL_LOOPTEST_OFF         0x00000000
  152 #define RL_LOOPTEST_ON          0x00020000
  153 #define RL_LOOPTEST_ON_CPLUS    0x00060000
  154 
  155 /* Known revision codes. */
  156 
  157 #define RL_HWREV_8169           0x00000000
  158 #define RL_HWREV_8169S          0x00800000
  159 #define RL_HWREV_8110S          0x04000000
  160 #define RL_HWREV_8169_8110SB    0x10000000
  161 #define RL_HWREV_8169_8110SC    0x18000000
  162 #define RL_HWREV_8102EL         0x24800000
  163 #define RL_HWREV_8102EL_SPIN1   0x24C00000
  164 #define RL_HWREV_8168D          0x28000000
  165 #define RL_HWREV_8168DP         0x28800000
  166 #define RL_HWREV_8168E          0x2C000000
  167 #define RL_HWREV_8168_SPIN1     0x30000000
  168 #define RL_HWREV_8100E          0x30800000
  169 #define RL_HWREV_8101E          0x34000000
  170 #define RL_HWREV_8102E          0x34800000
  171 #define RL_HWREV_8103E          0x34C00000
  172 #define RL_HWREV_8168_SPIN2     0x38000000
  173 #define RL_HWREV_8168_SPIN3     0x38400000
  174 #define RL_HWREV_8168C          0x3C000000
  175 #define RL_HWREV_8168C_SPIN2    0x3C400000
  176 #define RL_HWREV_8168CP         0x3C800000
  177 #define RL_HWREV_8139           0x60000000
  178 #define RL_HWREV_8139A          0x70000000
  179 #define RL_HWREV_8139AG         0x70800000
  180 #define RL_HWREV_8139B          0x78000000
  181 #define RL_HWREV_8130           0x7C000000
  182 #define RL_HWREV_8139C          0x74000000
  183 #define RL_HWREV_8139D          0x74400000
  184 #define RL_HWREV_8139CPLUS      0x74800000
  185 #define RL_HWREV_8101           0x74C00000
  186 #define RL_HWREV_8100           0x78800000
  187 #define RL_HWREV_8169_8110SBL   0x7CC00000
  188 #define RL_HWREV_8169_8110SCE   0x98000000
  189 
  190 #define RL_TXDMA_16BYTES        0x00000000
  191 #define RL_TXDMA_32BYTES        0x00000100
  192 #define RL_TXDMA_64BYTES        0x00000200
  193 #define RL_TXDMA_128BYTES       0x00000300
  194 #define RL_TXDMA_256BYTES       0x00000400
  195 #define RL_TXDMA_512BYTES       0x00000500
  196 #define RL_TXDMA_1024BYTES      0x00000600
  197 #define RL_TXDMA_2048BYTES      0x00000700
  198 
  199 /*
  200  * Transmit descriptor status register bits.
  201  */
  202 #define RL_TXSTAT_LENMASK       0x00001FFF
  203 #define RL_TXSTAT_OWN           0x00002000
  204 #define RL_TXSTAT_TX_UNDERRUN   0x00004000
  205 #define RL_TXSTAT_TX_OK         0x00008000
  206 #define RL_TXSTAT_EARLY_THRESH  0x003F0000
  207 #define RL_TXSTAT_COLLCNT       0x0F000000
  208 #define RL_TXSTAT_CARR_HBEAT    0x10000000
  209 #define RL_TXSTAT_OUTOFWIN      0x20000000
  210 #define RL_TXSTAT_TXABRT        0x40000000
  211 #define RL_TXSTAT_CARRLOSS      0x80000000
  212 
  213 /*
  214  * Interrupt status register bits.
  215  */
  216 #define RL_ISR_RX_OK            0x0001
  217 #define RL_ISR_RX_ERR           0x0002
  218 #define RL_ISR_TX_OK            0x0004
  219 #define RL_ISR_TX_ERR           0x0008
  220 #define RL_ISR_RX_OVERRUN       0x0010
  221 #define RL_ISR_PKT_UNDERRUN     0x0020
  222 #define RL_ISR_LINKCHG          0x0020  /* 8169 only */
  223 #define RL_ISR_FIFO_OFLOW       0x0040  /* 8139 only */
  224 #define RL_ISR_TX_DESC_UNAVAIL  0x0080  /* C+ only */
  225 #define RL_ISR_SWI              0x0100  /* C+ only */
  226 #define RL_ISR_CABLE_LEN_CHGD   0x2000
  227 #define RL_ISR_PCS_TIMEOUT      0x4000  /* 8129 only */
  228 #define RL_ISR_TIMEOUT_EXPIRED  0x4000
  229 #define RL_ISR_SYSTEM_ERR       0x8000
  230 
  231 #define RL_INTRS        \
  232         (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|         \
  233         RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
  234         RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
  235 
  236 #ifdef RE_TX_MODERATION
  237 #define RL_INTRS_CPLUS  \
  238         (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|                      \
  239         RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
  240         RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
  241 #else
  242 #define RL_INTRS_CPLUS  \
  243         (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK|         \
  244         RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
  245         RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
  246 #endif
  247 
  248 /*
  249  * Media status register. (8139 only)
  250  */
  251 #define RL_MEDIASTAT_RXPAUSE    0x01
  252 #define RL_MEDIASTAT_TXPAUSE    0x02
  253 #define RL_MEDIASTAT_LINK       0x04
  254 #define RL_MEDIASTAT_SPEED10    0x08
  255 #define RL_MEDIASTAT_RXFLOWCTL  0x40    /* duplex mode */
  256 #define RL_MEDIASTAT_TXFLOWCTL  0x80    /* duplex mode */
  257 
  258 /*
  259  * Receive config register.
  260  */
  261 #define RL_RXCFG_RX_ALLPHYS     0x00000001      /* accept all nodes */
  262 #define RL_RXCFG_RX_INDIV       0x00000002      /* match filter */
  263 #define RL_RXCFG_RX_MULTI       0x00000004      /* accept all multicast */
  264 #define RL_RXCFG_RX_BROAD       0x00000008      /* accept all broadcast */
  265 #define RL_RXCFG_RX_RUNT        0x00000010
  266 #define RL_RXCFG_RX_ERRPKT      0x00000020
  267 #define RL_RXCFG_WRAP           0x00000080
  268 #define RL_RXCFG_MAXDMA         0x00000700
  269 #define RL_RXCFG_BUFSZ          0x00001800
  270 #define RL_RXCFG_FIFOTHRESH     0x0000E000
  271 #define RL_RXCFG_EARLYTHRESH    0x07000000
  272 
  273 #define RL_RXDMA_16BYTES        0x00000000
  274 #define RL_RXDMA_32BYTES        0x00000100
  275 #define RL_RXDMA_64BYTES        0x00000200
  276 #define RL_RXDMA_128BYTES       0x00000300
  277 #define RL_RXDMA_256BYTES       0x00000400
  278 #define RL_RXDMA_512BYTES       0x00000500
  279 #define RL_RXDMA_1024BYTES      0x00000600
  280 #define RL_RXDMA_UNLIMITED      0x00000700
  281 
  282 #define RL_RXBUF_8              0x00000000
  283 #define RL_RXBUF_16             0x00000800
  284 #define RL_RXBUF_32             0x00001000
  285 #define RL_RXBUF_64             0x00001800
  286 
  287 #define RL_RXFIFO_16BYTES       0x00000000
  288 #define RL_RXFIFO_32BYTES       0x00002000
  289 #define RL_RXFIFO_64BYTES       0x00004000
  290 #define RL_RXFIFO_128BYTES      0x00006000
  291 #define RL_RXFIFO_256BYTES      0x00008000
  292 #define RL_RXFIFO_512BYTES      0x0000A000
  293 #define RL_RXFIFO_1024BYTES     0x0000C000
  294 #define RL_RXFIFO_NOTHRESH      0x0000E000
  295 
  296 /*
  297  * Bits in RX status header (included with RX'ed packet
  298  * in ring buffer).
  299  */
  300 #define RL_RXSTAT_RXOK          0x00000001
  301 #define RL_RXSTAT_ALIGNERR      0x00000002
  302 #define RL_RXSTAT_CRCERR        0x00000004
  303 #define RL_RXSTAT_GIANT         0x00000008
  304 #define RL_RXSTAT_RUNT          0x00000010
  305 #define RL_RXSTAT_BADSYM        0x00000020
  306 #define RL_RXSTAT_BROAD         0x00002000
  307 #define RL_RXSTAT_INDIV         0x00004000
  308 #define RL_RXSTAT_MULTI         0x00008000
  309 #define RL_RXSTAT_LENMASK       0xFFFF0000
  310 
  311 #define RL_RXSTAT_UNFINISHED    0xFFF0          /* DMA still in progress */
  312 /*
  313  * Command register.
  314  */
  315 #define RL_CMD_EMPTY_RXBUF      0x0001
  316 #define RL_CMD_TX_ENB           0x0004
  317 #define RL_CMD_RX_ENB           0x0008
  318 #define RL_CMD_RESET            0x0010
  319 #define RL_CMD_STOPREQ          0x0080
  320 
  321 /*
  322  * Twister register values.  These are completely undocumented and derived
  323  * from public sources.
  324  */
  325 #define RL_CSCFG_LINK_OK        0x0400
  326 #define RL_CSCFG_CHANGE         0x0800
  327 #define RL_CSCFG_STATUS         0xf000
  328 #define RL_CSCFG_ROW3           0x7000
  329 #define RL_CSCFG_ROW2           0x3000
  330 #define RL_CSCFG_ROW1           0x1000
  331 #define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0
  332 #define RL_CSCFG_LINK_DOWN_CMD  0xf3c0
  333 
  334 #define RL_NWAYTST_RESET        0
  335 #define RL_NWAYTST_CBL_TEST     0x20
  336 
  337 #define RL_PARA78               0x78
  338 #define RL_PARA78_DEF           0x78fa8388
  339 #define RL_PARA7C               0x7C
  340 #define RL_PARA7C_DEF           0xcb38de43
  341 #define RL_PARA7C_RETUNE        0xfb38de03
  342 /*
  343  * EEPROM control register
  344  */
  345 #define RL_EE_DATAOUT           0x01    /* Data out */
  346 #define RL_EE_DATAIN            0x02    /* Data in */
  347 #define RL_EE_CLK               0x04    /* clock */
  348 #define RL_EE_SEL               0x08    /* chip select */
  349 #define RL_EE_MODE              (0x40|0x80)
  350 
  351 #define RL_EEMODE_OFF           0x00
  352 #define RL_EEMODE_AUTOLOAD      0x40
  353 #define RL_EEMODE_PROGRAM       0x80
  354 #define RL_EEMODE_WRITECFG      (0x80|0x40)
  355 
  356 /* 9346 EEPROM commands */
  357 #define RL_9346_ADDR_LEN        6       /* 93C46 1K: 128x16 */
  358 #define RL_9356_ADDR_LEN        8       /* 93C56 2K: 256x16 */
  359 
  360 #define RL_9346_WRITE          0x5
  361 #define RL_9346_READ           0x6
  362 #define RL_9346_ERASE          0x7
  363 #define RL_9346_EWEN           0x4
  364 #define RL_9346_EWEN_ADDR      0x30
  365 #define RL_9456_EWDS           0x4
  366 #define RL_9346_EWDS_ADDR      0x00
  367 
  368 #define RL_EECMD_WRITE          0x140
  369 #define RL_EECMD_READ_6BIT      0x180
  370 #define RL_EECMD_READ_8BIT      0x600
  371 #define RL_EECMD_ERASE          0x1c0
  372 
  373 #define RL_EE_ID                0x00
  374 #define RL_EE_PCI_VID           0x01
  375 #define RL_EE_PCI_DID           0x02
  376 /* Location of station address inside EEPROM */
  377 #define RL_EE_EADDR             0x07
  378 
  379 /*
  380  * MII register (8129 only)
  381  */
  382 #define RL_MII_CLK              0x01
  383 #define RL_MII_DATAIN           0x02
  384 #define RL_MII_DATAOUT          0x04
  385 #define RL_MII_DIR              0x80    /* 0 == input, 1 == output */
  386 
  387 /*
  388  * Config 0 register
  389  */
  390 #define RL_CFG0_ROM0            0x01
  391 #define RL_CFG0_ROM1            0x02
  392 #define RL_CFG0_ROM2            0x04
  393 #define RL_CFG0_PL0             0x08
  394 #define RL_CFG0_PL1             0x10
  395 #define RL_CFG0_10MBPS          0x20    /* 10 Mbps internal mode */
  396 #define RL_CFG0_PCS             0x40
  397 #define RL_CFG0_SCR             0x80
  398 
  399 /*
  400  * Config 1 register
  401  */
  402 #define RL_CFG1_PWRDWN          0x01
  403 #define RL_CFG1_PME             0x01    
  404 #define RL_CFG1_SLEEP           0x02
  405 #define RL_CFG1_VPDEN           0x02
  406 #define RL_CFG1_IOMAP           0x04
  407 #define RL_CFG1_MEMMAP          0x08
  408 #define RL_CFG1_RSVD            0x10
  409 #define RL_CFG1_LWACT           0x10
  410 #define RL_CFG1_DRVLOAD         0x20
  411 #define RL_CFG1_LED0            0x40
  412 #define RL_CFG1_FULLDUPLEX      0x40    /* 8129 only */
  413 #define RL_CFG1_LED1            0x80
  414 
  415 /*
  416  * Config 2 register
  417  */
  418 #define RL_CFG2_PCI33MHZ        0x00
  419 #define RL_CFG2_PCI66MHZ        0x01
  420 #define RL_CFG2_PCI64BIT        0x08
  421 #define RL_CFG2_AUXPWR          0x10
  422 #define RL_CFG2_MSI             0x20
  423 
  424 /*
  425  * Config 3 register
  426  */
  427 #define RL_CFG3_GRANTSEL        0x80
  428 #define RL_CFG3_WOL_MAGIC       0x20
  429 #define RL_CFG3_WOL_LINK        0x10
  430 #define RL_CFG3_FAST_B2B        0x01
  431 
  432 /*
  433  * Config 4 register
  434  */
  435 #define RL_CFG4_LWPTN           0x04
  436 #define RL_CFG4_LWPME           0x10
  437 
  438 /*
  439  * Config 5 register
  440  */
  441 #define RL_CFG5_WOL_BCAST       0x40
  442 #define RL_CFG5_WOL_MCAST       0x20
  443 #define RL_CFG5_WOL_UCAST       0x10
  444 #define RL_CFG5_WOL_LANWAKE     0x02
  445 #define RL_CFG5_PME_STS         0x01
  446 
  447 /*
  448  * 8139C+ register definitions
  449  */
  450 
  451 /* RL_DUMPSTATS_LO register */
  452 
  453 #define RL_DUMPSTATS_START      0x00000008
  454 
  455 /* Transmit start register */
  456 
  457 #define RL_TXSTART_SWI          0x01    /* generate TX interrupt */
  458 #define RL_TXSTART_START        0x40    /* start normal queue transmit */
  459 #define RL_TXSTART_HPRIO_START  0x80    /* start hi prio queue transmit */
  460 
  461 /*
  462  * Config 2 register, 8139C+/8169/8169S/8110S only
  463  */
  464 #define RL_CFG2_BUSFREQ         0x07
  465 #define RL_CFG2_BUSWIDTH        0x08
  466 #define RL_CFG2_AUXPWRSTS       0x10
  467 
  468 #define RL_BUSFREQ_33MHZ        0x00
  469 #define RL_BUSFREQ_66MHZ        0x01
  470                                         
  471 #define RL_BUSWIDTH_32BITS      0x00
  472 #define RL_BUSWIDTH_64BITS      0x08
  473 
  474 /* C+ mode command register */
  475 
  476 #define RL_CPLUSCMD_TXENB       0x0001  /* enable C+ transmit mode */
  477 #define RL_CPLUSCMD_RXENB       0x0002  /* enable C+ receive mode */
  478 #define RL_CPLUSCMD_PCI_MRW     0x0008  /* enable PCI multi-read/write */
  479 #define RL_CPLUSCMD_PCI_DAC     0x0010  /* PCI dual-address cycle only */
  480 #define RL_CPLUSCMD_RXCSUM_ENB  0x0020  /* enable RX checksum offload */
  481 #define RL_CPLUSCMD_VLANSTRIP   0x0040  /* enable VLAN tag stripping */
  482 #define RL_CPLUSCMD_MACSTAT_DIS 0x0080  /* 8168B/C/CP */
  483 #define RL_CPLUSCMD_ASF         0x0100  /* 8168C/CP */
  484 #define RL_CPLUSCMD_DBG_SEL     0x0200  /* 8168C/CP */
  485 #define RL_CPLUSCMD_FORCE_TXFC  0x0400  /* 8168C/CP */
  486 #define RL_CPLUSCMD_FORCE_RXFC  0x0800  /* 8168C/CP */
  487 #define RL_CPLUSCMD_FORCE_HDPX  0x1000  /* 8168C/CP */
  488 #define RL_CPLUSCMD_NORMAL_MODE 0x2000  /* 8168C/CP */
  489 #define RL_CPLUSCMD_DBG_ENB     0x4000  /* 8168C/CP */
  490 #define RL_CPLUSCMD_BIST_ENB    0x8000  /* 8168C/CP */
  491 
  492 /* C+ early transmit threshold */
  493 
  494 #define RL_EARLYTXTHRESH_CNT    0x003F  /* byte count times 8 */ 
  495 
  496 /*
  497  * Gigabit PHY access register (8169 only)
  498  */
  499 
  500 #define RL_PHYAR_PHYDATA        0x0000FFFF
  501 #define RL_PHYAR_PHYREG         0x001F0000
  502 #define RL_PHYAR_BUSY           0x80000000
  503 
  504 /*
  505  * Gigabit media status (8169 only)
  506  */
  507 #define RL_GMEDIASTAT_FDX       0x01    /* full duplex */
  508 #define RL_GMEDIASTAT_LINK      0x02    /* link up */
  509 #define RL_GMEDIASTAT_10MBPS    0x04    /* 10mps link */
  510 #define RL_GMEDIASTAT_100MBPS   0x08    /* 100mbps link */
  511 #define RL_GMEDIASTAT_1000MBPS  0x10    /* gigE link */
  512 #define RL_GMEDIASTAT_RXFLOW    0x20    /* RX flow control on */
  513 #define RL_GMEDIASTAT_TXFLOW    0x40    /* TX flow control on */
  514 #define RL_GMEDIASTAT_TBI       0x80    /* TBI enabled */
  515 
  516 /*
  517  * The RealTek doesn't use a fragment-based descriptor mechanism.
  518  * Instead, there are only four register sets, each or which represents
  519  * one 'descriptor.' Basically, each TX descriptor is just a contiguous
  520  * packet buffer (32-bit aligned!) and we place the buffer addresses in
  521  * the registers so the chip knows where they are.
  522  *
  523  * We can sort of kludge together the same kind of buffer management
  524  * used in previous drivers, but we have to do buffer copies almost all
  525  * the time, so it doesn't really buy us much.
  526  *
  527  * For reception, there's just one large buffer where the chip stores
  528  * all received packets.
  529  */
  530 
  531 #define RL_RX_BUF_SZ            RL_RXBUF_64
  532 #define RL_RXBUFLEN             (1 << ((RL_RX_BUF_SZ >> 11) + 13))
  533 #define RL_TX_LIST_CNT          4
  534 #define RL_MIN_FRAMELEN         60
  535 #define RL_TX_8139_BUF_ALIGN    4
  536 #define RL_RX_8139_BUF_ALIGN    8
  537 #define RL_RX_8139_BUF_RESERVE  sizeof(int64_t)
  538 #define RL_RX_8139_BUF_GUARD_SZ \
  539         (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 
  540 #define RL_TXTHRESH(x)          ((x) << 11)
  541 #define RL_TX_THRESH_INIT       96
  542 #define RL_RX_FIFOTHRESH        RL_RXFIFO_NOTHRESH
  543 #define RL_RX_MAXDMA            RL_RXDMA_UNLIMITED
  544 #define RL_TX_MAXDMA            RL_TXDMA_2048BYTES
  545 
  546 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
  547 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
  548 
  549 #define RL_ETHER_ALIGN  2
  550 
  551 /*
  552  * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
  553  */
  554 #define RL_IP4CSUMTX_MINLEN     28
  555 #define RL_IP4CSUMTX_PADLEN     (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
  556 
  557 struct rl_chain_data {
  558         uint16_t                cur_rx;
  559         uint8_t                 *rl_rx_buf;
  560         uint8_t                 *rl_rx_buf_ptr;
  561 
  562         struct mbuf             *rl_tx_chain[RL_TX_LIST_CNT];
  563         bus_dmamap_t            rl_tx_dmamap[RL_TX_LIST_CNT];
  564         bus_dma_tag_t           rl_tx_tag;
  565         bus_dma_tag_t           rl_rx_tag;
  566         bus_dmamap_t            rl_rx_dmamap;
  567         bus_addr_t              rl_rx_buf_paddr;
  568         uint8_t                 last_tx;
  569         uint8_t                 cur_tx;
  570 };
  571 
  572 #define RL_INC(x)               (x = (x + 1) % RL_TX_LIST_CNT)
  573 #define RL_CUR_TXADDR(x)        ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
  574 #define RL_CUR_TXSTAT(x)        ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
  575 #define RL_CUR_TXMBUF(x)        (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
  576 #define RL_CUR_DMAMAP(x)        (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
  577 #define RL_LAST_TXADDR(x)       ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
  578 #define RL_LAST_TXSTAT(x)       ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
  579 #define RL_LAST_TXMBUF(x)       (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
  580 #define RL_LAST_DMAMAP(x)       (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
  581 
  582 struct rl_type {
  583         uint16_t                rl_vid;
  584         uint16_t                rl_did;
  585         int                     rl_basetype;
  586         char                    *rl_name;
  587 };
  588 
  589 struct rl_hwrev {
  590         uint32_t                rl_rev;
  591         int                     rl_type;
  592         char                    *rl_desc;
  593 };
  594 
  595 struct rl_mii_frame {
  596         uint8_t         mii_stdelim;
  597         uint8_t         mii_opcode;
  598         uint8_t         mii_phyaddr;
  599         uint8_t         mii_regaddr;
  600         uint8_t         mii_turnaround;
  601         uint16_t        mii_data;
  602 };
  603 
  604 /*
  605  * MII constants
  606  */
  607 #define RL_MII_STARTDELIM       0x01
  608 #define RL_MII_READOP           0x02
  609 #define RL_MII_WRITEOP          0x01
  610 #define RL_MII_TURNAROUND       0x02
  611 
  612 #define RL_8129                 1
  613 #define RL_8139                 2
  614 #define RL_8139CPLUS            3
  615 #define RL_8169                 4
  616 
  617 #define RL_ISCPLUS(x)           ((x)->rl_type == RL_8139CPLUS ||        \
  618                                  (x)->rl_type == RL_8169)
  619 
  620 /*
  621  * The 8139C+ and 8160 gigE chips support descriptor-based TX
  622  * and RX. In fact, they even support TCP large send. Descriptors
  623  * must be allocated in contiguous blocks that are aligned on a
  624  * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
  625  */
  626 
  627 /*
  628  * RX/TX descriptor definition. When large send mode is enabled, the
  629  * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
  630  * the checksum offload bits are disabled. The structure layout is
  631  * the same for RX and TX descriptors
  632  */
  633 
  634 struct rl_desc {
  635         uint32_t                rl_cmdstat;
  636         uint32_t                rl_vlanctl;
  637         uint32_t                rl_bufaddr_lo;
  638         uint32_t                rl_bufaddr_hi;
  639 };
  640 
  641 #define RL_TDESC_CMD_FRAGLEN    0x0000FFFF
  642 #define RL_TDESC_CMD_TCPCSUM    0x00010000      /* TCP checksum enable */
  643 #define RL_TDESC_CMD_UDPCSUM    0x00020000      /* UDP checksum enable */
  644 #define RL_TDESC_CMD_IPCSUM     0x00040000      /* IP header checksum enable */
  645 #define RL_TDESC_CMD_MSSVAL     0x07FF0000      /* Large send MSS value */
  646 #define RL_TDESC_CMD_MSSVAL_SHIFT       16      /* Large send MSS value shift */
  647 #define RL_TDESC_CMD_LGSEND     0x08000000      /* TCP large send enb */
  648 #define RL_TDESC_CMD_EOF        0x10000000      /* end of frame marker */
  649 #define RL_TDESC_CMD_SOF        0x20000000      /* start of frame marker */
  650 #define RL_TDESC_CMD_EOR        0x40000000      /* end of ring marker */
  651 #define RL_TDESC_CMD_OWN        0x80000000      /* chip owns descriptor */
  652 
  653 #define RL_TDESC_VLANCTL_TAG    0x00020000      /* Insert VLAN tag */
  654 #define RL_TDESC_VLANCTL_DATA   0x0000FFFF      /* TAG data */
  655 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
  656 #define RL_TDESC_CMD_UDPCSUMV2  0x80000000
  657 #define RL_TDESC_CMD_TCPCSUMV2  0x40000000      
  658 #define RL_TDESC_CMD_IPCSUMV2   0x20000000      
  659 
  660 /*
  661  * Error bits are valid only on the last descriptor of a frame
  662  * (i.e. RL_TDESC_CMD_EOF == 1)
  663  */
  664 
  665 #define RL_TDESC_STAT_COLCNT    0x000F0000      /* collision count */
  666 #define RL_TDESC_STAT_EXCESSCOL 0x00100000      /* excessive collisions */
  667 #define RL_TDESC_STAT_LINKFAIL  0x00200000      /* link faulure */
  668 #define RL_TDESC_STAT_OWINCOL   0x00400000      /* out-of-window collision */
  669 #define RL_TDESC_STAT_TXERRSUM  0x00800000      /* transmit error summary */
  670 #define RL_TDESC_STAT_UNDERRUN  0x02000000      /* TX underrun occured */
  671 #define RL_TDESC_STAT_OWN       0x80000000
  672 
  673 /*
  674  * RX descriptor cmd/vlan definitions
  675  */
  676 
  677 #define RL_RDESC_CMD_EOR        0x40000000
  678 #define RL_RDESC_CMD_OWN        0x80000000
  679 #define RL_RDESC_CMD_BUFLEN     0x00001FFF
  680 
  681 #define RL_RDESC_STAT_OWN       0x80000000
  682 #define RL_RDESC_STAT_EOR       0x40000000
  683 #define RL_RDESC_STAT_SOF       0x20000000
  684 #define RL_RDESC_STAT_EOF       0x10000000
  685 #define RL_RDESC_STAT_FRALIGN   0x08000000      /* frame alignment error */
  686 #define RL_RDESC_STAT_MCAST     0x04000000      /* multicast pkt received */
  687 #define RL_RDESC_STAT_UCAST     0x02000000      /* unicast pkt received */
  688 #define RL_RDESC_STAT_BCAST     0x01000000      /* broadcast pkt received */
  689 #define RL_RDESC_STAT_BUFOFLOW  0x00800000      /* out of buffer space */
  690 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000      /* FIFO overrun */
  691 #define RL_RDESC_STAT_GIANT     0x00200000      /* pkt > 4096 bytes */
  692 #define RL_RDESC_STAT_RXERRSUM  0x00100000      /* RX error summary */
  693 #define RL_RDESC_STAT_RUNT      0x00080000      /* runt packet received */
  694 #define RL_RDESC_STAT_CRCERR    0x00040000      /* CRC error */
  695 #define RL_RDESC_STAT_PROTOID   0x00030000      /* Protocol type */
  696 #define RL_RDESC_STAT_UDP       0x00020000      /* UDP, 8168C/CP, 8111C/CP */
  697 #define RL_RDESC_STAT_TCP       0x00010000      /* TCP, 8168C/CP, 8111C/CP */
  698 #define RL_RDESC_STAT_IPSUMBAD  0x00008000      /* IP header checksum bad */
  699 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000      /* UDP checksum bad */
  700 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000      /* TCP checksum bad */
  701 #define RL_RDESC_STAT_FRAGLEN   0x00001FFF      /* RX'ed frame/frag len */
  702 #define RL_RDESC_STAT_GFRAGLEN  0x00003FFF      /* RX'ed frame/frag len */
  703 #define RL_RDESC_STAT_ERRS      (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
  704                                  RL_RDESC_STAT_CRCERR)
  705 
  706 #define RL_RDESC_VLANCTL_TAG    0x00010000      /* VLAN tag available
  707                                                    (rl_vlandata valid)*/
  708 #define RL_RDESC_VLANCTL_DATA   0x0000FFFF      /* TAG data */
  709 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
  710 #define RL_RDESC_IPV6           0x80000000
  711 #define RL_RDESC_IPV4           0x40000000
  712 
  713 #define RL_PROTOID_NONIP        0x00000000
  714 #define RL_PROTOID_TCPIP        0x00010000
  715 #define RL_PROTOID_UDPIP        0x00020000
  716 #define RL_PROTOID_IP           0x00030000
  717 #define RL_TCPPKT(x)            (((x) & RL_RDESC_STAT_PROTOID) == \
  718                                  RL_PROTOID_TCPIP)
  719 #define RL_UDPPKT(x)            (((x) & RL_RDESC_STAT_PROTOID) == \
  720                                  RL_PROTOID_UDPIP)
  721 
  722 /*
  723  * Statistics counter structure (8139C+ and 8169 only)
  724  */
  725 struct rl_stats {
  726         uint32_t                rl_tx_pkts_lo;
  727         uint32_t                rl_tx_pkts_hi;
  728         uint32_t                rl_tx_errs_lo;
  729         uint32_t                rl_tx_errs_hi;
  730         uint32_t                rl_tx_errs;
  731         uint16_t                rl_missed_pkts;
  732         uint16_t                rl_rx_framealign_errs;
  733         uint32_t                rl_tx_onecoll;
  734         uint32_t                rl_tx_multicolls;
  735         uint32_t                rl_rx_ucasts_hi;
  736         uint32_t                rl_rx_ucasts_lo;
  737         uint32_t                rl_rx_bcasts_lo;
  738         uint32_t                rl_rx_bcasts_hi;
  739         uint32_t                rl_rx_mcasts;
  740         uint16_t                rl_tx_aborts;
  741         uint16_t                rl_rx_underruns;
  742 };
  743 
  744 /*
  745  * Rx/Tx descriptor parameters (8139C+ and 8169 only)
  746  *
  747  * 8139C+
  748  *  Number of descriptors supported : up to 64
  749  *  Descriptor alignment : 256 bytes
  750  *  Tx buffer : At least 4 bytes in length.
  751  *  Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
  752  *  
  753  * 8169
  754  *  Number of descriptors supported : up to 1024
  755  *  Descriptor alignment : 256 bytes
  756  *  Tx buffer : At least 4 bytes in length.
  757  *  Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
  758  */
  759 #ifndef __NO_STRICT_ALIGNMENT
  760 #define RE_FIXUP_RX     1
  761 #endif
  762 
  763 #define RL_8169_TX_DESC_CNT     256
  764 #define RL_8169_RX_DESC_CNT     256
  765 #define RL_8139_TX_DESC_CNT     64
  766 #define RL_8139_RX_DESC_CNT     64
  767 #define RL_TX_DESC_CNT          RL_8169_TX_DESC_CNT
  768 #define RL_RX_DESC_CNT          RL_8169_RX_DESC_CNT
  769 #define RL_NTXSEGS              32
  770 
  771 #define RL_RING_ALIGN           256
  772 #define RL_IFQ_MAXLEN           512
  773 #define RL_TX_DESC_NXT(sc,x)    ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
  774 #define RL_TX_DESC_PRV(sc,x)    ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
  775 #define RL_RX_DESC_NXT(sc,x)    ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
  776 #define RL_OWN(x)               (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
  777 #define RL_RXBYTES(x)           (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
  778 #define RL_PKTSZ(x)             ((x)/* >> 3*/)
  779 #ifdef RE_FIXUP_RX
  780 #define RE_ETHER_ALIGN  sizeof(uint64_t)
  781 #define RE_RX_DESC_BUFLEN       (MCLBYTES - RE_ETHER_ALIGN)
  782 #else
  783 #define RE_ETHER_ALIGN  0
  784 #define RE_RX_DESC_BUFLEN       MCLBYTES
  785 #endif
  786 
  787 #define RL_MSI_MESSAGES 1
  788 
  789 #define RL_ADDR_LO(y)           ((uint64_t) (y) & 0xFFFFFFFF)
  790 #define RL_ADDR_HI(y)           ((uint64_t) (y) >> 32)
  791 
  792 /*
  793  * The number of bits reserved for MSS in RealTek controllers is
  794  * 11bits. This limits the maximum interface MTU size in TSO case
  795  * as upper stack should not generate TCP segments with MSS greater
  796  * than the limit.
  797  */
  798 #define RL_TSO_MTU              (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
  799 
  800 /* see comment in dev/re/if_re.c */
  801 #define RL_JUMBO_FRAMELEN       7440
  802 #define RL_JUMBO_MTU            (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
  803 #define RL_MAX_FRAMELEN         \
  804         (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
  805 
  806 struct rl_txdesc {
  807         struct mbuf             *tx_m;
  808         bus_dmamap_t            tx_dmamap;
  809 };
  810 
  811 struct rl_rxdesc {
  812         struct mbuf             *rx_m;
  813         bus_dmamap_t            rx_dmamap;
  814         bus_size_t              rx_size;
  815 };
  816 
  817 struct rl_list_data {
  818         struct rl_txdesc        rl_tx_desc[RL_TX_DESC_CNT];
  819         struct rl_rxdesc        rl_rx_desc[RL_RX_DESC_CNT];
  820         int                     rl_tx_desc_cnt;
  821         int                     rl_rx_desc_cnt;
  822         int                     rl_tx_prodidx;
  823         int                     rl_rx_prodidx;
  824         int                     rl_tx_considx;
  825         int                     rl_tx_free;
  826         bus_dma_tag_t           rl_tx_mtag;     /* mbuf TX mapping tag */
  827         bus_dma_tag_t           rl_rx_mtag;     /* mbuf RX mapping tag */
  828         bus_dmamap_t            rl_rx_sparemap;
  829         bus_dma_tag_t           rl_stag;        /* stats mapping tag */
  830         bus_dmamap_t            rl_smap;        /* stats map */
  831         struct rl_stats         *rl_stats;
  832         bus_addr_t              rl_stats_addr;
  833         bus_dma_tag_t           rl_rx_list_tag;
  834         bus_dmamap_t            rl_rx_list_map;
  835         struct rl_desc          *rl_rx_list;
  836         bus_addr_t              rl_rx_list_addr;
  837         bus_dma_tag_t           rl_tx_list_tag;
  838         bus_dmamap_t            rl_tx_list_map;
  839         struct rl_desc          *rl_tx_list;
  840         bus_addr_t              rl_tx_list_addr;
  841 };
  842 
  843 enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE };
  844 
  845 struct rl_softc {
  846         struct ifnet            *rl_ifp;        /* interface info */
  847         bus_space_handle_t      rl_bhandle;     /* bus space handle */
  848         bus_space_tag_t         rl_btag;        /* bus space tag */
  849         device_t                rl_dev;
  850         struct resource         *rl_res;
  851         int                     rl_res_id;
  852         int                     rl_res_type;
  853         struct resource         *rl_irq[RL_MSI_MESSAGES];
  854         void                    *rl_intrhand[RL_MSI_MESSAGES];
  855         device_t                rl_miibus;
  856         bus_dma_tag_t           rl_parent_tag;
  857         uint8_t                 rl_type;
  858         int                     rl_eecmd_read;
  859         int                     rl_eewidth;
  860         uint8_t                 rl_stats_no_timeout;
  861         int                     rl_txthresh;
  862         struct rl_chain_data    rl_cdata;
  863         struct rl_list_data     rl_ldata;
  864         struct callout          rl_stat_callout;
  865         int                     rl_watchdog_timer;
  866         struct mtx              rl_mtx;
  867         struct mbuf             *rl_head;
  868         struct mbuf             *rl_tail;
  869         uint32_t                rl_hwrev;
  870         uint32_t                rl_rxlenmask;
  871         int                     rl_testmode;
  872         int                     rl_if_flags;
  873         int                     rl_twister_enable;
  874         enum rl_twist           rl_twister;
  875         int                     rl_twist_row;
  876         int                     rl_twist_col;
  877         int                     suspended;      /* 0 = normal  1 = suspended */
  878 #ifdef DEVICE_POLLING
  879         int                     rxcycles;
  880 #endif
  881 
  882         struct task             rl_txtask;
  883         struct task             rl_inttask;
  884 
  885         int                     rl_txstart;
  886         uint32_t                rl_flags;
  887 #define RL_FLAG_MSI             0x0001
  888 #define RL_FLAG_AUTOPAD         0x0002
  889 #define RL_FLAG_PHYWAKE_PM      0x0004
  890 #define RL_FLAG_PHYWAKE         0x0008
  891 #define RL_FLAG_NOJUMBO         0x0010
  892 #define RL_FLAG_PAR             0x0020
  893 #define RL_FLAG_DESCV2          0x0040
  894 #define RL_FLAG_MACSTAT         0x0080
  895 #define RL_FLAG_FASTETHER       0x0100
  896 #define RL_FLAG_CMDSTOP         0x0200
  897 #define RL_FLAG_MACRESET        0x0400
  898 #define RL_FLAG_WOLRXENB        0x1000
  899 #define RL_FLAG_MACSLEEP        0x2000
  900 #define RL_FLAG_PCIE            0x4000
  901 #define RL_FLAG_LINK            0x8000
  902 };
  903 
  904 #define RL_LOCK(_sc)            mtx_lock(&(_sc)->rl_mtx)
  905 #define RL_UNLOCK(_sc)          mtx_unlock(&(_sc)->rl_mtx)
  906 #define RL_LOCK_ASSERT(_sc)     mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
  907 
  908 /*
  909  * register space access macros
  910  */
  911 #define CSR_WRITE_STREAM_4(sc, reg, val)        \
  912         bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
  913 #define CSR_WRITE_4(sc, reg, val)       \
  914         bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
  915 #define CSR_WRITE_2(sc, reg, val)       \
  916         bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
  917 #define CSR_WRITE_1(sc, reg, val)       \
  918         bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
  919 
  920 #define CSR_READ_4(sc, reg)             \
  921         bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
  922 #define CSR_READ_2(sc, reg)             \
  923         bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
  924 #define CSR_READ_1(sc, reg)             \
  925         bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
  926 
  927 #define CSR_SETBIT_1(sc, offset, val)           \
  928         CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
  929 
  930 #define CSR_CLRBIT_1(sc, offset, val)           \
  931         CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
  932 
  933 #define CSR_SETBIT_2(sc, offset, val)           \
  934         CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
  935 
  936 #define CSR_CLRBIT_2(sc, offset, val)           \
  937         CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
  938 
  939 #define CSR_SETBIT_4(sc, offset, val)           \
  940         CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
  941 
  942 #define CSR_CLRBIT_4(sc, offset, val)           \
  943         CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
  944 
  945 #define RL_TIMEOUT              1000
  946 #define RL_PHY_TIMEOUT          2000
  947 
  948 /*
  949  * General constants that are fun to know.
  950  *
  951  * RealTek PCI vendor ID
  952  */
  953 #define RT_VENDORID                             0x10EC
  954 
  955 /*
  956  * RealTek chip device IDs.
  957  */
  958 #define RT_DEVICEID_8139D                       0x8039
  959 #define RT_DEVICEID_8129                        0x8129
  960 #define RT_DEVICEID_8101E                       0x8136
  961 #define RT_DEVICEID_8138                        0x8138
  962 #define RT_DEVICEID_8139                        0x8139
  963 #define RT_DEVICEID_8169SC                      0x8167
  964 #define RT_DEVICEID_8168                        0x8168
  965 #define RT_DEVICEID_8169                        0x8169
  966 #define RT_DEVICEID_8100                        0x8100
  967 
  968 #define RT_REVID_8139CPLUS                      0x20
  969 
  970 /*
  971  * Accton PCI vendor ID
  972  */
  973 #define ACCTON_VENDORID                         0x1113
  974 
  975 /*
  976  * Accton MPX 5030/5038 device ID.
  977  */
  978 #define ACCTON_DEVICEID_5030                    0x1211
  979 
  980 /*
  981  * Nortel PCI vendor ID
  982  */
  983 #define NORTEL_VENDORID                         0x126C
  984 
  985 /*
  986  * Delta Electronics Vendor ID.
  987  */
  988 #define DELTA_VENDORID                          0x1500
  989 
  990 /*
  991  * Delta device IDs.
  992  */
  993 #define DELTA_DEVICEID_8139                     0x1360
  994 
  995 /*
  996  * Addtron vendor ID.
  997  */
  998 #define ADDTRON_VENDORID                        0x4033
  999 
 1000 /*
 1001  * Addtron device IDs.
 1002  */
 1003 #define ADDTRON_DEVICEID_8139                   0x1360
 1004 
 1005 /*
 1006  * D-Link vendor ID.
 1007  */
 1008 #define DLINK_VENDORID                          0x1186
 1009 
 1010 /*
 1011  * D-Link DFE-530TX+ device ID
 1012  */
 1013 #define DLINK_DEVICEID_530TXPLUS                0x1300
 1014 
 1015 /*
 1016  * D-Link DFE-5280T device ID
 1017  */
 1018 #define DLINK_DEVICEID_528T                     0x4300
 1019 
 1020 /*
 1021  * D-Link DFE-690TXD device ID
 1022  */
 1023 #define DLINK_DEVICEID_690TXD                   0x1340
 1024 
 1025 /*
 1026  * Corega K.K vendor ID
 1027  */
 1028 #define COREGA_VENDORID                         0x1259
 1029 
 1030 /*
 1031  * Corega FEther CB-TXD device ID
 1032  */
 1033 #define COREGA_DEVICEID_FETHERCBTXD             0xa117
 1034 
 1035 /*
 1036  * Corega FEtherII CB-TXD device ID
 1037  */
 1038 #define COREGA_DEVICEID_FETHERIICBTXD           0xa11e
 1039 
 1040 /*
 1041  * Corega CG-LAPCIGT device ID
 1042  */
 1043 #define COREGA_DEVICEID_CGLAPCIGT               0xc107
 1044 
 1045 /*
 1046  * Linksys vendor ID
 1047  */
 1048 #define LINKSYS_VENDORID                        0x1737
 1049 
 1050 /*
 1051  * Linksys EG1032 device ID
 1052  */
 1053 #define LINKSYS_DEVICEID_EG1032                 0x1032
 1054 
 1055 /*
 1056  * Linksys EG1032 rev 3 sub-device ID
 1057  */
 1058 #define LINKSYS_SUBDEVICE_EG1032_REV3           0x0024
 1059 
 1060 /*
 1061  * Peppercon vendor ID
 1062  */
 1063 #define PEPPERCON_VENDORID                      0x1743
 1064 
 1065 /*
 1066  * Peppercon ROL-F device ID
 1067  */
 1068 #define PEPPERCON_DEVICEID_ROLF                 0x8139
 1069 
 1070 /*
 1071  * Planex Communications, Inc. vendor ID
 1072  */
 1073 #define PLANEX_VENDORID                         0x14ea
 1074 
 1075 /*
 1076  * Planex FNW-3603-TX device ID
 1077  */
 1078 #define PLANEX_DEVICEID_FNW3603TX               0xab06
 1079 
 1080 /*
 1081  * Planex FNW-3800-TX device ID
 1082  */
 1083 #define PLANEX_DEVICEID_FNW3800TX               0xab07
 1084 
 1085 /*
 1086  * LevelOne vendor ID
 1087  */
 1088 #define LEVEL1_VENDORID                         0x018A
 1089 
 1090 /*
 1091  * LevelOne FPC-0106TX devide ID
 1092  */
 1093 #define LEVEL1_DEVICEID_FPC0106TX               0x0106
 1094 
 1095 /*
 1096  * Compaq vendor ID
 1097  */
 1098 #define CP_VENDORID                             0x021B
 1099 
 1100 /*
 1101  * Edimax vendor ID
 1102  */
 1103 #define EDIMAX_VENDORID                         0x13D1
 1104 
 1105 /*
 1106  * Edimax EP-4103DL cardbus device ID
 1107  */
 1108 #define EDIMAX_DEVICEID_EP4103DL                0xAB06
 1109 
 1110 /* US Robotics vendor ID */
 1111 
 1112 #define USR_VENDORID            0x16EC
 1113 
 1114 /* US Robotics 997902 device ID */
 1115 
 1116 #define USR_DEVICEID_997902     0x0116
 1117 
 1118 /*
 1119  * PCI low memory base and low I/O base register, and
 1120  * other PCI registers.
 1121  */
 1122 
 1123 #define RL_PCI_VENDOR_ID        0x00
 1124 #define RL_PCI_DEVICE_ID        0x02
 1125 #define RL_PCI_COMMAND          0x04
 1126 #define RL_PCI_STATUS           0x06
 1127 #define RL_PCI_CLASSCODE        0x09
 1128 #define RL_PCI_LATENCY_TIMER    0x0D
 1129 #define RL_PCI_HEADER_TYPE      0x0E
 1130 #define RL_PCI_LOIO             0x10
 1131 #define RL_PCI_LOMEM            0x14
 1132 #define RL_PCI_BIOSROM          0x30
 1133 #define RL_PCI_INTLINE          0x3C
 1134 #define RL_PCI_INTPIN           0x3D
 1135 #define RL_PCI_MINGNT           0x3E
 1136 #define RL_PCI_MINLAT           0x0F
 1137 #define RL_PCI_RESETOPT         0x48
 1138 #define RL_PCI_EEPROM_DATA      0x4C
 1139 
 1140 #define RL_PCI_CAPID            0x50 /* 8 bits */
 1141 #define RL_PCI_NEXTPTR          0x51 /* 8 bits */
 1142 #define RL_PCI_PWRMGMTCAP       0x52 /* 16 bits */
 1143 #define RL_PCI_PWRMGMTCTRL      0x54 /* 16 bits */
 1144 
 1145 #define RL_PSTATE_MASK          0x0003
 1146 #define RL_PSTATE_D0            0x0000
 1147 #define RL_PSTATE_D1            0x0002
 1148 #define RL_PSTATE_D2            0x0002
 1149 #define RL_PSTATE_D3            0x0003
 1150 #define RL_PME_EN               0x0010
 1151 #define RL_PME_STATUS           0x8000

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