FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sf.c
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD$
33 */
34
35 /*
36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
37 * Programming manual is available from www.adaptec.com.
38 *
39 * Written by Bill Paul <wpaul@ctr.columbia.edu>
40 * Department of Electical Engineering
41 * Columbia University, New York City
42 */
43
44 /*
45 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
46 * controller designed with flexibility and reducing CPU load in mind.
47 * The Starfire offers high and low priority buffer queues, a
48 * producer/consumer index mechanism and several different buffer
49 * queue and completion queue descriptor types. Any one of a number
50 * of different driver designs can be used, depending on system and
51 * OS requirements. This driver makes use of type0 transmit frame
52 * descriptors (since BSD fragments packets across an mbuf chain)
53 * and two RX buffer queues prioritized on size (one queue for small
54 * frames that will fit into a single mbuf, another with full size
55 * mbuf clusters for everything else). The producer/consumer indexes
56 * and completion queues are also used.
57 *
58 * One downside to the Starfire has to do with alignment: buffer
59 * queues must be aligned on 256-byte boundaries, and receive buffers
60 * must be aligned on longword boundaries. The receive buffer alignment
61 * causes problems on the Alpha platform, where the packet payload
62 * should be longword aligned. There is no simple way around this.
63 *
64 * For receive filtering, the Starfire offers 16 perfect filter slots
65 * and a 512-bit hash table.
66 *
67 * The Starfire has no internal transceiver, relying instead on an
68 * external MII-based transceiver. Accessing registers on external
69 * PHYs is done through a special register map rather than with the
70 * usual bitbang MDIO method.
71 *
72 * Acesssing the registers on the Starfire is a little tricky. The
73 * Starfire has a 512K internal register space. When programmed for
74 * PCI memory mapped mode, the entire register space can be accessed
75 * directly. However in I/O space mode, only 256 bytes are directly
76 * mapped into PCI I/O space. The other registers can be accessed
77 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
78 * registers inside the 256-byte I/O window.
79 */
80
81 #include "bpfilter.h"
82
83 #include <sys/param.h>
84 #include <sys/systm.h>
85 #include <sys/sockio.h>
86 #include <sys/mbuf.h>
87 #include <sys/malloc.h>
88 #include <sys/kernel.h>
89 #include <sys/socket.h>
90
91 #include <net/if.h>
92 #include <net/if_arp.h>
93 #include <net/ethernet.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96
97 #if NBPFILTER > 0
98 #include <net/bpf.h>
99 #endif
100
101 #include <vm/vm.h> /* for vtophys */
102 #include <vm/pmap.h> /* for vtophys */
103 #include <machine/clock.h> /* for DELAY */
104 #include <machine/bus_pio.h>
105 #include <machine/bus_memio.h>
106 #include <machine/bus.h>
107
108 #include <pci/pcireg.h>
109 #include <pci/pcivar.h>
110
111 #define SF_USEIOSPACE
112
113 /* #define SF_BACKGROUND_AUTONEG */
114
115 #include <pci/if_sfreg.h>
116
117 #ifndef lint
118 static const char rcsid[] =
119 "$FreeBSD$";
120 #endif
121
122 static struct sf_type sf_devs[] = {
123 { AD_VENDORID, AD_DEVICEID_STARFIRE,
124 "Adaptec AIC-6915 10/100BaseTX" },
125 { 0, 0, NULL }
126 };
127
128 static struct sf_type sf_phys[] = {
129 { 0, 0, "<MII-compliant physical interface>" }
130 };
131
132 static unsigned long sf_count = 0;
133 static const char *sf_probe __P((pcici_t, pcidi_t));
134 static void sf_attach __P((pcici_t, int));
135 static void sf_intr __P((void *));
136 static void sf_stats_update __P((void *));
137 static void sf_rxeof __P((struct sf_softc *));
138 static void sf_txeof __P((struct sf_softc *));
139 static int sf_encap __P((struct sf_softc *,
140 struct sf_tx_bufdesc_type0 *,
141 struct mbuf *));
142 static void sf_start __P((struct ifnet *));
143 static int sf_ioctl __P((struct ifnet *, u_long, caddr_t));
144 static void sf_init __P((void *));
145 static void sf_stop __P((struct sf_softc *));
146 static void sf_watchdog __P((struct ifnet *));
147 static void sf_shutdown __P((int, void *));
148 static int sf_ifmedia_upd __P((struct ifnet *));
149 static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
150 static void sf_reset __P((struct sf_softc *));
151 static int sf_init_rx_ring __P((struct sf_softc *));
152 static void sf_init_tx_ring __P((struct sf_softc *));
153 static int sf_newbuf __P((struct sf_softc *,
154 struct sf_rx_bufdesc_type0 *,
155 struct mbuf *));
156 static void sf_setmulti __P((struct sf_softc *));
157 static int sf_setperf __P((struct sf_softc *, int, caddr_t));
158 static int sf_sethash __P((struct sf_softc *, caddr_t, int));
159 #ifdef notdef
160 static int sf_setvlan __P((struct sf_softc *, int, u_int32_t));
161 #endif
162
163 static u_int8_t sf_read_eeprom __P((struct sf_softc *, int));
164 static u_int32_t sf_calchash __P((caddr_t));
165
166 static int sf_phy_readreg __P((struct sf_softc *, int));
167 static void sf_phy_writereg __P((struct sf_softc *, int, int));
168 static void sf_autoneg_xmit __P((struct sf_softc *));
169 static void sf_autoneg_mii __P((struct sf_softc *, int, int));
170 static void sf_getmode_mii __P((struct sf_softc *));
171 static void sf_setmode_mii __P((struct sf_softc *, int));
172
173 static u_int32_t csr_read_4 __P((struct sf_softc *, int));
174 static void csr_write_4 __P((struct sf_softc *, int, u_int32_t));
175
176 #ifdef __i386__
177 #define SF_BUS_SPACE_MEM I386_BUS_SPACE_MEM
178 #define SF_BUS_SPACE_IO I386_BUS_SPACE_IO
179 #endif
180
181 #ifdef __alpha__
182 #define SF_BUS_SPACE_MEM ALPHA_BUS_SPACE_MEM
183 #define SF_BUS_SPACE_IO ALPHA_BUS_SPACE_IO
184 #endif
185
186 #define SF_SETBIT(sc, reg, x) \
187 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
188
189 #define SF_CLRBIT(sc, reg, x) \
190 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
191
192 static u_int32_t csr_read_4(sc, reg)
193 struct sf_softc *sc;
194 int reg;
195 {
196 u_int32_t val;
197
198 switch(sc->sf_btag) {
199 case SF_BUS_SPACE_MEM:
200 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
201 break;
202 case SF_BUS_SPACE_IO:
203 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
204 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
205 break;
206 default:
207 printf("sf%d: bad btag value\n", sc->sf_unit);
208 val = 0;
209 break;
210 }
211
212 return(val);
213 }
214
215 static u_int8_t sf_read_eeprom(sc, reg)
216 struct sf_softc *sc;
217 int reg;
218 {
219 u_int8_t val;
220
221 val = (csr_read_4(sc, SF_EEADDR_BASE +
222 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
223
224 return(val);
225 }
226
227 static void csr_write_4(sc, reg, val)
228 struct sf_softc *sc;
229 int reg;
230 u_int32_t val;
231 {
232 switch(sc->sf_btag) {
233 case SF_BUS_SPACE_MEM:
234 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
235 break;
236 case SF_BUS_SPACE_IO:
237 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
238 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
239 break;
240 default:
241 printf("sf%d: bad btag value\n", sc->sf_unit);
242 break;
243 }
244
245 return;
246 }
247
248 static u_int32_t sf_calchash(addr)
249 caddr_t addr;
250 {
251 u_int32_t crc, carry;
252 int i, j;
253 u_int8_t c;
254
255 /* Compute CRC for the address value. */
256 crc = 0xFFFFFFFF; /* initial value */
257
258 for (i = 0; i < 6; i++) {
259 c = *(addr + i);
260 for (j = 0; j < 8; j++) {
261 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
262 crc <<= 1;
263 c >>= 1;
264 if (carry)
265 crc = (crc ^ 0x04c11db6) | carry;
266 }
267 }
268
269 /* return the filter bit position */
270 return(crc >> 23 & 0x1FF);
271 }
272
273 /*
274 * Copy the address 'mac' into the perfect RX filter entry at
275 * offset 'ifx.' The perfect filter only has 16 entries so do
276 * some sanity tests.
277 */
278 static int sf_setperf(sc, idx, mac)
279 struct sf_softc *sc;
280 int idx;
281 caddr_t mac;
282 {
283 u_int16_t *p;
284
285 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
286 return(EINVAL);
287
288 if (mac == NULL)
289 return(EINVAL);
290
291 p = (u_int16_t *)mac;
292
293 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
294 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
295 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
296 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
297 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
298 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
299
300 return(0);
301 }
302
303 /*
304 * Set the bit in the 512-bit hash table that corresponds to the
305 * specified mac address 'mac.' If 'prio' is nonzero, update the
306 * priority hash table instead of the filter hash table.
307 */
308 static int sf_sethash(sc, mac, prio)
309 struct sf_softc *sc;
310 caddr_t mac;
311 int prio;
312 {
313 u_int32_t h = 0;
314
315 if (mac == NULL)
316 return(EINVAL);
317
318 h = sf_calchash(mac);
319
320 if (prio) {
321 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
322 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
323 } else {
324 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
325 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
326 }
327
328 return(0);
329 }
330
331 #ifdef notdef
332 /*
333 * Set a VLAN tag in the receive filter.
334 */
335 static int sf_setvlan(sc, idx, vlan)
336 struct sf_softc *sc;
337 int idx;
338 u_int32_t vlan;
339 {
340 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
341 return(EINVAL);
342
343 csr_write_4(sc, SF_RXFILT_HASH_BASE +
344 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
345
346 return(0);
347 }
348 #endif
349
350 static int sf_phy_readreg(sc, reg)
351 struct sf_softc *sc;
352 int reg;
353 {
354 int i;
355 u_int32_t val = 0;
356
357 for (i = 0; i < SF_TIMEOUT; i++) {
358 val = csr_read_4(sc, SF_PHY_REG(sc->sf_phy_addr, reg));
359 if (val & SF_MII_DATAVALID)
360 break;
361 }
362
363 if (i == SF_TIMEOUT)
364 return(0);
365
366 if ((val & 0x0000FFFF) == 0xFFFF)
367 return(0);
368
369 return(val & 0x0000FFFF);
370 }
371
372 static void sf_phy_writereg(sc, reg, val)
373 struct sf_softc *sc;
374 int reg, val;
375 {
376 int i;
377 int busy;
378
379 csr_write_4(sc, SF_PHY_REG(sc->sf_phy_addr, reg), val);
380
381 for (i = 0; i < SF_TIMEOUT; i++) {
382 busy = csr_read_4(sc, SF_PHY_REG(sc->sf_phy_addr, reg));
383 if (!(busy & SF_MII_BUSY))
384 break;
385 }
386
387 return;
388 }
389
390 static void sf_setmulti(sc)
391 struct sf_softc *sc;
392 {
393 struct ifnet *ifp;
394 int i;
395 struct ifmultiaddr *ifma;
396 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
397
398 ifp = &sc->arpcom.ac_if;
399
400 /* First zot all the existing filters. */
401 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
402 sf_setperf(sc, i, (char *)&dummy);
403 for (i = SF_RXFILT_HASH_BASE;
404 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
405 csr_write_4(sc, i, 0);
406 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
407
408 /* Now program new ones. */
409 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
410 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
411 } else {
412 i = 1;
413 /* First find the tail of the list. */
414 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
415 ifma = ifma->ifma_link.le_next) {
416 if (ifma->ifma_link.le_next == NULL)
417 break;
418 }
419 /* Now traverse the list backwards. */
420 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
421 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
422 if (ifma->ifma_addr->sa_family != AF_LINK)
423 continue;
424 /*
425 * Program the first 15 multicast groups
426 * into the perfect filter. For all others,
427 * use the hash table.
428 */
429 if (i < SF_RXFILT_PERFECT_CNT) {
430 sf_setperf(sc, i,
431 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
432 i++;
433 continue;
434 }
435
436 sf_sethash(sc,
437 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
438 }
439 }
440
441 return;
442 }
443
444 /*
445 * Initiate an autonegotiation session.
446 */
447 static void sf_autoneg_xmit(sc)
448 struct sf_softc *sc;
449 {
450 u_int16_t phy_sts;
451
452 sf_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
453 DELAY(500);
454 while(sf_phy_readreg(sc, PHY_BMCR)
455 & PHY_BMCR_RESET);
456
457 phy_sts = sf_phy_readreg(sc, PHY_BMCR);
458 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
459 sf_phy_writereg(sc, PHY_BMCR, phy_sts);
460
461 return;
462 }
463
464 /*
465 * Invoke autonegotiation on a PHY.
466 */
467 static void sf_autoneg_mii(sc, flag, verbose)
468 struct sf_softc *sc;
469 int flag;
470 int verbose;
471 {
472 u_int16_t phy_sts = 0, media, advert, ability;
473 struct ifnet *ifp;
474 struct ifmedia *ifm;
475
476 ifm = &sc->ifmedia;
477 ifp = &sc->arpcom.ac_if;
478
479 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
480
481 #ifndef FORCE_AUTONEG_TFOUR
482 /*
483 * First, see if autoneg is supported. If not, there's
484 * no point in continuing.
485 */
486 phy_sts = sf_phy_readreg(sc, PHY_BMSR);
487 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
488 if (verbose)
489 printf("sf%d: autonegotiation not supported\n",
490 sc->sf_unit);
491 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
492 return;
493 }
494 #endif
495
496 switch (flag) {
497 case SF_FLAG_FORCEDELAY:
498 /*
499 * XXX Never use this option anywhere but in the probe
500 * routine: making the kernel stop dead in its tracks
501 * for three whole seconds after we've gone multi-user
502 * is really bad manners.
503 */
504 sf_autoneg_xmit(sc);
505 DELAY(5000000);
506 break;
507 case SF_FLAG_SCHEDDELAY:
508 /*
509 * Wait for the transmitter to go idle before starting
510 * an autoneg session, otherwise sf_start() may clobber
511 * our timeout, and we don't want to allow transmission
512 * during an autoneg session since that can screw it up.
513 */
514 if (sc->sf_tx_cnt) {
515 sc->sf_want_auto = 1;
516 return;
517 }
518 sf_autoneg_xmit(sc);
519 ifp->if_timer = 5;
520 sc->sf_autoneg = 1;
521 sc->sf_want_auto = 0;
522 return;
523 break;
524 case SF_FLAG_DELAYTIMEO:
525 ifp->if_timer = 0;
526 sc->sf_autoneg = 0;
527 break;
528 default:
529 printf("sf%d: invalid autoneg flag: %d\n", sc->sf_unit, flag);
530 return;
531 }
532
533 if (sf_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
534 if (verbose)
535 printf("sf%d: autoneg complete, ", sc->sf_unit);
536 phy_sts = sf_phy_readreg(sc, PHY_BMSR);
537 } else {
538 if (verbose)
539 printf("sf%d: autoneg not complete, ", sc->sf_unit);
540 }
541
542 media = sf_phy_readreg(sc, PHY_BMCR);
543
544 /* Link is good. Report modes and set duplex mode. */
545 if (sf_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
546 if (verbose)
547 printf("link status good ");
548 advert = sf_phy_readreg(sc, PHY_ANAR);
549 ability = sf_phy_readreg(sc, PHY_LPAR);
550
551 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
552 ifm->ifm_media = IFM_ETHER|IFM_100_T4;
553 media |= PHY_BMCR_SPEEDSEL;
554 media &= ~PHY_BMCR_DUPLEX;
555 printf("(100baseT4)\n");
556 } else if (advert & PHY_ANAR_100BTXFULL &&
557 ability & PHY_ANAR_100BTXFULL) {
558 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
559 media |= PHY_BMCR_SPEEDSEL;
560 media |= PHY_BMCR_DUPLEX;
561 printf("(full-duplex, 100Mbps)\n");
562 } else if (advert & PHY_ANAR_100BTXHALF &&
563 ability & PHY_ANAR_100BTXHALF) {
564 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
565 media |= PHY_BMCR_SPEEDSEL;
566 media &= ~PHY_BMCR_DUPLEX;
567 printf("(half-duplex, 100Mbps)\n");
568 } else if (advert & PHY_ANAR_10BTFULL &&
569 ability & PHY_ANAR_10BTFULL) {
570 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
571 media &= ~PHY_BMCR_SPEEDSEL;
572 media |= PHY_BMCR_DUPLEX;
573 printf("(full-duplex, 10Mbps)\n");
574 } else if (advert & PHY_ANAR_10BTHALF &&
575 ability & PHY_ANAR_10BTHALF) {
576 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
577 media &= ~PHY_BMCR_SPEEDSEL;
578 media &= ~PHY_BMCR_DUPLEX;
579 printf("(half-duplex, 10Mbps)\n");
580 }
581
582 media &= ~PHY_BMCR_AUTONEGENBL;
583
584 /* Set ASIC's duplex mode to match the PHY. */
585 sf_phy_writereg(sc, PHY_BMCR, media);
586 if ((media & IFM_GMASK) == IFM_FDX) {
587 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
588 } else {
589 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
590 }
591 } else {
592 if (verbose)
593 printf("no carrier\n");
594 }
595
596 sf_init(sc);
597
598 if (sc->sf_tx_pend) {
599 sc->sf_autoneg = 0;
600 sc->sf_tx_pend = 0;
601 sf_start(ifp);
602 }
603
604 return;
605 }
606
607 static void sf_getmode_mii(sc)
608 struct sf_softc *sc;
609 {
610 u_int16_t bmsr;
611 struct ifnet *ifp;
612
613 ifp = &sc->arpcom.ac_if;
614
615 bmsr = sf_phy_readreg(sc, PHY_BMSR);
616 if (bootverbose)
617 printf("sf%d: PHY status word: %x\n", sc->sf_unit, bmsr);
618
619 /* fallback */
620 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
621
622 if (bmsr & PHY_BMSR_10BTHALF) {
623 if (bootverbose)
624 printf("sf%d: 10Mbps half-duplex mode supported\n",
625 sc->sf_unit);
626 ifmedia_add(&sc->ifmedia,
627 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
628 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
629 }
630
631 if (bmsr & PHY_BMSR_10BTFULL) {
632 if (bootverbose)
633 printf("sf%d: 10Mbps full-duplex mode supported\n",
634 sc->sf_unit);
635 ifmedia_add(&sc->ifmedia,
636 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
637 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
638 }
639
640 if (bmsr & PHY_BMSR_100BTXHALF) {
641 if (bootverbose)
642 printf("sf%d: 100Mbps half-duplex mode supported\n",
643 sc->sf_unit);
644 ifp->if_baudrate = 100000000;
645 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
646 ifmedia_add(&sc->ifmedia,
647 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
648 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
649 }
650
651 if (bmsr & PHY_BMSR_100BTXFULL) {
652 if (bootverbose)
653 printf("sf%d: 100Mbps full-duplex mode supported\n",
654 sc->sf_unit);
655 ifp->if_baudrate = 100000000;
656 ifmedia_add(&sc->ifmedia,
657 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
658 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
659 }
660
661 /* Some also support 100BaseT4. */
662 if (bmsr & PHY_BMSR_100BT4) {
663 if (bootverbose)
664 printf("sf%d: 100baseT4 mode supported\n", sc->sf_unit);
665 ifp->if_baudrate = 100000000;
666 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
667 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
668 #ifdef FORCE_AUTONEG_TFOUR
669 if (bootverbose)
670 printf("sf%d: forcing on autoneg support for BT4\n",
671 sc->sf_unit);
672 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
673 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
674 #endif
675 }
676
677 if (bmsr & PHY_BMSR_CANAUTONEG) {
678 if (bootverbose)
679 printf("sf%d: autoneg supported\n", sc->sf_unit);
680 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
681 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
682 }
683
684 return;
685 }
686
687 /*
688 * Set speed and duplex mode.
689 */
690 static void sf_setmode_mii(sc, media)
691 struct sf_softc *sc;
692 int media;
693 {
694 u_int16_t bmcr;
695 struct ifnet *ifp;
696
697 ifp = &sc->arpcom.ac_if;
698
699 /*
700 * If an autoneg session is in progress, stop it.
701 */
702 if (sc->sf_autoneg) {
703 printf("sf%d: canceling autoneg session\n", sc->sf_unit);
704 ifp->if_timer = sc->sf_autoneg = sc->sf_want_auto = 0;
705 bmcr = sf_phy_readreg(sc, PHY_BMCR);
706 bmcr &= ~PHY_BMCR_AUTONEGENBL;
707 sf_phy_writereg(sc, PHY_BMCR, bmcr);
708 }
709
710 printf("sf%d: selecting MII, ", sc->sf_unit);
711
712 bmcr = sf_phy_readreg(sc, PHY_BMCR);
713
714 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
715 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
716
717 if (IFM_SUBTYPE(media) == IFM_100_T4) {
718 printf("100Mbps/T4, half-duplex\n");
719 bmcr |= PHY_BMCR_SPEEDSEL;
720 bmcr &= ~PHY_BMCR_DUPLEX;
721 }
722
723 if (IFM_SUBTYPE(media) == IFM_100_TX) {
724 printf("100Mbps, ");
725 bmcr |= PHY_BMCR_SPEEDSEL;
726 }
727
728 if (IFM_SUBTYPE(media) == IFM_10_T) {
729 printf("10Mbps, ");
730 bmcr &= ~PHY_BMCR_SPEEDSEL;
731 }
732
733 if ((media & IFM_GMASK) == IFM_FDX) {
734 printf("full duplex\n");
735 bmcr |= PHY_BMCR_DUPLEX;
736 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
737 } else {
738 printf("half duplex\n");
739 bmcr &= ~PHY_BMCR_DUPLEX;
740 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
741 }
742
743 sf_phy_writereg(sc, PHY_BMCR, bmcr);
744
745 return;
746 }
747
748 /*
749 * Set media options.
750 */
751 static int sf_ifmedia_upd(ifp)
752 struct ifnet *ifp;
753 {
754 struct sf_softc *sc;
755 struct ifmedia *ifm;
756
757 sc = ifp->if_softc;
758 ifm = &sc->ifmedia;
759
760 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
761 return(EINVAL);
762
763 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
764 sf_autoneg_mii(sc, SF_FLAG_SCHEDDELAY, 1);
765 else {
766 sf_setmode_mii(sc, ifm->ifm_media);
767 }
768
769 return(0);
770 }
771
772 /*
773 * Report current media status.
774 */
775 static void sf_ifmedia_sts(ifp, ifmr)
776 struct ifnet *ifp;
777 struct ifmediareq *ifmr;
778 {
779 struct sf_softc *sc;
780 u_int16_t advert = 0, ability = 0;
781
782 sc = ifp->if_softc;
783
784 ifmr->ifm_active = IFM_ETHER;
785
786 if (!(sf_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
787 if (sf_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
788 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
789 else
790 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
791 if (sf_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
792 ifmr->ifm_active |= IFM_FDX;
793 else
794 ifmr->ifm_active |= IFM_HDX;
795 return;
796 }
797
798 ability = sf_phy_readreg(sc, PHY_LPAR);
799 advert = sf_phy_readreg(sc, PHY_ANAR);
800 if (advert & PHY_ANAR_100BT4 &&
801 ability & PHY_ANAR_100BT4) {
802 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
803 } else if (advert & PHY_ANAR_100BTXFULL &&
804 ability & PHY_ANAR_100BTXFULL) {
805 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
806 } else if (advert & PHY_ANAR_100BTXHALF &&
807 ability & PHY_ANAR_100BTXHALF) {
808 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
809 } else if (advert & PHY_ANAR_10BTFULL &&
810 ability & PHY_ANAR_10BTFULL) {
811 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
812 } else if (advert & PHY_ANAR_10BTHALF &&
813 ability & PHY_ANAR_10BTHALF) {
814 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
815 }
816
817 return;
818 }
819
820 static int sf_ioctl(ifp, command, data)
821 struct ifnet *ifp;
822 u_long command;
823 caddr_t data;
824 {
825 struct sf_softc *sc = ifp->if_softc;
826 struct ifreq *ifr = (struct ifreq *) data;
827 int s, error = 0;
828
829 s = splimp();
830
831 switch(command) {
832 case SIOCSIFADDR:
833 case SIOCGIFADDR:
834 case SIOCSIFMTU:
835 error = ether_ioctl(ifp, command, data);
836 break;
837 case SIOCSIFFLAGS:
838 if (ifp->if_flags & IFF_UP) {
839 sf_init(sc);
840 } else {
841 if (ifp->if_flags & IFF_RUNNING)
842 sf_stop(sc);
843 }
844 error = 0;
845 break;
846 case SIOCADDMULTI:
847 case SIOCDELMULTI:
848 sf_setmulti(sc);
849 error = 0;
850 break;
851 case SIOCGIFMEDIA:
852 case SIOCSIFMEDIA:
853 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
854 break;
855 default:
856 error = EINVAL;
857 break;
858 }
859
860 (void)splx(s);
861
862 return(error);
863 }
864
865 static void sf_reset(sc)
866 struct sf_softc *sc;
867 {
868 register int i;
869
870 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
871 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
872 DELAY(1000);
873 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
874
875 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
876
877 for (i = 0; i < SF_TIMEOUT; i++) {
878 DELAY(10);
879 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
880 break;
881 }
882
883 if (i == SF_TIMEOUT)
884 printf("sf%d: reset never completed!\n", sc->sf_unit);
885
886 /* Wait a little while for the chip to get its brains in order. */
887 DELAY(1000);
888 return;
889 }
890
891 /*
892 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
893 * IDs against our list and return a device name if we find a match.
894 * We also check the subsystem ID so that we can identify exactly which
895 * NIC has been found, if possible.
896 */
897 static const char *sf_probe(config_id, device_id)
898 pcici_t config_id;
899 pcidi_t device_id;
900 {
901 struct sf_type *t;
902
903 t = sf_devs;
904
905 while(t->sf_name != NULL) {
906 if ((device_id & 0xFFFF) == t->sf_vid &&
907 ((device_id >> 16) & 0xFFFF) == t->sf_did) {
908 switch((pci_conf_read(config_id,
909 SF_PCI_SUBVEN_ID) >> 16) & 0x8FFF) {
910 case AD_SUBSYSID_62011_REV0:
911 case AD_SUBSYSID_62011_REV1:
912 return("Adaptec ANA-62011 10/100BaseTX");
913 break;
914 case AD_SUBSYSID_62022:
915 return("Adaptec ANA-62022 10/100BaseTX");
916 break;
917 case AD_SUBSYSID_62044:
918 return("Adaptec ANA-62044 10/100BaseTX");
919 break;
920 case AD_SUBSYSID_62020:
921 return("Adaptec ANA-62020 10/100BaseFX");
922 break;
923 case AD_SUBSYSID_69011:
924 return("Adaptec ANA-69011 10/100BaseTX");
925 break;
926 default:
927 return(t->sf_name);
928 break;
929 }
930 }
931 t++;
932 }
933
934 return(NULL);
935 }
936
937 /*
938 * Attach the interface. Allocate softc structures, do ifmedia
939 * setup and ethernet/BPF attach.
940 */
941 static void
942 sf_attach(config_id, unit)
943 pcici_t config_id;
944 int unit;
945 {
946 int s, i;
947 #ifndef SF_USEIOSPACE
948 vm_offset_t pbase, vbase;
949 #endif
950 u_int32_t command;
951 struct sf_softc *sc;
952 struct ifnet *ifp;
953 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
954 struct sf_type *p;
955 u_int16_t phy_vid, phy_did, phy_sts;
956
957 s = splimp();
958
959 sc = malloc(sizeof(struct sf_softc), M_DEVBUF, M_NOWAIT);
960 if (sc == NULL) {
961 printf("sf%d: no memory for softc struct!\n", unit);
962 goto fail;
963 }
964 bzero(sc, sizeof(struct sf_softc));
965
966 /*
967 * Handle power management nonsense.
968 */
969 command = pci_conf_read(config_id, SF_PCI_CAPID) & 0x000000FF;
970 if (command == 0x01) {
971
972 command = pci_conf_read(config_id, SF_PCI_PWRMGMTCTRL);
973 if (command & SF_PSTATE_MASK) {
974 u_int32_t iobase, membase, irq;
975
976 /* Save important PCI config data. */
977 iobase = pci_conf_read(config_id, SF_PCI_LOIO);
978 membase = pci_conf_read(config_id, SF_PCI_LOMEM);
979 irq = pci_conf_read(config_id, SF_PCI_INTLINE);
980
981 /* Reset the power state. */
982 printf("sf%d: chip is in D%d power mode "
983 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
984 command &= 0xFFFFFFFC;
985 pci_conf_write(config_id, SF_PCI_PWRMGMTCTRL, command);
986
987 /* Restore PCI config data. */
988 pci_conf_write(config_id, SF_PCI_LOIO, iobase);
989 pci_conf_write(config_id, SF_PCI_LOMEM, membase);
990 pci_conf_write(config_id, SF_PCI_INTLINE, irq);
991 }
992 }
993
994 /*
995 * Map control/status registers.
996 */
997 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
998 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
999 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1000 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1001
1002 #ifdef SF_USEIOSPACE
1003 if (!(command & PCIM_CMD_PORTEN)) {
1004 printf("sf%d: failed to enable I/O ports!\n", unit);
1005 free(sc, M_DEVBUF);
1006 goto fail;
1007 }
1008
1009 if (!pci_map_port(config_id, SF_PCI_LOIO,
1010 (u_short *)&(sc->sf_bhandle))) {
1011 printf ("sf%d: couldn't map ports\n", unit);
1012 goto fail;
1013 }
1014
1015 sc->sf_btag = SF_BUS_SPACE_IO;
1016 #else
1017 if (!(command & PCIM_CMD_MEMEN)) {
1018 printf("sf%d: failed to enable memory mapping!\n", unit);
1019 goto fail;
1020 }
1021
1022 if (!pci_map_mem(config_id, SF_PCI_LOMEM, &vbase, &pbase)) {
1023 printf ("sf%d: couldn't map memory\n", unit);
1024 goto fail;
1025 }
1026 sc->sf_btag = SF_BUS_SPACE_MEM;
1027 sc->sf_bhandle = vbase;
1028 #endif
1029
1030 /* Allocate interrupt */
1031 if (!pci_map_int(config_id, sf_intr, sc, &net_imask)) {
1032 printf("sf%d: couldn't map interrupt\n", unit);
1033 goto fail;
1034 }
1035
1036 callout_handle_init(&sc->sf_stat_ch);
1037
1038 /* Reset the adapter. */
1039 sf_reset(sc);
1040
1041 /*
1042 * Get station address from the EEPROM.
1043 */
1044 for (i = 0; i < ETHER_ADDR_LEN; i++)
1045 sc->arpcom.ac_enaddr[i] =
1046 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
1047
1048 /*
1049 * An Adaptec chip was detected. Inform the world.
1050 */
1051 printf("sf%d: Ethernet address: %6D\n", unit,
1052 sc->arpcom.ac_enaddr, ":");
1053
1054 sc->sf_unit = unit;
1055
1056 /* Allocate the descriptor queues. */
1057 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
1058 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
1059
1060 if (sc->sf_ldata == NULL) {
1061 free(sc, M_DEVBUF);
1062 printf("sf%d: no memory for list buffers!\n", unit);
1063 goto fail;
1064 }
1065
1066 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
1067
1068 if (bootverbose)
1069 printf("sf%d: probing for a PHY\n", sc->sf_unit);
1070 for (i = SF_PHYADDR_MIN; i < SF_PHYADDR_MAX + 1; i++) {
1071 if (bootverbose)
1072 printf("sf%d: checking address: %d\n",
1073 sc->sf_unit, i);
1074 sc->sf_phy_addr = i;
1075 sf_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1076 DELAY(500);
1077 while(sf_phy_readreg(sc, PHY_BMCR)
1078 & PHY_BMCR_RESET);
1079 if ((phy_sts = sf_phy_readreg(sc, PHY_BMSR)))
1080 break;
1081 }
1082 if (phy_sts) {
1083 phy_vid = sf_phy_readreg(sc, PHY_VENID);
1084 phy_did = sf_phy_readreg(sc, PHY_DEVID);
1085 if (bootverbose)
1086 printf("sf%d: found PHY at address %d, ",
1087 sc->sf_unit, sc->sf_phy_addr);
1088 if (bootverbose)
1089 printf("vendor id: %x device id: %x\n",
1090 phy_vid, phy_did);
1091 p = sf_phys;
1092 while(p->sf_vid) {
1093 if (phy_vid == p->sf_vid &&
1094 (phy_did | 0x000F) == p->sf_did) {
1095 sc->sf_pinfo = p;
1096 break;
1097 }
1098 p++;
1099 }
1100 if (sc->sf_pinfo == NULL)
1101 sc->sf_pinfo = &sf_phys[PHY_UNKNOWN];
1102 if (bootverbose)
1103 printf("sf%d: PHY type: %s\n",
1104 sc->sf_unit, sc->sf_pinfo->sf_name);
1105 } else {
1106 printf("sf%d: MII without any phy!\n", sc->sf_unit);
1107 free(sc->sf_ldata, M_DEVBUF);
1108 free(sc, M_DEVBUF);
1109 goto fail;
1110 }
1111
1112 ifp = &sc->arpcom.ac_if;
1113 ifp->if_softc = sc;
1114 ifp->if_unit = unit;
1115 ifp->if_name = "sf";
1116 ifp->if_mtu = ETHERMTU;
1117 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1118 ifp->if_ioctl = sf_ioctl;
1119 ifp->if_output = ether_output;
1120 ifp->if_start = sf_start;
1121 ifp->if_watchdog = sf_watchdog;
1122 ifp->if_init = sf_init;
1123 ifp->if_baudrate = 10000000;
1124 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1;
1125
1126 /*
1127 * Do ifmedia setup.
1128 */
1129 ifmedia_init(&sc->ifmedia, 0, sf_ifmedia_upd, sf_ifmedia_sts);
1130
1131 sf_getmode_mii(sc);
1132 sf_autoneg_mii(sc, SF_FLAG_FORCEDELAY, 1);
1133 media = sc->ifmedia.ifm_media;
1134 sf_stop(sc);
1135
1136 ifmedia_set(&sc->ifmedia, media);
1137
1138 /*
1139 * Call MI attach routines.
1140 */
1141 if_attach(ifp);
1142 ether_ifattach(ifp);
1143
1144 #if NBPFILTER > 0
1145 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1146 #endif
1147
1148 at_shutdown(sf_shutdown, sc, SHUTDOWN_POST_SYNC);
1149
1150 fail:
1151 splx(s);
1152 return;
1153 }
1154
1155 static int sf_init_rx_ring(sc)
1156 struct sf_softc *sc;
1157 {
1158 struct sf_list_data *ld;
1159 int i;
1160
1161 ld = sc->sf_ldata;
1162
1163 bzero((char *)ld->sf_rx_dlist_big,
1164 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
1165 bzero((char *)ld->sf_rx_clist,
1166 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
1167
1168 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1169 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
1170 return(ENOBUFS);
1171 }
1172
1173 return(0);
1174 }
1175
1176 static void sf_init_tx_ring(sc)
1177 struct sf_softc *sc;
1178 {
1179 struct sf_list_data *ld;
1180 int i;
1181
1182 ld = sc->sf_ldata;
1183
1184 bzero((char *)ld->sf_tx_dlist,
1185 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
1186 bzero((char *)ld->sf_tx_clist,
1187 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
1188
1189 for (i = 0; i < SF_TX_DLIST_CNT; i++)
1190 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
1191 for (i = 0; i < SF_TX_CLIST_CNT; i++)
1192 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
1193
1194 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
1195 sc->sf_tx_cnt = 0;
1196
1197 return;
1198 }
1199
1200 static int sf_newbuf(sc, c, m)
1201 struct sf_softc *sc;
1202 struct sf_rx_bufdesc_type0 *c;
1203 struct mbuf *m;
1204 {
1205 struct mbuf *m_new = NULL;
1206
1207 if (m == NULL) {
1208 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1209 if (m_new == NULL) {
1210 printf("sf%d: no memory for rx list -- "
1211 "packet dropped!\n", sc->sf_unit);
1212 return(ENOBUFS);
1213 }
1214
1215 MCLGET(m_new, M_DONTWAIT);
1216 if (!(m_new->m_flags & M_EXT)) {
1217 printf("sf%d: no memory for rx list -- "
1218 "packet dropped!\n", sc->sf_unit);
1219 m_freem(m_new);
1220 return(ENOBUFS);
1221 }
1222 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1223 } else {
1224 m_new = m;
1225 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1226 m_new->m_data = m_new->m_ext.ext_buf;
1227 }
1228
1229 m_adj(m_new, sizeof(u_int64_t));
1230
1231 c->sf_mbuf = m_new;
1232 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
1233 c->sf_valid = 1;
1234
1235 return(0);
1236 }
1237
1238 /*
1239 * The starfire is programmed to use 'normal' mode for packet reception,
1240 * which means we use the consumer/producer model for both the buffer
1241 * descriptor queue and the completion descriptor queue. The only problem
1242 * with this is that it involves a lot of register accesses: we have to
1243 * read the RX completion consumer and producer indexes and the RX buffer
1244 * producer index, plus the RX completion consumer and RX buffer producer
1245 * indexes have to be updated. It would have been easier if Adaptec had
1246 * put each index in a separate register, especially given that the damn
1247 * NIC has a 512K register space.
1248 *
1249 * In spite of all the lovely features that Adaptec crammed into the 6915,
1250 * it is marred by one truly stupid design flaw, which is that receive
1251 * buffer addresses must be aligned on a longword boundary. This forces
1252 * the packet payload to be unaligned, which is suboptimal on the x86 and
1253 * completely unuseable on the Alpha. Our only recourse is to copy received
1254 * packets into properly aligned buffers before handing them off.
1255 */
1256
1257 static void sf_rxeof(sc)
1258 struct sf_softc *sc;
1259 {
1260 struct ether_header *eh;
1261 struct mbuf *m;
1262 struct ifnet *ifp;
1263 struct sf_rx_bufdesc_type0 *desc;
1264 struct sf_rx_cmpdesc_type3 *cur_rx;
1265 u_int32_t rxcons, rxprod;
1266 int cmpprodidx, cmpconsidx, bufprodidx;
1267
1268 ifp = &sc->arpcom.ac_if;
1269
1270 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
1271 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
1272 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
1273 cmpconsidx = SF_IDX_LO(rxcons);
1274 bufprodidx = SF_IDX_LO(rxprod);
1275
1276 while (cmpconsidx != cmpprodidx) {
1277 struct mbuf *m0;
1278
1279 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
1280 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
1281 m = desc->sf_mbuf;
1282 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
1283 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
1284
1285 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
1286 ifp->if_ierrors++;
1287 sf_newbuf(sc, desc, m);
1288 continue;
1289 }
1290
1291 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1292 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
1293 sf_newbuf(sc, desc, m);
1294 if (m0 == NULL) {
1295 ifp->if_ierrors++;
1296 continue;
1297 }
1298 m_adj(m0, ETHER_ALIGN);
1299 m = m0;
1300
1301 eh = mtod(m, struct ether_header *);
1302 ifp->if_ipackets++;
1303
1304 #if NBPFILTER > 0
1305 if (ifp->if_bpf) {
1306 bpf_mtap(ifp, m);
1307 if (ifp->if_flags & IFF_PROMISC &&
1308 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1309 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) {
1310 m_freem(m);
1311 continue;
1312 }
1313 }
1314 #endif
1315
1316 /* Remove header from mbuf and pass it on. */
1317 m_adj(m, sizeof(struct ether_header));
1318 ether_input(ifp, eh, m);
1319
1320 }
1321
1322 csr_write_4(sc, SF_CQ_CONSIDX,
1323 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
1324 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1325 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
1326
1327 return;
1328 }
1329
1330 /*
1331 * Read the transmit status from the completion queue and release
1332 * mbufs. Note that the buffer descriptor index in the completion
1333 * descriptor is an offset from the start of the transmit buffer
1334 * descriptor list in bytes. This is important because the manual
1335 * gives the impression that it should match the producer/consumer
1336 * index, which is the offset in 8 byte blocks.
1337 */
1338 static void sf_txeof(sc)
1339 struct sf_softc *sc;
1340 {
1341 int txcons, cmpprodidx, cmpconsidx;
1342 struct sf_tx_cmpdesc_type1 *cur_cmp;
1343 struct sf_tx_bufdesc_type0 *cur_tx;
1344 struct ifnet *ifp;
1345
1346 ifp = &sc->arpcom.ac_if;
1347
1348 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1349 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1350 cmpconsidx = SF_IDX_HI(txcons);
1351
1352 while (cmpconsidx != cmpprodidx) {
1353 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1354 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1355 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1356
1357 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1358 ifp->if_opackets++;
1359 else
1360 ifp->if_oerrors++;
1361
1362 sc->sf_tx_cnt--;
1363 if (cur_tx->sf_mbuf != NULL) {
1364 m_freem(cur_tx->sf_mbuf);
1365 cur_tx->sf_mbuf = NULL;
1366 }
1367 }
1368
1369 ifp->if_timer = 0;
1370 ifp->if_flags &= ~IFF_OACTIVE;
1371
1372 csr_write_4(sc, SF_CQ_CONSIDX,
1373 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1374 ((cmpconsidx << 16) & 0xFFFF0000));
1375
1376 return;
1377 }
1378
1379 static void sf_intr(arg)
1380 void *arg;
1381 {
1382 struct sf_softc *sc;
1383 struct ifnet *ifp;
1384 u_int32_t status;
1385
1386 sc = arg;
1387 ifp = &sc->arpcom.ac_if;
1388
1389 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
1390 return;
1391
1392 /* Disable interrupts. */
1393 csr_write_4(sc, SF_IMR, 0x00000000);
1394
1395 for (;;) {
1396 status = csr_read_4(sc, SF_ISR);
1397 if (status)
1398 csr_write_4(sc, SF_ISR, status);
1399
1400 if (!(status & SF_INTRS))
1401 break;
1402
1403 if (status & SF_ISR_RXDQ1_DMADONE)
1404 sf_rxeof(sc);
1405
1406 if (status & SF_ISR_TX_TXDONE)
1407 sf_txeof(sc);
1408
1409 if (status & SF_ISR_ABNORMALINTR) {
1410 if (status & SF_ISR_STATSOFLOW) {
1411 untimeout(sf_stats_update, sc,
1412 sc->sf_stat_ch);
1413 sf_stats_update(sc);
1414 } else
1415 sf_init(sc);
1416 }
1417 }
1418
1419 /* Re-enable interrupts. */
1420 csr_write_4(sc, SF_IMR, SF_INTRS);
1421
1422 if (ifp->if_snd.ifq_head != NULL)
1423 sf_start(ifp);
1424
1425 return;
1426 }
1427
1428 static void sf_init(xsc)
1429 void *xsc;
1430 {
1431 struct sf_softc *sc;
1432 struct ifnet *ifp;
1433 int i, s;
1434
1435 s = splimp();
1436
1437 sc = xsc;
1438 ifp = &sc->arpcom.ac_if;
1439
1440 sf_stop(sc);
1441 sf_reset(sc);
1442
1443 /* Init all the receive filter registers */
1444 for (i = SF_RXFILT_PERFECT_BASE;
1445 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1446 csr_write_4(sc, i, 0);
1447
1448 /* Empty stats counter registers */
1449 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1450 csr_write_4(sc, SF_STATS_BASE +
1451 (i + sizeof(u_int32_t)), 0);
1452
1453 /* Init our MAC address */
1454 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1455 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1456 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1457
1458 if (sf_init_rx_ring(sc) == ENOBUFS) {
1459 printf("sf%d: initialization failed: no "
1460 "memory for rx buffers\n", sc->sf_unit);
1461 (void)splx(s);
1462 return;
1463 }
1464
1465 sf_init_tx_ring(sc);
1466
1467 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1468
1469 /* If we want promiscuous mode, set the allframes bit. */
1470 if (ifp->if_flags & IFF_PROMISC) {
1471 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1472 } else {
1473 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1474 }
1475
1476 if (ifp->if_flags & IFF_BROADCAST) {
1477 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1478 } else {
1479 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1480 }
1481
1482 /* Init the completion queue indexes */
1483 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1484 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1485
1486 /* Init the RX completion queue */
1487 csr_write_4(sc, SF_RXCQ_CTL_1,
1488 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1489 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1490
1491 /* Init RX DMA control. */
1492 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1493
1494 /* Init the RX buffer descriptor queue. */
1495 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1496 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1497 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1498 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1499
1500 /* Init the TX completion queue */
1501 csr_write_4(sc, SF_TXCQ_CTL,
1502 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1503
1504 /* Init the TX buffer descriptor queue. */
1505 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1506 vtophys(sc->sf_ldata->sf_tx_dlist));
1507 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1508 csr_write_4(sc, SF_TXDQ_CTL,
1509 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1510 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1511
1512 /* Enable autopadding of short TX frames. */
1513 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1514
1515 /* Make sure the duplex mode is set correctly. */
1516 if ((sc->ifmedia.ifm_media & IFM_GMASK) == IFM_FDX) {
1517 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
1518 } else {
1519 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
1520 }
1521
1522 /* Enable interrupts. */
1523 csr_write_4(sc, SF_IMR, SF_INTRS);
1524 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1525
1526 /* Enable the RX and TX engines. */
1527 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1528 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1529
1530 ifp->if_flags |= IFF_RUNNING;
1531 ifp->if_flags &= ~IFF_OACTIVE;
1532
1533 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1534
1535 splx(s);
1536
1537 return;
1538 }
1539
1540 static int sf_encap(sc, c, m_head)
1541 struct sf_softc *sc;
1542 struct sf_tx_bufdesc_type0 *c;
1543 struct mbuf *m_head;
1544 {
1545 int frag = 0;
1546 struct sf_frag *f = NULL;
1547 struct mbuf *m;
1548
1549 m = m_head;
1550
1551 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1552 if (m->m_len != 0) {
1553 if (frag == SF_MAXFRAGS)
1554 break;
1555 f = &c->sf_frags[frag];
1556 if (frag == 0)
1557 f->sf_pktlen = m_head->m_pkthdr.len;
1558 f->sf_fraglen = m->m_len;
1559 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1560 frag++;
1561 }
1562 }
1563
1564 if (m != NULL) {
1565 struct mbuf *m_new = NULL;
1566
1567 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1568 if (m_new == NULL) {
1569 printf("sf%d: no memory for tx list", sc->sf_unit);
1570 return(1);
1571 }
1572
1573 if (m_head->m_pkthdr.len > MHLEN) {
1574 MCLGET(m_new, M_DONTWAIT);
1575 if (!(m_new->m_flags & M_EXT)) {
1576 m_freem(m_new);
1577 printf("sf%d: no memory for tx list",
1578 sc->sf_unit);
1579 return(1);
1580 }
1581 }
1582 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1583 mtod(m_new, caddr_t));
1584 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1585 m_freem(m_head);
1586 m_head = m_new;
1587 f = &c->sf_frags[0];
1588 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1589 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1590 frag = 1;
1591 }
1592
1593 c->sf_mbuf = m_head;
1594 c->sf_id = SF_TX_BUFDESC_ID;
1595 c->sf_fragcnt = frag;
1596 c->sf_intr = 1;
1597 c->sf_caltcp = 0;
1598 c->sf_crcen = 1;
1599
1600 return(0);
1601 }
1602
1603 static void sf_start(ifp)
1604 struct ifnet *ifp;
1605 {
1606 struct sf_softc *sc;
1607 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1608 struct mbuf *m_head = NULL;
1609 int i, txprod;
1610
1611 sc = ifp->if_softc;
1612
1613 if (ifp->if_flags & IFF_OACTIVE)
1614 return;
1615
1616 if (sc->sf_autoneg) {
1617 sc->sf_tx_pend = 1;
1618 return;
1619 }
1620
1621 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1622 i = SF_IDX_HI(txprod) >> 4;
1623
1624 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1625 IF_DEQUEUE(&ifp->if_snd, m_head);
1626 if (m_head == NULL)
1627 break;
1628
1629 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1630 sf_encap(sc, cur_tx, m_head);
1631
1632 /*
1633 * If there's a BPF listener, bounce a copy of this frame
1634 * to him.
1635 */
1636 #if NBPFILTER > 0
1637 if (ifp->if_bpf)
1638 bpf_mtap(ifp, m_head);
1639 #endif
1640 SF_INC(i, SF_TX_DLIST_CNT);
1641 sc->sf_tx_cnt++;
1642 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2))
1643 break;
1644 }
1645
1646 if (cur_tx == NULL)
1647 return;
1648
1649 /* Transmit */
1650 csr_write_4(sc, SF_TXDQ_PRODIDX,
1651 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1652 ((i << 20) & 0xFFFF0000));
1653
1654 ifp->if_timer = 5;
1655
1656 return;
1657 }
1658
1659 static void sf_stop(sc)
1660 struct sf_softc *sc;
1661 {
1662 int i;
1663 struct ifnet *ifp;
1664
1665 ifp = &sc->arpcom.ac_if;
1666
1667 untimeout(sf_stats_update, sc, sc->sf_stat_ch);
1668
1669 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1670 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1671 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1672 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1673 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1674 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1675 csr_write_4(sc, SF_TXCQ_CTL, 0);
1676 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1677 csr_write_4(sc, SF_TXDQ_CTL, 0);
1678 sf_reset(sc);
1679
1680 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1681 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1682 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1683 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1684 }
1685 }
1686
1687 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1688 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1689 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1690 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1691 }
1692 }
1693
1694 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1695
1696 return;
1697 }
1698
1699 /*
1700 * Note: it is important that this function not be interrupted. We
1701 * use a two-stage register access scheme: if we are interrupted in
1702 * between setting the indirect address register and reading from the
1703 * indirect data register, the contents of the address register could
1704 * be changed out from under us.
1705 */
1706 static void sf_stats_update(xsc)
1707 void *xsc;
1708 {
1709 struct sf_softc *sc;
1710 struct ifnet *ifp;
1711 struct sf_stats stats;
1712 u_int32_t *ptr;
1713 int i, s;
1714
1715 s = splimp();
1716
1717 sc = xsc;
1718 ifp = &sc->arpcom.ac_if;
1719
1720 ptr = (u_int32_t *)&stats;
1721 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1722 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1723 (i + sizeof(u_int32_t)));
1724
1725 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1726 csr_write_4(sc, SF_STATS_BASE +
1727 (i + sizeof(u_int32_t)), 0);
1728
1729 ifp->if_collisions += stats.sf_tx_single_colls +
1730 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1731
1732 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1733
1734 splx(s);
1735
1736 return;
1737 }
1738
1739 static void sf_watchdog(ifp)
1740 struct ifnet *ifp;
1741 {
1742 struct sf_softc *sc;
1743
1744 sc = ifp->if_softc;
1745
1746 if (sc->sf_autoneg) {
1747 sf_autoneg_mii(sc, SF_FLAG_DELAYTIMEO, 1);
1748 return;
1749 }
1750
1751 ifp->if_oerrors++;
1752 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1753
1754 if (sc->sf_pinfo != NULL) {
1755 if (!(sf_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1756 printf("sf%d: no carrier - transceiver "
1757 "cable problem?\n", sc->sf_unit);
1758 }
1759
1760 sf_stop(sc);
1761 sf_reset(sc);
1762 sf_init(sc);
1763
1764 if (ifp->if_snd.ifq_head != NULL)
1765 sf_start(ifp);
1766
1767 return;
1768 }
1769
1770 static void sf_shutdown(howto, arg)
1771 int howto;
1772 void *arg;
1773 {
1774 struct sf_softc *sc;
1775
1776 sc = (struct sf_softc *)arg;
1777
1778 sf_stop(sc);
1779
1780 return;
1781 }
1782
1783 static struct pci_device sf_device = {
1784 "sf",
1785 sf_probe,
1786 sf_attach,
1787 &sf_count,
1788 NULL
1789 };
1790
1791 #ifdef COMPAT_PCI_DRIVER
1792 COMPAT_PCI_DRIVER(sf, sf_device);
1793 #else
1794 DATA_SET(pcidevice_set, sf_device);
1795 #endif
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