Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sf.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/sockio.h> 85 #include <sys/mbuf.h> 86 #include <sys/malloc.h> 87 #include <sys/kernel.h> 88 #include <sys/socket.h> 89 90 #include <net/if.h> 91 #include <net/if_arp.h> 92 #include <net/ethernet.h> 93 #include <net/if_dl.h> 94 #include <net/if_media.h> 95 96 #include <net/bpf.h> 97 98 #include <vm/vm.h> /* for vtophys */ 99 #include <vm/pmap.h> /* for vtophys */ 100 #include <machine/clock.h> /* for DELAY */ 101 #include <machine/bus_pio.h> 102 #include <machine/bus_memio.h> 103 #include <machine/bus.h> 104 #include <machine/resource.h> 105 #include <sys/bus.h> 106 #include <sys/rman.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 /* "controller miibus0" required. See GENERIC if you get errors here. */ 112 #include "miibus_if.h" 113 114 #include <pci/pcireg.h> 115 #include <pci/pcivar.h> 116 117 #define SF_USEIOSPACE 118 119 #include <pci/if_sfreg.h> 120 121 #ifndef lint 122 static const char rcsid[] = 123 "$FreeBSD$"; 124 #endif 125 126 static struct sf_type sf_devs[] = { 127 { AD_VENDORID, AD_DEVICEID_STARFIRE, 128 "Adaptec AIC-6915 10/100BaseTX" }, 129 { 0, 0, NULL } 130 }; 131 132 static int sf_probe __P((device_t)); 133 static int sf_attach __P((device_t)); 134 static int sf_detach __P((device_t)); 135 static void sf_intr __P((void *)); 136 static void sf_stats_update __P((void *)); 137 static void sf_rxeof __P((struct sf_softc *)); 138 static void sf_txeof __P((struct sf_softc *)); 139 static int sf_encap __P((struct sf_softc *, 140 struct sf_tx_bufdesc_type0 *, 141 struct mbuf *)); 142 static void sf_start __P((struct ifnet *)); 143 static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 144 static void sf_init __P((void *)); 145 static void sf_stop __P((struct sf_softc *)); 146 static void sf_watchdog __P((struct ifnet *)); 147 static void sf_shutdown __P((device_t)); 148 static int sf_ifmedia_upd __P((struct ifnet *)); 149 static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 150 static void sf_reset __P((struct sf_softc *)); 151 static int sf_init_rx_ring __P((struct sf_softc *)); 152 static void sf_init_tx_ring __P((struct sf_softc *)); 153 static int sf_newbuf __P((struct sf_softc *, 154 struct sf_rx_bufdesc_type0 *, 155 struct mbuf *)); 156 static void sf_setmulti __P((struct sf_softc *)); 157 static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 158 static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 159 #ifdef notdef 160 static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 161 #endif 162 163 static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 164 static u_int32_t sf_calchash __P((caddr_t)); 165 166 static int sf_miibus_readreg __P((device_t, int, int)); 167 static int sf_miibus_writereg __P((device_t, int, int, int)); 168 static void sf_miibus_statchg __P((device_t)); 169 170 static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 171 static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 172 static void sf_txthresh_adjust __P((struct sf_softc *)); 173 174 #ifdef SF_USEIOSPACE 175 #define SF_RES SYS_RES_IOPORT 176 #define SF_RID SF_PCI_LOIO 177 #else 178 #define SF_RES SYS_RES_MEMORY 179 #define SF_RID SF_PCI_LOMEM 180 #endif 181 182 static device_method_t sf_methods[] = { 183 /* Device interface */ 184 DEVMETHOD(device_probe, sf_probe), 185 DEVMETHOD(device_attach, sf_attach), 186 DEVMETHOD(device_detach, sf_detach), 187 DEVMETHOD(device_shutdown, sf_shutdown), 188 189 /* bus interface */ 190 DEVMETHOD(bus_print_child, bus_generic_print_child), 191 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 192 193 /* MII interface */ 194 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 195 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 196 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 197 198 { 0, 0 } 199 }; 200 201 static driver_t sf_driver = { 202 "sf", 203 sf_methods, 204 sizeof(struct sf_softc), 205 }; 206 207 static devclass_t sf_devclass; 208 209 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 210 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 211 212 #define SF_SETBIT(sc, reg, x) \ 213 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 214 215 #define SF_CLRBIT(sc, reg, x) \ 216 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 217 218 static u_int32_t csr_read_4(sc, reg) 219 struct sf_softc *sc; 220 int reg; 221 { 222 u_int32_t val; 223 224 #ifdef SF_USEIOSPACE 225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 227 #else 228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 229 #endif 230 231 return(val); 232 } 233 234 static u_int8_t sf_read_eeprom(sc, reg) 235 struct sf_softc *sc; 236 int reg; 237 { 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244 } 245 246 static void csr_write_4(sc, reg, val) 247 struct sf_softc *sc; 248 int reg; 249 u_int32_t val; 250 { 251 #ifdef SF_USEIOSPACE 252 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 253 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 254 #else 255 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 256 #endif 257 return; 258 } 259 260 static u_int32_t sf_calchash(addr) 261 caddr_t addr; 262 { 263 u_int32_t crc, carry; 264 int i, j; 265 u_int8_t c; 266 267 /* Compute CRC for the address value. */ 268 crc = 0xFFFFFFFF; /* initial value */ 269 270 for (i = 0; i < 6; i++) { 271 c = *(addr + i); 272 for (j = 0; j < 8; j++) { 273 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 274 crc <<= 1; 275 c >>= 1; 276 if (carry) 277 crc = (crc ^ 0x04c11db6) | carry; 278 } 279 } 280 281 /* return the filter bit position */ 282 return(crc >> 23 & 0x1FF); 283 } 284 285 /* 286 * Copy the address 'mac' into the perfect RX filter entry at 287 * offset 'idx.' The perfect filter only has 16 entries so do 288 * some sanity tests. 289 */ 290 static int sf_setperf(sc, idx, mac) 291 struct sf_softc *sc; 292 int idx; 293 caddr_t mac; 294 { 295 u_int16_t *p; 296 297 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 298 return(EINVAL); 299 300 if (mac == NULL) 301 return(EINVAL); 302 303 p = (u_int16_t *)mac; 304 305 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 306 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 311 312 return(0); 313 } 314 315 /* 316 * Set the bit in the 512-bit hash table that corresponds to the 317 * specified mac address 'mac.' If 'prio' is nonzero, update the 318 * priority hash table instead of the filter hash table. 319 */ 320 static int sf_sethash(sc, mac, prio) 321 struct sf_softc *sc; 322 caddr_t mac; 323 int prio; 324 { 325 u_int32_t h = 0; 326 327 if (mac == NULL) 328 return(EINVAL); 329 330 h = sf_calchash(mac); 331 332 if (prio) { 333 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 334 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 335 } else { 336 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 337 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 338 } 339 340 return(0); 341 } 342 343 #ifdef notdef 344 /* 345 * Set a VLAN tag in the receive filter. 346 */ 347 static int sf_setvlan(sc, idx, vlan) 348 struct sf_softc *sc; 349 int idx; 350 u_int32_t vlan; 351 { 352 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 353 return(EINVAL); 354 355 csr_write_4(sc, SF_RXFILT_HASH_BASE + 356 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 357 358 return(0); 359 } 360 #endif 361 362 static int sf_miibus_readreg(dev, phy, reg) 363 device_t dev; 364 int phy, reg; 365 { 366 struct sf_softc *sc; 367 int i; 368 u_int32_t val = 0; 369 370 sc = device_get_softc(dev); 371 372 for (i = 0; i < SF_TIMEOUT; i++) { 373 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 374 if (val & SF_MII_DATAVALID) 375 break; 376 } 377 378 if (i == SF_TIMEOUT) 379 return(0); 380 381 if ((val & 0x0000FFFF) == 0xFFFF) 382 return(0); 383 384 return(val & 0x0000FFFF); 385 } 386 387 static int sf_miibus_writereg(dev, phy, reg, val) 388 device_t dev; 389 int phy, reg, val; 390 { 391 struct sf_softc *sc; 392 int i; 393 int busy; 394 395 sc = device_get_softc(dev); 396 397 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 398 399 for (i = 0; i < SF_TIMEOUT; i++) { 400 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 401 if (!(busy & SF_MII_BUSY)) 402 break; 403 } 404 405 return(0); 406 } 407 408 static void sf_miibus_statchg(dev) 409 device_t dev; 410 { 411 struct sf_softc *sc; 412 struct mii_data *mii; 413 414 sc = device_get_softc(dev); 415 mii = device_get_softc(sc->sf_miibus); 416 417 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 418 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 419 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 420 } else { 421 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 422 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 423 } 424 425 return; 426 } 427 428 static void sf_setmulti(sc) 429 struct sf_softc *sc; 430 { 431 struct ifnet *ifp; 432 int i; 433 struct ifmultiaddr *ifma; 434 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 435 436 ifp = &sc->arpcom.ac_if; 437 438 /* First zot all the existing filters. */ 439 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 440 sf_setperf(sc, i, (char *)&dummy); 441 for (i = SF_RXFILT_HASH_BASE; 442 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 443 csr_write_4(sc, i, 0); 444 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 445 446 /* Now program new ones. */ 447 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 448 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 449 } else { 450 i = 1; 451 /* First find the tail of the list. */ 452 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 453 ifma = ifma->ifma_link.le_next) { 454 if (ifma->ifma_link.le_next == NULL) 455 break; 456 } 457 /* Now traverse the list backwards. */ 458 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 459 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 460 if (ifma->ifma_addr->sa_family != AF_LINK) 461 continue; 462 /* 463 * Program the first 15 multicast groups 464 * into the perfect filter. For all others, 465 * use the hash table. 466 */ 467 if (i < SF_RXFILT_PERFECT_CNT) { 468 sf_setperf(sc, i, 469 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 470 i++; 471 continue; 472 } 473 474 sf_sethash(sc, 475 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 476 } 477 } 478 479 return; 480 } 481 482 /* 483 * Set media options. 484 */ 485 static int sf_ifmedia_upd(ifp) 486 struct ifnet *ifp; 487 { 488 struct sf_softc *sc; 489 struct mii_data *mii; 490 491 sc = ifp->if_softc; 492 mii = device_get_softc(sc->sf_miibus); 493 sc->sf_link = 0; 494 if (mii->mii_instance) { 495 struct mii_softc *miisc; 496 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 497 miisc = LIST_NEXT(miisc, mii_list)) 498 mii_phy_reset(miisc); 499 } 500 mii_mediachg(mii); 501 502 return(0); 503 } 504 505 /* 506 * Report current media status. 507 */ 508 static void sf_ifmedia_sts(ifp, ifmr) 509 struct ifnet *ifp; 510 struct ifmediareq *ifmr; 511 { 512 struct sf_softc *sc; 513 struct mii_data *mii; 514 515 sc = ifp->if_softc; 516 mii = device_get_softc(sc->sf_miibus); 517 518 mii_pollstat(mii); 519 ifmr->ifm_active = mii->mii_media_active; 520 ifmr->ifm_status = mii->mii_media_status; 521 522 return; 523 } 524 525 static int sf_ioctl(ifp, command, data) 526 struct ifnet *ifp; 527 u_long command; 528 caddr_t data; 529 { 530 struct sf_softc *sc = ifp->if_softc; 531 struct ifreq *ifr = (struct ifreq *) data; 532 struct mii_data *mii; 533 int s, error = 0; 534 535 s = splimp(); 536 537 switch(command) { 538 case SIOCSIFADDR: 539 case SIOCGIFADDR: 540 case SIOCSIFMTU: 541 error = ether_ioctl(ifp, command, data); 542 break; 543 case SIOCSIFFLAGS: 544 if (ifp->if_flags & IFF_UP) { 545 if (ifp->if_flags & IFF_RUNNING && 546 ifp->if_flags & IFF_PROMISC && 547 !(sc->sf_if_flags & IFF_PROMISC)) { 548 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 549 } else if (ifp->if_flags & IFF_RUNNING && 550 !(ifp->if_flags & IFF_PROMISC) && 551 sc->sf_if_flags & IFF_PROMISC) { 552 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 553 } else if (!(ifp->if_flags & IFF_RUNNING)) 554 sf_init(sc); 555 } else { 556 if (ifp->if_flags & IFF_RUNNING) 557 sf_stop(sc); 558 } 559 sc->sf_if_flags = ifp->if_flags; 560 error = 0; 561 break; 562 case SIOCADDMULTI: 563 case SIOCDELMULTI: 564 sf_setmulti(sc); 565 error = 0; 566 break; 567 case SIOCGIFMEDIA: 568 case SIOCSIFMEDIA: 569 mii = device_get_softc(sc->sf_miibus); 570 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 571 break; 572 default: 573 error = EINVAL; 574 break; 575 } 576 577 (void)splx(s); 578 579 return(error); 580 } 581 582 static void sf_reset(sc) 583 struct sf_softc *sc; 584 { 585 register int i; 586 587 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 588 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 589 DELAY(1000); 590 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 591 592 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 593 594 for (i = 0; i < SF_TIMEOUT; i++) { 595 DELAY(10); 596 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 597 break; 598 } 599 600 if (i == SF_TIMEOUT) 601 printf("sf%d: reset never completed!\n", sc->sf_unit); 602 603 /* Wait a little while for the chip to get its brains in order. */ 604 DELAY(1000); 605 return; 606 } 607 608 /* 609 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 610 * IDs against our list and return a device name if we find a match. 611 * We also check the subsystem ID so that we can identify exactly which 612 * NIC has been found, if possible. 613 */ 614 static int sf_probe(dev) 615 device_t dev; 616 { 617 struct sf_type *t; 618 619 t = sf_devs; 620 621 while(t->sf_name != NULL) { 622 if ((pci_get_vendor(dev) == t->sf_vid) && 623 (pci_get_device(dev) == t->sf_did)) { 624 switch((pci_read_config(dev, 625 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 626 case AD_SUBSYSID_62011_REV0: 627 case AD_SUBSYSID_62011_REV1: 628 device_set_desc(dev, 629 "Adaptec ANA-62011 10/100BaseTX"); 630 return(0); 631 break; 632 case AD_SUBSYSID_62022: 633 device_set_desc(dev, 634 "Adaptec ANA-62022 10/100BaseTX"); 635 return(0); 636 break; 637 case AD_SUBSYSID_62044_REV0: 638 case AD_SUBSYSID_62044_REV1: 639 device_set_desc(dev, 640 "Adaptec ANA-62044 10/100BaseTX"); 641 return(0); 642 break; 643 case AD_SUBSYSID_62020: 644 device_set_desc(dev, 645 "Adaptec ANA-62020 10/100BaseFX"); 646 return(0); 647 break; 648 case AD_SUBSYSID_69011: 649 device_set_desc(dev, 650 "Adaptec ANA-69011 10/100BaseTX"); 651 return(0); 652 break; 653 default: 654 device_set_desc(dev, t->sf_name); 655 return(0); 656 break; 657 } 658 } 659 t++; 660 } 661 662 return(ENXIO); 663 } 664 665 /* 666 * Attach the interface. Allocate softc structures, do ifmedia 667 * setup and ethernet/BPF attach. 668 */ 669 static int sf_attach(dev) 670 device_t dev; 671 { 672 int s, i; 673 u_int32_t command; 674 struct sf_softc *sc; 675 struct ifnet *ifp; 676 int unit, rid, error = 0; 677 678 s = splimp(); 679 680 sc = device_get_softc(dev); 681 unit = device_get_unit(dev); 682 bzero(sc, sizeof(struct sf_softc)); 683 684 /* 685 * Handle power management nonsense. 686 */ 687 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 688 if (command == 0x01) { 689 690 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 691 if (command & SF_PSTATE_MASK) { 692 u_int32_t iobase, membase, irq; 693 694 /* Save important PCI config data. */ 695 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 696 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 697 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 698 699 /* Reset the power state. */ 700 printf("sf%d: chip is in D%d power mode " 701 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 702 command &= 0xFFFFFFFC; 703 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 704 705 /* Restore PCI config data. */ 706 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 707 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 708 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 709 } 710 } 711 712 /* 713 * Map control/status registers. 714 */ 715 command = pci_read_config(dev, PCIR_COMMAND, 4); 716 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 717 pci_write_config(dev, PCIR_COMMAND, command, 4); 718 command = pci_read_config(dev, PCIR_COMMAND, 4); 719 720 #ifdef SF_USEIOSPACE 721 if (!(command & PCIM_CMD_PORTEN)) { 722 printf("sf%d: failed to enable I/O ports!\n", unit); 723 error = ENXIO; 724 goto fail; 725 } 726 #else 727 if (!(command & PCIM_CMD_MEMEN)) { 728 printf("sf%d: failed to enable memory mapping!\n", unit); 729 error = ENXIO; 730 goto fail; 731 } 732 #endif 733 734 rid = SF_RID; 735 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 736 0, ~0, 1, RF_ACTIVE); 737 738 if (sc->sf_res == NULL) { 739 printf ("sf%d: couldn't map ports\n", unit); 740 error = ENXIO; 741 goto fail; 742 } 743 744 sc->sf_btag = rman_get_bustag(sc->sf_res); 745 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 746 747 /* Allocate interrupt */ 748 rid = 0; 749 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 750 RF_SHAREABLE | RF_ACTIVE); 751 752 if (sc->sf_irq == NULL) { 753 printf("sf%d: couldn't map interrupt\n", unit); 754 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 755 error = ENXIO; 756 goto fail; 757 } 758 759 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 760 sf_intr, sc, &sc->sf_intrhand); 761 762 if (error) { 763 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 764 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 765 printf("sf%d: couldn't set up irq\n", unit); 766 goto fail; 767 } 768 769 callout_handle_init(&sc->sf_stat_ch); 770 771 /* Reset the adapter. */ 772 sf_reset(sc); 773 774 /* 775 * Get station address from the EEPROM. 776 */ 777 for (i = 0; i < ETHER_ADDR_LEN; i++) 778 sc->arpcom.ac_enaddr[i] = 779 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 780 781 /* 782 * An Adaptec chip was detected. Inform the world. 783 */ 784 printf("sf%d: Ethernet address: %6D\n", unit, 785 sc->arpcom.ac_enaddr, ":"); 786 787 sc->sf_unit = unit; 788 789 /* Allocate the descriptor queues. */ 790 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 791 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 792 793 if (sc->sf_ldata == NULL) { 794 printf("sf%d: no memory for list buffers!\n", unit); 795 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 796 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 797 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 798 error = ENXIO; 799 goto fail; 800 } 801 802 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 803 804 /* Do MII setup. */ 805 if (mii_phy_probe(dev, &sc->sf_miibus, 806 sf_ifmedia_upd, sf_ifmedia_sts)) { 807 printf("sf%d: MII without any phy!\n", sc->sf_unit); 808 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 809 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 810 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 811 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 812 error = ENXIO; 813 goto fail; 814 } 815 816 ifp = &sc->arpcom.ac_if; 817 ifp->if_softc = sc; 818 ifp->if_unit = unit; 819 ifp->if_name = "sf"; 820 ifp->if_mtu = ETHERMTU; 821 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 822 ifp->if_ioctl = sf_ioctl; 823 ifp->if_output = ether_output; 824 ifp->if_start = sf_start; 825 ifp->if_watchdog = sf_watchdog; 826 ifp->if_init = sf_init; 827 ifp->if_baudrate = 10000000; 828 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 829 830 /* 831 * Call MI attach routine. 832 */ 833 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 834 835 fail: 836 splx(s); 837 return(error); 838 } 839 840 static int sf_detach(dev) 841 device_t dev; 842 { 843 struct sf_softc *sc; 844 struct ifnet *ifp; 845 int s; 846 847 s = splimp(); 848 849 sc = device_get_softc(dev); 850 ifp = &sc->arpcom.ac_if; 851 852 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 853 sf_stop(sc); 854 855 bus_generic_detach(dev); 856 device_delete_child(dev, sc->sf_miibus); 857 858 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 859 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 860 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 861 862 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 863 864 splx(s); 865 866 return(0); 867 } 868 869 static int sf_init_rx_ring(sc) 870 struct sf_softc *sc; 871 { 872 struct sf_list_data *ld; 873 int i; 874 875 ld = sc->sf_ldata; 876 877 bzero((char *)ld->sf_rx_dlist_big, 878 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 879 bzero((char *)ld->sf_rx_clist, 880 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 881 882 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 883 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 884 return(ENOBUFS); 885 } 886 887 return(0); 888 } 889 890 static void sf_init_tx_ring(sc) 891 struct sf_softc *sc; 892 { 893 struct sf_list_data *ld; 894 int i; 895 896 ld = sc->sf_ldata; 897 898 bzero((char *)ld->sf_tx_dlist, 899 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 900 bzero((char *)ld->sf_tx_clist, 901 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 902 903 for (i = 0; i < SF_TX_DLIST_CNT; i++) 904 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 905 for (i = 0; i < SF_TX_CLIST_CNT; i++) 906 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 907 908 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 909 sc->sf_tx_cnt = 0; 910 911 return; 912 } 913 914 static int sf_newbuf(sc, c, m) 915 struct sf_softc *sc; 916 struct sf_rx_bufdesc_type0 *c; 917 struct mbuf *m; 918 { 919 struct mbuf *m_new = NULL; 920 921 if (m == NULL) { 922 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 923 if (m_new == NULL) 924 return(ENOBUFS); 925 926 MCLGET(m_new, M_DONTWAIT); 927 if (!(m_new->m_flags & M_EXT)) { 928 m_freem(m_new); 929 return(ENOBUFS); 930 } 931 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 932 } else { 933 m_new = m; 934 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 935 m_new->m_data = m_new->m_ext.ext_buf; 936 } 937 938 m_adj(m_new, sizeof(u_int64_t)); 939 940 c->sf_mbuf = m_new; 941 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 942 c->sf_valid = 1; 943 944 return(0); 945 } 946 947 /* 948 * The starfire is programmed to use 'normal' mode for packet reception, 949 * which means we use the consumer/producer model for both the buffer 950 * descriptor queue and the completion descriptor queue. The only problem 951 * with this is that it involves a lot of register accesses: we have to 952 * read the RX completion consumer and producer indexes and the RX buffer 953 * producer index, plus the RX completion consumer and RX buffer producer 954 * indexes have to be updated. It would have been easier if Adaptec had 955 * put each index in a separate register, especially given that the damn 956 * NIC has a 512K register space. 957 * 958 * In spite of all the lovely features that Adaptec crammed into the 6915, 959 * it is marred by one truly stupid design flaw, which is that receive 960 * buffer addresses must be aligned on a longword boundary. This forces 961 * the packet payload to be unaligned, which is suboptimal on the x86 and 962 * completely unuseable on the Alpha. Our only recourse is to copy received 963 * packets into properly aligned buffers before handing them off. 964 */ 965 966 static void sf_rxeof(sc) 967 struct sf_softc *sc; 968 { 969 struct ether_header *eh; 970 struct mbuf *m; 971 struct ifnet *ifp; 972 struct sf_rx_bufdesc_type0 *desc; 973 struct sf_rx_cmpdesc_type3 *cur_rx; 974 u_int32_t rxcons, rxprod; 975 int cmpprodidx, cmpconsidx, bufprodidx; 976 977 ifp = &sc->arpcom.ac_if; 978 979 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 980 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 981 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 982 cmpconsidx = SF_IDX_LO(rxcons); 983 bufprodidx = SF_IDX_LO(rxprod); 984 985 while (cmpconsidx != cmpprodidx) { 986 struct mbuf *m0; 987 988 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 989 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 990 m = desc->sf_mbuf; 991 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 992 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 993 994 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 995 ifp->if_ierrors++; 996 sf_newbuf(sc, desc, m); 997 continue; 998 } 999 1000 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1001 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 1002 sf_newbuf(sc, desc, m); 1003 if (m0 == NULL) { 1004 ifp->if_ierrors++; 1005 continue; 1006 } 1007 m_adj(m0, ETHER_ALIGN); 1008 m = m0; 1009 1010 eh = mtod(m, struct ether_header *); 1011 ifp->if_ipackets++; 1012 1013 /* Remove header from mbuf and pass it on. */ 1014 m_adj(m, sizeof(struct ether_header)); 1015 ether_input(ifp, eh, m); 1016 } 1017 1018 csr_write_4(sc, SF_CQ_CONSIDX, 1019 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1020 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1021 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1022 1023 return; 1024 } 1025 1026 /* 1027 * Read the transmit status from the completion queue and release 1028 * mbufs. Note that the buffer descriptor index in the completion 1029 * descriptor is an offset from the start of the transmit buffer 1030 * descriptor list in bytes. This is important because the manual 1031 * gives the impression that it should match the producer/consumer 1032 * index, which is the offset in 8 byte blocks. 1033 */ 1034 static void sf_txeof(sc) 1035 struct sf_softc *sc; 1036 { 1037 int txcons, cmpprodidx, cmpconsidx; 1038 struct sf_tx_cmpdesc_type1 *cur_cmp; 1039 struct sf_tx_bufdesc_type0 *cur_tx; 1040 struct ifnet *ifp; 1041 1042 ifp = &sc->arpcom.ac_if; 1043 1044 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1045 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1046 cmpconsidx = SF_IDX_HI(txcons); 1047 1048 while (cmpconsidx != cmpprodidx) { 1049 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1050 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1051 1052 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1053 ifp->if_opackets++; 1054 else { 1055 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1056 sf_txthresh_adjust(sc); 1057 ifp->if_oerrors++; 1058 } 1059 1060 sc->sf_tx_cnt--; 1061 if (cur_tx->sf_mbuf != NULL) { 1062 m_freem(cur_tx->sf_mbuf); 1063 cur_tx->sf_mbuf = NULL; 1064 } else 1065 break; 1066 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1067 } 1068 1069 ifp->if_timer = 0; 1070 ifp->if_flags &= ~IFF_OACTIVE; 1071 1072 csr_write_4(sc, SF_CQ_CONSIDX, 1073 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1074 ((cmpconsidx << 16) & 0xFFFF0000)); 1075 1076 return; 1077 } 1078 1079 static void sf_txthresh_adjust(sc) 1080 struct sf_softc *sc; 1081 { 1082 u_int32_t txfctl; 1083 u_int8_t txthresh; 1084 1085 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1086 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1087 if (txthresh < 0xFF) { 1088 txthresh++; 1089 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1090 txfctl |= txthresh; 1091 #ifdef DIAGNOSTIC 1092 printf("sf%d: tx underrun, increasing " 1093 "tx threshold to %d bytes\n", 1094 sc->sf_unit, txthresh * 4); 1095 #endif 1096 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1097 } 1098 1099 return; 1100 } 1101 1102 static void sf_intr(arg) 1103 void *arg; 1104 { 1105 struct sf_softc *sc; 1106 struct ifnet *ifp; 1107 u_int32_t status; 1108 1109 sc = arg; 1110 ifp = &sc->arpcom.ac_if; 1111 1112 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1113 return; 1114 1115 /* Disable interrupts. */ 1116 csr_write_4(sc, SF_IMR, 0x00000000); 1117 1118 for (;;) { 1119 status = csr_read_4(sc, SF_ISR); 1120 if (status) 1121 csr_write_4(sc, SF_ISR, status); 1122 1123 if (!(status & SF_INTRS)) 1124 break; 1125 1126 if (status & SF_ISR_RXDQ1_DMADONE) 1127 sf_rxeof(sc); 1128 1129 if (status & SF_ISR_TX_TXDONE || 1130 status & SF_ISR_TX_DMADONE || 1131 status & SF_ISR_TX_QUEUEDONE) 1132 sf_txeof(sc); 1133 1134 if (status & SF_ISR_TX_LOFIFO) 1135 sf_txthresh_adjust(sc); 1136 1137 if (status & SF_ISR_ABNORMALINTR) { 1138 if (status & SF_ISR_STATSOFLOW) { 1139 untimeout(sf_stats_update, sc, 1140 sc->sf_stat_ch); 1141 sf_stats_update(sc); 1142 } else 1143 sf_init(sc); 1144 } 1145 } 1146 1147 /* Re-enable interrupts. */ 1148 csr_write_4(sc, SF_IMR, SF_INTRS); 1149 1150 if (ifp->if_snd.ifq_head != NULL) 1151 sf_start(ifp); 1152 1153 return; 1154 } 1155 1156 static void sf_init(xsc) 1157 void *xsc; 1158 { 1159 struct sf_softc *sc; 1160 struct ifnet *ifp; 1161 struct mii_data *mii; 1162 int i, s; 1163 1164 s = splimp(); 1165 1166 sc = xsc; 1167 ifp = &sc->arpcom.ac_if; 1168 mii = device_get_softc(sc->sf_miibus); 1169 1170 sf_stop(sc); 1171 sf_reset(sc); 1172 1173 /* Init all the receive filter registers */ 1174 for (i = SF_RXFILT_PERFECT_BASE; 1175 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1176 csr_write_4(sc, i, 0); 1177 1178 /* Empty stats counter registers. */ 1179 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1180 csr_write_4(sc, SF_STATS_BASE + 1181 (i + sizeof(u_int32_t)), 0); 1182 1183 /* Init our MAC address */ 1184 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1185 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1186 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1187 1188 if (sf_init_rx_ring(sc) == ENOBUFS) { 1189 printf("sf%d: initialization failed: no " 1190 "memory for rx buffers\n", sc->sf_unit); 1191 (void)splx(s); 1192 return; 1193 } 1194 1195 sf_init_tx_ring(sc); 1196 1197 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1198 1199 /* If we want promiscuous mode, set the allframes bit. */ 1200 if (ifp->if_flags & IFF_PROMISC) { 1201 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1202 } else { 1203 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1204 } 1205 1206 if (ifp->if_flags & IFF_BROADCAST) { 1207 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1208 } else { 1209 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1210 } 1211 1212 /* 1213 * Load the multicast filter. 1214 */ 1215 sf_setmulti(sc); 1216 1217 /* Init the completion queue indexes */ 1218 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1219 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1220 1221 /* Init the RX completion queue */ 1222 csr_write_4(sc, SF_RXCQ_CTL_1, 1223 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1224 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1225 1226 /* Init RX DMA control. */ 1227 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1228 1229 /* Init the RX buffer descriptor queue. */ 1230 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1231 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1232 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1233 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1234 1235 /* Init the TX completion queue */ 1236 csr_write_4(sc, SF_TXCQ_CTL, 1237 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1238 1239 /* Init the TX buffer descriptor queue. */ 1240 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1241 vtophys(sc->sf_ldata->sf_tx_dlist)); 1242 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1243 csr_write_4(sc, SF_TXDQ_CTL, 1244 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1245 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1246 1247 /* Enable autopadding of short TX frames. */ 1248 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1249 1250 /* Enable interrupts. */ 1251 csr_write_4(sc, SF_IMR, SF_INTRS); 1252 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1253 1254 /* Enable the RX and TX engines. */ 1255 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1256 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1257 1258 /*mii_mediachg(mii);*/ 1259 sf_ifmedia_upd(ifp); 1260 1261 ifp->if_flags |= IFF_RUNNING; 1262 ifp->if_flags &= ~IFF_OACTIVE; 1263 1264 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1265 1266 splx(s); 1267 1268 return; 1269 } 1270 1271 static int sf_encap(sc, c, m_head) 1272 struct sf_softc *sc; 1273 struct sf_tx_bufdesc_type0 *c; 1274 struct mbuf *m_head; 1275 { 1276 int frag = 0; 1277 struct sf_frag *f = NULL; 1278 struct mbuf *m; 1279 1280 m = m_head; 1281 1282 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1283 if (m->m_len != 0) { 1284 if (frag == SF_MAXFRAGS) 1285 break; 1286 f = &c->sf_frags[frag]; 1287 if (frag == 0) 1288 f->sf_pktlen = m_head->m_pkthdr.len; 1289 f->sf_fraglen = m->m_len; 1290 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1291 frag++; 1292 } 1293 } 1294 1295 if (m != NULL) { 1296 struct mbuf *m_new = NULL; 1297 1298 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1299 if (m_new == NULL) { 1300 printf("sf%d: no memory for tx list", sc->sf_unit); 1301 return(1); 1302 } 1303 1304 if (m_head->m_pkthdr.len > MHLEN) { 1305 MCLGET(m_new, M_DONTWAIT); 1306 if (!(m_new->m_flags & M_EXT)) { 1307 m_freem(m_new); 1308 printf("sf%d: no memory for tx list", 1309 sc->sf_unit); 1310 return(1); 1311 } 1312 } 1313 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1314 mtod(m_new, caddr_t)); 1315 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1316 m_freem(m_head); 1317 m_head = m_new; 1318 f = &c->sf_frags[0]; 1319 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1320 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1321 frag = 1; 1322 } 1323 1324 c->sf_mbuf = m_head; 1325 c->sf_id = SF_TX_BUFDESC_ID; 1326 c->sf_fragcnt = frag; 1327 c->sf_intr = 1; 1328 c->sf_caltcp = 0; 1329 c->sf_crcen = 1; 1330 1331 return(0); 1332 } 1333 1334 static void sf_start(ifp) 1335 struct ifnet *ifp; 1336 { 1337 struct sf_softc *sc; 1338 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1339 struct mbuf *m_head = NULL; 1340 int i, txprod; 1341 1342 sc = ifp->if_softc; 1343 1344 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) 1345 return; 1346 1347 if (ifp->if_flags & IFF_OACTIVE) 1348 return; 1349 1350 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1351 i = SF_IDX_HI(txprod) >> 4; 1352 1353 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1354 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1355 sf_init(sc); 1356 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1357 i = SF_IDX_HI(txprod) >> 4; 1358 } 1359 1360 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1361 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1362 ifp->if_flags |= IFF_OACTIVE; 1363 cur_tx = NULL; 1364 break; 1365 } 1366 IF_DEQUEUE(&ifp->if_snd, m_head); 1367 if (m_head == NULL) 1368 break; 1369 1370 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1371 if (sf_encap(sc, cur_tx, m_head)) { 1372 IF_PREPEND(&ifp->if_snd, m_head); 1373 ifp->if_flags |= IFF_OACTIVE; 1374 cur_tx = NULL; 1375 break; 1376 } 1377 1378 1379 /* 1380 * If there's a BPF listener, bounce a copy of this frame 1381 * to him. 1382 */ 1383 if (ifp->if_bpf) 1384 bpf_mtap(ifp, m_head); 1385 1386 SF_INC(i, SF_TX_DLIST_CNT); 1387 sc->sf_tx_cnt++; 1388 /* 1389 * Don't get the TX DMA queue get too full. 1390 */ 1391 if (sc->sf_tx_cnt > 64) 1392 break; 1393 } 1394 1395 if (cur_tx == NULL) 1396 return; 1397 1398 /* Transmit */ 1399 csr_write_4(sc, SF_TXDQ_PRODIDX, 1400 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1401 ((i << 20) & 0xFFFF0000)); 1402 1403 ifp->if_timer = 5; 1404 1405 return; 1406 } 1407 1408 static void sf_stop(sc) 1409 struct sf_softc *sc; 1410 { 1411 int i; 1412 struct ifnet *ifp; 1413 1414 ifp = &sc->arpcom.ac_if; 1415 1416 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1417 1418 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1419 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1420 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1421 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1422 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1423 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1424 csr_write_4(sc, SF_TXCQ_CTL, 0); 1425 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1426 csr_write_4(sc, SF_TXDQ_CTL, 0); 1427 sf_reset(sc); 1428 1429 sc->sf_link = 0; 1430 1431 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1432 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1433 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1434 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1435 } 1436 } 1437 1438 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1439 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1440 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1441 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1442 } 1443 } 1444 1445 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1446 1447 return; 1448 } 1449 1450 /* 1451 * Note: it is important that this function not be interrupted. We 1452 * use a two-stage register access scheme: if we are interrupted in 1453 * between setting the indirect address register and reading from the 1454 * indirect data register, the contents of the address register could 1455 * be changed out from under us. 1456 */ 1457 static void sf_stats_update(xsc) 1458 void *xsc; 1459 { 1460 struct sf_softc *sc; 1461 struct ifnet *ifp; 1462 struct mii_data *mii; 1463 struct sf_stats stats; 1464 u_int32_t *ptr; 1465 int i, s; 1466 1467 s = splimp(); 1468 1469 sc = xsc; 1470 ifp = &sc->arpcom.ac_if; 1471 mii = device_get_softc(sc->sf_miibus); 1472 1473 ptr = (u_int32_t *)&stats; 1474 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1475 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1476 (i + sizeof(u_int32_t))); 1477 1478 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1479 csr_write_4(sc, SF_STATS_BASE + 1480 (i + sizeof(u_int32_t)), 0); 1481 1482 ifp->if_collisions += stats.sf_tx_single_colls + 1483 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1484 1485 mii_tick(mii); 1486 if (!sc->sf_link) { 1487 mii_pollstat(mii); 1488 if (mii->mii_media_status & IFM_ACTIVE && 1489 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1490 sc->sf_link++; 1491 if (ifp->if_snd.ifq_head != NULL) 1492 sf_start(ifp); 1493 } 1494 1495 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1496 1497 splx(s); 1498 1499 return; 1500 } 1501 1502 static void sf_watchdog(ifp) 1503 struct ifnet *ifp; 1504 { 1505 struct sf_softc *sc; 1506 1507 sc = ifp->if_softc; 1508 1509 ifp->if_oerrors++; 1510 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1511 1512 sf_stop(sc); 1513 sf_reset(sc); 1514 sf_init(sc); 1515 1516 if (ifp->if_snd.ifq_head != NULL) 1517 sf_start(ifp); 1518 1519 return; 1520 } 1521 1522 static void sf_shutdown(dev) 1523 device_t dev; 1524 { 1525 struct sf_softc *sc; 1526 1527 sc = device_get_softc(dev); 1528 1529 sf_stop(sc); 1530 1531 return; 1532 }
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