FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sf.c
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: releng/5.0/sys/pci/if_sf.c 106936 2002-11-14 23:49:09Z sam $
33 */
34
35 /*
36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
37 * Programming manual is available from:
38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
39 *
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Department of Electical Engineering
42 * Columbia University, New York City
43 */
44
45 /*
46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
47 * controller designed with flexibility and reducing CPU load in mind.
48 * The Starfire offers high and low priority buffer queues, a
49 * producer/consumer index mechanism and several different buffer
50 * queue and completion queue descriptor types. Any one of a number
51 * of different driver designs can be used, depending on system and
52 * OS requirements. This driver makes use of type0 transmit frame
53 * descriptors (since BSD fragments packets across an mbuf chain)
54 * and two RX buffer queues prioritized on size (one queue for small
55 * frames that will fit into a single mbuf, another with full size
56 * mbuf clusters for everything else). The producer/consumer indexes
57 * and completion queues are also used.
58 *
59 * One downside to the Starfire has to do with alignment: buffer
60 * queues must be aligned on 256-byte boundaries, and receive buffers
61 * must be aligned on longword boundaries. The receive buffer alignment
62 * causes problems on the Alpha platform, where the packet payload
63 * should be longword aligned. There is no simple way around this.
64 *
65 * For receive filtering, the Starfire offers 16 perfect filter slots
66 * and a 512-bit hash table.
67 *
68 * The Starfire has no internal transceiver, relying instead on an
69 * external MII-based transceiver. Accessing registers on external
70 * PHYs is done through a special register map rather than with the
71 * usual bitbang MDIO method.
72 *
73 * Acesssing the registers on the Starfire is a little tricky. The
74 * Starfire has a 512K internal register space. When programmed for
75 * PCI memory mapped mode, the entire register space can be accessed
76 * directly. However in I/O space mode, only 256 bytes are directly
77 * mapped into PCI I/O space. The other registers can be accessed
78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
79 * registers inside the 256-byte I/O window.
80 */
81
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/sockio.h>
85 #include <sys/mbuf.h>
86 #include <sys/malloc.h>
87 #include <sys/kernel.h>
88 #include <sys/socket.h>
89
90 #include <net/if.h>
91 #include <net/if_arp.h>
92 #include <net/ethernet.h>
93 #include <net/if_dl.h>
94 #include <net/if_media.h>
95
96 #include <net/bpf.h>
97
98 #include <vm/vm.h> /* for vtophys */
99 #include <vm/pmap.h> /* for vtophys */
100 #include <machine/bus_pio.h>
101 #include <machine/bus_memio.h>
102 #include <machine/bus.h>
103 #include <machine/resource.h>
104 #include <sys/bus.h>
105 #include <sys/rman.h>
106
107 #include <dev/mii/mii.h>
108 #include <dev/mii/miivar.h>
109
110 /* "controller miibus0" required. See GENERIC if you get errors here. */
111 #include "miibus_if.h"
112
113 #include <pci/pcireg.h>
114 #include <pci/pcivar.h>
115
116 #define SF_USEIOSPACE
117
118 #include <pci/if_sfreg.h>
119
120 MODULE_DEPEND(sf, miibus, 1, 1, 1);
121
122 #ifndef lint
123 static const char rcsid[] =
124 "$FreeBSD: releng/5.0/sys/pci/if_sf.c 106936 2002-11-14 23:49:09Z sam $";
125 #endif
126
127 static struct sf_type sf_devs[] = {
128 { AD_VENDORID, AD_DEVICEID_STARFIRE,
129 "Adaptec AIC-6915 10/100BaseTX" },
130 { 0, 0, NULL }
131 };
132
133 static int sf_probe (device_t);
134 static int sf_attach (device_t);
135 static int sf_detach (device_t);
136 static void sf_intr (void *);
137 static void sf_stats_update (void *);
138 static void sf_rxeof (struct sf_softc *);
139 static void sf_txeof (struct sf_softc *);
140 static int sf_encap (struct sf_softc *,
141 struct sf_tx_bufdesc_type0 *,
142 struct mbuf *);
143 static void sf_start (struct ifnet *);
144 static int sf_ioctl (struct ifnet *, u_long, caddr_t);
145 static void sf_init (void *);
146 static void sf_stop (struct sf_softc *);
147 static void sf_watchdog (struct ifnet *);
148 static void sf_shutdown (device_t);
149 static int sf_ifmedia_upd (struct ifnet *);
150 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *);
151 static void sf_reset (struct sf_softc *);
152 static int sf_init_rx_ring (struct sf_softc *);
153 static void sf_init_tx_ring (struct sf_softc *);
154 static int sf_newbuf (struct sf_softc *,
155 struct sf_rx_bufdesc_type0 *,
156 struct mbuf *);
157 static void sf_setmulti (struct sf_softc *);
158 static int sf_setperf (struct sf_softc *, int, caddr_t);
159 static int sf_sethash (struct sf_softc *, caddr_t, int);
160 #ifdef notdef
161 static int sf_setvlan (struct sf_softc *, int, u_int32_t);
162 #endif
163
164 static u_int8_t sf_read_eeprom (struct sf_softc *, int);
165 static u_int32_t sf_calchash (caddr_t);
166
167 static int sf_miibus_readreg (device_t, int, int);
168 static int sf_miibus_writereg (device_t, int, int, int);
169 static void sf_miibus_statchg (device_t);
170
171 static u_int32_t csr_read_4 (struct sf_softc *, int);
172 static void csr_write_4 (struct sf_softc *, int, u_int32_t);
173 static void sf_txthresh_adjust (struct sf_softc *);
174
175 #ifdef SF_USEIOSPACE
176 #define SF_RES SYS_RES_IOPORT
177 #define SF_RID SF_PCI_LOIO
178 #else
179 #define SF_RES SYS_RES_MEMORY
180 #define SF_RID SF_PCI_LOMEM
181 #endif
182
183 static device_method_t sf_methods[] = {
184 /* Device interface */
185 DEVMETHOD(device_probe, sf_probe),
186 DEVMETHOD(device_attach, sf_attach),
187 DEVMETHOD(device_detach, sf_detach),
188 DEVMETHOD(device_shutdown, sf_shutdown),
189
190 /* bus interface */
191 DEVMETHOD(bus_print_child, bus_generic_print_child),
192 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
193
194 /* MII interface */
195 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
196 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
197 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
198
199 { 0, 0 }
200 };
201
202 static driver_t sf_driver = {
203 "sf",
204 sf_methods,
205 sizeof(struct sf_softc),
206 };
207
208 static devclass_t sf_devclass;
209
210 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
211 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
212
213 #define SF_SETBIT(sc, reg, x) \
214 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x))
215
216 #define SF_CLRBIT(sc, reg, x) \
217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x))
218
219 static u_int32_t
220 csr_read_4(sc, reg)
221 struct sf_softc *sc;
222 int reg;
223 {
224 u_int32_t val;
225
226 #ifdef SF_USEIOSPACE
227 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
228 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
229 #else
230 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
231 #endif
232
233 return(val);
234 }
235
236 static u_int8_t
237 sf_read_eeprom(sc, reg)
238 struct sf_softc *sc;
239 int reg;
240 {
241 u_int8_t val;
242
243 val = (csr_read_4(sc, SF_EEADDR_BASE +
244 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
245
246 return(val);
247 }
248
249 static void
250 csr_write_4(sc, reg, val)
251 struct sf_softc *sc;
252 int reg;
253 u_int32_t val;
254 {
255 #ifdef SF_USEIOSPACE
256 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
257 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
258 #else
259 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
260 #endif
261 return;
262 }
263
264 static u_int32_t
265 sf_calchash(addr)
266 caddr_t addr;
267 {
268 u_int32_t crc, carry;
269 int i, j;
270 u_int8_t c;
271
272 /* Compute CRC for the address value. */
273 crc = 0xFFFFFFFF; /* initial value */
274
275 for (i = 0; i < 6; i++) {
276 c = *(addr + i);
277 for (j = 0; j < 8; j++) {
278 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
279 crc <<= 1;
280 c >>= 1;
281 if (carry)
282 crc = (crc ^ 0x04c11db6) | carry;
283 }
284 }
285
286 /* return the filter bit position */
287 return(crc >> 23 & 0x1FF);
288 }
289
290 /*
291 * Copy the address 'mac' into the perfect RX filter entry at
292 * offset 'idx.' The perfect filter only has 16 entries so do
293 * some sanity tests.
294 */
295 static int
296 sf_setperf(sc, idx, mac)
297 struct sf_softc *sc;
298 int idx;
299 caddr_t mac;
300 {
301 u_int16_t *p;
302
303 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
304 return(EINVAL);
305
306 if (mac == NULL)
307 return(EINVAL);
308
309 p = (u_int16_t *)mac;
310
311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
312 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
313 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
314 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
315 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
316 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
317
318 return(0);
319 }
320
321 /*
322 * Set the bit in the 512-bit hash table that corresponds to the
323 * specified mac address 'mac.' If 'prio' is nonzero, update the
324 * priority hash table instead of the filter hash table.
325 */
326 static int
327 sf_sethash(sc, mac, prio)
328 struct sf_softc *sc;
329 caddr_t mac;
330 int prio;
331 {
332 u_int32_t h = 0;
333
334 if (mac == NULL)
335 return(EINVAL);
336
337 h = sf_calchash(mac);
338
339 if (prio) {
340 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
341 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
342 } else {
343 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
344 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
345 }
346
347 return(0);
348 }
349
350 #ifdef notdef
351 /*
352 * Set a VLAN tag in the receive filter.
353 */
354 static int
355 sf_setvlan(sc, idx, vlan)
356 struct sf_softc *sc;
357 int idx;
358 u_int32_t vlan;
359 {
360 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
361 return(EINVAL);
362
363 csr_write_4(sc, SF_RXFILT_HASH_BASE +
364 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
365
366 return(0);
367 }
368 #endif
369
370 static int
371 sf_miibus_readreg(dev, phy, reg)
372 device_t dev;
373 int phy, reg;
374 {
375 struct sf_softc *sc;
376 int i;
377 u_int32_t val = 0;
378
379 sc = device_get_softc(dev);
380
381 for (i = 0; i < SF_TIMEOUT; i++) {
382 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
383 if (val & SF_MII_DATAVALID)
384 break;
385 }
386
387 if (i == SF_TIMEOUT)
388 return(0);
389
390 if ((val & 0x0000FFFF) == 0xFFFF)
391 return(0);
392
393 return(val & 0x0000FFFF);
394 }
395
396 static int
397 sf_miibus_writereg(dev, phy, reg, val)
398 device_t dev;
399 int phy, reg, val;
400 {
401 struct sf_softc *sc;
402 int i;
403 int busy;
404
405 sc = device_get_softc(dev);
406
407 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
408
409 for (i = 0; i < SF_TIMEOUT; i++) {
410 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
411 if (!(busy & SF_MII_BUSY))
412 break;
413 }
414
415 return(0);
416 }
417
418 static void
419 sf_miibus_statchg(dev)
420 device_t dev;
421 {
422 struct sf_softc *sc;
423 struct mii_data *mii;
424
425 sc = device_get_softc(dev);
426 mii = device_get_softc(sc->sf_miibus);
427
428 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
429 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
430 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
431 } else {
432 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
433 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
434 }
435
436 return;
437 }
438
439 static void
440 sf_setmulti(sc)
441 struct sf_softc *sc;
442 {
443 struct ifnet *ifp;
444 int i;
445 struct ifmultiaddr *ifma;
446 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
447
448 ifp = &sc->arpcom.ac_if;
449
450 /* First zot all the existing filters. */
451 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
452 sf_setperf(sc, i, (char *)&dummy);
453 for (i = SF_RXFILT_HASH_BASE;
454 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
455 csr_write_4(sc, i, 0);
456 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
457
458 /* Now program new ones. */
459 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
460 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
461 } else {
462 i = 1;
463 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
464 if (ifma->ifma_addr->sa_family != AF_LINK)
465 continue;
466 /*
467 * Program the first 15 multicast groups
468 * into the perfect filter. For all others,
469 * use the hash table.
470 */
471 if (i < SF_RXFILT_PERFECT_CNT) {
472 sf_setperf(sc, i,
473 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
474 i++;
475 continue;
476 }
477
478 sf_sethash(sc,
479 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
480 }
481 }
482
483 return;
484 }
485
486 /*
487 * Set media options.
488 */
489 static int
490 sf_ifmedia_upd(ifp)
491 struct ifnet *ifp;
492 {
493 struct sf_softc *sc;
494 struct mii_data *mii;
495
496 sc = ifp->if_softc;
497 mii = device_get_softc(sc->sf_miibus);
498 sc->sf_link = 0;
499 if (mii->mii_instance) {
500 struct mii_softc *miisc;
501 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
502 mii_phy_reset(miisc);
503 }
504 mii_mediachg(mii);
505
506 return(0);
507 }
508
509 /*
510 * Report current media status.
511 */
512 static void
513 sf_ifmedia_sts(ifp, ifmr)
514 struct ifnet *ifp;
515 struct ifmediareq *ifmr;
516 {
517 struct sf_softc *sc;
518 struct mii_data *mii;
519
520 sc = ifp->if_softc;
521 mii = device_get_softc(sc->sf_miibus);
522
523 mii_pollstat(mii);
524 ifmr->ifm_active = mii->mii_media_active;
525 ifmr->ifm_status = mii->mii_media_status;
526
527 return;
528 }
529
530 static int
531 sf_ioctl(ifp, command, data)
532 struct ifnet *ifp;
533 u_long command;
534 caddr_t data;
535 {
536 struct sf_softc *sc = ifp->if_softc;
537 struct ifreq *ifr = (struct ifreq *) data;
538 struct mii_data *mii;
539 int error = 0;
540
541 SF_LOCK(sc);
542
543 switch(command) {
544 case SIOCSIFFLAGS:
545 if (ifp->if_flags & IFF_UP) {
546 if (ifp->if_flags & IFF_RUNNING &&
547 ifp->if_flags & IFF_PROMISC &&
548 !(sc->sf_if_flags & IFF_PROMISC)) {
549 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
550 } else if (ifp->if_flags & IFF_RUNNING &&
551 !(ifp->if_flags & IFF_PROMISC) &&
552 sc->sf_if_flags & IFF_PROMISC) {
553 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
554 } else if (!(ifp->if_flags & IFF_RUNNING))
555 sf_init(sc);
556 } else {
557 if (ifp->if_flags & IFF_RUNNING)
558 sf_stop(sc);
559 }
560 sc->sf_if_flags = ifp->if_flags;
561 error = 0;
562 break;
563 case SIOCADDMULTI:
564 case SIOCDELMULTI:
565 sf_setmulti(sc);
566 error = 0;
567 break;
568 case SIOCGIFMEDIA:
569 case SIOCSIFMEDIA:
570 mii = device_get_softc(sc->sf_miibus);
571 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
572 break;
573 default:
574 error = ether_ioctl(ifp, command, data);
575 break;
576 }
577
578 SF_UNLOCK(sc);
579
580 return(error);
581 }
582
583 static void
584 sf_reset(sc)
585 struct sf_softc *sc;
586 {
587 register int i;
588
589 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
590 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
591 DELAY(1000);
592 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
593
594 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
595
596 for (i = 0; i < SF_TIMEOUT; i++) {
597 DELAY(10);
598 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
599 break;
600 }
601
602 if (i == SF_TIMEOUT)
603 printf("sf%d: reset never completed!\n", sc->sf_unit);
604
605 /* Wait a little while for the chip to get its brains in order. */
606 DELAY(1000);
607 return;
608 }
609
610 /*
611 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
612 * IDs against our list and return a device name if we find a match.
613 * We also check the subsystem ID so that we can identify exactly which
614 * NIC has been found, if possible.
615 */
616 static int
617 sf_probe(dev)
618 device_t dev;
619 {
620 struct sf_type *t;
621
622 t = sf_devs;
623
624 while(t->sf_name != NULL) {
625 if ((pci_get_vendor(dev) == t->sf_vid) &&
626 (pci_get_device(dev) == t->sf_did)) {
627 switch((pci_read_config(dev,
628 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
629 case AD_SUBSYSID_62011_REV0:
630 case AD_SUBSYSID_62011_REV1:
631 device_set_desc(dev,
632 "Adaptec ANA-62011 10/100BaseTX");
633 return(0);
634 break;
635 case AD_SUBSYSID_62022:
636 device_set_desc(dev,
637 "Adaptec ANA-62022 10/100BaseTX");
638 return(0);
639 break;
640 case AD_SUBSYSID_62044_REV0:
641 case AD_SUBSYSID_62044_REV1:
642 device_set_desc(dev,
643 "Adaptec ANA-62044 10/100BaseTX");
644 return(0);
645 break;
646 case AD_SUBSYSID_62020:
647 device_set_desc(dev,
648 "Adaptec ANA-62020 10/100BaseFX");
649 return(0);
650 break;
651 case AD_SUBSYSID_69011:
652 device_set_desc(dev,
653 "Adaptec ANA-69011 10/100BaseTX");
654 return(0);
655 break;
656 default:
657 device_set_desc(dev, t->sf_name);
658 return(0);
659 break;
660 }
661 }
662 t++;
663 }
664
665 return(ENXIO);
666 }
667
668 /*
669 * Attach the interface. Allocate softc structures, do ifmedia
670 * setup and ethernet/BPF attach.
671 */
672 static int
673 sf_attach(dev)
674 device_t dev;
675 {
676 int i;
677 u_int32_t command;
678 struct sf_softc *sc;
679 struct ifnet *ifp;
680 int unit, rid, error = 0;
681
682 sc = device_get_softc(dev);
683 unit = device_get_unit(dev);
684 bzero(sc, sizeof(struct sf_softc));
685
686 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
687 MTX_DEF | MTX_RECURSE);
688 SF_LOCK(sc);
689 /*
690 * Handle power management nonsense.
691 */
692 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
693 u_int32_t iobase, membase, irq;
694
695 /* Save important PCI config data. */
696 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
697 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
698 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
699
700 /* Reset the power state. */
701 printf("sf%d: chip is in D%d power mode "
702 "-- setting to D0\n", unit,
703 pci_get_powerstate(dev));
704 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
705
706 /* Restore PCI config data. */
707 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
708 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
709 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
710 }
711
712 /*
713 * Map control/status registers.
714 */
715 pci_enable_busmaster(dev);
716 pci_enable_io(dev, SYS_RES_IOPORT);
717 pci_enable_io(dev, SYS_RES_MEMORY);
718 command = pci_read_config(dev, PCIR_COMMAND, 4);
719
720 #ifdef SF_USEIOSPACE
721 if (!(command & PCIM_CMD_PORTEN)) {
722 printf("sf%d: failed to enable I/O ports!\n", unit);
723 error = ENXIO;
724 goto fail;
725 }
726 #else
727 if (!(command & PCIM_CMD_MEMEN)) {
728 printf("sf%d: failed to enable memory mapping!\n", unit);
729 error = ENXIO;
730 goto fail;
731 }
732 #endif
733
734 rid = SF_RID;
735 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid,
736 0, ~0, 1, RF_ACTIVE);
737
738 if (sc->sf_res == NULL) {
739 printf ("sf%d: couldn't map ports\n", unit);
740 error = ENXIO;
741 goto fail;
742 }
743
744 sc->sf_btag = rman_get_bustag(sc->sf_res);
745 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
746
747 /* Allocate interrupt */
748 rid = 0;
749 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
750 RF_SHAREABLE | RF_ACTIVE);
751
752 if (sc->sf_irq == NULL) {
753 printf("sf%d: couldn't map interrupt\n", unit);
754 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
755 error = ENXIO;
756 goto fail;
757 }
758
759 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET,
760 sf_intr, sc, &sc->sf_intrhand);
761
762 if (error) {
763 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res);
764 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
765 printf("sf%d: couldn't set up irq\n", unit);
766 goto fail;
767 }
768
769 callout_handle_init(&sc->sf_stat_ch);
770 /* Reset the adapter. */
771 sf_reset(sc);
772
773 /*
774 * Get station address from the EEPROM.
775 */
776 for (i = 0; i < ETHER_ADDR_LEN; i++)
777 sc->arpcom.ac_enaddr[i] =
778 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
779
780 /*
781 * An Adaptec chip was detected. Inform the world.
782 */
783 printf("sf%d: Ethernet address: %6D\n", unit,
784 sc->arpcom.ac_enaddr, ":");
785
786 sc->sf_unit = unit;
787
788 /* Allocate the descriptor queues. */
789 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
790 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
791
792 if (sc->sf_ldata == NULL) {
793 printf("sf%d: no memory for list buffers!\n", unit);
794 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
795 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
796 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
797 error = ENXIO;
798 goto fail;
799 }
800
801 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
802
803 /* Do MII setup. */
804 if (mii_phy_probe(dev, &sc->sf_miibus,
805 sf_ifmedia_upd, sf_ifmedia_sts)) {
806 printf("sf%d: MII without any phy!\n", sc->sf_unit);
807 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF);
808 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
809 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
810 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
811 error = ENXIO;
812 goto fail;
813 }
814
815 ifp = &sc->arpcom.ac_if;
816 ifp->if_softc = sc;
817 ifp->if_unit = unit;
818 ifp->if_name = "sf";
819 ifp->if_mtu = ETHERMTU;
820 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
821 ifp->if_ioctl = sf_ioctl;
822 ifp->if_output = ether_output;
823 ifp->if_start = sf_start;
824 ifp->if_watchdog = sf_watchdog;
825 ifp->if_init = sf_init;
826 ifp->if_baudrate = 10000000;
827 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1;
828
829 /*
830 * Call MI attach routine.
831 */
832 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
833 SF_UNLOCK(sc);
834 return(0);
835
836 fail:
837 SF_UNLOCK(sc);
838 mtx_destroy(&sc->sf_mtx);
839 return(error);
840 }
841
842 static int
843 sf_detach(dev)
844 device_t dev;
845 {
846 struct sf_softc *sc;
847 struct ifnet *ifp;
848
849 sc = device_get_softc(dev);
850 SF_LOCK(sc);
851 ifp = &sc->arpcom.ac_if;
852
853 ether_ifdetach(ifp);
854 sf_stop(sc);
855
856 bus_generic_detach(dev);
857 device_delete_child(dev, sc->sf_miibus);
858
859 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
860 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
861 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
862
863 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF);
864
865 SF_UNLOCK(sc);
866 mtx_destroy(&sc->sf_mtx);
867
868 return(0);
869 }
870
871 static int
872 sf_init_rx_ring(sc)
873 struct sf_softc *sc;
874 {
875 struct sf_list_data *ld;
876 int i;
877
878 ld = sc->sf_ldata;
879
880 bzero((char *)ld->sf_rx_dlist_big,
881 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
882 bzero((char *)ld->sf_rx_clist,
883 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
884
885 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
886 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
887 return(ENOBUFS);
888 }
889
890 return(0);
891 }
892
893 static void
894 sf_init_tx_ring(sc)
895 struct sf_softc *sc;
896 {
897 struct sf_list_data *ld;
898 int i;
899
900 ld = sc->sf_ldata;
901
902 bzero((char *)ld->sf_tx_dlist,
903 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
904 bzero((char *)ld->sf_tx_clist,
905 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
906
907 for (i = 0; i < SF_TX_DLIST_CNT; i++)
908 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
909 for (i = 0; i < SF_TX_CLIST_CNT; i++)
910 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
911
912 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
913 sc->sf_tx_cnt = 0;
914
915 return;
916 }
917
918 static int
919 sf_newbuf(sc, c, m)
920 struct sf_softc *sc;
921 struct sf_rx_bufdesc_type0 *c;
922 struct mbuf *m;
923 {
924 struct mbuf *m_new = NULL;
925
926 if (m == NULL) {
927 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
928 if (m_new == NULL)
929 return(ENOBUFS);
930
931 MCLGET(m_new, M_DONTWAIT);
932 if (!(m_new->m_flags & M_EXT)) {
933 m_freem(m_new);
934 return(ENOBUFS);
935 }
936 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
937 } else {
938 m_new = m;
939 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
940 m_new->m_data = m_new->m_ext.ext_buf;
941 }
942
943 m_adj(m_new, sizeof(u_int64_t));
944
945 c->sf_mbuf = m_new;
946 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
947 c->sf_valid = 1;
948
949 return(0);
950 }
951
952 /*
953 * The starfire is programmed to use 'normal' mode for packet reception,
954 * which means we use the consumer/producer model for both the buffer
955 * descriptor queue and the completion descriptor queue. The only problem
956 * with this is that it involves a lot of register accesses: we have to
957 * read the RX completion consumer and producer indexes and the RX buffer
958 * producer index, plus the RX completion consumer and RX buffer producer
959 * indexes have to be updated. It would have been easier if Adaptec had
960 * put each index in a separate register, especially given that the damn
961 * NIC has a 512K register space.
962 *
963 * In spite of all the lovely features that Adaptec crammed into the 6915,
964 * it is marred by one truly stupid design flaw, which is that receive
965 * buffer addresses must be aligned on a longword boundary. This forces
966 * the packet payload to be unaligned, which is suboptimal on the x86 and
967 * completely unuseable on the Alpha. Our only recourse is to copy received
968 * packets into properly aligned buffers before handing them off.
969 */
970
971 static void
972 sf_rxeof(sc)
973 struct sf_softc *sc;
974 {
975 struct mbuf *m;
976 struct ifnet *ifp;
977 struct sf_rx_bufdesc_type0 *desc;
978 struct sf_rx_cmpdesc_type3 *cur_rx;
979 u_int32_t rxcons, rxprod;
980 int cmpprodidx, cmpconsidx, bufprodidx;
981
982 ifp = &sc->arpcom.ac_if;
983
984 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
985 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
986 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
987 cmpconsidx = SF_IDX_LO(rxcons);
988 bufprodidx = SF_IDX_LO(rxprod);
989
990 while (cmpconsidx != cmpprodidx) {
991 struct mbuf *m0;
992
993 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
994 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
995 m = desc->sf_mbuf;
996 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
997 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
998
999 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
1000 ifp->if_ierrors++;
1001 sf_newbuf(sc, desc, m);
1002 continue;
1003 }
1004
1005 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN,
1006 ifp, NULL);
1007 sf_newbuf(sc, desc, m);
1008 if (m0 == NULL) {
1009 ifp->if_ierrors++;
1010 continue;
1011 }
1012 m = m0;
1013
1014 ifp->if_ipackets++;
1015 (*ifp->if_input)(ifp, m);
1016 }
1017
1018 csr_write_4(sc, SF_CQ_CONSIDX,
1019 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
1020 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1021 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
1022
1023 return;
1024 }
1025
1026 /*
1027 * Read the transmit status from the completion queue and release
1028 * mbufs. Note that the buffer descriptor index in the completion
1029 * descriptor is an offset from the start of the transmit buffer
1030 * descriptor list in bytes. This is important because the manual
1031 * gives the impression that it should match the producer/consumer
1032 * index, which is the offset in 8 byte blocks.
1033 */
1034 static void
1035 sf_txeof(sc)
1036 struct sf_softc *sc;
1037 {
1038 int txcons, cmpprodidx, cmpconsidx;
1039 struct sf_tx_cmpdesc_type1 *cur_cmp;
1040 struct sf_tx_bufdesc_type0 *cur_tx;
1041 struct ifnet *ifp;
1042
1043 ifp = &sc->arpcom.ac_if;
1044
1045 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1046 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1047 cmpconsidx = SF_IDX_HI(txcons);
1048
1049 while (cmpconsidx != cmpprodidx) {
1050 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1051 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1052
1053 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1054 ifp->if_opackets++;
1055 else {
1056 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
1057 sf_txthresh_adjust(sc);
1058 ifp->if_oerrors++;
1059 }
1060
1061 sc->sf_tx_cnt--;
1062 if (cur_tx->sf_mbuf != NULL) {
1063 m_freem(cur_tx->sf_mbuf);
1064 cur_tx->sf_mbuf = NULL;
1065 } else
1066 break;
1067 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1068 }
1069
1070 ifp->if_timer = 0;
1071 ifp->if_flags &= ~IFF_OACTIVE;
1072
1073 csr_write_4(sc, SF_CQ_CONSIDX,
1074 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1075 ((cmpconsidx << 16) & 0xFFFF0000));
1076
1077 return;
1078 }
1079
1080 static void
1081 sf_txthresh_adjust(sc)
1082 struct sf_softc *sc;
1083 {
1084 u_int32_t txfctl;
1085 u_int8_t txthresh;
1086
1087 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1088 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
1089 if (txthresh < 0xFF) {
1090 txthresh++;
1091 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1092 txfctl |= txthresh;
1093 #ifdef DIAGNOSTIC
1094 printf("sf%d: tx underrun, increasing "
1095 "tx threshold to %d bytes\n",
1096 sc->sf_unit, txthresh * 4);
1097 #endif
1098 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1099 }
1100
1101 return;
1102 }
1103
1104 static void
1105 sf_intr(arg)
1106 void *arg;
1107 {
1108 struct sf_softc *sc;
1109 struct ifnet *ifp;
1110 u_int32_t status;
1111
1112 sc = arg;
1113 SF_LOCK(sc);
1114
1115 ifp = &sc->arpcom.ac_if;
1116
1117 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) {
1118 SF_UNLOCK(sc);
1119 return;
1120 }
1121
1122 /* Disable interrupts. */
1123 csr_write_4(sc, SF_IMR, 0x00000000);
1124
1125 for (;;) {
1126 status = csr_read_4(sc, SF_ISR);
1127 if (status)
1128 csr_write_4(sc, SF_ISR, status);
1129
1130 if (!(status & SF_INTRS))
1131 break;
1132
1133 if (status & SF_ISR_RXDQ1_DMADONE)
1134 sf_rxeof(sc);
1135
1136 if (status & SF_ISR_TX_TXDONE ||
1137 status & SF_ISR_TX_DMADONE ||
1138 status & SF_ISR_TX_QUEUEDONE)
1139 sf_txeof(sc);
1140
1141 if (status & SF_ISR_TX_LOFIFO)
1142 sf_txthresh_adjust(sc);
1143
1144 if (status & SF_ISR_ABNORMALINTR) {
1145 if (status & SF_ISR_STATSOFLOW) {
1146 untimeout(sf_stats_update, sc,
1147 sc->sf_stat_ch);
1148 sf_stats_update(sc);
1149 } else
1150 sf_init(sc);
1151 }
1152 }
1153
1154 /* Re-enable interrupts. */
1155 csr_write_4(sc, SF_IMR, SF_INTRS);
1156
1157 if (ifp->if_snd.ifq_head != NULL)
1158 sf_start(ifp);
1159
1160 SF_UNLOCK(sc);
1161 return;
1162 }
1163
1164 static void
1165 sf_init(xsc)
1166 void *xsc;
1167 {
1168 struct sf_softc *sc;
1169 struct ifnet *ifp;
1170 struct mii_data *mii;
1171 int i;
1172
1173 sc = xsc;
1174 SF_LOCK(sc);
1175 ifp = &sc->arpcom.ac_if;
1176 mii = device_get_softc(sc->sf_miibus);
1177
1178 sf_stop(sc);
1179 sf_reset(sc);
1180
1181 /* Init all the receive filter registers */
1182 for (i = SF_RXFILT_PERFECT_BASE;
1183 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1184 csr_write_4(sc, i, 0);
1185
1186 /* Empty stats counter registers. */
1187 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1188 csr_write_4(sc, SF_STATS_BASE +
1189 (i + sizeof(u_int32_t)), 0);
1190
1191 /* Init our MAC address */
1192 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1193 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1194 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1195
1196 if (sf_init_rx_ring(sc) == ENOBUFS) {
1197 printf("sf%d: initialization failed: no "
1198 "memory for rx buffers\n", sc->sf_unit);
1199 SF_UNLOCK(sc);
1200 return;
1201 }
1202
1203 sf_init_tx_ring(sc);
1204
1205 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1206
1207 /* If we want promiscuous mode, set the allframes bit. */
1208 if (ifp->if_flags & IFF_PROMISC) {
1209 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1210 } else {
1211 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1212 }
1213
1214 if (ifp->if_flags & IFF_BROADCAST) {
1215 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1216 } else {
1217 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1218 }
1219
1220 /*
1221 * Load the multicast filter.
1222 */
1223 sf_setmulti(sc);
1224
1225 /* Init the completion queue indexes */
1226 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1227 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1228
1229 /* Init the RX completion queue */
1230 csr_write_4(sc, SF_RXCQ_CTL_1,
1231 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1232 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1233
1234 /* Init RX DMA control. */
1235 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1236
1237 /* Init the RX buffer descriptor queue. */
1238 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1239 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1240 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1241 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1242
1243 /* Init the TX completion queue */
1244 csr_write_4(sc, SF_TXCQ_CTL,
1245 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1246
1247 /* Init the TX buffer descriptor queue. */
1248 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1249 vtophys(sc->sf_ldata->sf_tx_dlist));
1250 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1251 csr_write_4(sc, SF_TXDQ_CTL,
1252 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1253 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1254
1255 /* Enable autopadding of short TX frames. */
1256 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1257
1258 /* Enable interrupts. */
1259 csr_write_4(sc, SF_IMR, SF_INTRS);
1260 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1261
1262 /* Enable the RX and TX engines. */
1263 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1264 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1265
1266 /*mii_mediachg(mii);*/
1267 sf_ifmedia_upd(ifp);
1268
1269 ifp->if_flags |= IFF_RUNNING;
1270 ifp->if_flags &= ~IFF_OACTIVE;
1271
1272 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1273
1274 SF_UNLOCK(sc);
1275
1276 return;
1277 }
1278
1279 static int
1280 sf_encap(sc, c, m_head)
1281 struct sf_softc *sc;
1282 struct sf_tx_bufdesc_type0 *c;
1283 struct mbuf *m_head;
1284 {
1285 int frag = 0;
1286 struct sf_frag *f = NULL;
1287 struct mbuf *m;
1288
1289 m = m_head;
1290
1291 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1292 if (m->m_len != 0) {
1293 if (frag == SF_MAXFRAGS)
1294 break;
1295 f = &c->sf_frags[frag];
1296 if (frag == 0)
1297 f->sf_pktlen = m_head->m_pkthdr.len;
1298 f->sf_fraglen = m->m_len;
1299 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1300 frag++;
1301 }
1302 }
1303
1304 if (m != NULL) {
1305 struct mbuf *m_new = NULL;
1306
1307 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1308 if (m_new == NULL) {
1309 printf("sf%d: no memory for tx list\n", sc->sf_unit);
1310 return(1);
1311 }
1312
1313 if (m_head->m_pkthdr.len > MHLEN) {
1314 MCLGET(m_new, M_DONTWAIT);
1315 if (!(m_new->m_flags & M_EXT)) {
1316 m_freem(m_new);
1317 printf("sf%d: no memory for tx list\n",
1318 sc->sf_unit);
1319 return(1);
1320 }
1321 }
1322 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1323 mtod(m_new, caddr_t));
1324 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1325 m_freem(m_head);
1326 m_head = m_new;
1327 f = &c->sf_frags[0];
1328 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1329 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1330 frag = 1;
1331 }
1332
1333 c->sf_mbuf = m_head;
1334 c->sf_id = SF_TX_BUFDESC_ID;
1335 c->sf_fragcnt = frag;
1336 c->sf_intr = 1;
1337 c->sf_caltcp = 0;
1338 c->sf_crcen = 1;
1339
1340 return(0);
1341 }
1342
1343 static void
1344 sf_start(ifp)
1345 struct ifnet *ifp;
1346 {
1347 struct sf_softc *sc;
1348 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1349 struct mbuf *m_head = NULL;
1350 int i, txprod;
1351
1352 sc = ifp->if_softc;
1353 SF_LOCK(sc);
1354
1355 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) {
1356 SF_UNLOCK(sc);
1357 return;
1358 }
1359
1360 if (ifp->if_flags & IFF_OACTIVE) {
1361 SF_UNLOCK(sc);
1362 return;
1363 }
1364
1365 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1366 i = SF_IDX_HI(txprod) >> 4;
1367
1368 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1369 printf("sf%d: TX ring full, resetting\n", sc->sf_unit);
1370 sf_init(sc);
1371 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1372 i = SF_IDX_HI(txprod) >> 4;
1373 }
1374
1375 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1376 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
1377 ifp->if_flags |= IFF_OACTIVE;
1378 cur_tx = NULL;
1379 break;
1380 }
1381 IF_DEQUEUE(&ifp->if_snd, m_head);
1382 if (m_head == NULL)
1383 break;
1384
1385 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1386 if (sf_encap(sc, cur_tx, m_head)) {
1387 IF_PREPEND(&ifp->if_snd, m_head);
1388 ifp->if_flags |= IFF_OACTIVE;
1389 cur_tx = NULL;
1390 break;
1391 }
1392
1393 /*
1394 * If there's a BPF listener, bounce a copy of this frame
1395 * to him.
1396 */
1397 BPF_MTAP(ifp, m_head);
1398
1399 SF_INC(i, SF_TX_DLIST_CNT);
1400 sc->sf_tx_cnt++;
1401 /*
1402 * Don't get the TX DMA queue get too full.
1403 */
1404 if (sc->sf_tx_cnt > 64)
1405 break;
1406 }
1407
1408 if (cur_tx == NULL) {
1409 SF_UNLOCK(sc);
1410 return;
1411 }
1412
1413 /* Transmit */
1414 csr_write_4(sc, SF_TXDQ_PRODIDX,
1415 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1416 ((i << 20) & 0xFFFF0000));
1417
1418 ifp->if_timer = 5;
1419
1420 SF_UNLOCK(sc);
1421
1422 return;
1423 }
1424
1425 static void
1426 sf_stop(sc)
1427 struct sf_softc *sc;
1428 {
1429 int i;
1430 struct ifnet *ifp;
1431
1432 SF_LOCK(sc);
1433
1434 ifp = &sc->arpcom.ac_if;
1435
1436 untimeout(sf_stats_update, sc, sc->sf_stat_ch);
1437
1438 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1439 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1440 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1441 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1442 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1443 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1444 csr_write_4(sc, SF_TXCQ_CTL, 0);
1445 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1446 csr_write_4(sc, SF_TXDQ_CTL, 0);
1447 sf_reset(sc);
1448
1449 sc->sf_link = 0;
1450
1451 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1452 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1453 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1454 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1455 }
1456 }
1457
1458 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1459 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1460 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1461 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1462 }
1463 }
1464
1465 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1466 SF_UNLOCK(sc);
1467
1468 return;
1469 }
1470
1471 /*
1472 * Note: it is important that this function not be interrupted. We
1473 * use a two-stage register access scheme: if we are interrupted in
1474 * between setting the indirect address register and reading from the
1475 * indirect data register, the contents of the address register could
1476 * be changed out from under us.
1477 */
1478 static void
1479 sf_stats_update(xsc)
1480 void *xsc;
1481 {
1482 struct sf_softc *sc;
1483 struct ifnet *ifp;
1484 struct mii_data *mii;
1485 struct sf_stats stats;
1486 u_int32_t *ptr;
1487 int i;
1488
1489 sc = xsc;
1490 SF_LOCK(sc);
1491 ifp = &sc->arpcom.ac_if;
1492 mii = device_get_softc(sc->sf_miibus);
1493
1494 ptr = (u_int32_t *)&stats;
1495 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1496 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1497 (i + sizeof(u_int32_t)));
1498
1499 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1500 csr_write_4(sc, SF_STATS_BASE +
1501 (i + sizeof(u_int32_t)), 0);
1502
1503 ifp->if_collisions += stats.sf_tx_single_colls +
1504 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1505
1506 mii_tick(mii);
1507
1508 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE &&
1509 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1510 sc->sf_link++;
1511 if (ifp->if_snd.ifq_head != NULL)
1512 sf_start(ifp);
1513 }
1514
1515 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1516
1517 SF_UNLOCK(sc);
1518
1519 return;
1520 }
1521
1522 static void
1523 sf_watchdog(ifp)
1524 struct ifnet *ifp;
1525 {
1526 struct sf_softc *sc;
1527
1528 sc = ifp->if_softc;
1529
1530 SF_LOCK(sc);
1531
1532 ifp->if_oerrors++;
1533 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1534
1535 sf_stop(sc);
1536 sf_reset(sc);
1537 sf_init(sc);
1538
1539 if (ifp->if_snd.ifq_head != NULL)
1540 sf_start(ifp);
1541
1542 SF_UNLOCK(sc);
1543
1544 return;
1545 }
1546
1547 static void
1548 sf_shutdown(dev)
1549 device_t dev;
1550 {
1551 struct sf_softc *sc;
1552
1553 sc = device_get_softc(dev);
1554
1555 sf_stop(sc);
1556
1557 return;
1558 }
Cache object: 2d04bc3f7d95032d8856c3ec0a2f86d3
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