Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sf.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/5.2/sys/pci/if_sf.c 122689 2003-11-14 19:00:32Z sam $"); 35 36 /* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45 /* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/sockio.h> 85 #include <sys/mbuf.h> 86 #include <sys/malloc.h> 87 #include <sys/kernel.h> 88 #include <sys/socket.h> 89 90 #include <net/if.h> 91 #include <net/if_arp.h> 92 #include <net/ethernet.h> 93 #include <net/if_dl.h> 94 #include <net/if_media.h> 95 96 #include <net/bpf.h> 97 98 #include <vm/vm.h> /* for vtophys */ 99 #include <vm/pmap.h> /* for vtophys */ 100 #include <machine/bus_pio.h> 101 #include <machine/bus_memio.h> 102 #include <machine/bus.h> 103 #include <machine/resource.h> 104 #include <sys/bus.h> 105 #include <sys/rman.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 110 /* "controller miibus0" required. See GENERIC if you get errors here. */ 111 #include "miibus_if.h" 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 116 #define SF_USEIOSPACE 117 118 #include <pci/if_sfreg.h> 119 120 MODULE_DEPEND(sf, pci, 1, 1, 1); 121 MODULE_DEPEND(sf, ether, 1, 1, 1); 122 MODULE_DEPEND(sf, miibus, 1, 1, 1); 123 124 static struct sf_type sf_devs[] = { 125 { AD_VENDORID, AD_DEVICEID_STARFIRE, 126 "Adaptec AIC-6915 10/100BaseTX" }, 127 { 0, 0, NULL } 128 }; 129 130 static int sf_probe (device_t); 131 static int sf_attach (device_t); 132 static int sf_detach (device_t); 133 static void sf_intr (void *); 134 static void sf_stats_update (void *); 135 static void sf_rxeof (struct sf_softc *); 136 static void sf_txeof (struct sf_softc *); 137 static int sf_encap (struct sf_softc *, 138 struct sf_tx_bufdesc_type0 *, 139 struct mbuf *); 140 static void sf_start (struct ifnet *); 141 static int sf_ioctl (struct ifnet *, u_long, caddr_t); 142 static void sf_init (void *); 143 static void sf_stop (struct sf_softc *); 144 static void sf_watchdog (struct ifnet *); 145 static void sf_shutdown (device_t); 146 static int sf_ifmedia_upd (struct ifnet *); 147 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148 static void sf_reset (struct sf_softc *); 149 static int sf_init_rx_ring (struct sf_softc *); 150 static void sf_init_tx_ring (struct sf_softc *); 151 static int sf_newbuf (struct sf_softc *, 152 struct sf_rx_bufdesc_type0 *, 153 struct mbuf *); 154 static void sf_setmulti (struct sf_softc *); 155 static int sf_setperf (struct sf_softc *, int, caddr_t); 156 static int sf_sethash (struct sf_softc *, caddr_t, int); 157 #ifdef notdef 158 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 159 #endif 160 161 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 162 static u_int32_t sf_mchash (caddr_t); 163 164 static int sf_miibus_readreg (device_t, int, int); 165 static int sf_miibus_writereg (device_t, int, int, int); 166 static void sf_miibus_statchg (device_t); 167 168 static u_int32_t csr_read_4 (struct sf_softc *, int); 169 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 170 static void sf_txthresh_adjust (struct sf_softc *); 171 172 #ifdef SF_USEIOSPACE 173 #define SF_RES SYS_RES_IOPORT 174 #define SF_RID SF_PCI_LOIO 175 #else 176 #define SF_RES SYS_RES_MEMORY 177 #define SF_RID SF_PCI_LOMEM 178 #endif 179 180 static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197 }; 198 199 static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203 }; 204 205 static devclass_t sf_devclass; 206 207 DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 208 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 209 210 #define SF_SETBIT(sc, reg, x) \ 211 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 212 213 #define SF_CLRBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 215 216 static u_int32_t 217 csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220 { 221 u_int32_t val; 222 223 #ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226 #else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228 #endif 229 230 return(val); 231 } 232 233 static u_int8_t 234 sf_read_eeprom(sc, reg) 235 struct sf_softc *sc; 236 int reg; 237 { 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244 } 245 246 static void 247 csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251 { 252 #ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255 #else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257 #endif 258 return; 259 } 260 261 static u_int32_t 262 sf_mchash(addr) 263 caddr_t addr; 264 { 265 u_int32_t crc, carry; 266 int idx, bit; 267 u_int8_t data; 268 269 /* Compute CRC for the address value. */ 270 crc = 0xFFFFFFFF; /* initial value */ 271 272 for (idx = 0; idx < 6; idx++) { 273 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 274 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 275 crc <<= 1; 276 if (carry) 277 crc = (crc ^ 0x04c11db6) | carry; 278 } 279 } 280 281 /* return the filter bit position */ 282 return(crc >> 23 & 0x1FF); 283 } 284 285 /* 286 * Copy the address 'mac' into the perfect RX filter entry at 287 * offset 'idx.' The perfect filter only has 16 entries so do 288 * some sanity tests. 289 */ 290 static int 291 sf_setperf(sc, idx, mac) 292 struct sf_softc *sc; 293 int idx; 294 caddr_t mac; 295 { 296 u_int16_t *p; 297 298 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 299 return(EINVAL); 300 301 if (mac == NULL) 302 return(EINVAL); 303 304 p = (u_int16_t *)mac; 305 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 310 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 311 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 312 313 return(0); 314 } 315 316 /* 317 * Set the bit in the 512-bit hash table that corresponds to the 318 * specified mac address 'mac.' If 'prio' is nonzero, update the 319 * priority hash table instead of the filter hash table. 320 */ 321 static int 322 sf_sethash(sc, mac, prio) 323 struct sf_softc *sc; 324 caddr_t mac; 325 int prio; 326 { 327 u_int32_t h = 0; 328 329 if (mac == NULL) 330 return(EINVAL); 331 332 h = sf_mchash(mac); 333 334 if (prio) { 335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 337 } else { 338 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 339 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 340 } 341 342 return(0); 343 } 344 345 #ifdef notdef 346 /* 347 * Set a VLAN tag in the receive filter. 348 */ 349 static int 350 sf_setvlan(sc, idx, vlan) 351 struct sf_softc *sc; 352 int idx; 353 u_int32_t vlan; 354 { 355 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 356 return(EINVAL); 357 358 csr_write_4(sc, SF_RXFILT_HASH_BASE + 359 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 360 361 return(0); 362 } 363 #endif 364 365 static int 366 sf_miibus_readreg(dev, phy, reg) 367 device_t dev; 368 int phy, reg; 369 { 370 struct sf_softc *sc; 371 int i; 372 u_int32_t val = 0; 373 374 sc = device_get_softc(dev); 375 376 for (i = 0; i < SF_TIMEOUT; i++) { 377 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 378 if (val & SF_MII_DATAVALID) 379 break; 380 } 381 382 if (i == SF_TIMEOUT) 383 return(0); 384 385 if ((val & 0x0000FFFF) == 0xFFFF) 386 return(0); 387 388 return(val & 0x0000FFFF); 389 } 390 391 static int 392 sf_miibus_writereg(dev, phy, reg, val) 393 device_t dev; 394 int phy, reg, val; 395 { 396 struct sf_softc *sc; 397 int i; 398 int busy; 399 400 sc = device_get_softc(dev); 401 402 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 403 404 for (i = 0; i < SF_TIMEOUT; i++) { 405 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 406 if (!(busy & SF_MII_BUSY)) 407 break; 408 } 409 410 return(0); 411 } 412 413 static void 414 sf_miibus_statchg(dev) 415 device_t dev; 416 { 417 struct sf_softc *sc; 418 struct mii_data *mii; 419 420 sc = device_get_softc(dev); 421 mii = device_get_softc(sc->sf_miibus); 422 423 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 424 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 425 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 426 } else { 427 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 428 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 429 } 430 431 return; 432 } 433 434 static void 435 sf_setmulti(sc) 436 struct sf_softc *sc; 437 { 438 struct ifnet *ifp; 439 int i; 440 struct ifmultiaddr *ifma; 441 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 442 443 ifp = &sc->arpcom.ac_if; 444 445 /* First zot all the existing filters. */ 446 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 447 sf_setperf(sc, i, (char *)&dummy); 448 for (i = SF_RXFILT_HASH_BASE; 449 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 450 csr_write_4(sc, i, 0); 451 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 452 453 /* Now program new ones. */ 454 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 455 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 456 } else { 457 i = 1; 458 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 459 if (ifma->ifma_addr->sa_family != AF_LINK) 460 continue; 461 /* 462 * Program the first 15 multicast groups 463 * into the perfect filter. For all others, 464 * use the hash table. 465 */ 466 if (i < SF_RXFILT_PERFECT_CNT) { 467 sf_setperf(sc, i, 468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 469 i++; 470 continue; 471 } 472 473 sf_sethash(sc, 474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 475 } 476 } 477 478 return; 479 } 480 481 /* 482 * Set media options. 483 */ 484 static int 485 sf_ifmedia_upd(ifp) 486 struct ifnet *ifp; 487 { 488 struct sf_softc *sc; 489 struct mii_data *mii; 490 491 sc = ifp->if_softc; 492 mii = device_get_softc(sc->sf_miibus); 493 sc->sf_link = 0; 494 if (mii->mii_instance) { 495 struct mii_softc *miisc; 496 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 497 mii_phy_reset(miisc); 498 } 499 mii_mediachg(mii); 500 501 return(0); 502 } 503 504 /* 505 * Report current media status. 506 */ 507 static void 508 sf_ifmedia_sts(ifp, ifmr) 509 struct ifnet *ifp; 510 struct ifmediareq *ifmr; 511 { 512 struct sf_softc *sc; 513 struct mii_data *mii; 514 515 sc = ifp->if_softc; 516 mii = device_get_softc(sc->sf_miibus); 517 518 mii_pollstat(mii); 519 ifmr->ifm_active = mii->mii_media_active; 520 ifmr->ifm_status = mii->mii_media_status; 521 522 return; 523 } 524 525 static int 526 sf_ioctl(ifp, command, data) 527 struct ifnet *ifp; 528 u_long command; 529 caddr_t data; 530 { 531 struct sf_softc *sc = ifp->if_softc; 532 struct ifreq *ifr = (struct ifreq *) data; 533 struct mii_data *mii; 534 int error = 0; 535 536 SF_LOCK(sc); 537 538 switch(command) { 539 case SIOCSIFFLAGS: 540 if (ifp->if_flags & IFF_UP) { 541 if (ifp->if_flags & IFF_RUNNING && 542 ifp->if_flags & IFF_PROMISC && 543 !(sc->sf_if_flags & IFF_PROMISC)) { 544 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 545 } else if (ifp->if_flags & IFF_RUNNING && 546 !(ifp->if_flags & IFF_PROMISC) && 547 sc->sf_if_flags & IFF_PROMISC) { 548 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 549 } else if (!(ifp->if_flags & IFF_RUNNING)) 550 sf_init(sc); 551 } else { 552 if (ifp->if_flags & IFF_RUNNING) 553 sf_stop(sc); 554 } 555 sc->sf_if_flags = ifp->if_flags; 556 error = 0; 557 break; 558 case SIOCADDMULTI: 559 case SIOCDELMULTI: 560 sf_setmulti(sc); 561 error = 0; 562 break; 563 case SIOCGIFMEDIA: 564 case SIOCSIFMEDIA: 565 mii = device_get_softc(sc->sf_miibus); 566 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 567 break; 568 default: 569 error = ether_ioctl(ifp, command, data); 570 break; 571 } 572 573 SF_UNLOCK(sc); 574 575 return(error); 576 } 577 578 static void 579 sf_reset(sc) 580 struct sf_softc *sc; 581 { 582 register int i; 583 584 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 585 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 586 DELAY(1000); 587 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 588 589 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 590 591 for (i = 0; i < SF_TIMEOUT; i++) { 592 DELAY(10); 593 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 594 break; 595 } 596 597 if (i == SF_TIMEOUT) 598 printf("sf%d: reset never completed!\n", sc->sf_unit); 599 600 /* Wait a little while for the chip to get its brains in order. */ 601 DELAY(1000); 602 return; 603 } 604 605 /* 606 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 607 * IDs against our list and return a device name if we find a match. 608 * We also check the subsystem ID so that we can identify exactly which 609 * NIC has been found, if possible. 610 */ 611 static int 612 sf_probe(dev) 613 device_t dev; 614 { 615 struct sf_type *t; 616 617 t = sf_devs; 618 619 while(t->sf_name != NULL) { 620 if ((pci_get_vendor(dev) == t->sf_vid) && 621 (pci_get_device(dev) == t->sf_did)) { 622 switch((pci_read_config(dev, 623 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 624 case AD_SUBSYSID_62011_REV0: 625 case AD_SUBSYSID_62011_REV1: 626 device_set_desc(dev, 627 "Adaptec ANA-62011 10/100BaseTX"); 628 return(0); 629 case AD_SUBSYSID_62022: 630 device_set_desc(dev, 631 "Adaptec ANA-62022 10/100BaseTX"); 632 return(0); 633 case AD_SUBSYSID_62044_REV0: 634 case AD_SUBSYSID_62044_REV1: 635 device_set_desc(dev, 636 "Adaptec ANA-62044 10/100BaseTX"); 637 return(0); 638 case AD_SUBSYSID_62020: 639 device_set_desc(dev, 640 "Adaptec ANA-62020 10/100BaseFX"); 641 return(0); 642 case AD_SUBSYSID_69011: 643 device_set_desc(dev, 644 "Adaptec ANA-69011 10/100BaseTX"); 645 return(0); 646 default: 647 device_set_desc(dev, t->sf_name); 648 return(0); 649 break; 650 } 651 } 652 t++; 653 } 654 655 return(ENXIO); 656 } 657 658 /* 659 * Attach the interface. Allocate softc structures, do ifmedia 660 * setup and ethernet/BPF attach. 661 */ 662 static int 663 sf_attach(dev) 664 device_t dev; 665 { 666 int i; 667 struct sf_softc *sc; 668 struct ifnet *ifp; 669 int unit, rid, error = 0; 670 671 sc = device_get_softc(dev); 672 unit = device_get_unit(dev); 673 674 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 675 MTX_DEF | MTX_RECURSE); 676 #ifndef BURN_BRIDGES 677 /* 678 * Handle power management nonsense. 679 */ 680 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 681 u_int32_t iobase, membase, irq; 682 683 /* Save important PCI config data. */ 684 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 685 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 686 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 687 688 /* Reset the power state. */ 689 printf("sf%d: chip is in D%d power mode " 690 "-- setting to D0\n", unit, 691 pci_get_powerstate(dev)); 692 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 693 694 /* Restore PCI config data. */ 695 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 696 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 697 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 698 } 699 #endif 700 /* 701 * Map control/status registers. 702 */ 703 pci_enable_busmaster(dev); 704 705 rid = SF_RID; 706 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 707 0, ~0, 1, RF_ACTIVE); 708 709 if (sc->sf_res == NULL) { 710 printf ("sf%d: couldn't map ports\n", unit); 711 error = ENXIO; 712 goto fail; 713 } 714 715 sc->sf_btag = rman_get_bustag(sc->sf_res); 716 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 717 718 /* Allocate interrupt */ 719 rid = 0; 720 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 721 RF_SHAREABLE | RF_ACTIVE); 722 723 if (sc->sf_irq == NULL) { 724 printf("sf%d: couldn't map interrupt\n", unit); 725 error = ENXIO; 726 goto fail; 727 } 728 729 callout_handle_init(&sc->sf_stat_ch); 730 /* Reset the adapter. */ 731 sf_reset(sc); 732 733 /* 734 * Get station address from the EEPROM. 735 */ 736 for (i = 0; i < ETHER_ADDR_LEN; i++) 737 sc->arpcom.ac_enaddr[i] = 738 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 739 740 /* 741 * An Adaptec chip was detected. Inform the world. 742 */ 743 printf("sf%d: Ethernet address: %6D\n", unit, 744 sc->arpcom.ac_enaddr, ":"); 745 746 sc->sf_unit = unit; 747 748 /* Allocate the descriptor queues. */ 749 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 750 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 751 752 if (sc->sf_ldata == NULL) { 753 printf("sf%d: no memory for list buffers!\n", unit); 754 error = ENXIO; 755 goto fail; 756 } 757 758 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 759 760 /* Do MII setup. */ 761 if (mii_phy_probe(dev, &sc->sf_miibus, 762 sf_ifmedia_upd, sf_ifmedia_sts)) { 763 printf("sf%d: MII without any phy!\n", sc->sf_unit); 764 error = ENXIO; 765 goto fail; 766 } 767 768 ifp = &sc->arpcom.ac_if; 769 ifp->if_softc = sc; 770 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 771 ifp->if_mtu = ETHERMTU; 772 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 773 ifp->if_ioctl = sf_ioctl; 774 ifp->if_output = ether_output; 775 ifp->if_start = sf_start; 776 ifp->if_watchdog = sf_watchdog; 777 ifp->if_init = sf_init; 778 ifp->if_baudrate = 10000000; 779 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 780 781 /* 782 * Call MI attach routine. 783 */ 784 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 785 786 /* Hook interrupt last to avoid having to lock softc */ 787 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 788 sf_intr, sc, &sc->sf_intrhand); 789 790 if (error) { 791 printf("sf%d: couldn't set up irq\n", unit); 792 ether_ifdetach(ifp); 793 goto fail; 794 } 795 796 fail: 797 if (error) 798 sf_detach(dev); 799 800 return(error); 801 } 802 803 /* 804 * Shutdown hardware and free up resources. This can be called any 805 * time after the mutex has been initialized. It is called in both 806 * the error case in attach and the normal detach case so it needs 807 * to be careful about only freeing resources that have actually been 808 * allocated. 809 */ 810 static int 811 sf_detach(dev) 812 device_t dev; 813 { 814 struct sf_softc *sc; 815 struct ifnet *ifp; 816 817 sc = device_get_softc(dev); 818 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 819 SF_LOCK(sc); 820 ifp = &sc->arpcom.ac_if; 821 822 /* These should only be active if attach succeeded */ 823 if (device_is_attached(dev)) { 824 sf_stop(sc); 825 ether_ifdetach(ifp); 826 } 827 if (sc->sf_miibus) 828 device_delete_child(dev, sc->sf_miibus); 829 bus_generic_detach(dev); 830 831 if (sc->sf_intrhand) 832 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 833 if (sc->sf_irq) 834 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 835 if (sc->sf_res) 836 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 837 838 if (sc->sf_ldata) 839 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 840 841 SF_UNLOCK(sc); 842 mtx_destroy(&sc->sf_mtx); 843 844 return(0); 845 } 846 847 static int 848 sf_init_rx_ring(sc) 849 struct sf_softc *sc; 850 { 851 struct sf_list_data *ld; 852 int i; 853 854 ld = sc->sf_ldata; 855 856 bzero((char *)ld->sf_rx_dlist_big, 857 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 858 bzero((char *)ld->sf_rx_clist, 859 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 860 861 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 862 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 863 return(ENOBUFS); 864 } 865 866 return(0); 867 } 868 869 static void 870 sf_init_tx_ring(sc) 871 struct sf_softc *sc; 872 { 873 struct sf_list_data *ld; 874 int i; 875 876 ld = sc->sf_ldata; 877 878 bzero((char *)ld->sf_tx_dlist, 879 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 880 bzero((char *)ld->sf_tx_clist, 881 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 882 883 for (i = 0; i < SF_TX_DLIST_CNT; i++) 884 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 885 for (i = 0; i < SF_TX_CLIST_CNT; i++) 886 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 887 888 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 889 sc->sf_tx_cnt = 0; 890 891 return; 892 } 893 894 static int 895 sf_newbuf(sc, c, m) 896 struct sf_softc *sc; 897 struct sf_rx_bufdesc_type0 *c; 898 struct mbuf *m; 899 { 900 struct mbuf *m_new = NULL; 901 902 if (m == NULL) { 903 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 904 if (m_new == NULL) 905 return(ENOBUFS); 906 907 MCLGET(m_new, M_DONTWAIT); 908 if (!(m_new->m_flags & M_EXT)) { 909 m_freem(m_new); 910 return(ENOBUFS); 911 } 912 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 913 } else { 914 m_new = m; 915 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 916 m_new->m_data = m_new->m_ext.ext_buf; 917 } 918 919 m_adj(m_new, sizeof(u_int64_t)); 920 921 c->sf_mbuf = m_new; 922 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 923 c->sf_valid = 1; 924 925 return(0); 926 } 927 928 /* 929 * The starfire is programmed to use 'normal' mode for packet reception, 930 * which means we use the consumer/producer model for both the buffer 931 * descriptor queue and the completion descriptor queue. The only problem 932 * with this is that it involves a lot of register accesses: we have to 933 * read the RX completion consumer and producer indexes and the RX buffer 934 * producer index, plus the RX completion consumer and RX buffer producer 935 * indexes have to be updated. It would have been easier if Adaptec had 936 * put each index in a separate register, especially given that the damn 937 * NIC has a 512K register space. 938 * 939 * In spite of all the lovely features that Adaptec crammed into the 6915, 940 * it is marred by one truly stupid design flaw, which is that receive 941 * buffer addresses must be aligned on a longword boundary. This forces 942 * the packet payload to be unaligned, which is suboptimal on the x86 and 943 * completely unuseable on the Alpha. Our only recourse is to copy received 944 * packets into properly aligned buffers before handing them off. 945 */ 946 947 static void 948 sf_rxeof(sc) 949 struct sf_softc *sc; 950 { 951 struct mbuf *m; 952 struct ifnet *ifp; 953 struct sf_rx_bufdesc_type0 *desc; 954 struct sf_rx_cmpdesc_type3 *cur_rx; 955 u_int32_t rxcons, rxprod; 956 int cmpprodidx, cmpconsidx, bufprodidx; 957 958 SF_LOCK_ASSERT(sc); 959 960 ifp = &sc->arpcom.ac_if; 961 962 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 963 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 964 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 965 cmpconsidx = SF_IDX_LO(rxcons); 966 bufprodidx = SF_IDX_LO(rxprod); 967 968 while (cmpconsidx != cmpprodidx) { 969 struct mbuf *m0; 970 971 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 972 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 973 m = desc->sf_mbuf; 974 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 975 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 976 977 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 978 ifp->if_ierrors++; 979 sf_newbuf(sc, desc, m); 980 continue; 981 } 982 983 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 984 ifp, NULL); 985 sf_newbuf(sc, desc, m); 986 if (m0 == NULL) { 987 ifp->if_ierrors++; 988 continue; 989 } 990 m = m0; 991 992 ifp->if_ipackets++; 993 SF_UNLOCK(sc); 994 (*ifp->if_input)(ifp, m); 995 SF_LOCK(sc); 996 } 997 998 csr_write_4(sc, SF_CQ_CONSIDX, 999 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1000 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1001 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1002 1003 return; 1004 } 1005 1006 /* 1007 * Read the transmit status from the completion queue and release 1008 * mbufs. Note that the buffer descriptor index in the completion 1009 * descriptor is an offset from the start of the transmit buffer 1010 * descriptor list in bytes. This is important because the manual 1011 * gives the impression that it should match the producer/consumer 1012 * index, which is the offset in 8 byte blocks. 1013 */ 1014 static void 1015 sf_txeof(sc) 1016 struct sf_softc *sc; 1017 { 1018 int txcons, cmpprodidx, cmpconsidx; 1019 struct sf_tx_cmpdesc_type1 *cur_cmp; 1020 struct sf_tx_bufdesc_type0 *cur_tx; 1021 struct ifnet *ifp; 1022 1023 ifp = &sc->arpcom.ac_if; 1024 1025 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1026 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1027 cmpconsidx = SF_IDX_HI(txcons); 1028 1029 while (cmpconsidx != cmpprodidx) { 1030 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1031 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1032 1033 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1034 ifp->if_opackets++; 1035 else { 1036 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1037 sf_txthresh_adjust(sc); 1038 ifp->if_oerrors++; 1039 } 1040 1041 sc->sf_tx_cnt--; 1042 if (cur_tx->sf_mbuf != NULL) { 1043 m_freem(cur_tx->sf_mbuf); 1044 cur_tx->sf_mbuf = NULL; 1045 } else 1046 break; 1047 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1048 } 1049 1050 ifp->if_timer = 0; 1051 ifp->if_flags &= ~IFF_OACTIVE; 1052 1053 csr_write_4(sc, SF_CQ_CONSIDX, 1054 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1055 ((cmpconsidx << 16) & 0xFFFF0000)); 1056 1057 return; 1058 } 1059 1060 static void 1061 sf_txthresh_adjust(sc) 1062 struct sf_softc *sc; 1063 { 1064 u_int32_t txfctl; 1065 u_int8_t txthresh; 1066 1067 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1068 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1069 if (txthresh < 0xFF) { 1070 txthresh++; 1071 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1072 txfctl |= txthresh; 1073 #ifdef DIAGNOSTIC 1074 printf("sf%d: tx underrun, increasing " 1075 "tx threshold to %d bytes\n", 1076 sc->sf_unit, txthresh * 4); 1077 #endif 1078 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1079 } 1080 1081 return; 1082 } 1083 1084 static void 1085 sf_intr(arg) 1086 void *arg; 1087 { 1088 struct sf_softc *sc; 1089 struct ifnet *ifp; 1090 u_int32_t status; 1091 1092 sc = arg; 1093 SF_LOCK(sc); 1094 1095 ifp = &sc->arpcom.ac_if; 1096 1097 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1098 SF_UNLOCK(sc); 1099 return; 1100 } 1101 1102 /* Disable interrupts. */ 1103 csr_write_4(sc, SF_IMR, 0x00000000); 1104 1105 for (;;) { 1106 status = csr_read_4(sc, SF_ISR); 1107 if (status) 1108 csr_write_4(sc, SF_ISR, status); 1109 1110 if (!(status & SF_INTRS)) 1111 break; 1112 1113 if (status & SF_ISR_RXDQ1_DMADONE) 1114 sf_rxeof(sc); 1115 1116 if (status & SF_ISR_TX_TXDONE || 1117 status & SF_ISR_TX_DMADONE || 1118 status & SF_ISR_TX_QUEUEDONE) 1119 sf_txeof(sc); 1120 1121 if (status & SF_ISR_TX_LOFIFO) 1122 sf_txthresh_adjust(sc); 1123 1124 if (status & SF_ISR_ABNORMALINTR) { 1125 if (status & SF_ISR_STATSOFLOW) { 1126 untimeout(sf_stats_update, sc, 1127 sc->sf_stat_ch); 1128 sf_stats_update(sc); 1129 } else 1130 sf_init(sc); 1131 } 1132 } 1133 1134 /* Re-enable interrupts. */ 1135 csr_write_4(sc, SF_IMR, SF_INTRS); 1136 1137 if (ifp->if_snd.ifq_head != NULL) 1138 sf_start(ifp); 1139 1140 SF_UNLOCK(sc); 1141 return; 1142 } 1143 1144 static void 1145 sf_init(xsc) 1146 void *xsc; 1147 { 1148 struct sf_softc *sc; 1149 struct ifnet *ifp; 1150 struct mii_data *mii; 1151 int i; 1152 1153 sc = xsc; 1154 SF_LOCK(sc); 1155 ifp = &sc->arpcom.ac_if; 1156 mii = device_get_softc(sc->sf_miibus); 1157 1158 sf_stop(sc); 1159 sf_reset(sc); 1160 1161 /* Init all the receive filter registers */ 1162 for (i = SF_RXFILT_PERFECT_BASE; 1163 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1164 csr_write_4(sc, i, 0); 1165 1166 /* Empty stats counter registers. */ 1167 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1168 csr_write_4(sc, SF_STATS_BASE + 1169 (i + sizeof(u_int32_t)), 0); 1170 1171 /* Init our MAC address */ 1172 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1173 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1174 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1175 1176 if (sf_init_rx_ring(sc) == ENOBUFS) { 1177 printf("sf%d: initialization failed: no " 1178 "memory for rx buffers\n", sc->sf_unit); 1179 SF_UNLOCK(sc); 1180 return; 1181 } 1182 1183 sf_init_tx_ring(sc); 1184 1185 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1186 1187 /* If we want promiscuous mode, set the allframes bit. */ 1188 if (ifp->if_flags & IFF_PROMISC) { 1189 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1190 } else { 1191 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1192 } 1193 1194 if (ifp->if_flags & IFF_BROADCAST) { 1195 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1196 } else { 1197 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1198 } 1199 1200 /* 1201 * Load the multicast filter. 1202 */ 1203 sf_setmulti(sc); 1204 1205 /* Init the completion queue indexes */ 1206 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1207 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1208 1209 /* Init the RX completion queue */ 1210 csr_write_4(sc, SF_RXCQ_CTL_1, 1211 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1212 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1213 1214 /* Init RX DMA control. */ 1215 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1216 1217 /* Init the RX buffer descriptor queue. */ 1218 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1219 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1220 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1221 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1222 1223 /* Init the TX completion queue */ 1224 csr_write_4(sc, SF_TXCQ_CTL, 1225 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1226 1227 /* Init the TX buffer descriptor queue. */ 1228 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1229 vtophys(sc->sf_ldata->sf_tx_dlist)); 1230 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1231 csr_write_4(sc, SF_TXDQ_CTL, 1232 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1233 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1234 1235 /* Enable autopadding of short TX frames. */ 1236 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1237 1238 /* Enable interrupts. */ 1239 csr_write_4(sc, SF_IMR, SF_INTRS); 1240 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1241 1242 /* Enable the RX and TX engines. */ 1243 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1244 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1245 1246 /*mii_mediachg(mii);*/ 1247 sf_ifmedia_upd(ifp); 1248 1249 ifp->if_flags |= IFF_RUNNING; 1250 ifp->if_flags &= ~IFF_OACTIVE; 1251 1252 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1253 1254 SF_UNLOCK(sc); 1255 1256 return; 1257 } 1258 1259 static int 1260 sf_encap(sc, c, m_head) 1261 struct sf_softc *sc; 1262 struct sf_tx_bufdesc_type0 *c; 1263 struct mbuf *m_head; 1264 { 1265 int frag = 0; 1266 struct sf_frag *f = NULL; 1267 struct mbuf *m; 1268 1269 m = m_head; 1270 1271 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1272 if (m->m_len != 0) { 1273 if (frag == SF_MAXFRAGS) 1274 break; 1275 f = &c->sf_frags[frag]; 1276 if (frag == 0) 1277 f->sf_pktlen = m_head->m_pkthdr.len; 1278 f->sf_fraglen = m->m_len; 1279 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1280 frag++; 1281 } 1282 } 1283 1284 if (m != NULL) { 1285 struct mbuf *m_new = NULL; 1286 1287 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1288 if (m_new == NULL) { 1289 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1290 return(1); 1291 } 1292 1293 if (m_head->m_pkthdr.len > MHLEN) { 1294 MCLGET(m_new, M_DONTWAIT); 1295 if (!(m_new->m_flags & M_EXT)) { 1296 m_freem(m_new); 1297 printf("sf%d: no memory for tx list\n", 1298 sc->sf_unit); 1299 return(1); 1300 } 1301 } 1302 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1303 mtod(m_new, caddr_t)); 1304 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1305 m_freem(m_head); 1306 m_head = m_new; 1307 f = &c->sf_frags[0]; 1308 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1309 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1310 frag = 1; 1311 } 1312 1313 c->sf_mbuf = m_head; 1314 c->sf_id = SF_TX_BUFDESC_ID; 1315 c->sf_fragcnt = frag; 1316 c->sf_intr = 1; 1317 c->sf_caltcp = 0; 1318 c->sf_crcen = 1; 1319 1320 return(0); 1321 } 1322 1323 static void 1324 sf_start(ifp) 1325 struct ifnet *ifp; 1326 { 1327 struct sf_softc *sc; 1328 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1329 struct mbuf *m_head = NULL; 1330 int i, txprod; 1331 1332 sc = ifp->if_softc; 1333 SF_LOCK(sc); 1334 1335 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1336 SF_UNLOCK(sc); 1337 return; 1338 } 1339 1340 if (ifp->if_flags & IFF_OACTIVE) { 1341 SF_UNLOCK(sc); 1342 return; 1343 } 1344 1345 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1346 i = SF_IDX_HI(txprod) >> 4; 1347 1348 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1349 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1350 sf_init(sc); 1351 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1352 i = SF_IDX_HI(txprod) >> 4; 1353 } 1354 1355 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1356 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1357 ifp->if_flags |= IFF_OACTIVE; 1358 cur_tx = NULL; 1359 break; 1360 } 1361 IF_DEQUEUE(&ifp->if_snd, m_head); 1362 if (m_head == NULL) 1363 break; 1364 1365 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1366 if (sf_encap(sc, cur_tx, m_head)) { 1367 IF_PREPEND(&ifp->if_snd, m_head); 1368 ifp->if_flags |= IFF_OACTIVE; 1369 cur_tx = NULL; 1370 break; 1371 } 1372 1373 /* 1374 * If there's a BPF listener, bounce a copy of this frame 1375 * to him. 1376 */ 1377 BPF_MTAP(ifp, m_head); 1378 1379 SF_INC(i, SF_TX_DLIST_CNT); 1380 sc->sf_tx_cnt++; 1381 /* 1382 * Don't get the TX DMA queue get too full. 1383 */ 1384 if (sc->sf_tx_cnt > 64) 1385 break; 1386 } 1387 1388 if (cur_tx == NULL) { 1389 SF_UNLOCK(sc); 1390 return; 1391 } 1392 1393 /* Transmit */ 1394 csr_write_4(sc, SF_TXDQ_PRODIDX, 1395 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1396 ((i << 20) & 0xFFFF0000)); 1397 1398 ifp->if_timer = 5; 1399 1400 SF_UNLOCK(sc); 1401 1402 return; 1403 } 1404 1405 static void 1406 sf_stop(sc) 1407 struct sf_softc *sc; 1408 { 1409 int i; 1410 struct ifnet *ifp; 1411 1412 SF_LOCK(sc); 1413 1414 ifp = &sc->arpcom.ac_if; 1415 1416 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1417 1418 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1419 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1420 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1421 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1422 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1423 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1424 csr_write_4(sc, SF_TXCQ_CTL, 0); 1425 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1426 csr_write_4(sc, SF_TXDQ_CTL, 0); 1427 sf_reset(sc); 1428 1429 sc->sf_link = 0; 1430 1431 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1432 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1433 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1434 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1435 } 1436 } 1437 1438 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1439 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1440 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1441 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1442 } 1443 } 1444 1445 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1446 SF_UNLOCK(sc); 1447 1448 return; 1449 } 1450 1451 /* 1452 * Note: it is important that this function not be interrupted. We 1453 * use a two-stage register access scheme: if we are interrupted in 1454 * between setting the indirect address register and reading from the 1455 * indirect data register, the contents of the address register could 1456 * be changed out from under us. 1457 */ 1458 static void 1459 sf_stats_update(xsc) 1460 void *xsc; 1461 { 1462 struct sf_softc *sc; 1463 struct ifnet *ifp; 1464 struct mii_data *mii; 1465 struct sf_stats stats; 1466 u_int32_t *ptr; 1467 int i; 1468 1469 sc = xsc; 1470 SF_LOCK(sc); 1471 ifp = &sc->arpcom.ac_if; 1472 mii = device_get_softc(sc->sf_miibus); 1473 1474 ptr = (u_int32_t *)&stats; 1475 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1476 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1477 (i + sizeof(u_int32_t))); 1478 1479 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1480 csr_write_4(sc, SF_STATS_BASE + 1481 (i + sizeof(u_int32_t)), 0); 1482 1483 ifp->if_collisions += stats.sf_tx_single_colls + 1484 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1485 1486 mii_tick(mii); 1487 1488 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1489 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1490 sc->sf_link++; 1491 if (ifp->if_snd.ifq_head != NULL) 1492 sf_start(ifp); 1493 } 1494 1495 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1496 1497 SF_UNLOCK(sc); 1498 1499 return; 1500 } 1501 1502 static void 1503 sf_watchdog(ifp) 1504 struct ifnet *ifp; 1505 { 1506 struct sf_softc *sc; 1507 1508 sc = ifp->if_softc; 1509 1510 SF_LOCK(sc); 1511 1512 ifp->if_oerrors++; 1513 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1514 1515 sf_stop(sc); 1516 sf_reset(sc); 1517 sf_init(sc); 1518 1519 if (ifp->if_snd.ifq_head != NULL) 1520 sf_start(ifp); 1521 1522 SF_UNLOCK(sc); 1523 1524 return; 1525 } 1526 1527 static void 1528 sf_shutdown(dev) 1529 device_t dev; 1530 { 1531 struct sf_softc *sc; 1532 1533 sc = device_get_softc(dev); 1534 1535 sf_stop(sc); 1536 1537 return; 1538 }
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