Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sf.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/5.3/sys/pci/if_sf.c 134658 2004-09-02 20:57:40Z rwatson $"); 35 36 /* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45 /* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/sockio.h> 85 #include <sys/mbuf.h> 86 #include <sys/malloc.h> 87 #include <sys/kernel.h> 88 #include <sys/module.h> 89 #include <sys/socket.h> 90 91 #include <net/if.h> 92 #include <net/if_arp.h> 93 #include <net/ethernet.h> 94 #include <net/if_dl.h> 95 #include <net/if_media.h> 96 97 #include <net/bpf.h> 98 99 #include <vm/vm.h> /* for vtophys */ 100 #include <vm/pmap.h> /* for vtophys */ 101 #include <machine/bus_pio.h> 102 #include <machine/bus_memio.h> 103 #include <machine/bus.h> 104 #include <machine/resource.h> 105 #include <sys/bus.h> 106 #include <sys/rman.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 /* "controller miibus0" required. See GENERIC if you get errors here. */ 112 #include "miibus_if.h" 113 114 #include <dev/pci/pcireg.h> 115 #include <dev/pci/pcivar.h> 116 117 #define SF_USEIOSPACE 118 119 #include <pci/if_sfreg.h> 120 121 MODULE_DEPEND(sf, pci, 1, 1, 1); 122 MODULE_DEPEND(sf, ether, 1, 1, 1); 123 MODULE_DEPEND(sf, miibus, 1, 1, 1); 124 125 static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129 }; 130 131 static int sf_probe (device_t); 132 static int sf_attach (device_t); 133 static int sf_detach (device_t); 134 static void sf_intr (void *); 135 static void sf_stats_update (void *); 136 static void sf_rxeof (struct sf_softc *); 137 static void sf_txeof (struct sf_softc *); 138 static int sf_encap (struct sf_softc *, 139 struct sf_tx_bufdesc_type0 *, 140 struct mbuf *); 141 static void sf_start (struct ifnet *); 142 static int sf_ioctl (struct ifnet *, u_long, caddr_t); 143 static void sf_init (void *); 144 static void sf_stop (struct sf_softc *); 145 static void sf_watchdog (struct ifnet *); 146 static void sf_shutdown (device_t); 147 static int sf_ifmedia_upd (struct ifnet *); 148 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149 static void sf_reset (struct sf_softc *); 150 static int sf_init_rx_ring (struct sf_softc *); 151 static void sf_init_tx_ring (struct sf_softc *); 152 static int sf_newbuf (struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155 static void sf_setmulti (struct sf_softc *); 156 static int sf_setperf (struct sf_softc *, int, caddr_t); 157 static int sf_sethash (struct sf_softc *, caddr_t, int); 158 #ifdef notdef 159 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 160 #endif 161 162 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 163 164 static int sf_miibus_readreg (device_t, int, int); 165 static int sf_miibus_writereg (device_t, int, int, int); 166 static void sf_miibus_statchg (device_t); 167 168 static u_int32_t csr_read_4 (struct sf_softc *, int); 169 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 170 static void sf_txthresh_adjust (struct sf_softc *); 171 172 #ifdef SF_USEIOSPACE 173 #define SF_RES SYS_RES_IOPORT 174 #define SF_RID SF_PCI_LOIO 175 #else 176 #define SF_RES SYS_RES_MEMORY 177 #define SF_RID SF_PCI_LOMEM 178 #endif 179 180 static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197 }; 198 199 static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203 }; 204 205 static devclass_t sf_devclass; 206 207 DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 208 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 209 210 #define SF_SETBIT(sc, reg, x) \ 211 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 212 213 #define SF_CLRBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 215 216 static u_int32_t 217 csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220 { 221 u_int32_t val; 222 223 #ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226 #else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228 #endif 229 230 return(val); 231 } 232 233 static u_int8_t 234 sf_read_eeprom(sc, reg) 235 struct sf_softc *sc; 236 int reg; 237 { 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244 } 245 246 static void 247 csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251 { 252 #ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255 #else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257 #endif 258 } 259 260 /* 261 * Copy the address 'mac' into the perfect RX filter entry at 262 * offset 'idx.' The perfect filter only has 16 entries so do 263 * some sanity tests. 264 */ 265 static int 266 sf_setperf(sc, idx, mac) 267 struct sf_softc *sc; 268 int idx; 269 caddr_t mac; 270 { 271 u_int16_t *p; 272 273 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 274 return(EINVAL); 275 276 if (mac == NULL) 277 return(EINVAL); 278 279 p = (u_int16_t *)mac; 280 281 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 282 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 283 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 284 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 285 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 286 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 287 288 return(0); 289 } 290 291 /* 292 * Set the bit in the 512-bit hash table that corresponds to the 293 * specified mac address 'mac.' If 'prio' is nonzero, update the 294 * priority hash table instead of the filter hash table. 295 */ 296 static int 297 sf_sethash(sc, mac, prio) 298 struct sf_softc *sc; 299 caddr_t mac; 300 int prio; 301 { 302 u_int32_t h; 303 304 if (mac == NULL) 305 return(EINVAL); 306 307 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 308 309 if (prio) { 310 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 311 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 312 } else { 313 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 314 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 315 } 316 317 return(0); 318 } 319 320 #ifdef notdef 321 /* 322 * Set a VLAN tag in the receive filter. 323 */ 324 static int 325 sf_setvlan(sc, idx, vlan) 326 struct sf_softc *sc; 327 int idx; 328 u_int32_t vlan; 329 { 330 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 331 return(EINVAL); 332 333 csr_write_4(sc, SF_RXFILT_HASH_BASE + 334 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 335 336 return(0); 337 } 338 #endif 339 340 static int 341 sf_miibus_readreg(dev, phy, reg) 342 device_t dev; 343 int phy, reg; 344 { 345 struct sf_softc *sc; 346 int i; 347 u_int32_t val = 0; 348 349 sc = device_get_softc(dev); 350 351 for (i = 0; i < SF_TIMEOUT; i++) { 352 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 353 if (val & SF_MII_DATAVALID) 354 break; 355 } 356 357 if (i == SF_TIMEOUT) 358 return(0); 359 360 if ((val & 0x0000FFFF) == 0xFFFF) 361 return(0); 362 363 return(val & 0x0000FFFF); 364 } 365 366 static int 367 sf_miibus_writereg(dev, phy, reg, val) 368 device_t dev; 369 int phy, reg, val; 370 { 371 struct sf_softc *sc; 372 int i; 373 int busy; 374 375 sc = device_get_softc(dev); 376 377 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 378 379 for (i = 0; i < SF_TIMEOUT; i++) { 380 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 381 if (!(busy & SF_MII_BUSY)) 382 break; 383 } 384 385 return(0); 386 } 387 388 static void 389 sf_miibus_statchg(dev) 390 device_t dev; 391 { 392 struct sf_softc *sc; 393 struct mii_data *mii; 394 395 sc = device_get_softc(dev); 396 mii = device_get_softc(sc->sf_miibus); 397 398 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 399 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 400 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 401 } else { 402 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 403 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 404 } 405 } 406 407 static void 408 sf_setmulti(sc) 409 struct sf_softc *sc; 410 { 411 struct ifnet *ifp; 412 int i; 413 struct ifmultiaddr *ifma; 414 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 415 416 ifp = &sc->arpcom.ac_if; 417 418 /* First zot all the existing filters. */ 419 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 420 sf_setperf(sc, i, (char *)&dummy); 421 for (i = SF_RXFILT_HASH_BASE; 422 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 423 csr_write_4(sc, i, 0); 424 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 425 426 /* Now program new ones. */ 427 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 428 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 429 } else { 430 i = 1; 431 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 432 if (ifma->ifma_addr->sa_family != AF_LINK) 433 continue; 434 /* 435 * Program the first 15 multicast groups 436 * into the perfect filter. For all others, 437 * use the hash table. 438 */ 439 if (i < SF_RXFILT_PERFECT_CNT) { 440 sf_setperf(sc, i, 441 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 442 i++; 443 continue; 444 } 445 446 sf_sethash(sc, 447 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 448 } 449 } 450 } 451 452 /* 453 * Set media options. 454 */ 455 static int 456 sf_ifmedia_upd(ifp) 457 struct ifnet *ifp; 458 { 459 struct sf_softc *sc; 460 struct mii_data *mii; 461 462 sc = ifp->if_softc; 463 mii = device_get_softc(sc->sf_miibus); 464 sc->sf_link = 0; 465 if (mii->mii_instance) { 466 struct mii_softc *miisc; 467 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 468 mii_phy_reset(miisc); 469 } 470 mii_mediachg(mii); 471 472 return(0); 473 } 474 475 /* 476 * Report current media status. 477 */ 478 static void 479 sf_ifmedia_sts(ifp, ifmr) 480 struct ifnet *ifp; 481 struct ifmediareq *ifmr; 482 { 483 struct sf_softc *sc; 484 struct mii_data *mii; 485 486 sc = ifp->if_softc; 487 mii = device_get_softc(sc->sf_miibus); 488 489 mii_pollstat(mii); 490 ifmr->ifm_active = mii->mii_media_active; 491 ifmr->ifm_status = mii->mii_media_status; 492 } 493 494 static int 495 sf_ioctl(ifp, command, data) 496 struct ifnet *ifp; 497 u_long command; 498 caddr_t data; 499 { 500 struct sf_softc *sc = ifp->if_softc; 501 struct ifreq *ifr = (struct ifreq *) data; 502 struct mii_data *mii; 503 int error = 0; 504 505 SF_LOCK(sc); 506 507 switch(command) { 508 case SIOCSIFFLAGS: 509 if (ifp->if_flags & IFF_UP) { 510 if (ifp->if_flags & IFF_RUNNING && 511 ifp->if_flags & IFF_PROMISC && 512 !(sc->sf_if_flags & IFF_PROMISC)) { 513 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 514 } else if (ifp->if_flags & IFF_RUNNING && 515 !(ifp->if_flags & IFF_PROMISC) && 516 sc->sf_if_flags & IFF_PROMISC) { 517 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 518 } else if (!(ifp->if_flags & IFF_RUNNING)) 519 sf_init(sc); 520 } else { 521 if (ifp->if_flags & IFF_RUNNING) 522 sf_stop(sc); 523 } 524 sc->sf_if_flags = ifp->if_flags; 525 error = 0; 526 break; 527 case SIOCADDMULTI: 528 case SIOCDELMULTI: 529 sf_setmulti(sc); 530 error = 0; 531 break; 532 case SIOCGIFMEDIA: 533 case SIOCSIFMEDIA: 534 mii = device_get_softc(sc->sf_miibus); 535 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 536 break; 537 default: 538 error = ether_ioctl(ifp, command, data); 539 break; 540 } 541 542 SF_UNLOCK(sc); 543 544 return(error); 545 } 546 547 static void 548 sf_reset(sc) 549 struct sf_softc *sc; 550 { 551 register int i; 552 553 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 554 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 555 DELAY(1000); 556 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 557 558 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 559 560 for (i = 0; i < SF_TIMEOUT; i++) { 561 DELAY(10); 562 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 563 break; 564 } 565 566 if (i == SF_TIMEOUT) 567 printf("sf%d: reset never completed!\n", sc->sf_unit); 568 569 /* Wait a little while for the chip to get its brains in order. */ 570 DELAY(1000); 571 } 572 573 /* 574 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 575 * IDs against our list and return a device name if we find a match. 576 * We also check the subsystem ID so that we can identify exactly which 577 * NIC has been found, if possible. 578 */ 579 static int 580 sf_probe(dev) 581 device_t dev; 582 { 583 struct sf_type *t; 584 585 t = sf_devs; 586 587 while(t->sf_name != NULL) { 588 if ((pci_get_vendor(dev) == t->sf_vid) && 589 (pci_get_device(dev) == t->sf_did)) { 590 switch((pci_read_config(dev, 591 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 592 case AD_SUBSYSID_62011_REV0: 593 case AD_SUBSYSID_62011_REV1: 594 device_set_desc(dev, 595 "Adaptec ANA-62011 10/100BaseTX"); 596 return(0); 597 case AD_SUBSYSID_62022: 598 device_set_desc(dev, 599 "Adaptec ANA-62022 10/100BaseTX"); 600 return(0); 601 case AD_SUBSYSID_62044_REV0: 602 case AD_SUBSYSID_62044_REV1: 603 device_set_desc(dev, 604 "Adaptec ANA-62044 10/100BaseTX"); 605 return(0); 606 case AD_SUBSYSID_62020: 607 device_set_desc(dev, 608 "Adaptec ANA-62020 10/100BaseFX"); 609 return(0); 610 case AD_SUBSYSID_69011: 611 device_set_desc(dev, 612 "Adaptec ANA-69011 10/100BaseTX"); 613 return(0); 614 default: 615 device_set_desc(dev, t->sf_name); 616 return(0); 617 break; 618 } 619 } 620 t++; 621 } 622 623 return(ENXIO); 624 } 625 626 /* 627 * Attach the interface. Allocate softc structures, do ifmedia 628 * setup and ethernet/BPF attach. 629 */ 630 static int 631 sf_attach(dev) 632 device_t dev; 633 { 634 int i; 635 struct sf_softc *sc; 636 struct ifnet *ifp; 637 int unit, rid, error = 0; 638 639 sc = device_get_softc(dev); 640 unit = device_get_unit(dev); 641 642 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 643 MTX_DEF | MTX_RECURSE); 644 /* 645 * Map control/status registers. 646 */ 647 pci_enable_busmaster(dev); 648 649 rid = SF_RID; 650 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 651 652 if (sc->sf_res == NULL) { 653 printf ("sf%d: couldn't map ports\n", unit); 654 error = ENXIO; 655 goto fail; 656 } 657 658 sc->sf_btag = rman_get_bustag(sc->sf_res); 659 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 660 661 /* Allocate interrupt */ 662 rid = 0; 663 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 664 RF_SHAREABLE | RF_ACTIVE); 665 666 if (sc->sf_irq == NULL) { 667 printf("sf%d: couldn't map interrupt\n", unit); 668 error = ENXIO; 669 goto fail; 670 } 671 672 callout_handle_init(&sc->sf_stat_ch); 673 /* Reset the adapter. */ 674 sf_reset(sc); 675 676 /* 677 * Get station address from the EEPROM. 678 */ 679 for (i = 0; i < ETHER_ADDR_LEN; i++) 680 sc->arpcom.ac_enaddr[i] = 681 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 682 683 sc->sf_unit = unit; 684 685 /* Allocate the descriptor queues. */ 686 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 687 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 688 689 if (sc->sf_ldata == NULL) { 690 printf("sf%d: no memory for list buffers!\n", unit); 691 error = ENXIO; 692 goto fail; 693 } 694 695 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 696 697 /* Do MII setup. */ 698 if (mii_phy_probe(dev, &sc->sf_miibus, 699 sf_ifmedia_upd, sf_ifmedia_sts)) { 700 printf("sf%d: MII without any phy!\n", sc->sf_unit); 701 error = ENXIO; 702 goto fail; 703 } 704 705 ifp = &sc->arpcom.ac_if; 706 ifp->if_softc = sc; 707 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 708 ifp->if_mtu = ETHERMTU; 709 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 710 IFF_NEEDSGIANT; 711 ifp->if_ioctl = sf_ioctl; 712 ifp->if_start = sf_start; 713 ifp->if_watchdog = sf_watchdog; 714 ifp->if_init = sf_init; 715 ifp->if_baudrate = 10000000; 716 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 717 718 /* 719 * Call MI attach routine. 720 */ 721 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 722 723 /* Hook interrupt last to avoid having to lock softc */ 724 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 725 sf_intr, sc, &sc->sf_intrhand); 726 727 if (error) { 728 printf("sf%d: couldn't set up irq\n", unit); 729 ether_ifdetach(ifp); 730 goto fail; 731 } 732 733 fail: 734 if (error) 735 sf_detach(dev); 736 737 return(error); 738 } 739 740 /* 741 * Shutdown hardware and free up resources. This can be called any 742 * time after the mutex has been initialized. It is called in both 743 * the error case in attach and the normal detach case so it needs 744 * to be careful about only freeing resources that have actually been 745 * allocated. 746 */ 747 static int 748 sf_detach(dev) 749 device_t dev; 750 { 751 struct sf_softc *sc; 752 struct ifnet *ifp; 753 754 sc = device_get_softc(dev); 755 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 756 SF_LOCK(sc); 757 ifp = &sc->arpcom.ac_if; 758 759 /* These should only be active if attach succeeded */ 760 if (device_is_attached(dev)) { 761 sf_stop(sc); 762 ether_ifdetach(ifp); 763 } 764 if (sc->sf_miibus) 765 device_delete_child(dev, sc->sf_miibus); 766 bus_generic_detach(dev); 767 768 if (sc->sf_intrhand) 769 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 770 if (sc->sf_irq) 771 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 772 if (sc->sf_res) 773 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 774 775 if (sc->sf_ldata) 776 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 777 778 SF_UNLOCK(sc); 779 mtx_destroy(&sc->sf_mtx); 780 781 return(0); 782 } 783 784 static int 785 sf_init_rx_ring(sc) 786 struct sf_softc *sc; 787 { 788 struct sf_list_data *ld; 789 int i; 790 791 ld = sc->sf_ldata; 792 793 bzero((char *)ld->sf_rx_dlist_big, 794 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 795 bzero((char *)ld->sf_rx_clist, 796 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 797 798 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 799 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 800 return(ENOBUFS); 801 } 802 803 return(0); 804 } 805 806 static void 807 sf_init_tx_ring(sc) 808 struct sf_softc *sc; 809 { 810 struct sf_list_data *ld; 811 int i; 812 813 ld = sc->sf_ldata; 814 815 bzero((char *)ld->sf_tx_dlist, 816 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 817 bzero((char *)ld->sf_tx_clist, 818 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 819 820 for (i = 0; i < SF_TX_DLIST_CNT; i++) 821 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 822 for (i = 0; i < SF_TX_CLIST_CNT; i++) 823 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 824 825 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 826 sc->sf_tx_cnt = 0; 827 } 828 829 static int 830 sf_newbuf(sc, c, m) 831 struct sf_softc *sc; 832 struct sf_rx_bufdesc_type0 *c; 833 struct mbuf *m; 834 { 835 struct mbuf *m_new = NULL; 836 837 if (m == NULL) { 838 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 839 if (m_new == NULL) 840 return(ENOBUFS); 841 842 MCLGET(m_new, M_DONTWAIT); 843 if (!(m_new->m_flags & M_EXT)) { 844 m_freem(m_new); 845 return(ENOBUFS); 846 } 847 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 848 } else { 849 m_new = m; 850 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 851 m_new->m_data = m_new->m_ext.ext_buf; 852 } 853 854 m_adj(m_new, sizeof(u_int64_t)); 855 856 c->sf_mbuf = m_new; 857 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 858 c->sf_valid = 1; 859 860 return(0); 861 } 862 863 /* 864 * The starfire is programmed to use 'normal' mode for packet reception, 865 * which means we use the consumer/producer model for both the buffer 866 * descriptor queue and the completion descriptor queue. The only problem 867 * with this is that it involves a lot of register accesses: we have to 868 * read the RX completion consumer and producer indexes and the RX buffer 869 * producer index, plus the RX completion consumer and RX buffer producer 870 * indexes have to be updated. It would have been easier if Adaptec had 871 * put each index in a separate register, especially given that the damn 872 * NIC has a 512K register space. 873 * 874 * In spite of all the lovely features that Adaptec crammed into the 6915, 875 * it is marred by one truly stupid design flaw, which is that receive 876 * buffer addresses must be aligned on a longword boundary. This forces 877 * the packet payload to be unaligned, which is suboptimal on the x86 and 878 * completely unuseable on the Alpha. Our only recourse is to copy received 879 * packets into properly aligned buffers before handing them off. 880 */ 881 882 static void 883 sf_rxeof(sc) 884 struct sf_softc *sc; 885 { 886 struct mbuf *m; 887 struct ifnet *ifp; 888 struct sf_rx_bufdesc_type0 *desc; 889 struct sf_rx_cmpdesc_type3 *cur_rx; 890 u_int32_t rxcons, rxprod; 891 int cmpprodidx, cmpconsidx, bufprodidx; 892 893 SF_LOCK_ASSERT(sc); 894 895 ifp = &sc->arpcom.ac_if; 896 897 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 898 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 899 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 900 cmpconsidx = SF_IDX_LO(rxcons); 901 bufprodidx = SF_IDX_LO(rxprod); 902 903 while (cmpconsidx != cmpprodidx) { 904 struct mbuf *m0; 905 906 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 907 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 908 m = desc->sf_mbuf; 909 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 910 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 911 912 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 913 ifp->if_ierrors++; 914 sf_newbuf(sc, desc, m); 915 continue; 916 } 917 918 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 919 ifp, NULL); 920 sf_newbuf(sc, desc, m); 921 if (m0 == NULL) { 922 ifp->if_ierrors++; 923 continue; 924 } 925 m = m0; 926 927 ifp->if_ipackets++; 928 SF_UNLOCK(sc); 929 (*ifp->if_input)(ifp, m); 930 SF_LOCK(sc); 931 } 932 933 csr_write_4(sc, SF_CQ_CONSIDX, 934 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 935 csr_write_4(sc, SF_RXDQ_PTR_Q1, 936 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 937 } 938 939 /* 940 * Read the transmit status from the completion queue and release 941 * mbufs. Note that the buffer descriptor index in the completion 942 * descriptor is an offset from the start of the transmit buffer 943 * descriptor list in bytes. This is important because the manual 944 * gives the impression that it should match the producer/consumer 945 * index, which is the offset in 8 byte blocks. 946 */ 947 static void 948 sf_txeof(sc) 949 struct sf_softc *sc; 950 { 951 int txcons, cmpprodidx, cmpconsidx; 952 struct sf_tx_cmpdesc_type1 *cur_cmp; 953 struct sf_tx_bufdesc_type0 *cur_tx; 954 struct ifnet *ifp; 955 956 ifp = &sc->arpcom.ac_if; 957 958 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 959 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 960 cmpconsidx = SF_IDX_HI(txcons); 961 962 while (cmpconsidx != cmpprodidx) { 963 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 964 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 965 966 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 967 ifp->if_opackets++; 968 else { 969 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 970 sf_txthresh_adjust(sc); 971 ifp->if_oerrors++; 972 } 973 974 sc->sf_tx_cnt--; 975 if (cur_tx->sf_mbuf != NULL) { 976 m_freem(cur_tx->sf_mbuf); 977 cur_tx->sf_mbuf = NULL; 978 } else 979 break; 980 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 981 } 982 983 ifp->if_timer = 0; 984 ifp->if_flags &= ~IFF_OACTIVE; 985 986 csr_write_4(sc, SF_CQ_CONSIDX, 987 (txcons & ~SF_CQ_CONSIDX_TXQ) | 988 ((cmpconsidx << 16) & 0xFFFF0000)); 989 } 990 991 static void 992 sf_txthresh_adjust(sc) 993 struct sf_softc *sc; 994 { 995 u_int32_t txfctl; 996 u_int8_t txthresh; 997 998 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 999 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1000 if (txthresh < 0xFF) { 1001 txthresh++; 1002 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1003 txfctl |= txthresh; 1004 #ifdef DIAGNOSTIC 1005 printf("sf%d: tx underrun, increasing " 1006 "tx threshold to %d bytes\n", 1007 sc->sf_unit, txthresh * 4); 1008 #endif 1009 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1010 } 1011 } 1012 1013 static void 1014 sf_intr(arg) 1015 void *arg; 1016 { 1017 struct sf_softc *sc; 1018 struct ifnet *ifp; 1019 u_int32_t status; 1020 1021 sc = arg; 1022 SF_LOCK(sc); 1023 1024 ifp = &sc->arpcom.ac_if; 1025 1026 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1027 SF_UNLOCK(sc); 1028 return; 1029 } 1030 1031 /* Disable interrupts. */ 1032 csr_write_4(sc, SF_IMR, 0x00000000); 1033 1034 for (;;) { 1035 status = csr_read_4(sc, SF_ISR); 1036 if (status) 1037 csr_write_4(sc, SF_ISR, status); 1038 1039 if (!(status & SF_INTRS)) 1040 break; 1041 1042 if (status & SF_ISR_RXDQ1_DMADONE) 1043 sf_rxeof(sc); 1044 1045 if (status & SF_ISR_TX_TXDONE || 1046 status & SF_ISR_TX_DMADONE || 1047 status & SF_ISR_TX_QUEUEDONE) 1048 sf_txeof(sc); 1049 1050 if (status & SF_ISR_TX_LOFIFO) 1051 sf_txthresh_adjust(sc); 1052 1053 if (status & SF_ISR_ABNORMALINTR) { 1054 if (status & SF_ISR_STATSOFLOW) { 1055 untimeout(sf_stats_update, sc, 1056 sc->sf_stat_ch); 1057 sf_stats_update(sc); 1058 } else 1059 sf_init(sc); 1060 } 1061 } 1062 1063 /* Re-enable interrupts. */ 1064 csr_write_4(sc, SF_IMR, SF_INTRS); 1065 1066 if (ifp->if_snd.ifq_head != NULL) 1067 sf_start(ifp); 1068 1069 SF_UNLOCK(sc); 1070 } 1071 1072 static void 1073 sf_init(xsc) 1074 void *xsc; 1075 { 1076 struct sf_softc *sc; 1077 struct ifnet *ifp; 1078 struct mii_data *mii; 1079 int i; 1080 1081 sc = xsc; 1082 SF_LOCK(sc); 1083 ifp = &sc->arpcom.ac_if; 1084 mii = device_get_softc(sc->sf_miibus); 1085 1086 sf_stop(sc); 1087 sf_reset(sc); 1088 1089 /* Init all the receive filter registers */ 1090 for (i = SF_RXFILT_PERFECT_BASE; 1091 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1092 csr_write_4(sc, i, 0); 1093 1094 /* Empty stats counter registers. */ 1095 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1096 csr_write_4(sc, SF_STATS_BASE + 1097 (i + sizeof(u_int32_t)), 0); 1098 1099 /* Init our MAC address */ 1100 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1101 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1102 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1103 1104 if (sf_init_rx_ring(sc) == ENOBUFS) { 1105 printf("sf%d: initialization failed: no " 1106 "memory for rx buffers\n", sc->sf_unit); 1107 SF_UNLOCK(sc); 1108 return; 1109 } 1110 1111 sf_init_tx_ring(sc); 1112 1113 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1114 1115 /* If we want promiscuous mode, set the allframes bit. */ 1116 if (ifp->if_flags & IFF_PROMISC) { 1117 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1118 } else { 1119 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1120 } 1121 1122 if (ifp->if_flags & IFF_BROADCAST) { 1123 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1124 } else { 1125 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1126 } 1127 1128 /* 1129 * Load the multicast filter. 1130 */ 1131 sf_setmulti(sc); 1132 1133 /* Init the completion queue indexes */ 1134 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1135 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1136 1137 /* Init the RX completion queue */ 1138 csr_write_4(sc, SF_RXCQ_CTL_1, 1139 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1140 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1141 1142 /* Init RX DMA control. */ 1143 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1144 1145 /* Init the RX buffer descriptor queue. */ 1146 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1147 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1148 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1149 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1150 1151 /* Init the TX completion queue */ 1152 csr_write_4(sc, SF_TXCQ_CTL, 1153 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1154 1155 /* Init the TX buffer descriptor queue. */ 1156 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1157 vtophys(sc->sf_ldata->sf_tx_dlist)); 1158 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1159 csr_write_4(sc, SF_TXDQ_CTL, 1160 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1161 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1162 1163 /* Enable autopadding of short TX frames. */ 1164 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1165 1166 /* Enable interrupts. */ 1167 csr_write_4(sc, SF_IMR, SF_INTRS); 1168 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1169 1170 /* Enable the RX and TX engines. */ 1171 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1172 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1173 1174 /*mii_mediachg(mii);*/ 1175 sf_ifmedia_upd(ifp); 1176 1177 ifp->if_flags |= IFF_RUNNING; 1178 ifp->if_flags &= ~IFF_OACTIVE; 1179 1180 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1181 1182 SF_UNLOCK(sc); 1183 } 1184 1185 static int 1186 sf_encap(sc, c, m_head) 1187 struct sf_softc *sc; 1188 struct sf_tx_bufdesc_type0 *c; 1189 struct mbuf *m_head; 1190 { 1191 int frag = 0; 1192 struct sf_frag *f = NULL; 1193 struct mbuf *m; 1194 1195 m = m_head; 1196 1197 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1198 if (m->m_len != 0) { 1199 if (frag == SF_MAXFRAGS) 1200 break; 1201 f = &c->sf_frags[frag]; 1202 if (frag == 0) 1203 f->sf_pktlen = m_head->m_pkthdr.len; 1204 f->sf_fraglen = m->m_len; 1205 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1206 frag++; 1207 } 1208 } 1209 1210 if (m != NULL) { 1211 struct mbuf *m_new = NULL; 1212 1213 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1214 if (m_new == NULL) { 1215 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1216 return(1); 1217 } 1218 1219 if (m_head->m_pkthdr.len > MHLEN) { 1220 MCLGET(m_new, M_DONTWAIT); 1221 if (!(m_new->m_flags & M_EXT)) { 1222 m_freem(m_new); 1223 printf("sf%d: no memory for tx list\n", 1224 sc->sf_unit); 1225 return(1); 1226 } 1227 } 1228 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1229 mtod(m_new, caddr_t)); 1230 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1231 m_freem(m_head); 1232 m_head = m_new; 1233 f = &c->sf_frags[0]; 1234 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1235 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1236 frag = 1; 1237 } 1238 1239 c->sf_mbuf = m_head; 1240 c->sf_id = SF_TX_BUFDESC_ID; 1241 c->sf_fragcnt = frag; 1242 c->sf_intr = 1; 1243 c->sf_caltcp = 0; 1244 c->sf_crcen = 1; 1245 1246 return(0); 1247 } 1248 1249 static void 1250 sf_start(ifp) 1251 struct ifnet *ifp; 1252 { 1253 struct sf_softc *sc; 1254 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1255 struct mbuf *m_head = NULL; 1256 int i, txprod; 1257 1258 sc = ifp->if_softc; 1259 SF_LOCK(sc); 1260 1261 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1262 SF_UNLOCK(sc); 1263 return; 1264 } 1265 1266 if (ifp->if_flags & IFF_OACTIVE) { 1267 SF_UNLOCK(sc); 1268 return; 1269 } 1270 1271 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1272 i = SF_IDX_HI(txprod) >> 4; 1273 1274 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1275 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1276 sf_init(sc); 1277 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1278 i = SF_IDX_HI(txprod) >> 4; 1279 } 1280 1281 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1282 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1283 ifp->if_flags |= IFF_OACTIVE; 1284 cur_tx = NULL; 1285 break; 1286 } 1287 IF_DEQUEUE(&ifp->if_snd, m_head); 1288 if (m_head == NULL) 1289 break; 1290 1291 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1292 if (sf_encap(sc, cur_tx, m_head)) { 1293 IF_PREPEND(&ifp->if_snd, m_head); 1294 ifp->if_flags |= IFF_OACTIVE; 1295 cur_tx = NULL; 1296 break; 1297 } 1298 1299 /* 1300 * If there's a BPF listener, bounce a copy of this frame 1301 * to him. 1302 */ 1303 BPF_MTAP(ifp, m_head); 1304 1305 SF_INC(i, SF_TX_DLIST_CNT); 1306 sc->sf_tx_cnt++; 1307 /* 1308 * Don't get the TX DMA queue get too full. 1309 */ 1310 if (sc->sf_tx_cnt > 64) 1311 break; 1312 } 1313 1314 if (cur_tx == NULL) { 1315 SF_UNLOCK(sc); 1316 return; 1317 } 1318 1319 /* Transmit */ 1320 csr_write_4(sc, SF_TXDQ_PRODIDX, 1321 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1322 ((i << 20) & 0xFFFF0000)); 1323 1324 ifp->if_timer = 5; 1325 1326 SF_UNLOCK(sc); 1327 } 1328 1329 static void 1330 sf_stop(sc) 1331 struct sf_softc *sc; 1332 { 1333 int i; 1334 struct ifnet *ifp; 1335 1336 SF_LOCK(sc); 1337 1338 ifp = &sc->arpcom.ac_if; 1339 1340 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1341 1342 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1343 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1344 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1345 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1346 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1347 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1348 csr_write_4(sc, SF_TXCQ_CTL, 0); 1349 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1350 csr_write_4(sc, SF_TXDQ_CTL, 0); 1351 sf_reset(sc); 1352 1353 sc->sf_link = 0; 1354 1355 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1356 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1357 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1358 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1359 } 1360 } 1361 1362 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1363 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1364 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1365 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1366 } 1367 } 1368 1369 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1370 SF_UNLOCK(sc); 1371 } 1372 1373 /* 1374 * Note: it is important that this function not be interrupted. We 1375 * use a two-stage register access scheme: if we are interrupted in 1376 * between setting the indirect address register and reading from the 1377 * indirect data register, the contents of the address register could 1378 * be changed out from under us. 1379 */ 1380 static void 1381 sf_stats_update(xsc) 1382 void *xsc; 1383 { 1384 struct sf_softc *sc; 1385 struct ifnet *ifp; 1386 struct mii_data *mii; 1387 struct sf_stats stats; 1388 u_int32_t *ptr; 1389 int i; 1390 1391 sc = xsc; 1392 SF_LOCK(sc); 1393 ifp = &sc->arpcom.ac_if; 1394 mii = device_get_softc(sc->sf_miibus); 1395 1396 ptr = (u_int32_t *)&stats; 1397 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1398 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1399 (i + sizeof(u_int32_t))); 1400 1401 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1402 csr_write_4(sc, SF_STATS_BASE + 1403 (i + sizeof(u_int32_t)), 0); 1404 1405 ifp->if_collisions += stats.sf_tx_single_colls + 1406 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1407 1408 mii_tick(mii); 1409 1410 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1411 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1412 sc->sf_link++; 1413 if (ifp->if_snd.ifq_head != NULL) 1414 sf_start(ifp); 1415 } 1416 1417 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1418 1419 SF_UNLOCK(sc); 1420 } 1421 1422 static void 1423 sf_watchdog(ifp) 1424 struct ifnet *ifp; 1425 { 1426 struct sf_softc *sc; 1427 1428 sc = ifp->if_softc; 1429 1430 SF_LOCK(sc); 1431 1432 ifp->if_oerrors++; 1433 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1434 1435 sf_stop(sc); 1436 sf_reset(sc); 1437 sf_init(sc); 1438 1439 if (ifp->if_snd.ifq_head != NULL) 1440 sf_start(ifp); 1441 1442 SF_UNLOCK(sc); 1443 } 1444 1445 static void 1446 sf_shutdown(dev) 1447 device_t dev; 1448 { 1449 struct sf_softc *sc; 1450 1451 sc = device_get_softc(dev); 1452 1453 sf_stop(sc); 1454 }
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