FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sf.c
1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/5.4/sys/pci/if_sf.c 142884 2005-03-01 08:11:52Z imp $");
35
36 /*
37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
38 * Programming manual is available from:
39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf.
40 *
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Department of Electical Engineering
43 * Columbia University, New York City
44 */
45 /*
46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
47 * controller designed with flexibility and reducing CPU load in mind.
48 * The Starfire offers high and low priority buffer queues, a
49 * producer/consumer index mechanism and several different buffer
50 * queue and completion queue descriptor types. Any one of a number
51 * of different driver designs can be used, depending on system and
52 * OS requirements. This driver makes use of type0 transmit frame
53 * descriptors (since BSD fragments packets across an mbuf chain)
54 * and two RX buffer queues prioritized on size (one queue for small
55 * frames that will fit into a single mbuf, another with full size
56 * mbuf clusters for everything else). The producer/consumer indexes
57 * and completion queues are also used.
58 *
59 * One downside to the Starfire has to do with alignment: buffer
60 * queues must be aligned on 256-byte boundaries, and receive buffers
61 * must be aligned on longword boundaries. The receive buffer alignment
62 * causes problems on the Alpha platform, where the packet payload
63 * should be longword aligned. There is no simple way around this.
64 *
65 * For receive filtering, the Starfire offers 16 perfect filter slots
66 * and a 512-bit hash table.
67 *
68 * The Starfire has no internal transceiver, relying instead on an
69 * external MII-based transceiver. Accessing registers on external
70 * PHYs is done through a special register map rather than with the
71 * usual bitbang MDIO method.
72 *
73 * Acesssing the registers on the Starfire is a little tricky. The
74 * Starfire has a 512K internal register space. When programmed for
75 * PCI memory mapped mode, the entire register space can be accessed
76 * directly. However in I/O space mode, only 256 bytes are directly
77 * mapped into PCI I/O space. The other registers can be accessed
78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
79 * registers inside the 256-byte I/O window.
80 */
81
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/sockio.h>
85 #include <sys/mbuf.h>
86 #include <sys/malloc.h>
87 #include <sys/kernel.h>
88 #include <sys/module.h>
89 #include <sys/socket.h>
90
91 #include <net/if.h>
92 #include <net/if_arp.h>
93 #include <net/ethernet.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96
97 #include <net/bpf.h>
98
99 #include <vm/vm.h> /* for vtophys */
100 #include <vm/pmap.h> /* for vtophys */
101 #include <machine/bus_pio.h>
102 #include <machine/bus_memio.h>
103 #include <machine/bus.h>
104 #include <machine/resource.h>
105 #include <sys/bus.h>
106 #include <sys/rman.h>
107
108 #include <dev/mii/mii.h>
109 #include <dev/mii/miivar.h>
110
111 /* "controller miibus0" required. See GENERIC if you get errors here. */
112 #include "miibus_if.h"
113
114 #include <dev/pci/pcireg.h>
115 #include <dev/pci/pcivar.h>
116
117 #define SF_USEIOSPACE
118
119 #include <pci/if_sfreg.h>
120
121 MODULE_DEPEND(sf, pci, 1, 1, 1);
122 MODULE_DEPEND(sf, ether, 1, 1, 1);
123 MODULE_DEPEND(sf, miibus, 1, 1, 1);
124
125 static struct sf_type sf_devs[] = {
126 { AD_VENDORID, AD_DEVICEID_STARFIRE,
127 "Adaptec AIC-6915 10/100BaseTX" },
128 { 0, 0, NULL }
129 };
130
131 static int sf_probe(device_t);
132 static int sf_attach(device_t);
133 static int sf_detach(device_t);
134 static void sf_intr(void *);
135 static void sf_stats_update(void *);
136 static void sf_rxeof(struct sf_softc *);
137 static void sf_txeof(struct sf_softc *);
138 static int sf_encap(struct sf_softc *, struct sf_tx_bufdesc_type0 *,
139 struct mbuf *);
140 static void sf_start(struct ifnet *);
141 static int sf_ioctl(struct ifnet *, u_long, caddr_t);
142 static void sf_init(void *);
143 static void sf_stop(struct sf_softc *);
144 static void sf_watchdog(struct ifnet *);
145 static void sf_shutdown(device_t);
146 static int sf_ifmedia_upd(struct ifnet *);
147 static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *);
148 static void sf_reset(struct sf_softc *);
149 static int sf_init_rx_ring(struct sf_softc *);
150 static void sf_init_tx_ring(struct sf_softc *);
151 static int sf_newbuf(struct sf_softc *, struct sf_rx_bufdesc_type0 *,
152 struct mbuf *);
153 static void sf_setmulti(struct sf_softc *);
154 static int sf_setperf(struct sf_softc *, int, caddr_t);
155 static int sf_sethash(struct sf_softc *, caddr_t, int);
156 #ifdef notdef
157 static int sf_setvlan(struct sf_softc *, int, u_int32_t);
158 #endif
159
160 static u_int8_t sf_read_eeprom(struct sf_softc *, int);
161
162 static int sf_miibus_readreg(device_t, int, int);
163 static int sf_miibus_writereg(device_t, int, int, int);
164 static void sf_miibus_statchg(device_t);
165 #ifdef DEVICE_POLLING
166 static void sf_poll(struct ifnet *ifp, enum poll_cmd cmd,
167 int count);
168 static void sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd,
169 int count);
170 #endif /* DEVICE_POLLING */
171
172 static u_int32_t csr_read_4(struct sf_softc *, int);
173 static void csr_write_4(struct sf_softc *, int, u_int32_t);
174 static void sf_txthresh_adjust(struct sf_softc *);
175
176 #ifdef SF_USEIOSPACE
177 #define SF_RES SYS_RES_IOPORT
178 #define SF_RID SF_PCI_LOIO
179 #else
180 #define SF_RES SYS_RES_MEMORY
181 #define SF_RID SF_PCI_LOMEM
182 #endif
183
184 static device_method_t sf_methods[] = {
185 /* Device interface */
186 DEVMETHOD(device_probe, sf_probe),
187 DEVMETHOD(device_attach, sf_attach),
188 DEVMETHOD(device_detach, sf_detach),
189 DEVMETHOD(device_shutdown, sf_shutdown),
190
191 /* bus interface */
192 DEVMETHOD(bus_print_child, bus_generic_print_child),
193 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
194
195 /* MII interface */
196 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
197 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
198 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
199
200 { 0, 0 }
201 };
202
203 static driver_t sf_driver = {
204 "sf",
205 sf_methods,
206 sizeof(struct sf_softc),
207 };
208
209 static devclass_t sf_devclass;
210
211 DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0);
212 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
213
214 #define SF_SETBIT(sc, reg, x) \
215 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x))
216
217 #define SF_CLRBIT(sc, reg, x) \
218 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x))
219
220 static u_int32_t
221 csr_read_4(sc, reg)
222 struct sf_softc *sc;
223 int reg;
224 {
225 u_int32_t val;
226
227 #ifdef SF_USEIOSPACE
228 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
229 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
230 #else
231 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
232 #endif
233
234 return(val);
235 }
236
237 static u_int8_t
238 sf_read_eeprom(sc, reg)
239 struct sf_softc *sc;
240 int reg;
241 {
242 u_int8_t val;
243
244 val = (csr_read_4(sc, SF_EEADDR_BASE +
245 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
246
247 return(val);
248 }
249
250 static void
251 csr_write_4(sc, reg, val)
252 struct sf_softc *sc;
253 int reg;
254 u_int32_t val;
255 {
256 #ifdef SF_USEIOSPACE
257 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
258 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
259 #else
260 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
261 #endif
262 }
263
264 /*
265 * Copy the address 'mac' into the perfect RX filter entry at
266 * offset 'idx.' The perfect filter only has 16 entries so do
267 * some sanity tests.
268 */
269 static int
270 sf_setperf(sc, idx, mac)
271 struct sf_softc *sc;
272 int idx;
273 caddr_t mac;
274 {
275 u_int16_t *p;
276
277 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
278 return(EINVAL);
279
280 if (mac == NULL)
281 return(EINVAL);
282
283 p = (u_int16_t *)mac;
284
285 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
286 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
287 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
288 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
289 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
290 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
291
292 return(0);
293 }
294
295 /*
296 * Set the bit in the 512-bit hash table that corresponds to the
297 * specified mac address 'mac.' If 'prio' is nonzero, update the
298 * priority hash table instead of the filter hash table.
299 */
300 static int
301 sf_sethash(sc, mac, prio)
302 struct sf_softc *sc;
303 caddr_t mac;
304 int prio;
305 {
306 u_int32_t h;
307
308 if (mac == NULL)
309 return(EINVAL);
310
311 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23;
312
313 if (prio) {
314 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
315 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
316 } else {
317 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
318 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
319 }
320
321 return(0);
322 }
323
324 #ifdef notdef
325 /*
326 * Set a VLAN tag in the receive filter.
327 */
328 static int
329 sf_setvlan(sc, idx, vlan)
330 struct sf_softc *sc;
331 int idx;
332 u_int32_t vlan;
333 {
334 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
335 return(EINVAL);
336
337 csr_write_4(sc, SF_RXFILT_HASH_BASE +
338 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
339
340 return(0);
341 }
342 #endif
343
344 static int
345 sf_miibus_readreg(dev, phy, reg)
346 device_t dev;
347 int phy, reg;
348 {
349 struct sf_softc *sc;
350 int i;
351 u_int32_t val = 0;
352
353 sc = device_get_softc(dev);
354
355 for (i = 0; i < SF_TIMEOUT; i++) {
356 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
357 if (val & SF_MII_DATAVALID)
358 break;
359 }
360
361 if (i == SF_TIMEOUT)
362 return(0);
363
364 if ((val & 0x0000FFFF) == 0xFFFF)
365 return(0);
366
367 return(val & 0x0000FFFF);
368 }
369
370 static int
371 sf_miibus_writereg(dev, phy, reg, val)
372 device_t dev;
373 int phy, reg, val;
374 {
375 struct sf_softc *sc;
376 int i;
377 int busy;
378
379 sc = device_get_softc(dev);
380
381 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
382
383 for (i = 0; i < SF_TIMEOUT; i++) {
384 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
385 if (!(busy & SF_MII_BUSY))
386 break;
387 }
388
389 return(0);
390 }
391
392 static void
393 sf_miibus_statchg(dev)
394 device_t dev;
395 {
396 struct sf_softc *sc;
397 struct mii_data *mii;
398
399 sc = device_get_softc(dev);
400 mii = device_get_softc(sc->sf_miibus);
401
402 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
403 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
404 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
405 } else {
406 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
407 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
408 }
409 }
410
411 static void
412 sf_setmulti(sc)
413 struct sf_softc *sc;
414 {
415 struct ifnet *ifp;
416 int i;
417 struct ifmultiaddr *ifma;
418 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
419
420 ifp = &sc->arpcom.ac_if;
421
422 /* First zot all the existing filters. */
423 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
424 sf_setperf(sc, i, (char *)&dummy);
425 for (i = SF_RXFILT_HASH_BASE;
426 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
427 csr_write_4(sc, i, 0);
428 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
429
430 /* Now program new ones. */
431 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
432 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
433 } else {
434 i = 1;
435 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
436 if (ifma->ifma_addr->sa_family != AF_LINK)
437 continue;
438 /*
439 * Program the first 15 multicast groups
440 * into the perfect filter. For all others,
441 * use the hash table.
442 */
443 if (i < SF_RXFILT_PERFECT_CNT) {
444 sf_setperf(sc, i,
445 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
446 i++;
447 continue;
448 }
449
450 sf_sethash(sc,
451 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
452 }
453 }
454 }
455
456 /*
457 * Set media options.
458 */
459 static int
460 sf_ifmedia_upd(ifp)
461 struct ifnet *ifp;
462 {
463 struct sf_softc *sc;
464 struct mii_data *mii;
465
466 sc = ifp->if_softc;
467 mii = device_get_softc(sc->sf_miibus);
468 sc->sf_link = 0;
469 if (mii->mii_instance) {
470 struct mii_softc *miisc;
471 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
472 mii_phy_reset(miisc);
473 }
474 mii_mediachg(mii);
475
476 return(0);
477 }
478
479 /*
480 * Report current media status.
481 */
482 static void
483 sf_ifmedia_sts(ifp, ifmr)
484 struct ifnet *ifp;
485 struct ifmediareq *ifmr;
486 {
487 struct sf_softc *sc;
488 struct mii_data *mii;
489
490 sc = ifp->if_softc;
491 mii = device_get_softc(sc->sf_miibus);
492
493 mii_pollstat(mii);
494 ifmr->ifm_active = mii->mii_media_active;
495 ifmr->ifm_status = mii->mii_media_status;
496 }
497
498 static int
499 sf_ioctl(ifp, command, data)
500 struct ifnet *ifp;
501 u_long command;
502 caddr_t data;
503 {
504 struct sf_softc *sc = ifp->if_softc;
505 struct ifreq *ifr = (struct ifreq *) data;
506 struct mii_data *mii;
507 int error = 0;
508
509 SF_LOCK(sc);
510
511 switch(command) {
512 case SIOCSIFFLAGS:
513 if (ifp->if_flags & IFF_UP) {
514 if (ifp->if_flags & IFF_RUNNING &&
515 ifp->if_flags & IFF_PROMISC &&
516 !(sc->sf_if_flags & IFF_PROMISC)) {
517 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
518 } else if (ifp->if_flags & IFF_RUNNING &&
519 !(ifp->if_flags & IFF_PROMISC) &&
520 sc->sf_if_flags & IFF_PROMISC) {
521 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
522 } else if (!(ifp->if_flags & IFF_RUNNING))
523 sf_init(sc);
524 } else {
525 if (ifp->if_flags & IFF_RUNNING)
526 sf_stop(sc);
527 }
528 sc->sf_if_flags = ifp->if_flags;
529 error = 0;
530 break;
531 case SIOCADDMULTI:
532 case SIOCDELMULTI:
533 sf_setmulti(sc);
534 error = 0;
535 break;
536 case SIOCGIFMEDIA:
537 case SIOCSIFMEDIA:
538 mii = device_get_softc(sc->sf_miibus);
539 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
540 break;
541 case SIOCSIFCAP:
542 ifp->if_capenable &= ~IFCAP_POLLING;
543 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING;
544 break;
545 default:
546 error = ether_ioctl(ifp, command, data);
547 break;
548 }
549
550 SF_UNLOCK(sc);
551
552 return(error);
553 }
554
555 static void
556 sf_reset(sc)
557 struct sf_softc *sc;
558 {
559 register int i;
560
561 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
562 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
563 DELAY(1000);
564 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
565
566 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
567
568 for (i = 0; i < SF_TIMEOUT; i++) {
569 DELAY(10);
570 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
571 break;
572 }
573
574 if (i == SF_TIMEOUT)
575 printf("sf%d: reset never completed!\n", sc->sf_unit);
576
577 /* Wait a little while for the chip to get its brains in order. */
578 DELAY(1000);
579 }
580
581 /*
582 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
583 * IDs against our list and return a device name if we find a match.
584 * We also check the subsystem ID so that we can identify exactly which
585 * NIC has been found, if possible.
586 */
587 static int
588 sf_probe(dev)
589 device_t dev;
590 {
591 struct sf_type *t;
592
593 t = sf_devs;
594
595 while(t->sf_name != NULL) {
596 if ((pci_get_vendor(dev) == t->sf_vid) &&
597 (pci_get_device(dev) == t->sf_did)) {
598 switch((pci_read_config(dev,
599 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
600 case AD_SUBSYSID_62011_REV0:
601 case AD_SUBSYSID_62011_REV1:
602 device_set_desc(dev,
603 "Adaptec ANA-62011 10/100BaseTX");
604 return (BUS_PROBE_DEFAULT);
605 case AD_SUBSYSID_62022:
606 device_set_desc(dev,
607 "Adaptec ANA-62022 10/100BaseTX");
608 return (BUS_PROBE_DEFAULT);
609 case AD_SUBSYSID_62044_REV0:
610 case AD_SUBSYSID_62044_REV1:
611 device_set_desc(dev,
612 "Adaptec ANA-62044 10/100BaseTX");
613 return (BUS_PROBE_DEFAULT);
614 case AD_SUBSYSID_62020:
615 device_set_desc(dev,
616 "Adaptec ANA-62020 10/100BaseFX");
617 return (BUS_PROBE_DEFAULT);
618 case AD_SUBSYSID_69011:
619 device_set_desc(dev,
620 "Adaptec ANA-69011 10/100BaseTX");
621 return (BUS_PROBE_DEFAULT);
622 default:
623 device_set_desc(dev, t->sf_name);
624 return (BUS_PROBE_DEFAULT);
625 break;
626 }
627 }
628 t++;
629 }
630
631 return(ENXIO);
632 }
633
634 /*
635 * Attach the interface. Allocate softc structures, do ifmedia
636 * setup and ethernet/BPF attach.
637 */
638 static int
639 sf_attach(dev)
640 device_t dev;
641 {
642 int i;
643 struct sf_softc *sc;
644 struct ifnet *ifp;
645 int unit, rid, error = 0;
646
647 sc = device_get_softc(dev);
648 unit = device_get_unit(dev);
649
650 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
651 MTX_DEF | MTX_RECURSE);
652 /*
653 * Map control/status registers.
654 */
655 pci_enable_busmaster(dev);
656
657 rid = SF_RID;
658 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE);
659
660 if (sc->sf_res == NULL) {
661 printf ("sf%d: couldn't map ports\n", unit);
662 error = ENXIO;
663 goto fail;
664 }
665
666 sc->sf_btag = rman_get_bustag(sc->sf_res);
667 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
668
669 /* Allocate interrupt */
670 rid = 0;
671 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
672 RF_SHAREABLE | RF_ACTIVE);
673
674 if (sc->sf_irq == NULL) {
675 printf("sf%d: couldn't map interrupt\n", unit);
676 error = ENXIO;
677 goto fail;
678 }
679
680 callout_handle_init(&sc->sf_stat_ch);
681 /* Reset the adapter. */
682 sf_reset(sc);
683
684 /*
685 * Get station address from the EEPROM.
686 */
687 for (i = 0; i < ETHER_ADDR_LEN; i++)
688 sc->arpcom.ac_enaddr[i] =
689 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
690
691 sc->sf_unit = unit;
692
693 /* Allocate the descriptor queues. */
694 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
695 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
696
697 if (sc->sf_ldata == NULL) {
698 printf("sf%d: no memory for list buffers!\n", unit);
699 error = ENXIO;
700 goto fail;
701 }
702
703 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
704
705 /* Do MII setup. */
706 if (mii_phy_probe(dev, &sc->sf_miibus,
707 sf_ifmedia_upd, sf_ifmedia_sts)) {
708 printf("sf%d: MII without any phy!\n", sc->sf_unit);
709 error = ENXIO;
710 goto fail;
711 }
712
713 ifp = &sc->arpcom.ac_if;
714 ifp->if_softc = sc;
715 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
716 ifp->if_mtu = ETHERMTU;
717 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
718 IFF_NEEDSGIANT;
719 ifp->if_ioctl = sf_ioctl;
720 ifp->if_start = sf_start;
721 ifp->if_watchdog = sf_watchdog;
722 ifp->if_init = sf_init;
723 ifp->if_baudrate = 10000000;
724 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
725 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1;
726 IFQ_SET_READY(&ifp->if_snd);
727 #ifdef DEVICE_POLLING
728 ifp->if_capabilities |= IFCAP_POLLING;
729 #endif /* DEVICE_POLLING */
730 ifp->if_capenable = ifp->if_capabilities;
731
732 /*
733 * Call MI attach routine.
734 */
735 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
736
737 /* Hook interrupt last to avoid having to lock softc */
738 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET,
739 sf_intr, sc, &sc->sf_intrhand);
740
741 if (error) {
742 printf("sf%d: couldn't set up irq\n", unit);
743 ether_ifdetach(ifp);
744 goto fail;
745 }
746
747 fail:
748 if (error)
749 sf_detach(dev);
750
751 return(error);
752 }
753
754 /*
755 * Shutdown hardware and free up resources. This can be called any
756 * time after the mutex has been initialized. It is called in both
757 * the error case in attach and the normal detach case so it needs
758 * to be careful about only freeing resources that have actually been
759 * allocated.
760 */
761 static int
762 sf_detach(dev)
763 device_t dev;
764 {
765 struct sf_softc *sc;
766 struct ifnet *ifp;
767
768 sc = device_get_softc(dev);
769 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized"));
770 SF_LOCK(sc);
771 ifp = &sc->arpcom.ac_if;
772
773 /* These should only be active if attach succeeded */
774 if (device_is_attached(dev)) {
775 sf_stop(sc);
776 ether_ifdetach(ifp);
777 }
778 if (sc->sf_miibus)
779 device_delete_child(dev, sc->sf_miibus);
780 bus_generic_detach(dev);
781
782 if (sc->sf_intrhand)
783 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
784 if (sc->sf_irq)
785 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
786 if (sc->sf_res)
787 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
788
789 if (sc->sf_ldata)
790 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF);
791
792 SF_UNLOCK(sc);
793 mtx_destroy(&sc->sf_mtx);
794
795 return(0);
796 }
797
798 static int
799 sf_init_rx_ring(sc)
800 struct sf_softc *sc;
801 {
802 struct sf_list_data *ld;
803 int i;
804
805 ld = sc->sf_ldata;
806
807 bzero((char *)ld->sf_rx_dlist_big,
808 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
809 bzero((char *)ld->sf_rx_clist,
810 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
811
812 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
813 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
814 return(ENOBUFS);
815 }
816
817 return(0);
818 }
819
820 static void
821 sf_init_tx_ring(sc)
822 struct sf_softc *sc;
823 {
824 struct sf_list_data *ld;
825 int i;
826
827 ld = sc->sf_ldata;
828
829 bzero((char *)ld->sf_tx_dlist,
830 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
831 bzero((char *)ld->sf_tx_clist,
832 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
833
834 for (i = 0; i < SF_TX_DLIST_CNT; i++)
835 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
836 for (i = 0; i < SF_TX_CLIST_CNT; i++)
837 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
838
839 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
840 sc->sf_tx_cnt = 0;
841 }
842
843 static int
844 sf_newbuf(sc, c, m)
845 struct sf_softc *sc;
846 struct sf_rx_bufdesc_type0 *c;
847 struct mbuf *m;
848 {
849 struct mbuf *m_new = NULL;
850
851 if (m == NULL) {
852 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
853 if (m_new == NULL)
854 return(ENOBUFS);
855
856 MCLGET(m_new, M_DONTWAIT);
857 if (!(m_new->m_flags & M_EXT)) {
858 m_freem(m_new);
859 return(ENOBUFS);
860 }
861 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
862 } else {
863 m_new = m;
864 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
865 m_new->m_data = m_new->m_ext.ext_buf;
866 }
867
868 m_adj(m_new, sizeof(u_int64_t));
869
870 c->sf_mbuf = m_new;
871 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
872 c->sf_valid = 1;
873
874 return(0);
875 }
876
877 /*
878 * The starfire is programmed to use 'normal' mode for packet reception,
879 * which means we use the consumer/producer model for both the buffer
880 * descriptor queue and the completion descriptor queue. The only problem
881 * with this is that it involves a lot of register accesses: we have to
882 * read the RX completion consumer and producer indexes and the RX buffer
883 * producer index, plus the RX completion consumer and RX buffer producer
884 * indexes have to be updated. It would have been easier if Adaptec had
885 * put each index in a separate register, especially given that the damn
886 * NIC has a 512K register space.
887 *
888 * In spite of all the lovely features that Adaptec crammed into the 6915,
889 * it is marred by one truly stupid design flaw, which is that receive
890 * buffer addresses must be aligned on a longword boundary. This forces
891 * the packet payload to be unaligned, which is suboptimal on the x86 and
892 * completely unuseable on the Alpha. Our only recourse is to copy received
893 * packets into properly aligned buffers before handing them off.
894 */
895
896 static void
897 sf_rxeof(sc)
898 struct sf_softc *sc;
899 {
900 struct mbuf *m;
901 struct ifnet *ifp;
902 struct sf_rx_bufdesc_type0 *desc;
903 struct sf_rx_cmpdesc_type3 *cur_rx;
904 u_int32_t rxcons, rxprod;
905 int cmpprodidx, cmpconsidx, bufprodidx;
906
907 SF_LOCK_ASSERT(sc);
908
909 ifp = &sc->arpcom.ac_if;
910
911 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
912 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
913 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
914 cmpconsidx = SF_IDX_LO(rxcons);
915 bufprodidx = SF_IDX_LO(rxprod);
916
917 while (cmpconsidx != cmpprodidx) {
918 struct mbuf *m0;
919
920 #ifdef DEVICE_POLLING
921 if (ifp->if_flags & IFF_POLLING) {
922 if (sc->rxcycles <= 0)
923 break;
924 sc->rxcycles--;
925 }
926 #endif /* DEVICE_POLLING */
927
928 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
929 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
930 m = desc->sf_mbuf;
931 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
932 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
933
934 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
935 ifp->if_ierrors++;
936 sf_newbuf(sc, desc, m);
937 continue;
938 }
939
940 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN,
941 ifp, NULL);
942 sf_newbuf(sc, desc, m);
943 if (m0 == NULL) {
944 ifp->if_ierrors++;
945 continue;
946 }
947 m = m0;
948
949 ifp->if_ipackets++;
950 SF_UNLOCK(sc);
951 (*ifp->if_input)(ifp, m);
952 SF_LOCK(sc);
953 }
954
955 csr_write_4(sc, SF_CQ_CONSIDX,
956 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
957 csr_write_4(sc, SF_RXDQ_PTR_Q1,
958 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
959 }
960
961 /*
962 * Read the transmit status from the completion queue and release
963 * mbufs. Note that the buffer descriptor index in the completion
964 * descriptor is an offset from the start of the transmit buffer
965 * descriptor list in bytes. This is important because the manual
966 * gives the impression that it should match the producer/consumer
967 * index, which is the offset in 8 byte blocks.
968 */
969 static void
970 sf_txeof(sc)
971 struct sf_softc *sc;
972 {
973 int txcons, cmpprodidx, cmpconsidx;
974 struct sf_tx_cmpdesc_type1 *cur_cmp;
975 struct sf_tx_bufdesc_type0 *cur_tx;
976 struct ifnet *ifp;
977
978 ifp = &sc->arpcom.ac_if;
979
980 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
981 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
982 cmpconsidx = SF_IDX_HI(txcons);
983
984 while (cmpconsidx != cmpprodidx) {
985 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
986 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
987
988 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
989 ifp->if_opackets++;
990 else {
991 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
992 sf_txthresh_adjust(sc);
993 ifp->if_oerrors++;
994 }
995
996 sc->sf_tx_cnt--;
997 if (cur_tx->sf_mbuf != NULL) {
998 m_freem(cur_tx->sf_mbuf);
999 cur_tx->sf_mbuf = NULL;
1000 } else
1001 break;
1002 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1003 }
1004
1005 ifp->if_timer = 0;
1006 ifp->if_flags &= ~IFF_OACTIVE;
1007
1008 csr_write_4(sc, SF_CQ_CONSIDX,
1009 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1010 ((cmpconsidx << 16) & 0xFFFF0000));
1011 }
1012
1013 static void
1014 sf_txthresh_adjust(sc)
1015 struct sf_softc *sc;
1016 {
1017 u_int32_t txfctl;
1018 u_int8_t txthresh;
1019
1020 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1021 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
1022 if (txthresh < 0xFF) {
1023 txthresh++;
1024 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1025 txfctl |= txthresh;
1026 #ifdef DIAGNOSTIC
1027 printf("sf%d: tx underrun, increasing "
1028 "tx threshold to %d bytes\n",
1029 sc->sf_unit, txthresh * 4);
1030 #endif
1031 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1032 }
1033 }
1034
1035 #ifdef DEVICE_POLLING
1036 static void
1037 sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1038 {
1039 struct sf_softc *sc = ifp->if_softc;
1040
1041 SF_LOCK(sc);
1042 sf_poll_locked(ifp, cmd, count);
1043 SF_UNLOCK(sc);
1044 }
1045
1046 static void
1047 sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1048 {
1049 struct sf_softc *sc = ifp->if_softc;
1050
1051 SF_LOCK_ASSERT(sc);
1052
1053 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1054 ether_poll_deregister(ifp);
1055 cmd = POLL_DEREGISTER;
1056 }
1057
1058 if (cmd == POLL_DEREGISTER) {
1059 /* Final call, enable interrupts. */
1060 csr_write_4(sc, SF_IMR, SF_INTRS);
1061 return;
1062 }
1063
1064 sc->rxcycles = count;
1065 sf_rxeof(sc);
1066 sf_txeof(sc);
1067 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1068 sf_start(ifp);
1069
1070 if (cmd == POLL_AND_CHECK_STATUS) {
1071 u_int32_t status;
1072
1073 status = csr_read_4(sc, SF_ISR);
1074 if (status)
1075 csr_write_4(sc, SF_ISR, status);
1076
1077 if (status & SF_ISR_TX_LOFIFO)
1078 sf_txthresh_adjust(sc);
1079
1080 if (status & SF_ISR_ABNORMALINTR) {
1081 if (status & SF_ISR_STATSOFLOW) {
1082 untimeout(sf_stats_update, sc,
1083 sc->sf_stat_ch);
1084 sf_stats_update(sc);
1085 } else
1086 sf_init(sc);
1087 }
1088 }
1089 }
1090 #endif /* DEVICE_POLLING */
1091
1092 static void
1093 sf_intr(arg)
1094 void *arg;
1095 {
1096 struct sf_softc *sc;
1097 struct ifnet *ifp;
1098 u_int32_t status;
1099
1100 sc = arg;
1101 SF_LOCK(sc);
1102
1103 ifp = &sc->arpcom.ac_if;
1104
1105 #ifdef DEVICE_POLLING
1106 if (ifp->if_flags & IFF_POLLING)
1107 goto done_locked;
1108
1109 if ((ifp->if_capenable & IFCAP_POLLING) &&
1110 ether_poll_register(sf_poll, ifp)) {
1111 /* OK, disable interrupts. */
1112 csr_write_4(sc, SF_IMR, 0x00000000);
1113 sf_poll_locked(ifp, 0, 1);
1114 goto done_locked;
1115 }
1116 #endif /* DEVICE_POLLING */
1117
1118 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) {
1119 SF_UNLOCK(sc);
1120 return;
1121 }
1122
1123 /* Disable interrupts. */
1124 csr_write_4(sc, SF_IMR, 0x00000000);
1125
1126 for (;;) {
1127 status = csr_read_4(sc, SF_ISR);
1128 if (status)
1129 csr_write_4(sc, SF_ISR, status);
1130
1131 if (!(status & SF_INTRS))
1132 break;
1133
1134 if (status & SF_ISR_RXDQ1_DMADONE)
1135 sf_rxeof(sc);
1136
1137 if (status & SF_ISR_TX_TXDONE ||
1138 status & SF_ISR_TX_DMADONE ||
1139 status & SF_ISR_TX_QUEUEDONE)
1140 sf_txeof(sc);
1141
1142 if (status & SF_ISR_TX_LOFIFO)
1143 sf_txthresh_adjust(sc);
1144
1145 if (status & SF_ISR_ABNORMALINTR) {
1146 if (status & SF_ISR_STATSOFLOW) {
1147 untimeout(sf_stats_update, sc,
1148 sc->sf_stat_ch);
1149 sf_stats_update(sc);
1150 } else
1151 sf_init(sc);
1152 }
1153 }
1154
1155 /* Re-enable interrupts. */
1156 csr_write_4(sc, SF_IMR, SF_INTRS);
1157
1158 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1159 sf_start(ifp);
1160
1161 #ifdef DEVICE_POLLING
1162 done_locked:
1163 #endif /* DEVICE_POLLING */
1164 SF_UNLOCK(sc);
1165 }
1166
1167 static void
1168 sf_init(xsc)
1169 void *xsc;
1170 {
1171 struct sf_softc *sc;
1172 struct ifnet *ifp;
1173 struct mii_data *mii;
1174 int i;
1175
1176 sc = xsc;
1177 SF_LOCK(sc);
1178 ifp = &sc->arpcom.ac_if;
1179 mii = device_get_softc(sc->sf_miibus);
1180
1181 sf_stop(sc);
1182 sf_reset(sc);
1183
1184 /* Init all the receive filter registers */
1185 for (i = SF_RXFILT_PERFECT_BASE;
1186 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1187 csr_write_4(sc, i, 0);
1188
1189 /* Empty stats counter registers. */
1190 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1191 csr_write_4(sc, SF_STATS_BASE +
1192 (i + sizeof(u_int32_t)), 0);
1193
1194 /* Init our MAC address */
1195 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1196 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1197 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1198
1199 if (sf_init_rx_ring(sc) == ENOBUFS) {
1200 printf("sf%d: initialization failed: no "
1201 "memory for rx buffers\n", sc->sf_unit);
1202 SF_UNLOCK(sc);
1203 return;
1204 }
1205
1206 sf_init_tx_ring(sc);
1207
1208 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1209
1210 /* If we want promiscuous mode, set the allframes bit. */
1211 if (ifp->if_flags & IFF_PROMISC) {
1212 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1213 } else {
1214 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1215 }
1216
1217 if (ifp->if_flags & IFF_BROADCAST) {
1218 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1219 } else {
1220 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1221 }
1222
1223 /*
1224 * Load the multicast filter.
1225 */
1226 sf_setmulti(sc);
1227
1228 /* Init the completion queue indexes */
1229 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1230 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1231
1232 /* Init the RX completion queue */
1233 csr_write_4(sc, SF_RXCQ_CTL_1,
1234 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1235 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1236
1237 /* Init RX DMA control. */
1238 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1239
1240 /* Init the RX buffer descriptor queue. */
1241 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1242 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1243 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1244 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1245
1246 /* Init the TX completion queue */
1247 csr_write_4(sc, SF_TXCQ_CTL,
1248 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1249
1250 /* Init the TX buffer descriptor queue. */
1251 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1252 vtophys(sc->sf_ldata->sf_tx_dlist));
1253 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1254 csr_write_4(sc, SF_TXDQ_CTL,
1255 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1256 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1257
1258 /* Enable autopadding of short TX frames. */
1259 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1260
1261 #ifdef DEVICE_POLLING
1262 /* Disable interrupts if we are polling. */
1263 if (ifp->if_flags & IFF_POLLING)
1264 csr_write_4(sc, SF_IMR, 0x00000000);
1265 else
1266 #endif /* DEVICE_POLLING */
1267
1268 /* Enable interrupts. */
1269 csr_write_4(sc, SF_IMR, SF_INTRS);
1270 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1271
1272 /* Enable the RX and TX engines. */
1273 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1274 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1275
1276 /*mii_mediachg(mii);*/
1277 sf_ifmedia_upd(ifp);
1278
1279 ifp->if_flags |= IFF_RUNNING;
1280 ifp->if_flags &= ~IFF_OACTIVE;
1281
1282 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1283
1284 SF_UNLOCK(sc);
1285 }
1286
1287 static int
1288 sf_encap(sc, c, m_head)
1289 struct sf_softc *sc;
1290 struct sf_tx_bufdesc_type0 *c;
1291 struct mbuf *m_head;
1292 {
1293 int frag = 0;
1294 struct sf_frag *f = NULL;
1295 struct mbuf *m;
1296
1297 m = m_head;
1298
1299 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1300 if (m->m_len != 0) {
1301 if (frag == SF_MAXFRAGS)
1302 break;
1303 f = &c->sf_frags[frag];
1304 if (frag == 0)
1305 f->sf_pktlen = m_head->m_pkthdr.len;
1306 f->sf_fraglen = m->m_len;
1307 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1308 frag++;
1309 }
1310 }
1311
1312 if (m != NULL) {
1313 struct mbuf *m_new = NULL;
1314
1315 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1316 if (m_new == NULL) {
1317 printf("sf%d: no memory for tx list\n", sc->sf_unit);
1318 return(1);
1319 }
1320
1321 if (m_head->m_pkthdr.len > MHLEN) {
1322 MCLGET(m_new, M_DONTWAIT);
1323 if (!(m_new->m_flags & M_EXT)) {
1324 m_freem(m_new);
1325 printf("sf%d: no memory for tx list\n",
1326 sc->sf_unit);
1327 return(1);
1328 }
1329 }
1330 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1331 mtod(m_new, caddr_t));
1332 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1333 m_freem(m_head);
1334 m_head = m_new;
1335 f = &c->sf_frags[0];
1336 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1337 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1338 frag = 1;
1339 }
1340
1341 c->sf_mbuf = m_head;
1342 c->sf_id = SF_TX_BUFDESC_ID;
1343 c->sf_fragcnt = frag;
1344 c->sf_intr = 1;
1345 c->sf_caltcp = 0;
1346 c->sf_crcen = 1;
1347
1348 return(0);
1349 }
1350
1351 static void
1352 sf_start(ifp)
1353 struct ifnet *ifp;
1354 {
1355 struct sf_softc *sc;
1356 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1357 struct mbuf *m_head = NULL;
1358 int i, txprod;
1359
1360 sc = ifp->if_softc;
1361 SF_LOCK(sc);
1362
1363 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) {
1364 SF_UNLOCK(sc);
1365 return;
1366 }
1367
1368 if (ifp->if_flags & IFF_OACTIVE) {
1369 SF_UNLOCK(sc);
1370 return;
1371 }
1372
1373 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1374 i = SF_IDX_HI(txprod) >> 4;
1375
1376 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1377 printf("sf%d: TX ring full, resetting\n", sc->sf_unit);
1378 sf_init(sc);
1379 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1380 i = SF_IDX_HI(txprod) >> 4;
1381 }
1382
1383 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1384 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
1385 ifp->if_flags |= IFF_OACTIVE;
1386 cur_tx = NULL;
1387 break;
1388 }
1389 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1390 if (m_head == NULL)
1391 break;
1392
1393 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1394 if (sf_encap(sc, cur_tx, m_head)) {
1395 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1396 ifp->if_flags |= IFF_OACTIVE;
1397 cur_tx = NULL;
1398 break;
1399 }
1400
1401 /*
1402 * If there's a BPF listener, bounce a copy of this frame
1403 * to him.
1404 */
1405 BPF_MTAP(ifp, m_head);
1406
1407 SF_INC(i, SF_TX_DLIST_CNT);
1408 sc->sf_tx_cnt++;
1409 /*
1410 * Don't get the TX DMA queue get too full.
1411 */
1412 if (sc->sf_tx_cnt > 64)
1413 break;
1414 }
1415
1416 if (cur_tx == NULL) {
1417 SF_UNLOCK(sc);
1418 return;
1419 }
1420
1421 /* Transmit */
1422 csr_write_4(sc, SF_TXDQ_PRODIDX,
1423 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1424 ((i << 20) & 0xFFFF0000));
1425
1426 ifp->if_timer = 5;
1427
1428 SF_UNLOCK(sc);
1429 }
1430
1431 static void
1432 sf_stop(sc)
1433 struct sf_softc *sc;
1434 {
1435 int i;
1436 struct ifnet *ifp;
1437
1438 SF_LOCK(sc);
1439
1440 ifp = &sc->arpcom.ac_if;
1441
1442 untimeout(sf_stats_update, sc, sc->sf_stat_ch);
1443
1444 #ifdef DEVICE_POLLING
1445 ether_poll_deregister(ifp);
1446 #endif /* DEVICE_POLLING */
1447
1448 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1449 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1450 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1451 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1452 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1453 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1454 csr_write_4(sc, SF_TXCQ_CTL, 0);
1455 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1456 csr_write_4(sc, SF_TXDQ_CTL, 0);
1457 sf_reset(sc);
1458
1459 sc->sf_link = 0;
1460
1461 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1462 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1463 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1464 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1465 }
1466 }
1467
1468 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1469 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1470 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1471 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1472 }
1473 }
1474
1475 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1476 SF_UNLOCK(sc);
1477 }
1478
1479 /*
1480 * Note: it is important that this function not be interrupted. We
1481 * use a two-stage register access scheme: if we are interrupted in
1482 * between setting the indirect address register and reading from the
1483 * indirect data register, the contents of the address register could
1484 * be changed out from under us.
1485 */
1486 static void
1487 sf_stats_update(xsc)
1488 void *xsc;
1489 {
1490 struct sf_softc *sc;
1491 struct ifnet *ifp;
1492 struct mii_data *mii;
1493 struct sf_stats stats;
1494 u_int32_t *ptr;
1495 int i;
1496
1497 sc = xsc;
1498 SF_LOCK(sc);
1499 ifp = &sc->arpcom.ac_if;
1500 mii = device_get_softc(sc->sf_miibus);
1501
1502 ptr = (u_int32_t *)&stats;
1503 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1504 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1505 (i + sizeof(u_int32_t)));
1506
1507 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1508 csr_write_4(sc, SF_STATS_BASE +
1509 (i + sizeof(u_int32_t)), 0);
1510
1511 ifp->if_collisions += stats.sf_tx_single_colls +
1512 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1513
1514 mii_tick(mii);
1515
1516 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE &&
1517 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1518 sc->sf_link++;
1519 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1520 sf_start(ifp);
1521 }
1522
1523 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1524
1525 SF_UNLOCK(sc);
1526 }
1527
1528 static void
1529 sf_watchdog(ifp)
1530 struct ifnet *ifp;
1531 {
1532 struct sf_softc *sc;
1533
1534 sc = ifp->if_softc;
1535
1536 SF_LOCK(sc);
1537
1538 ifp->if_oerrors++;
1539 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1540
1541 sf_stop(sc);
1542 sf_reset(sc);
1543 sf_init(sc);
1544
1545 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1546 sf_start(ifp);
1547
1548 SF_UNLOCK(sc);
1549 }
1550
1551 static void
1552 sf_shutdown(dev)
1553 device_t dev;
1554 {
1555 struct sf_softc *sc;
1556
1557 sc = device_get_softc(dev);
1558
1559 sf_stop(sc);
1560 }
Cache object: 4fec18eb1ec16705987dab04f997b1ff
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