FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sf.c
1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/6.0/sys/pci/if_sf.c 151140 2005-10-09 04:11:20Z delphij $");
35
36 /*
37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
38 * Programming manual is available from:
39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf.
40 *
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Department of Electical Engineering
43 * Columbia University, New York City
44 */
45 /*
46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
47 * controller designed with flexibility and reducing CPU load in mind.
48 * The Starfire offers high and low priority buffer queues, a
49 * producer/consumer index mechanism and several different buffer
50 * queue and completion queue descriptor types. Any one of a number
51 * of different driver designs can be used, depending on system and
52 * OS requirements. This driver makes use of type0 transmit frame
53 * descriptors (since BSD fragments packets across an mbuf chain)
54 * and two RX buffer queues prioritized on size (one queue for small
55 * frames that will fit into a single mbuf, another with full size
56 * mbuf clusters for everything else). The producer/consumer indexes
57 * and completion queues are also used.
58 *
59 * One downside to the Starfire has to do with alignment: buffer
60 * queues must be aligned on 256-byte boundaries, and receive buffers
61 * must be aligned on longword boundaries. The receive buffer alignment
62 * causes problems on the Alpha platform, where the packet payload
63 * should be longword aligned. There is no simple way around this.
64 *
65 * For receive filtering, the Starfire offers 16 perfect filter slots
66 * and a 512-bit hash table.
67 *
68 * The Starfire has no internal transceiver, relying instead on an
69 * external MII-based transceiver. Accessing registers on external
70 * PHYs is done through a special register map rather than with the
71 * usual bitbang MDIO method.
72 *
73 * Acesssing the registers on the Starfire is a little tricky. The
74 * Starfire has a 512K internal register space. When programmed for
75 * PCI memory mapped mode, the entire register space can be accessed
76 * directly. However in I/O space mode, only 256 bytes are directly
77 * mapped into PCI I/O space. The other registers can be accessed
78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
79 * registers inside the 256-byte I/O window.
80 */
81
82 #ifdef HAVE_KERNEL_OPTION_HEADERS
83 #include "opt_device_polling.h"
84 #endif
85
86 #include <sys/param.h>
87 #include <sys/systm.h>
88 #include <sys/sockio.h>
89 #include <sys/mbuf.h>
90 #include <sys/malloc.h>
91 #include <sys/kernel.h>
92 #include <sys/module.h>
93 #include <sys/socket.h>
94
95 #include <net/if.h>
96 #include <net/if_arp.h>
97 #include <net/ethernet.h>
98 #include <net/if_dl.h>
99 #include <net/if_media.h>
100 #include <net/if_types.h>
101
102 #include <net/bpf.h>
103
104 #include <vm/vm.h> /* for vtophys */
105 #include <vm/pmap.h> /* for vtophys */
106 #include <machine/bus.h>
107 #include <machine/resource.h>
108 #include <sys/bus.h>
109 #include <sys/rman.h>
110
111 #include <dev/mii/mii.h>
112 #include <dev/mii/miivar.h>
113
114 /* "controller miibus0" required. See GENERIC if you get errors here. */
115 #include "miibus_if.h"
116
117 #include <dev/pci/pcireg.h>
118 #include <dev/pci/pcivar.h>
119
120 #define SF_USEIOSPACE
121
122 #include <pci/if_sfreg.h>
123
124 MODULE_DEPEND(sf, pci, 1, 1, 1);
125 MODULE_DEPEND(sf, ether, 1, 1, 1);
126 MODULE_DEPEND(sf, miibus, 1, 1, 1);
127
128 static struct sf_type sf_devs[] = {
129 { AD_VENDORID, AD_DEVICEID_STARFIRE,
130 "Adaptec AIC-6915 10/100BaseTX" },
131 { 0, 0, NULL }
132 };
133
134 static int sf_probe(device_t);
135 static int sf_attach(device_t);
136 static int sf_detach(device_t);
137 static void sf_intr(void *);
138 static void sf_stats_update(void *);
139 static void sf_rxeof(struct sf_softc *);
140 static void sf_txeof(struct sf_softc *);
141 static int sf_encap(struct sf_softc *, struct sf_tx_bufdesc_type0 *,
142 struct mbuf *);
143 static void sf_start(struct ifnet *);
144 static void sf_start_locked(struct ifnet *);
145 static int sf_ioctl(struct ifnet *, u_long, caddr_t);
146 static void sf_init(void *);
147 static void sf_init_locked(struct sf_softc *);
148 static void sf_stop(struct sf_softc *);
149 static void sf_watchdog(struct ifnet *);
150 static void sf_shutdown(device_t);
151 static int sf_ifmedia_upd(struct ifnet *);
152 static void sf_ifmedia_upd_locked(struct ifnet *);
153 static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *);
154 static void sf_reset(struct sf_softc *);
155 static int sf_init_rx_ring(struct sf_softc *);
156 static void sf_init_tx_ring(struct sf_softc *);
157 static int sf_newbuf(struct sf_softc *, struct sf_rx_bufdesc_type0 *,
158 struct mbuf *);
159 static void sf_setmulti(struct sf_softc *);
160 static int sf_setperf(struct sf_softc *, int, caddr_t);
161 static int sf_sethash(struct sf_softc *, caddr_t, int);
162 #ifdef notdef
163 static int sf_setvlan(struct sf_softc *, int, u_int32_t);
164 #endif
165
166 static u_int8_t sf_read_eeprom(struct sf_softc *, int);
167
168 static int sf_miibus_readreg(device_t, int, int);
169 static int sf_miibus_writereg(device_t, int, int, int);
170 static void sf_miibus_statchg(device_t);
171 #ifdef DEVICE_POLLING
172 static void sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
173 static void sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
174 #endif
175
176 static u_int32_t csr_read_4(struct sf_softc *, int);
177 static void csr_write_4(struct sf_softc *, int, u_int32_t);
178 static void sf_txthresh_adjust(struct sf_softc *);
179
180 #ifdef SF_USEIOSPACE
181 #define SF_RES SYS_RES_IOPORT
182 #define SF_RID SF_PCI_LOIO
183 #else
184 #define SF_RES SYS_RES_MEMORY
185 #define SF_RID SF_PCI_LOMEM
186 #endif
187
188 static device_method_t sf_methods[] = {
189 /* Device interface */
190 DEVMETHOD(device_probe, sf_probe),
191 DEVMETHOD(device_attach, sf_attach),
192 DEVMETHOD(device_detach, sf_detach),
193 DEVMETHOD(device_shutdown, sf_shutdown),
194
195 /* bus interface */
196 DEVMETHOD(bus_print_child, bus_generic_print_child),
197 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
198
199 /* MII interface */
200 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
201 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
202 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
203
204 { 0, 0 }
205 };
206
207 static driver_t sf_driver = {
208 "sf",
209 sf_methods,
210 sizeof(struct sf_softc),
211 };
212
213 static devclass_t sf_devclass;
214
215 DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0);
216 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
217
218 #define SF_SETBIT(sc, reg, x) \
219 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x))
220
221 #define SF_CLRBIT(sc, reg, x) \
222 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x))
223
224 static u_int32_t
225 csr_read_4(sc, reg)
226 struct sf_softc *sc;
227 int reg;
228 {
229 u_int32_t val;
230
231 #ifdef SF_USEIOSPACE
232 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
233 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
234 #else
235 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
236 #endif
237
238 return(val);
239 }
240
241 static u_int8_t
242 sf_read_eeprom(sc, reg)
243 struct sf_softc *sc;
244 int reg;
245 {
246 u_int8_t val;
247
248 val = (csr_read_4(sc, SF_EEADDR_BASE +
249 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
250
251 return(val);
252 }
253
254 static void
255 csr_write_4(sc, reg, val)
256 struct sf_softc *sc;
257 int reg;
258 u_int32_t val;
259 {
260 #ifdef SF_USEIOSPACE
261 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
262 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
263 #else
264 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
265 #endif
266 }
267
268 /*
269 * Copy the address 'mac' into the perfect RX filter entry at
270 * offset 'idx.' The perfect filter only has 16 entries so do
271 * some sanity tests.
272 */
273 static int
274 sf_setperf(sc, idx, mac)
275 struct sf_softc *sc;
276 int idx;
277 caddr_t mac;
278 {
279 u_int16_t *p;
280
281 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
282 return(EINVAL);
283
284 if (mac == NULL)
285 return(EINVAL);
286
287 p = (u_int16_t *)mac;
288
289 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
290 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
291 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
292 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
293 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
294 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
295
296 return(0);
297 }
298
299 /*
300 * Set the bit in the 512-bit hash table that corresponds to the
301 * specified mac address 'mac.' If 'prio' is nonzero, update the
302 * priority hash table instead of the filter hash table.
303 */
304 static int
305 sf_sethash(sc, mac, prio)
306 struct sf_softc *sc;
307 caddr_t mac;
308 int prio;
309 {
310 u_int32_t h;
311
312 if (mac == NULL)
313 return(EINVAL);
314
315 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23;
316
317 if (prio) {
318 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
319 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
320 } else {
321 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
322 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
323 }
324
325 return(0);
326 }
327
328 #ifdef notdef
329 /*
330 * Set a VLAN tag in the receive filter.
331 */
332 static int
333 sf_setvlan(sc, idx, vlan)
334 struct sf_softc *sc;
335 int idx;
336 u_int32_t vlan;
337 {
338 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
339 return(EINVAL);
340
341 csr_write_4(sc, SF_RXFILT_HASH_BASE +
342 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
343
344 return(0);
345 }
346 #endif
347
348 static int
349 sf_miibus_readreg(dev, phy, reg)
350 device_t dev;
351 int phy, reg;
352 {
353 struct sf_softc *sc;
354 int i;
355 u_int32_t val = 0;
356
357 sc = device_get_softc(dev);
358
359 for (i = 0; i < SF_TIMEOUT; i++) {
360 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
361 if (val & SF_MII_DATAVALID)
362 break;
363 }
364
365 if (i == SF_TIMEOUT)
366 return(0);
367
368 if ((val & 0x0000FFFF) == 0xFFFF)
369 return(0);
370
371 return(val & 0x0000FFFF);
372 }
373
374 static int
375 sf_miibus_writereg(dev, phy, reg, val)
376 device_t dev;
377 int phy, reg, val;
378 {
379 struct sf_softc *sc;
380 int i;
381 int busy;
382
383 sc = device_get_softc(dev);
384
385 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
386
387 for (i = 0; i < SF_TIMEOUT; i++) {
388 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
389 if (!(busy & SF_MII_BUSY))
390 break;
391 }
392
393 return(0);
394 }
395
396 static void
397 sf_miibus_statchg(dev)
398 device_t dev;
399 {
400 struct sf_softc *sc;
401 struct mii_data *mii;
402
403 sc = device_get_softc(dev);
404 mii = device_get_softc(sc->sf_miibus);
405
406 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
407 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
408 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
409 } else {
410 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
411 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
412 }
413 }
414
415 static void
416 sf_setmulti(sc)
417 struct sf_softc *sc;
418 {
419 struct ifnet *ifp;
420 int i;
421 struct ifmultiaddr *ifma;
422 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
423
424 ifp = sc->sf_ifp;
425
426 /* First zot all the existing filters. */
427 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
428 sf_setperf(sc, i, (char *)&dummy);
429 for (i = SF_RXFILT_HASH_BASE;
430 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
431 csr_write_4(sc, i, 0);
432 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
433
434 /* Now program new ones. */
435 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
436 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
437 } else {
438 i = 1;
439 IF_ADDR_LOCK(ifp);
440 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
441 if (ifma->ifma_addr->sa_family != AF_LINK)
442 continue;
443 /*
444 * Program the first 15 multicast groups
445 * into the perfect filter. For all others,
446 * use the hash table.
447 */
448 if (i < SF_RXFILT_PERFECT_CNT) {
449 sf_setperf(sc, i,
450 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
451 i++;
452 continue;
453 }
454
455 sf_sethash(sc,
456 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
457 }
458 IF_ADDR_UNLOCK(ifp);
459 }
460 }
461
462 /*
463 * Set media options.
464 */
465 static int
466 sf_ifmedia_upd(ifp)
467 struct ifnet *ifp;
468 {
469 struct sf_softc *sc;
470
471 sc = ifp->if_softc;
472 SF_LOCK(sc);
473 sf_ifmedia_upd_locked(ifp);
474 SF_UNLOCK(sc);
475
476 return(0);
477 }
478
479 static void
480 sf_ifmedia_upd_locked(ifp)
481 struct ifnet *ifp;
482 {
483 struct sf_softc *sc;
484 struct mii_data *mii;
485
486 sc = ifp->if_softc;
487 mii = device_get_softc(sc->sf_miibus);
488 SF_LOCK_ASSERT(sc);
489 sc->sf_link = 0;
490 if (mii->mii_instance) {
491 struct mii_softc *miisc;
492 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
493 mii_phy_reset(miisc);
494 }
495 mii_mediachg(mii);
496 }
497
498 /*
499 * Report current media status.
500 */
501 static void
502 sf_ifmedia_sts(ifp, ifmr)
503 struct ifnet *ifp;
504 struct ifmediareq *ifmr;
505 {
506 struct sf_softc *sc;
507 struct mii_data *mii;
508
509 sc = ifp->if_softc;
510 SF_LOCK(sc);
511 mii = device_get_softc(sc->sf_miibus);
512
513 mii_pollstat(mii);
514 ifmr->ifm_active = mii->mii_media_active;
515 ifmr->ifm_status = mii->mii_media_status;
516 SF_UNLOCK(sc);
517 }
518
519 static int
520 sf_ioctl(ifp, command, data)
521 struct ifnet *ifp;
522 u_long command;
523 caddr_t data;
524 {
525 struct sf_softc *sc = ifp->if_softc;
526 struct ifreq *ifr = (struct ifreq *) data;
527 struct mii_data *mii;
528 int error = 0;
529
530 switch(command) {
531 case SIOCSIFFLAGS:
532 SF_LOCK(sc);
533 if (ifp->if_flags & IFF_UP) {
534 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
535 ifp->if_flags & IFF_PROMISC &&
536 !(sc->sf_if_flags & IFF_PROMISC)) {
537 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
538 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
539 !(ifp->if_flags & IFF_PROMISC) &&
540 sc->sf_if_flags & IFF_PROMISC) {
541 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
542 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
543 sf_init_locked(sc);
544 } else {
545 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
546 sf_stop(sc);
547 }
548 sc->sf_if_flags = ifp->if_flags;
549 SF_UNLOCK(sc);
550 error = 0;
551 break;
552 case SIOCADDMULTI:
553 case SIOCDELMULTI:
554 SF_LOCK(sc);
555 sf_setmulti(sc);
556 SF_UNLOCK(sc);
557 error = 0;
558 break;
559 case SIOCGIFMEDIA:
560 case SIOCSIFMEDIA:
561 mii = device_get_softc(sc->sf_miibus);
562 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
563 break;
564 case SIOCSIFCAP:
565 #ifdef DEVICE_POLLING
566 if (ifr->ifr_reqcap & IFCAP_POLLING &&
567 !(ifp->if_capenable & IFCAP_POLLING)) {
568 error = ether_poll_register(sf_poll, ifp);
569 if (error)
570 return(error);
571 SF_LOCK(sc);
572 /* Disable interrupts */
573 csr_write_4(sc, SF_IMR, 0x00000000);
574 ifp->if_capenable |= IFCAP_POLLING;
575 SF_UNLOCK(sc);
576 return (error);
577
578 }
579 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
580 ifp->if_capenable & IFCAP_POLLING) {
581 error = ether_poll_deregister(ifp);
582 /* Enable interrupts. */
583 SF_LOCK(sc);
584 csr_write_4(sc, SF_IMR, SF_INTRS);
585 ifp->if_capenable &= ~IFCAP_POLLING;
586 SF_UNLOCK(sc);
587 return (error);
588 }
589 #endif /* DEVICE_POLLING */
590 break;
591 default:
592 error = ether_ioctl(ifp, command, data);
593 break;
594 }
595
596 return(error);
597 }
598
599 static void
600 sf_reset(sc)
601 struct sf_softc *sc;
602 {
603 register int i;
604
605 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
606 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
607 DELAY(1000);
608 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
609
610 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
611
612 for (i = 0; i < SF_TIMEOUT; i++) {
613 DELAY(10);
614 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
615 break;
616 }
617
618 if (i == SF_TIMEOUT)
619 if_printf(sc->sf_ifp, "reset never completed!\n");
620
621 /* Wait a little while for the chip to get its brains in order. */
622 DELAY(1000);
623 }
624
625 /*
626 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
627 * IDs against our list and return a device name if we find a match.
628 * We also check the subsystem ID so that we can identify exactly which
629 * NIC has been found, if possible.
630 */
631 static int
632 sf_probe(dev)
633 device_t dev;
634 {
635 struct sf_type *t;
636
637 t = sf_devs;
638
639 while(t->sf_name != NULL) {
640 if ((pci_get_vendor(dev) == t->sf_vid) &&
641 (pci_get_device(dev) == t->sf_did)) {
642 switch((pci_read_config(dev,
643 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
644 case AD_SUBSYSID_62011_REV0:
645 case AD_SUBSYSID_62011_REV1:
646 device_set_desc(dev,
647 "Adaptec ANA-62011 10/100BaseTX");
648 return (BUS_PROBE_DEFAULT);
649 case AD_SUBSYSID_62022:
650 device_set_desc(dev,
651 "Adaptec ANA-62022 10/100BaseTX");
652 return (BUS_PROBE_DEFAULT);
653 case AD_SUBSYSID_62044_REV0:
654 case AD_SUBSYSID_62044_REV1:
655 device_set_desc(dev,
656 "Adaptec ANA-62044 10/100BaseTX");
657 return (BUS_PROBE_DEFAULT);
658 case AD_SUBSYSID_62020:
659 device_set_desc(dev,
660 "Adaptec ANA-62020 10/100BaseFX");
661 return (BUS_PROBE_DEFAULT);
662 case AD_SUBSYSID_69011:
663 device_set_desc(dev,
664 "Adaptec ANA-69011 10/100BaseTX");
665 return (BUS_PROBE_DEFAULT);
666 default:
667 device_set_desc(dev, t->sf_name);
668 return (BUS_PROBE_DEFAULT);
669 break;
670 }
671 }
672 t++;
673 }
674
675 return(ENXIO);
676 }
677
678 /*
679 * Attach the interface. Allocate softc structures, do ifmedia
680 * setup and ethernet/BPF attach.
681 */
682 static int
683 sf_attach(dev)
684 device_t dev;
685 {
686 int i;
687 struct sf_softc *sc;
688 struct ifnet *ifp;
689 int rid, error = 0;
690 u_char eaddr[6];
691
692 sc = device_get_softc(dev);
693
694 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
695 MTX_DEF);
696 /*
697 * Map control/status registers.
698 */
699 pci_enable_busmaster(dev);
700
701 rid = SF_RID;
702 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE);
703
704 if (sc->sf_res == NULL) {
705 device_printf(dev, "couldn't map ports\n");
706 error = ENXIO;
707 goto fail;
708 }
709
710 sc->sf_btag = rman_get_bustag(sc->sf_res);
711 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
712
713 /* Allocate interrupt */
714 rid = 0;
715 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
716 RF_SHAREABLE | RF_ACTIVE);
717
718 if (sc->sf_irq == NULL) {
719 device_printf(dev, "couldn't map interrupt\n");
720 error = ENXIO;
721 goto fail;
722 }
723
724 callout_init_mtx(&sc->sf_stat_callout, &sc->sf_mtx, 0);
725
726 /* Reset the adapter. */
727 sf_reset(sc);
728
729 /*
730 * Get station address from the EEPROM.
731 */
732 for (i = 0; i < ETHER_ADDR_LEN; i++)
733 eaddr[i] =
734 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
735
736 /* Allocate the descriptor queues. */
737 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
738 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
739
740 if (sc->sf_ldata == NULL) {
741 device_printf(dev, "no memory for list buffers!\n");
742 error = ENXIO;
743 goto fail;
744 }
745
746 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
747
748 ifp = sc->sf_ifp = if_alloc(IFT_ETHER);
749 if (ifp == NULL) {
750 device_printf(dev, "can not if_alloc()\n");
751 error = ENOSPC;
752 goto fail;
753 }
754
755 /* Do MII setup. */
756 if (mii_phy_probe(dev, &sc->sf_miibus,
757 sf_ifmedia_upd, sf_ifmedia_sts)) {
758 device_printf(dev, "MII without any phy!\n");
759 error = ENXIO;
760 goto fail;
761 }
762
763 ifp->if_softc = sc;
764 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
765 ifp->if_mtu = ETHERMTU;
766 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
767 ifp->if_ioctl = sf_ioctl;
768 ifp->if_start = sf_start;
769 ifp->if_watchdog = sf_watchdog;
770 ifp->if_init = sf_init;
771 ifp->if_baudrate = 10000000;
772 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
773 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1;
774 IFQ_SET_READY(&ifp->if_snd);
775 ifp->if_capenable = ifp->if_capabilities;
776 #ifdef DEVICE_POLLING
777 ifp->if_capabilities |= IFCAP_POLLING;
778 #endif
779
780 /*
781 * Call MI attach routine.
782 */
783 ether_ifattach(ifp, eaddr);
784
785 /* Hook interrupt last to avoid having to lock softc */
786 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET | INTR_MPSAFE,
787 sf_intr, sc, &sc->sf_intrhand);
788
789 if (error) {
790 device_printf(dev, "couldn't set up irq\n");
791 ether_ifdetach(ifp);
792 goto fail;
793 }
794
795 fail:
796 if (error)
797 sf_detach(dev);
798
799 return(error);
800 }
801
802 /*
803 * Shutdown hardware and free up resources. This can be called any
804 * time after the mutex has been initialized. It is called in both
805 * the error case in attach and the normal detach case so it needs
806 * to be careful about only freeing resources that have actually been
807 * allocated.
808 */
809 static int
810 sf_detach(dev)
811 device_t dev;
812 {
813 struct sf_softc *sc;
814 struct ifnet *ifp;
815
816 sc = device_get_softc(dev);
817 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized"));
818 ifp = sc->sf_ifp;
819
820 #ifdef DEVICE_POLLING
821 if (ifp->if_capenable & IFCAP_POLLING)
822 ether_poll_deregister(ifp);
823 #endif
824
825 /* These should only be active if attach succeeded */
826 if (device_is_attached(dev)) {
827 SF_LOCK(sc);
828 sf_stop(sc);
829 SF_UNLOCK(sc);
830 callout_drain(&sc->sf_stat_callout);
831 ether_ifdetach(ifp);
832 }
833 if (ifp)
834 if_free(ifp);
835 if (sc->sf_miibus)
836 device_delete_child(dev, sc->sf_miibus);
837 bus_generic_detach(dev);
838
839 if (sc->sf_intrhand)
840 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
841 if (sc->sf_irq)
842 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
843 if (sc->sf_res)
844 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
845
846 if (sc->sf_ldata)
847 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF);
848
849 mtx_destroy(&sc->sf_mtx);
850
851 return(0);
852 }
853
854 static int
855 sf_init_rx_ring(sc)
856 struct sf_softc *sc;
857 {
858 struct sf_list_data *ld;
859 int i;
860
861 ld = sc->sf_ldata;
862
863 bzero((char *)ld->sf_rx_dlist_big,
864 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
865 bzero((char *)ld->sf_rx_clist,
866 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
867
868 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
869 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
870 return(ENOBUFS);
871 }
872
873 return(0);
874 }
875
876 static void
877 sf_init_tx_ring(sc)
878 struct sf_softc *sc;
879 {
880 struct sf_list_data *ld;
881 int i;
882
883 ld = sc->sf_ldata;
884
885 bzero((char *)ld->sf_tx_dlist,
886 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
887 bzero((char *)ld->sf_tx_clist,
888 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
889
890 for (i = 0; i < SF_TX_DLIST_CNT; i++)
891 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
892 for (i = 0; i < SF_TX_CLIST_CNT; i++)
893 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
894
895 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
896 sc->sf_tx_cnt = 0;
897 }
898
899 static int
900 sf_newbuf(sc, c, m)
901 struct sf_softc *sc;
902 struct sf_rx_bufdesc_type0 *c;
903 struct mbuf *m;
904 {
905 struct mbuf *m_new = NULL;
906
907 if (m == NULL) {
908 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
909 if (m_new == NULL)
910 return(ENOBUFS);
911
912 MCLGET(m_new, M_DONTWAIT);
913 if (!(m_new->m_flags & M_EXT)) {
914 m_freem(m_new);
915 return(ENOBUFS);
916 }
917 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
918 } else {
919 m_new = m;
920 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
921 m_new->m_data = m_new->m_ext.ext_buf;
922 }
923
924 m_adj(m_new, sizeof(u_int64_t));
925
926 c->sf_mbuf = m_new;
927 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
928 c->sf_valid = 1;
929
930 return(0);
931 }
932
933 /*
934 * The starfire is programmed to use 'normal' mode for packet reception,
935 * which means we use the consumer/producer model for both the buffer
936 * descriptor queue and the completion descriptor queue. The only problem
937 * with this is that it involves a lot of register accesses: we have to
938 * read the RX completion consumer and producer indexes and the RX buffer
939 * producer index, plus the RX completion consumer and RX buffer producer
940 * indexes have to be updated. It would have been easier if Adaptec had
941 * put each index in a separate register, especially given that the damn
942 * NIC has a 512K register space.
943 *
944 * In spite of all the lovely features that Adaptec crammed into the 6915,
945 * it is marred by one truly stupid design flaw, which is that receive
946 * buffer addresses must be aligned on a longword boundary. This forces
947 * the packet payload to be unaligned, which is suboptimal on the x86 and
948 * completely unuseable on the Alpha. Our only recourse is to copy received
949 * packets into properly aligned buffers before handing them off.
950 */
951
952 static void
953 sf_rxeof(sc)
954 struct sf_softc *sc;
955 {
956 struct mbuf *m;
957 struct ifnet *ifp;
958 struct sf_rx_bufdesc_type0 *desc;
959 struct sf_rx_cmpdesc_type3 *cur_rx;
960 u_int32_t rxcons, rxprod;
961 int cmpprodidx, cmpconsidx, bufprodidx;
962
963 SF_LOCK_ASSERT(sc);
964
965 ifp = sc->sf_ifp;
966
967 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
968 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
969 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
970 cmpconsidx = SF_IDX_LO(rxcons);
971 bufprodidx = SF_IDX_LO(rxprod);
972
973 while (cmpconsidx != cmpprodidx) {
974 struct mbuf *m0;
975
976 #ifdef DEVICE_POLLING
977 if (ifp->if_capenable & IFCAP_POLLING) {
978 if (sc->rxcycles <= 0)
979 break;
980 sc->rxcycles--;
981 }
982 #endif
983
984 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
985 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
986 m = desc->sf_mbuf;
987 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
988 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
989
990 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
991 ifp->if_ierrors++;
992 sf_newbuf(sc, desc, m);
993 continue;
994 }
995
996 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN,
997 ifp, NULL);
998 sf_newbuf(sc, desc, m);
999 if (m0 == NULL) {
1000 ifp->if_ierrors++;
1001 continue;
1002 }
1003 m = m0;
1004
1005 ifp->if_ipackets++;
1006 SF_UNLOCK(sc);
1007 (*ifp->if_input)(ifp, m);
1008 SF_LOCK(sc);
1009 }
1010
1011 csr_write_4(sc, SF_CQ_CONSIDX,
1012 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
1013 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1014 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
1015 }
1016
1017 /*
1018 * Read the transmit status from the completion queue and release
1019 * mbufs. Note that the buffer descriptor index in the completion
1020 * descriptor is an offset from the start of the transmit buffer
1021 * descriptor list in bytes. This is important because the manual
1022 * gives the impression that it should match the producer/consumer
1023 * index, which is the offset in 8 byte blocks.
1024 */
1025 static void
1026 sf_txeof(sc)
1027 struct sf_softc *sc;
1028 {
1029 int txcons, cmpprodidx, cmpconsidx;
1030 struct sf_tx_cmpdesc_type1 *cur_cmp;
1031 struct sf_tx_bufdesc_type0 *cur_tx;
1032 struct ifnet *ifp;
1033
1034 ifp = sc->sf_ifp;
1035
1036 SF_LOCK_ASSERT(sc);
1037 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1038 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1039 cmpconsidx = SF_IDX_HI(txcons);
1040
1041 while (cmpconsidx != cmpprodidx) {
1042 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1043 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1044
1045 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1046 ifp->if_opackets++;
1047 else {
1048 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
1049 sf_txthresh_adjust(sc);
1050 ifp->if_oerrors++;
1051 }
1052
1053 sc->sf_tx_cnt--;
1054 if (cur_tx->sf_mbuf != NULL) {
1055 m_freem(cur_tx->sf_mbuf);
1056 cur_tx->sf_mbuf = NULL;
1057 } else
1058 break;
1059 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1060 }
1061
1062 ifp->if_timer = 0;
1063 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1064
1065 csr_write_4(sc, SF_CQ_CONSIDX,
1066 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1067 ((cmpconsidx << 16) & 0xFFFF0000));
1068 }
1069
1070 static void
1071 sf_txthresh_adjust(sc)
1072 struct sf_softc *sc;
1073 {
1074 u_int32_t txfctl;
1075 u_int8_t txthresh;
1076
1077 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1078 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
1079 if (txthresh < 0xFF) {
1080 txthresh++;
1081 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1082 txfctl |= txthresh;
1083 #ifdef DIAGNOSTIC
1084 if_printf(sc->sf_ifp, "tx underrun, increasing "
1085 "tx threshold to %d bytes\n",
1086 txthresh * 4);
1087 #endif
1088 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1089 }
1090 }
1091
1092 #ifdef DEVICE_POLLING
1093 static void
1094 sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1095 {
1096 struct sf_softc *sc = ifp->if_softc;
1097
1098 SF_LOCK(sc);
1099 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1100 sf_poll_locked(ifp, cmd, count);
1101 SF_UNLOCK(sc);
1102 }
1103
1104 static void
1105 sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1106 {
1107 struct sf_softc *sc = ifp->if_softc;
1108
1109 SF_LOCK_ASSERT(sc);
1110
1111 sc->rxcycles = count;
1112 sf_rxeof(sc);
1113 sf_txeof(sc);
1114 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1115 sf_start_locked(ifp);
1116
1117 if (cmd == POLL_AND_CHECK_STATUS) {
1118 u_int32_t status;
1119
1120 status = csr_read_4(sc, SF_ISR);
1121 if (status)
1122 csr_write_4(sc, SF_ISR, status);
1123
1124 if (status & SF_ISR_TX_LOFIFO)
1125 sf_txthresh_adjust(sc);
1126
1127 if (status & SF_ISR_ABNORMALINTR) {
1128 if (status & SF_ISR_STATSOFLOW) {
1129 callout_stop(&sc->sf_stat_callout);
1130 sf_stats_update(sc);
1131 } else
1132 sf_init_locked(sc);
1133 }
1134 }
1135 }
1136 #endif /* DEVICE_POLLING */
1137
1138 static void
1139 sf_intr(arg)
1140 void *arg;
1141 {
1142 struct sf_softc *sc;
1143 struct ifnet *ifp;
1144 u_int32_t status;
1145
1146 sc = arg;
1147 SF_LOCK(sc);
1148
1149 ifp = sc->sf_ifp;
1150
1151 #ifdef DEVICE_POLLING
1152 if (ifp->if_capenable & IFCAP_POLLING) {
1153 SF_UNLOCK(sc);
1154 return;
1155 }
1156 #endif
1157
1158 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) {
1159 SF_UNLOCK(sc);
1160 return;
1161 }
1162
1163 /* Disable interrupts. */
1164 csr_write_4(sc, SF_IMR, 0x00000000);
1165
1166 for (;;) {
1167 status = csr_read_4(sc, SF_ISR);
1168 if (status)
1169 csr_write_4(sc, SF_ISR, status);
1170
1171 if (!(status & SF_INTRS))
1172 break;
1173
1174 if (status & SF_ISR_RXDQ1_DMADONE)
1175 sf_rxeof(sc);
1176
1177 if (status & SF_ISR_TX_TXDONE ||
1178 status & SF_ISR_TX_DMADONE ||
1179 status & SF_ISR_TX_QUEUEDONE)
1180 sf_txeof(sc);
1181
1182 if (status & SF_ISR_TX_LOFIFO)
1183 sf_txthresh_adjust(sc);
1184
1185 if (status & SF_ISR_ABNORMALINTR) {
1186 if (status & SF_ISR_STATSOFLOW) {
1187 callout_stop(&sc->sf_stat_callout);
1188 sf_stats_update(sc);
1189 } else
1190 sf_init_locked(sc);
1191 }
1192 }
1193
1194 /* Re-enable interrupts. */
1195 csr_write_4(sc, SF_IMR, SF_INTRS);
1196
1197 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1198 sf_start_locked(ifp);
1199
1200 SF_UNLOCK(sc);
1201 }
1202
1203 static void
1204 sf_init(xsc)
1205 void *xsc;
1206 {
1207 struct sf_softc *sc;
1208
1209 sc = xsc;
1210 SF_LOCK(sc);
1211 sf_init_locked(sc);
1212 SF_UNLOCK(sc);
1213 }
1214
1215 static void
1216 sf_init_locked(sc)
1217 struct sf_softc *sc;
1218 {
1219 struct ifnet *ifp;
1220 struct mii_data *mii;
1221 int i;
1222
1223 SF_LOCK_ASSERT(sc);
1224 ifp = sc->sf_ifp;
1225 mii = device_get_softc(sc->sf_miibus);
1226
1227 sf_stop(sc);
1228 sf_reset(sc);
1229
1230 /* Init all the receive filter registers */
1231 for (i = SF_RXFILT_PERFECT_BASE;
1232 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1233 csr_write_4(sc, i, 0);
1234
1235 /* Empty stats counter registers. */
1236 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1237 csr_write_4(sc, SF_STATS_BASE +
1238 (i + sizeof(u_int32_t)), 0);
1239
1240 /* Init our MAC address */
1241 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->sf_ifp)[0]));
1242 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->sf_ifp)[4]));
1243 sf_setperf(sc, 0, (caddr_t)&IFP2ENADDR(sc->sf_ifp));
1244
1245 if (sf_init_rx_ring(sc) == ENOBUFS) {
1246 if_printf(sc->sf_ifp,
1247 "initialization failed: no memory for rx buffers\n");
1248 return;
1249 }
1250
1251 sf_init_tx_ring(sc);
1252
1253 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1254
1255 /* If we want promiscuous mode, set the allframes bit. */
1256 if (ifp->if_flags & IFF_PROMISC) {
1257 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1258 } else {
1259 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1260 }
1261
1262 if (ifp->if_flags & IFF_BROADCAST) {
1263 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1264 } else {
1265 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1266 }
1267
1268 /*
1269 * Load the multicast filter.
1270 */
1271 sf_setmulti(sc);
1272
1273 /* Init the completion queue indexes */
1274 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1275 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1276
1277 /* Init the RX completion queue */
1278 csr_write_4(sc, SF_RXCQ_CTL_1,
1279 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1280 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1281
1282 /* Init RX DMA control. */
1283 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1284
1285 /* Init the RX buffer descriptor queue. */
1286 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1287 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1288 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1289 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1290
1291 /* Init the TX completion queue */
1292 csr_write_4(sc, SF_TXCQ_CTL,
1293 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1294
1295 /* Init the TX buffer descriptor queue. */
1296 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1297 vtophys(sc->sf_ldata->sf_tx_dlist));
1298 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1299 csr_write_4(sc, SF_TXDQ_CTL,
1300 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1301 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1302
1303 /* Enable autopadding of short TX frames. */
1304 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1305
1306 #ifdef DEVICE_POLLING
1307 /* Disable interrupts if we are polling. */
1308 if (ifp->if_capenable & IFCAP_POLLING)
1309 csr_write_4(sc, SF_IMR, 0x00000000);
1310 else
1311 #endif
1312
1313 /* Enable interrupts. */
1314 csr_write_4(sc, SF_IMR, SF_INTRS);
1315 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1316
1317 /* Enable the RX and TX engines. */
1318 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1319 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1320
1321 /*mii_mediachg(mii);*/
1322 sf_ifmedia_upd_locked(ifp);
1323
1324 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1325 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1326
1327 callout_reset(&sc->sf_stat_callout, hz, sf_stats_update, sc);
1328 }
1329
1330 static int
1331 sf_encap(sc, c, m_head)
1332 struct sf_softc *sc;
1333 struct sf_tx_bufdesc_type0 *c;
1334 struct mbuf *m_head;
1335 {
1336 int frag = 0;
1337 struct sf_frag *f = NULL;
1338 struct mbuf *m;
1339
1340 m = m_head;
1341
1342 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1343 if (m->m_len != 0) {
1344 if (frag == SF_MAXFRAGS)
1345 break;
1346 f = &c->sf_frags[frag];
1347 if (frag == 0)
1348 f->sf_pktlen = m_head->m_pkthdr.len;
1349 f->sf_fraglen = m->m_len;
1350 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1351 frag++;
1352 }
1353 }
1354
1355 if (m != NULL) {
1356 struct mbuf *m_new = NULL;
1357
1358 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1359 if (m_new == NULL) {
1360 if_printf(sc->sf_ifp, "no memory for tx list\n");
1361 return(1);
1362 }
1363
1364 if (m_head->m_pkthdr.len > MHLEN) {
1365 MCLGET(m_new, M_DONTWAIT);
1366 if (!(m_new->m_flags & M_EXT)) {
1367 m_freem(m_new);
1368 if_printf(sc->sf_ifp, "no memory for tx list\n");
1369 return(1);
1370 }
1371 }
1372 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1373 mtod(m_new, caddr_t));
1374 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1375 m_freem(m_head);
1376 m_head = m_new;
1377 f = &c->sf_frags[0];
1378 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1379 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1380 frag = 1;
1381 }
1382
1383 c->sf_mbuf = m_head;
1384 c->sf_id = SF_TX_BUFDESC_ID;
1385 c->sf_fragcnt = frag;
1386 c->sf_intr = 1;
1387 c->sf_caltcp = 0;
1388 c->sf_crcen = 1;
1389
1390 return(0);
1391 }
1392
1393 static void
1394 sf_start(ifp)
1395 struct ifnet *ifp;
1396 {
1397 struct sf_softc *sc;
1398
1399 sc = ifp->if_softc;
1400 SF_LOCK(sc);
1401 sf_start_locked(ifp);
1402 SF_UNLOCK(sc);
1403 }
1404
1405 static void
1406 sf_start_locked(ifp)
1407 struct ifnet *ifp;
1408 {
1409 struct sf_softc *sc;
1410 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1411 struct mbuf *m_head = NULL;
1412 int i, txprod;
1413
1414 sc = ifp->if_softc;
1415 SF_LOCK_ASSERT(sc);
1416
1417 if (!sc->sf_link && ifp->if_snd.ifq_len < 10)
1418 return;
1419
1420 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1421 return;
1422
1423 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1424 i = SF_IDX_HI(txprod) >> 4;
1425
1426 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1427 if_printf(ifp, "TX ring full, resetting\n");
1428 sf_init_locked(sc);
1429 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1430 i = SF_IDX_HI(txprod) >> 4;
1431 }
1432
1433 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1434 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
1435 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1436 cur_tx = NULL;
1437 break;
1438 }
1439 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1440 if (m_head == NULL)
1441 break;
1442
1443 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1444 if (sf_encap(sc, cur_tx, m_head)) {
1445 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1446 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1447 cur_tx = NULL;
1448 break;
1449 }
1450
1451 /*
1452 * If there's a BPF listener, bounce a copy of this frame
1453 * to him.
1454 */
1455 BPF_MTAP(ifp, m_head);
1456
1457 SF_INC(i, SF_TX_DLIST_CNT);
1458 sc->sf_tx_cnt++;
1459 /*
1460 * Don't get the TX DMA queue get too full.
1461 */
1462 if (sc->sf_tx_cnt > 64)
1463 break;
1464 }
1465
1466 if (cur_tx == NULL)
1467 return;
1468
1469 /* Transmit */
1470 csr_write_4(sc, SF_TXDQ_PRODIDX,
1471 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1472 ((i << 20) & 0xFFFF0000));
1473
1474 ifp->if_timer = 5;
1475 }
1476
1477 static void
1478 sf_stop(sc)
1479 struct sf_softc *sc;
1480 {
1481 int i;
1482 struct ifnet *ifp;
1483
1484 SF_LOCK_ASSERT(sc);
1485
1486 ifp = sc->sf_ifp;
1487
1488 callout_stop(&sc->sf_stat_callout);
1489
1490 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1491 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1492 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1493 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1494 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1495 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1496 csr_write_4(sc, SF_TXCQ_CTL, 0);
1497 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1498 csr_write_4(sc, SF_TXDQ_CTL, 0);
1499 sf_reset(sc);
1500
1501 sc->sf_link = 0;
1502
1503 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1504 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1505 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1506 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1507 }
1508 }
1509
1510 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1511 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1512 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1513 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1514 }
1515 }
1516
1517 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1518 }
1519
1520 /*
1521 * Note: it is important that this function not be interrupted. We
1522 * use a two-stage register access scheme: if we are interrupted in
1523 * between setting the indirect address register and reading from the
1524 * indirect data register, the contents of the address register could
1525 * be changed out from under us.
1526 */
1527 static void
1528 sf_stats_update(xsc)
1529 void *xsc;
1530 {
1531 struct sf_softc *sc;
1532 struct ifnet *ifp;
1533 struct mii_data *mii;
1534 struct sf_stats stats;
1535 u_int32_t *ptr;
1536 int i;
1537
1538 sc = xsc;
1539 SF_LOCK_ASSERT(sc);
1540 ifp = sc->sf_ifp;
1541 mii = device_get_softc(sc->sf_miibus);
1542
1543 ptr = (u_int32_t *)&stats;
1544 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1545 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1546 (i + sizeof(u_int32_t)));
1547
1548 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1549 csr_write_4(sc, SF_STATS_BASE +
1550 (i + sizeof(u_int32_t)), 0);
1551
1552 ifp->if_collisions += stats.sf_tx_single_colls +
1553 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1554
1555 mii_tick(mii);
1556
1557 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE &&
1558 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1559 sc->sf_link++;
1560 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1561 sf_start_locked(ifp);
1562 }
1563
1564 callout_reset(&sc->sf_stat_callout, hz, sf_stats_update, sc);
1565 }
1566
1567 static void
1568 sf_watchdog(ifp)
1569 struct ifnet *ifp;
1570 {
1571 struct sf_softc *sc;
1572
1573 sc = ifp->if_softc;
1574
1575 SF_LOCK(sc);
1576
1577 ifp->if_oerrors++;
1578 if_printf(ifp, "watchdog timeout\n");
1579
1580 sf_stop(sc);
1581 sf_reset(sc);
1582 sf_init_locked(sc);
1583
1584 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1585 sf_start_locked(ifp);
1586
1587 SF_UNLOCK(sc);
1588 }
1589
1590 static void
1591 sf_shutdown(dev)
1592 device_t dev;
1593 {
1594 struct sf_softc *sc;
1595
1596 sc = device_get_softc(dev);
1597
1598 SF_LOCK(sc);
1599 sf_stop(sc);
1600 SF_UNLOCK(sc);
1601 }
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