The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sfreg.h

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    1 /*-
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD$
   33  */
   34 
   35 /*
   36  * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K
   37  * register space. These registers can be accessed in the following way:
   38  * - PCI config registers are always accessible through PCI config space
   39  * - Full 512K space mapped into memory using PCI memory mapped access
   40  * - 256-byte I/O space mapped through PCI I/O access
   41  * - Full 512K space mapped through indirect I/O using PCI I/O access
   42  * It's possible to use either memory mapped mode or I/O mode to access
   43  * the registers, but memory mapped is usually the easiest. All registers
   44  * are 32 bits wide and must be accessed using 32-bit operations.
   45  */
   46 
   47 /*
   48  * Adaptec PCI vendor ID.
   49  */
   50 #define AD_VENDORID             0x9004
   51 
   52 /*
   53  * AIC-6915 PCI device ID.
   54  */
   55 #define AD_DEVICEID_STARFIRE    0x6915
   56 
   57 /*
   58  * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify
   59  * the exact kind of NIC on which the ASIC is mounted. Currently there
   60  * are six different variations. Note: the Adaptec manual lists code 0x28
   61  * for two different NICs: the 62044 and the 69011/TX. This is a typo:
   62  * the code for the 62044 is really 0x18.
   63  *
   64  * Note that there also appears to be an 0x19 code for a newer rev
   65  * 62044 card.
   66  */
   67 #define AD_SUBSYSID_62011_REV0  0x0008  /* single port 10/100baseTX 64-bit */
   68 #define AD_SUBSYSID_62011_REV1  0x0009  /* single port 10/100baseTX 64-bit */
   69 #define AD_SUBSYSID_62022       0x0010  /* dual port 10/100baseTX 64-bit */
   70 #define AD_SUBSYSID_62044_REV0  0x0018  /* quad port 10/100baseTX 64-bit */
   71 #define AD_SUBSYSID_62044_REV1  0x0019  /* quad port 10/100baseTX 64-bit */
   72 #define AD_SUBSYSID_62020       0x0020  /* single port 10/100baseFX 64-bit */
   73 #define AD_SUBSYSID_69011       0x0028  /* single port 10/100baseTX 32-bit */
   74 
   75 /*
   76  * Starfire internal register space map. The entire register space
   77  * is available using PCI memory mapped mode. The SF_RMAP_INTREG
   78  * space is available using PCI I/O mode. The entire space can be
   79  * accessed using indirect I/O using the indirect I/O addr and
   80  * indirect I/O data registers located within the SF_RMAP_INTREG space.
   81  */
   82 #define SF_RMAP_ROMADDR_BASE    0x00000 /* Expansion ROM space */
   83 #define SF_RMAP_ROMADDR_MAX     0x3FFFF
   84 
   85 #define SF_RMAP_EXGPIO_BASE     0x40000 /* External general purpose regs */
   86 #define SF_RMAP_EXGPIO_MAX      0x3FFFF
   87 
   88 #define SF_RMAP_INTREG_BASE     0x50000 /* Internal functional registers */
   89 #define SF_RMAP_INTREG_MAX      0x500FF
   90 #define SF_RMAP_GENREG_BASE     0x50100 /* General purpose registers */
   91 #define SF_RMAP_GENREG_MAX      0x5FFFF
   92 
   93 #define SF_RMAP_FIFO_BASE       0x60000
   94 #define SF_RMAP_FIFO_MAX        0x6FFFF
   95 
   96 #define SF_RMAP_STS_BASE        0x70000
   97 #define SF_RMAP_STS_MAX         0x70083
   98 
   99 #define SF_RMAP_RSVD_BASE       0x70084
  100 #define SF_RMAP_RSVD_MAX        0x7FFFF
  101 
  102 /*
  103  * PCI config header registers, 0x0000 to 0x003F
  104  */
  105 #define SF_PCI_VENDOR_ID        0x0000
  106 #define SF_PCI_DEVICE_ID        0x0002
  107 #define SF_PCI_COMMAND          0x0004
  108 #define SF_PCI_STATUS           0x0006
  109 #define SF_PCI_REVID            0x0008
  110 #define SF_PCI_CLASSCODE        0x0009
  111 #define SF_PCI_CACHELEN         0x000C
  112 #define SF_PCI_LATENCY_TIMER    0x000D
  113 #define SF_PCI_HEADER_TYPE      0x000E
  114 #define SF_PCI_LOMEM            0x0010
  115 #define SF_PCI_LOIO             0x0014
  116 #define SF_PCI_SUBVEN_ID        0x002C
  117 #define SF_PCI_SYBSYS_ID        0x002E
  118 #define SF_PCI_BIOSROM          0x0030
  119 #define SF_PCI_INTLINE          0x003C
  120 #define SF_PCI_INTPIN           0x003D
  121 #define SF_PCI_MINGNT           0x003E
  122 #define SF_PCI_MINLAT           0x003F
  123 
  124 /*
  125  * PCI registers, 0x0040 to 0x006F
  126  */
  127 #define SF_PCI_DEVCFG           0x0040
  128 #define SF_BACCTL               0x0044
  129 #define SF_PCI_MON1             0x0048
  130 #define SF_PCI_MON2             0x004C
  131 #define SF_PCI_CAPID            0x0050 /* 8 bits */
  132 #define SF_PCI_NEXTPTR          0x0051 /* 8 bits */
  133 #define SF_PCI_PWRMGMTCAP       0x0052 /* 16 bits */
  134 #define SF_PCI_PWRMGMTCTRL      0x0054 /* 16 bits */
  135 #define SF_PCI_PME_EVENT        0x0058
  136 #define SF_PCI_EECTL            0x0060
  137 #define SF_PCI_COMPLIANCE       0x0064
  138 #define SF_INDIRECTIO_ADDR      0x0068
  139 #define SF_INDIRECTIO_DATA      0x006C
  140 
  141 #define SF_PCIDEVCFG_RESET      0x00000001
  142 #define SF_PCIDEVCFG_FORCE64    0x00000002
  143 #define SF_PCIDEVCFG_SYSTEM64   0x00000004
  144 #define SF_PCIDEVCFG_RSVD0      0x00000008
  145 #define SF_PCIDEVCFG_INCR_INB   0x00000010
  146 #define SF_PCIDEVCFG_ABTONPERR  0x00000020
  147 #define SF_PCIDEVCFG_STPONPERR  0x00000040
  148 #define SF_PCIDEVCFG_MR_ENB     0x00000080
  149 #define SF_PCIDEVCFG_FIFOTHR    0x00000F00
  150 #define SF_PCIDEVCFG_STPONCA    0x00001000
  151 #define SF_PCIDEVCFG_PCIMEN     0x00002000      /* enable PCI bus master */
  152 #define SF_PCIDEVCFG_LATSTP     0x00004000
  153 #define SF_PCIDEVCFG_BYTE_ENB   0x00008000
  154 #define SF_PCIDEVCFG_EECSWIDTH  0x00070000
  155 #define SF_PCIDEVCFG_STPMWCA    0x00080000
  156 #define SF_PCIDEVCFG_REGCSWIDTH 0x00700000
  157 #define SF_PCIDEVCFG_INTR_ENB   0x00800000
  158 #define SF_PCIDEVCFG_DPR_ENB    0x01000000
  159 #define SF_PCIDEVCFG_RSVD1      0x02000000
  160 #define SF_PCIDEVCFG_RSVD2      0x04000000
  161 #define SF_PCIDEVCFG_STA_ENB    0x08000000
  162 #define SF_PCIDEVCFG_RTA_ENB    0x10000000
  163 #define SF_PCIDEVCFG_RMA_ENB    0x20000000
  164 #define SF_PCIDEVCFG_SSE_ENB    0x40000000
  165 #define SF_PCIDEVCFG_DPE_ENB    0x80000000
  166 
  167 #define SF_BACCTL_BACDMA_ENB    0x00000001
  168 #define SF_BACCTL_PREFER_RXDMA  0x00000002
  169 #define SF_BACCTL_PREFER_TXDMA  0x00000004
  170 #define SF_BACCTL_SINGLE_DMA    0x00000008
  171 #define SF_BACCTL_SWAPMODE_DATA 0x00000030
  172 #define SF_BACCTL_SWAPMODE_DESC 0x000000C0
  173 
  174 #define SF_SWAPMODE_LE          0x00000000
  175 #define SF_SWAPMODE_BE          0x00000010
  176 
  177 #define SF_PSTATE_MASK          0x0003
  178 #define SF_PSTATE_D0            0x0000
  179 #define SF_PSTATE_D1            0x0001
  180 #define SF_PSTATE_D2            0x0002
  181 #define SF_PSTATE_D3            0x0003
  182 #define SF_PME_EN               0x0010
  183 #define SF_PME_STATUS           0x8000
  184 
  185 
  186 /*
  187  * Ethernet registers 0x0070 to 0x00FF
  188  */
  189 #define SF_GEN_ETH_CTL          0x0070
  190 #define SF_TIMER_CTL            0x0074
  191 #define SF_CURTIME              0x0078
  192 #define SF_ISR                  0x0080
  193 #define SF_ISR_SHADOW           0x0084
  194 #define SF_IMR                  0x0088
  195 #define SF_GPIO                 0x008C
  196 #define SF_TXDQ_CTL             0x0090
  197 #define SF_TXDQ_ADDR_HIPRIO     0x0094
  198 #define SF_TXDQ_ADDR_LOPRIO     0x0098
  199 #define SF_TXDQ_ADDR_HIADDR     0x009C
  200 #define SF_TXDQ_PRODIDX         0x00A0
  201 #define SF_TXDQ_CONSIDX         0x00A4
  202 #define SF_TXDMA_STS1           0x00A8
  203 #define SF_TXDMA_STS2           0x00AC
  204 #define SF_TX_FRAMCTL           0x00B0
  205 #define SF_TXCQ_ADDR_HI         0x00B4
  206 #define SF_TXCQ_CTL             0x00B8
  207 #define SF_RXCQ_CTL_1           0x00BC
  208 #define SF_RXCQ_CTL_2           0x00C0
  209 #define SF_CQ_CONSIDX           0x00C4
  210 #define SF_CQ_PRODIDX           0x00C8
  211 #define SF_CQ_RXQ2              0x00CC
  212 #define SF_RXDMA_CTL            0x00D0
  213 #define SF_RXDQ_CTL_1           0x00D4
  214 #define SF_RXDQ_CTL_2           0x00D8
  215 #define SF_RXDQ_ADDR_HIADDR     0x00DC
  216 #define SF_RXDQ_ADDR_Q1         0x00E0
  217 #define SF_RXDQ_ADDR_Q2         0x00E4
  218 #define SF_RXDQ_PTR_Q1          0x00E8
  219 #define SF_RXDQ_PTR_Q2          0x00EC
  220 #define SF_RXDMA_STS            0x00F0
  221 #define SF_RXFILT               0x00F4
  222 #define SF_RX_FRAMETEST_OUT     0x00F8
  223 
  224 /* Ethernet control register */
  225 #define SF_ETHCTL_RX_ENB        0x00000001
  226 #define SF_ETHCTL_TX_ENB        0x00000002
  227 #define SF_ETHCTL_RXDMA_ENB     0x00000004
  228 #define SF_ETHCTL_TXDMA_ENB     0x00000008
  229 #define SF_ETHCTL_RXGFP_ENB     0x00000010
  230 #define SF_ETHCTL_TXGFP_ENB     0x00000020
  231 #define SF_ETHCTL_SOFTINTR      0x00000800
  232 
  233 /* Timer control register */
  234 #define SF_TIMER_IMASK_INTERVAL 0x0000001F
  235 #define SF_TIMER_IMASK_MODE     0x00000060
  236 #define SF_TIMER_SMALLFRAME_BYP 0x00000100
  237 #define SF_TIMER_SMALLRX_FRAME  0x00000600
  238 #define SF_TIMER_TIMES_TEN      0x00000800
  239 #define SF_TIMER_RXHIPRIO_BYP   0x00001000
  240 #define SF_TIMER_TX_DMADONE_DLY 0x00002000
  241 #define SF_TIMER_TX_QDONE_DLY   0x00004000
  242 #define SF_TIMER_TX_FRDONE_DLY  0x00008000
  243 #define SF_TIMER_GENTIMER       0x00FF0000
  244 #define SF_TIMER_ONESHOT        0x01000000
  245 #define SF_TIMER_GENTIMER_RES   0x02000000
  246 #define SF_TIMER_TIMEST_RES     0x04000000
  247 #define SF_TIMER_RXQ2DONE_DLY   0x10000000
  248 #define SF_TIMER_EARLYRX2_DLY   0x20000000
  249 #define SF_TIMER_RXQ1DONE_DLY   0x40000000
  250 #define SF_TIMER_EARLYRX1_DLY   0x80000000
  251 
  252 /* Interrupt status register */
  253 #define SF_ISR_PCIINT_ASSERTED  0x00000001
  254 #define SF_ISR_GFP_TX           0x00000002
  255 #define SF_ISR_GFP_RX           0x00000004
  256 #define SF_ISR_TX_BADID_HIPRIO  0x00000008
  257 #define SF_ISR_TX_BADID_LOPRIO  0x00000010
  258 #define SF_ISR_NO_TX_CSUM       0x00000020
  259 #define SF_ISR_RXDQ2_NOBUFS     0x00000040
  260 #define SF_ISR_RXGFP_NORESP     0x00000080
  261 #define SF_ISR_RXDQ1_DMADONE    0x00000100
  262 #define SF_ISR_RXDQ2_DMADONE    0x00000200
  263 #define SF_ISR_RXDQ1_EARLY      0x00000400
  264 #define SF_ISR_RXDQ2_EARLY      0x00000800
  265 #define SF_ISR_TX_QUEUEDONE     0x00001000
  266 #define SF_ISR_TX_DMADONE       0x00002000
  267 #define SF_ISR_TX_TXDONE        0x00004000
  268 #define SF_ISR_NORMALINTR       0x00008000
  269 #define SF_ISR_RXDQ1_NOBUFS     0x00010000
  270 #define SF_ISR_RXCQ2_NOBUFS     0x00020000
  271 #define SF_ISR_TX_LOFIFO        0x00040000
  272 #define SF_ISR_DMAERR           0x00080000
  273 #define SF_ISR_PCIINT           0x00100000
  274 #define SF_ISR_TXCQ_NOBUFS      0x00200000
  275 #define SF_ISR_RXCQ1_NOBUFS     0x00400000
  276 #define SF_ISR_SOFTINTR         0x00800000
  277 #define SF_ISR_GENTIMER         0x01000000
  278 #define SF_ISR_ABNORMALINTR     0x02000000
  279 #define SF_ISR_RSVD0            0x04000000
  280 #define SF_ISR_STATSOFLOW       0x08000000
  281 #define SF_ISR_GPIO             0xF0000000
  282 
  283 /*
  284  * Shadow interrupt status register. Unlike the normal IRQ register,
  285  * reading bits here does not automatically cause them to reset.
  286  */
  287 #define SF_SISR_PCIINT_ASSERTED 0x00000001
  288 #define SF_SISR_GFP_TX          0x00000002
  289 #define SF_SISR_GFP_RX          0x00000004
  290 #define SF_SISR_TX_BADID_HIPRIO 0x00000008
  291 #define SF_SISR_TX_BADID_LOPRIO 0x00000010
  292 #define SF_SISR_NO_TX_CSUM      0x00000020
  293 #define SF_SISR_RXDQ2_NOBUFS    0x00000040
  294 #define SF_SISR_RXGFP_NORESP    0x00000080
  295 #define SF_SISR_RXDQ1_DMADONE   0x00000100
  296 #define SF_SISR_RXDQ2_DMADONE   0x00000200
  297 #define SF_SISR_RXDQ1_EARLY     0x00000400
  298 #define SF_SISR_RXDQ2_EARLY     0x00000800
  299 #define SF_SISR_TX_QUEUEDONE    0x00001000
  300 #define SF_SISR_TX_DMADONE      0x00002000
  301 #define SF_SISR_TX_TXDONE       0x00004000
  302 #define SF_SISR_NORMALINTR      0x00008000
  303 #define SF_SISR_RXDQ1_NOBUFS    0x00010000
  304 #define SF_SISR_RXCQ2_NOBUFS    0x00020000
  305 #define SF_SISR_TX_LOFIFO       0x00040000
  306 #define SF_SISR_DMAERR          0x00080000
  307 #define SF_SISR_PCIINT          0x00100000
  308 #define SF_SISR_TXCQ_NOBUFS     0x00200000
  309 #define SF_SISR_RXCQ1_NOBUFS    0x00400000
  310 #define SF_SISR_SOFTINTR        0x00800000
  311 #define SF_SISR_GENTIMER        0x01000000
  312 #define SF_SISR_ABNORMALINTR    0x02000000
  313 #define SF_SISR_RSVD0           0x04000000
  314 #define SF_SISR_STATSOFLOW      0x08000000
  315 #define SF_SISR_GPIO            0xF0000000
  316 
  317 /* Interrupt mask register */
  318 #define SF_IMR_PCIINT_ASSERTED  0x00000001
  319 #define SF_IMR_GFP_TX           0x00000002
  320 #define SF_IMR_GFP_RX           0x00000004
  321 #define SF_IMR_TX_BADID_HIPRIO  0x00000008
  322 #define SF_IMR_TX_BADID_LOPRIO  0x00000010
  323 #define SF_IMR_NO_TX_CSUM       0x00000020
  324 #define SF_IMR_RXDQ2_NOBUFS     0x00000040
  325 #define SF_IMR_RXGFP_NORESP     0x00000080
  326 #define SF_IMR_RXDQ1_DMADONE    0x00000100
  327 #define SF_IMR_RXDQ2_DMADONE    0x00000200
  328 #define SF_IMR_RXDQ1_EARLY      0x00000400
  329 #define SF_IMR_RXDQ2_EARLY      0x00000800
  330 #define SF_IMR_TX_QUEUEDONE     0x00001000
  331 #define SF_IMR_TX_DMADONE       0x00002000
  332 #define SF_IMR_TX_TXDONE        0x00004000
  333 #define SF_IMR_NORMALINTR       0x00008000
  334 #define SF_IMR_RXDQ1_NOBUFS     0x00010000
  335 #define SF_IMR_RXCQ2_NOBUFS     0x00020000
  336 #define SF_IMR_TX_LOFIFO        0x00040000
  337 #define SF_IMR_DMAERR           0x00080000
  338 #define SF_IMR_PCIINT           0x00100000
  339 #define SF_IMR_TXCQ_NOBUFS      0x00200000
  340 #define SF_IMR_RXCQ1_NOBUFS     0x00400000
  341 #define SF_IMR_SOFTINTR         0x00800000
  342 #define SF_IMR_GENTIMER         0x01000000
  343 #define SF_IMR_ABNORMALINTR     0x02000000
  344 #define SF_IMR_RSVD0            0x04000000
  345 #define SF_IMR_STATSOFLOW       0x08000000
  346 #define SF_IMR_GPIO             0xF0000000
  347 
  348 #define SF_INTRS        \
  349         (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE| \
  350          SF_IMR_TX_TXDONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE|     \
  351          SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS|      \
  352          SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW|     \
  353          SF_IMR_TX_LOFIFO)
  354 
  355 /* TX descriptor queue control registers */
  356 #define SF_TXDQCTL_DESCTYPE     0x00000007
  357 #define SF_TXDQCTL_NODMACMP     0x00000008
  358 #define SF_TXDQCTL_MINSPACE     0x00000070
  359 #define SF_TXDQCTL_64BITADDR    0x00000080
  360 #define SF_TXDQCTL_BURSTLEN     0x00003F00
  361 #define SF_TXDQCTL_SKIPLEN      0x001F0000
  362 #define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000
  363 
  364 #define SF_TXBUFDESC_TYPE0      0x00000000
  365 #define SF_TXBUFDESC_TYPE1      0x00000001
  366 #define SF_TXBUFDESC_TYPE2      0x00000002
  367 #define SF_TXBUFDESC_TYPE3      0x00000003
  368 #define SF_TXBUFDESC_TYPE4      0x00000004
  369 
  370 #define SF_TXMINSPACE_UNLIMIT   0x00000000
  371 #define SF_TXMINSPACE_32BYTES   0x00000010
  372 #define SF_TXMINSPACE_64BYTES   0x00000020
  373 #define SF_TXMINSPACE_128BYTES  0x00000030
  374 #define SF_TXMINSPACE_256BYTES  0x00000040
  375 
  376 #define SF_TXSKIPLEN_0BYTES     0x00000000
  377 #define SF_TXSKIPLEN_8BYTES     0x00010000
  378 #define SF_TXSKIPLEN_16BYTES    0x00020000
  379 #define SF_TXSKIPLEN_24BYTES    0x00030000
  380 #define SF_TXSKIPLEN_32BYTES    0x00040000
  381 
  382 /* TX frame control register */
  383 #define SF_TXFRMCTL_TXTHRESH    0x000000FF
  384 #define SF_TXFRMCTL_CPLAFTERTX  0x00000100
  385 #define SF_TXFRMCRL_DEBUG       0x0000FE00
  386 #define SF_TXFRMCTL_STATUS      0x01FF0000
  387 #define SF_TXFRMCTL_MAC_TXIF    0xFE000000
  388 
  389 /* TX completion queue control register */
  390 #define SF_TXCQ_THRESH          0x0000000F
  391 #define SF_TXCQ_COMMON          0x00000010
  392 #define SF_TXCQ_SIZE            0x00000020
  393 #define SF_TXCQ_WRITEENB        0x00000040
  394 #define SF_TXCQ_USE_64BIT       0x00000080
  395 #define SF_TXCQ_ADDR            0xFFFFFF00
  396 
  397 /* RX completion queue control register */
  398 #define SF_RXCQ_THRESH          0x0000000F
  399 #define SF_RXCQ_TYPE            0x00000030
  400 #define SF_RXCQ_WRITEENB        0x00000040
  401 #define SF_RXCQ_USE_64BIT       0x00000080
  402 #define SF_RXCQ_ADDR            0xFFFFFF00
  403 
  404 #define SF_RXCQTYPE_0           0x00000000
  405 #define SF_RXCQTYPE_1           0x00000010
  406 #define SF_RXCQTYPE_2           0x00000020
  407 #define SF_RXCQTYPE_3           0x00000030
  408 
  409 /* TX descriptor queue producer index register */
  410 #define SF_TXDQ_PRODIDX_LOPRIO  0x000007FF
  411 #define SF_TXDQ_PRODIDX_HIPRIO  0x07FF0000
  412 
  413 /* TX descriptor queue consumer index register */
  414 #define SF_TXDQ_CONSIDX_LOPRIO  0x000007FF
  415 #define SF_TXDQ_CONSIDX_HIPRIO  0x07FF0000
  416 
  417 /* Completion queue consumer index register */
  418 #define SF_CQ_CONSIDX_RXQ1      0x000003FF
  419 #define SF_CQ_CONSIDX_RXTHRMODE 0x00008000
  420 #define SF_CQ_CONSIDX_TXQ       0x03FF0000
  421 #define SF_CQ_CONSIDX_TXTHRMODE 0x80000000
  422 
  423 /* Completion queue producer index register */
  424 #define SF_CQ_PRODIDX_RXQ1      0x000003FF
  425 #define SF_CQ_PRODIDX_TXQ       0x03FF0000
  426 
  427 /* RX completion queue 2 consumer/producer index register */
  428 #define SF_CQ_RXQ2_CONSIDX      0x000003FF
  429 #define SF_CQ_RXQ2_RXTHRMODE    0x00008000
  430 #define SF_CQ_RXQ2_PRODIDX      0x03FF0000
  431 
  432 #define SF_CQ_RXTHRMODE_INT_ON  0x00008000
  433 #define SF_CQ_RXTHRMODE_INT_OFF 0x00000000
  434 #define SF_CQ_TXTHRMODE_INT_ON  0x80000000
  435 #define SF_CQ_TXTHRMODE_INT_OFF 0x00000000
  436 
  437 #define SF_IDX_LO(x)            ((x) & 0x000007FF)
  438 #define SF_IDX_HI(x)            (((x) >> 16) & 0x000007FF)
  439 
  440 /* RX DMA control register */
  441 #define SF_RXDMA_BURSTSIZE      0x0000007F
  442 #define SF_RXDMA_FPTESTMODE     0x00000080
  443 #define SF_RXDMA_HIPRIOTHRESH   0x00000F00
  444 #define SF_RXDMA_RXEARLYTHRESH  0x0001F000
  445 #define SF_RXDMA_DMACRC         0x00040000
  446 #define SF_RXDMA_USEBKUPQUEUE   0x00080000
  447 #define SF_RXDMA_QUEUEMODE      0x00700000
  448 #define SF_RXDMA_RXCQ2_ON       0x00800000
  449 #define SF_RXDMA_CSUMMODE       0x03000000
  450 #define SF_RXDMA_DMAPAUSEPKTS   0x04000000
  451 #define SF_RXDMA_DMACTLPKTS     0x08000000
  452 #define SF_RXDMA_DMACRXERRPKTS  0x10000000
  453 #define SF_RXDMA_DMABADPKTS     0x20000000
  454 #define SF_RXDMA_DMARUNTS       0x40000000
  455 #define SF_RXDMA_REPORTBADPKTS  0x80000000
  456 
  457 #define SF_RXDQMODE_Q1ONLY      0x00100000
  458 #define SF_RXDQMODE_Q2_ON_FP    0x00200000
  459 #define SF_RXDQMODE_Q2_ON_SHORT 0x00300000
  460 #define SF_RXDQMODE_Q2_ON_PRIO  0x00400000
  461 #define SF_RXDQMODE_SPLITHDR    0x00500000
  462 
  463 #define SF_RXCSUMMODE_IGNORE    0x00000000
  464 #define SF_RXCSUMMODE_REJECT_BAD_TCP    0x01000000
  465 #define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000
  466 #define SF_RXCSUMMODE_RSVD      0x03000000
  467 
  468 /* RX descriptor queue control registers */
  469 #define SF_RXDQCTL_MINDESCTHR   0x0000007F
  470 #define SF_RXDQCTL_Q1_WE        0x00000080
  471 #define SF_RXDQCTL_DESCSPACE    0x00000700
  472 #define SF_RXDQCTL_64BITDADDR   0x00000800
  473 #define SF_RXDQCTL_64BITBADDR   0x00001000
  474 #define SF_RXDQCTL_VARIABLE     0x00002000
  475 #define SF_RXDQCTL_ENTRIES      0x00004000
  476 #define SF_RXDQCTL_PREFETCH     0x00008000
  477 #define SF_RXDQCTL_BUFLEN       0xFFFF0000
  478 
  479 #define SF_DESCSPACE_4BYTES     0x00000000
  480 #define SF_DESCSPACE_8BYTES     0x00000100
  481 #define SF_DESCSPACE_16BYTES    0x00000200
  482 #define SF_DESCSPACE_32BYTES    0x00000300
  483 #define SF_DESCSPACE_64BYTES    0x00000400
  484 #define SF_DESCSPACE_128_BYTES  0x00000500
  485 
  486 /* RX buffer consumer/producer index registers */
  487 #define SF_RXDQ_PRODIDX         0x000007FF
  488 #define SF_RXDQ_CONSIDX         0x07FF0000
  489 
  490 /* RX filter control register */
  491 #define SF_RXFILT_PROMISC       0x00000001
  492 #define SF_RXFILT_ALLMULTI      0x00000002
  493 #define SF_RXFILT_BROAD         0x00000004
  494 #define SF_RXFILT_HASHPRIO      0x00000008
  495 #define SF_RXFILT_HASHMODE      0x00000030
  496 #define SF_RXFILT_PERFMODE      0x000000C0
  497 #define SF_RXFILT_VLANMODE      0x00000300
  498 #define SF_RXFILT_WAKEMODE      0x00000C00
  499 #define SF_RXFILT_MULTI_NOBROAD 0x00001000
  500 #define SF_RXFILT_MIN_VLANPRIO  0x0000E000
  501 #define SF_RXFILT_PEFECTPRIO    0xFFFF0000
  502 
  503 /* Hash filtering mode */
  504 #define SF_HASHMODE_OFF         0x00000000
  505 #define SF_HASHMODE_WITHVLAN    0x00000010
  506 #define SF_HASHMODE_ANYVLAN     0x00000020
  507 #define SF_HASHMODE_ANY         0x00000030
  508 
  509 /* Perfect filtering mode */
  510 #define SF_PERFMODE_OFF         0x00000000
  511 #define SF_PERFMODE_NORMAL      0x00000040
  512 #define SF_PERFMODE_INVERSE     0x00000080
  513 #define SF_PERFMODE_VLAN        0x000000C0
  514 
  515 /* VLAN mode */
  516 #define SF_VLANMODE_OFF         0x00000000
  517 #define SF_VLANMODE_NOSTRIP     0x00000100
  518 #define SF_VLANMODE_STRIP       0x00000200
  519 #define SF_VLANMODE_RSVD        0x00000300
  520 
  521 /* Wakeup mode */
  522 #define SF_WAKEMODE_OFF         0x00000000
  523 #define SF_WAKEMODE_FILTER      0x00000400
  524 #define SF_WAKEMODE_FP          0x00000800
  525 #define SF_WAKEMODE_HIPRIO      0x00000C00
  526 
  527 /*
  528  * Extra PCI registers 0x0100 to 0x0FFF
  529  */
  530 #define SF_PCI_TARGSTAT         0x0100
  531 #define SF_PCI_MASTSTAT1        0x0104
  532 #define SF_PCI_MASTSTAT2        0x0108
  533 #define SF_PCI_DMAHOSTADDR_LO   0x010C
  534 #define SF_BAC_DMADIAG0         0x0110
  535 #define SF_BAC_DMADIAG1         0x0114
  536 #define SF_BAC_DMADIAG2         0x0118
  537 #define SF_BAC_DMADIAG3         0x011C
  538 #define SF_PAR0                 0x0120
  539 #define SF_PAR1                 0x0124
  540 #define SF_PCICB_FUNCEVENT      0x0130
  541 #define SF_PCICB_FUNCEVENT_MASK 0x0134
  542 #define SF_PCICB_FUNCSTATE      0x0138
  543 #define SF_PCICB_FUNCFORCE      0x013C
  544 
  545 /*
  546  * Serial EEPROM registers 0x1000 to 0x1FFF
  547  * Presumeably the EEPROM is mapped into this 8K window.
  548  */
  549 #define SF_EEADDR_BASE          0x1000
  550 #define SF_EEADDR_MAX           0x1FFF
  551 
  552 #define SF_EE_NODEADDR          14
  553 
  554 /*
  555  * MII registers registers 0x2000 to 0x3FFF
  556  * There are 32 sets of 32 registers, one set for each possible
  557  * PHY address. Each 32 bit register is split into a 16-bit data
  558  * port and a couple of status bits.
  559  */
  560 
  561 #define SF_MIIADDR_BASE         0x2000
  562 #define SF_MIIADDR_MAX          0x3FFF
  563 #define SF_MII_BLOCKS           32
  564 
  565 #define SF_MII_DATAVALID        0x80000000
  566 #define SF_MII_BUSY             0x40000000
  567 #define SF_MII_DATAPORT         0x0000FFFF
  568 
  569 #define SF_PHY_REG(phy, reg)                                            \
  570         (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) +  \
  571         (reg * sizeof(u_int32_t)))
  572 
  573 /*
  574  * Ethernet extra registers 0x4000 to 0x4FFF
  575  */
  576 #define SF_TESTMODE             0x4000
  577 #define SF_RX_FRAMEPROC_CTL     0x4004
  578 #define SF_TX_FRAMEPROC_CTL     0x4008
  579 
  580 /*
  581  * MAC registers 0x5000 to 0x5FFF
  582  */
  583 #define SF_MACCFG_1             0x5000
  584 #define SF_MACCFG_2             0x5004
  585 #define SF_BKTOBKIPG            0x5008
  586 #define SF_NONBKTOBKIPG         0x500C
  587 #define SF_COLRETRY             0x5010
  588 #define SF_MAXLEN               0x5014
  589 #define SF_TXNIBBLECNT          0x5018
  590 #define SF_TXBYTECNT            0x501C
  591 #define SF_RETXCNT              0x5020
  592 #define SF_RANDNUM              0x5024
  593 #define SF_RANDNUM_MASK         0x5028
  594 #define SF_TOTALTXCNT           0x5034
  595 #define SF_RXBYTECNT            0x5040
  596 #define SF_TXPAUSETIMER         0x5060
  597 #define SF_VLANTYPE             0x5064
  598 #define SF_MIISTATUS            0x5070
  599 
  600 #define SF_MACCFG1_HUGEFRAMES   0x00000001
  601 #define SF_MACCFG1_FULLDUPLEX   0x00000002
  602 #define SF_MACCFG1_AUTOPAD      0x00000004
  603 #define SF_MACCFG1_HDJAM        0x00000008
  604 #define SF_MACCFG1_DELAYCRC     0x00000010
  605 #define SF_MACCFG1_NOBACKOFF    0x00000020
  606 #define SF_MACCFG1_LENGTHCHECK  0x00000040
  607 #define SF_MACCFG1_PUREPREAMBLE 0x00000080
  608 #define SF_MACCFG1_PASSALLRX    0x00000100
  609 #define SF_MACCFG1_PREAM_DETCNT 0x00000200
  610 #define SF_MACCFG1_RX_FLOWENB   0x00000400
  611 #define SF_MACCFG1_TX_FLOWENB   0x00000800
  612 #define SF_MACCFG1_TESTMODE     0x00003000
  613 #define SF_MACCFG1_MIILOOPBK    0x00004000
  614 #define SF_MACCFG1_SOFTRESET    0x00008000
  615 
  616 /*
  617  * There are the recommended IPG nibble counter settings
  618  * specified in the Adaptec manual for full duplex and
  619  * half duplex operation.
  620  */
  621 #define SF_IPGT_FDX             0x15
  622 #define SF_IPGT_HDX             0x11
  623 
  624 /*
  625  * RX filter registers 0x6000 to 0x6FFF
  626  */
  627 #define SF_RXFILT_PERFECT_BASE  0x6000
  628 #define SF_RXFILT_PERFECT_MAX   0x60FF
  629 #define SF_RXFILT_PERFECT_SKIP  0x0010
  630 #define SF_RXFILT_PERFECT_CNT   0x0010
  631 
  632 #define SF_RXFILT_HASH_BASE     0x6100
  633 #define SF_RXFILT_HASH_MAX      0x62FF
  634 #define SF_RXFILT_HASH_SKIP     0x0010
  635 #define SF_RXFILT_HASH_CNT      0x001F
  636 #define SF_RXFILT_HASH_ADDROFF  0x0000
  637 #define SF_RXFILT_HASH_PRIOOFF  0x0004
  638 #define SF_RXFILT_HASH_VLANOFF  0x0008
  639 
  640 /*
  641  * Statistics registers 0x7000 to 0x7FFF
  642  */
  643 #define SF_STATS_BASE           0x7000
  644 #define SF_STATS_END            0x7FFF
  645 
  646 /*
  647  * TX frame processor instruction space 0x8000 to 0x9FFF
  648  */
  649 
  650 /*
  651  * RX frame processor instruction space 0xA000 to 0xBFFF
  652  */
  653 
  654 /*
  655  * Ethernet FIFO access space 0xC000 to 0xDFFF
  656  */
  657 
  658 /*
  659  * Reserved 0xE000 to 0xFFFF
  660  */
  661 
  662 /*
  663  * Descriptor data structures.
  664  */
  665 
  666 
  667 /* Receive descriptor formats. */
  668 #define SF_RX_MINSPACING        8
  669 #define SF_RX_DLIST_CNT         256
  670 #define SF_RX_CLIST_CNT         1024
  671 #define SF_RX_HOSTADDR(x)       (((x) >> 2) & 0x3FFFFFFF)
  672 
  673 /*
  674  * RX buffer descriptor type 0, 32-bit addressing. Note that we
  675  * program the RX buffer queue control register(s) to allow a
  676  * descriptor spacing of 16 bytes, which leaves room after each
  677  * descriptor to store a pointer to the mbuf for each buffer.
  678  */
  679 struct sf_rx_bufdesc_type0 {
  680         u_int32_t               sf_valid:1,
  681                                 sf_end:1,
  682                                 sf_addrlo:30;
  683         u_int32_t               sf_pad0;
  684 #ifdef __i386__
  685         u_int32_t               sf_pad1;
  686 #endif
  687         struct mbuf             *sf_mbuf;
  688 };
  689 
  690 /*
  691  * RX buffer descriptor type 0, 64-bit addressing.
  692  */
  693 struct sf_rx_bufdesc_type1 {
  694         u_int32_t               sf_valid:1,
  695                                 sf_end:1,
  696                                 sf_addrlo:30;
  697         u_int32_t               sf_addrhi;
  698 #ifdef __i386__
  699         u_int32_t               sf_pad;
  700 #endif
  701         struct mbuf             *sf_mbuf;
  702 };
  703 
  704 /*
  705  * RX completion descriptor, type 0 (short).
  706  */
  707 struct sf_rx_cmpdesc_type0 {
  708         u_int32_t               sf_len:16,
  709                                 sf_endidx:11,
  710                                 sf_status1:3,
  711                                 sf_id:2;
  712 };
  713 
  714 /*
  715  * RX completion descriptor, type 1 (basic). Includes vlan ID
  716  * if this is a vlan-addressed packet, plus extended status.
  717  */
  718 struct sf_rx_cmpdesc_type1 {
  719         u_int32_t               sf_len:16,
  720                                 sf_endidx:11,
  721                                 sf_status1:3,
  722                                 sf_id:2;
  723         u_int16_t               sf_status2;
  724         u_int16_t               sf_vlanid;
  725 };
  726 
  727 /*
  728  * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP
  729  * checksum instead of vlan tag, plus extended status.
  730  */
  731 struct sf_rx_cmpdesc_type2 {
  732         u_int32_t               sf_len:16,
  733                                 sf_endidx:11,
  734                                 sf_status1:3,
  735                                 sf_id:2;
  736         u_int16_t               sf_status2;
  737         u_int16_t               sf_cksum;
  738 };
  739 
  740 /*
  741  * RX completion descriptor type 3 (full). Includes timestamp, partial
  742  * TCP/IP checksum, vlan tag plus priority, two extended status fields.
  743  */
  744 struct sf_rx_cmpdesc_type3 {
  745         u_int32_t               sf_len:16,
  746                                 sf_endidx:11,
  747                                 sf_status1:3,
  748                                 sf_id:2;
  749         u_int32_t               sf_startidx:10,
  750                                 sf_status3:6,
  751                                 sf_status2:16;
  752         u_int16_t               sf_cksum;
  753         u_int16_t               sf_vlanid_prio;
  754         u_int32_t               sf_timestamp;
  755 };
  756 
  757 #define SF_RXSTAT1_QUEUE        0x1
  758 #define SF_RXSTAT1_FIFOFULL     0x2
  759 #define SF_RXSTAT1_OK           0x4
  760 
  761                                         /* 0=unknown,5=unsupported */
  762 #define SF_RXSTAT2_FRAMETYPE    0x0007  /* 1=IPv4,2=IPv2,3=IPX,4=ICMP */
  763 #define SF_RXSTAT2_UDP          0x0008
  764 #define SF_RXSTAT2_TCP          0x0010
  765 #define SF_RXSTAT2_FRAG         0x0020
  766 #define SF_RXSTAT2_PCSUM_OK     0x0040  /* partial checksum ok */
  767 #define SF_RXSTAT2_CSUM_BAD     0x0080  /* TCP/IP checksum bad */
  768 #define SF_RXSTAT2_CSUM_OK      0x0100  /* TCP/IP checksum ok */
  769 #define SF_RXSTAT2_VLAN         0x0200
  770 #define SF_RXSTAT2_BADRXCODE    0x0400
  771 #define SF_RXSTAT2_DRIBBLE      0x0800
  772 #define SF_RXSTAT2_ISL_CRCERR   0x1000
  773 #define SF_RXSTAT2_CRCERR       0x2000
  774 #define SF_RXSTAT2_HASH         0x4000
  775 #define SF_RXSTAT2_PERFECT      0x8000
  776 
  777 #define SF_RXSTAT3_TRAILER      0x01
  778 #define SF_RXSTAT3_HEADER       0x02
  779 #define SF_RXSTAT3_CONTROL      0x04
  780 #define SF_RXSTAT3_PAUSE        0x08
  781 #define SF_RXSTAT3_ISL          0x10
  782 
  783 /*
  784  * Transmit descriptor formats.
  785  * Each transmit descriptor type allows for a skip field at the
  786  * start of each structure. The size of the skip field can vary,
  787  * however we always set it for 8 bytes, which is enough to hold
  788  * a pointer (32 bits on x86, 64-bits on alpha) that we can use
  789  * to hold the address of the head of the mbuf chain for the
  790  * frame or fragment associated with the descriptor. This saves
  791  * us from having to create a separate pointer array to hold
  792  * the mbuf addresses.
  793  */
  794 #define SF_TX_BUFDESC_ID                0xB
  795 #define SF_MAXFRAGS                     14
  796 #define SF_TX_MINSPACING                128
  797 #define SF_TX_DLIST_CNT                 128
  798 #define SF_TX_DLIST_SIZE                16384
  799 #define SF_TX_SKIPLEN                   1
  800 #define SF_TX_CLIST_CNT                 1024
  801 
  802 struct sf_frag {
  803         u_int32_t               sf_addr;
  804         u_int16_t               sf_fraglen;
  805         u_int16_t               sf_pktlen;
  806 };
  807 
  808 struct sf_frag_msdos {
  809         u_int16_t               sf_pktlen;
  810         u_int16_t               sf_fraglen;
  811         u_int32_t               sf_addr;
  812 };
  813 
  814 /*
  815  * TX frame descriptor type 0, 32-bit addressing. One descriptor can
  816  * be used to map multiple packet fragments. We use this format since
  817  * BSD networking fragments packet data across mbuf chains. Note that
  818  * the number of fragments can be variable depending on how the descriptor
  819  * spacing is specified in the TX descriptor queue control register.
  820  * We always use a spacing of 128 bytes, and a skipfield length of 8
  821  * bytes: this means 16 bytes for the descriptor, including the skipfield,
  822  * with 121 bytes left for fragment maps. Each fragment requires 8 bytes,
  823  * which allows for 14 fragments per descriptor. The total size of the
  824  * transmit buffer queue is limited to 16384 bytes, so with a spacing of
  825  * 128 bytes per descriptor, we have room for 128 descriptors in the queue.
  826  */
  827 struct sf_tx_bufdesc_type0 {
  828 #ifdef __i386__
  829         u_int32_t               sf_pad;
  830 #endif
  831         struct mbuf             *sf_mbuf;
  832         u_int32_t               sf_rsvd0:24,
  833                                 sf_crcen:1,
  834                                 sf_caltcp:1,
  835                                 sf_end:1,
  836                                 sf_intr:1,
  837                                 sf_id:4;
  838         u_int8_t                sf_fragcnt;
  839         u_int8_t                sf_rsvd2;
  840         u_int16_t               sf_rsvd1;
  841         struct sf_frag          sf_frags[14];
  842 };
  843 
  844 /*
  845  * TX buffer descriptor type 1, 32-bit addressing. Each descriptor
  846  * maps a single fragment.
  847  */
  848 struct sf_tx_bufdesc_type1 {
  849 #ifdef __i386__
  850         u_int32_t               sf_pad;
  851 #endif
  852         struct mbuf             *sf_mbuf;
  853         u_int32_t               sf_fraglen:16,
  854                                 sf_fragcnt:8,
  855                                 sf_crcen:1,
  856                                 sf_caltcp:1,
  857                                 sf_end:1,
  858                                 sf_intr:1,
  859                                 sf_id:4;
  860         u_int32_t               sf_addr;
  861 };
  862 
  863 /*
  864  * TX buffer descriptor type 2, 64-bit addressing. Each descriptor
  865  * maps a single fragment.
  866  */
  867 struct sf_tx_bufdesc_type2 {
  868 #ifdef __i386__
  869         u_int32_t               sf_pad;
  870 #endif
  871         struct mbuf             *sf_mbuf;
  872         u_int32_t               sf_fraglen:16,
  873                                 sf_fragcnt:8,
  874                                 sf_crcen:1,
  875                                 sf_caltcp:1,
  876                                 sf_end:1,
  877                                 sf_intr:1,
  878                                 sf_id:4;
  879         u_int32_t               sf_addrlo;
  880         u_int32_t               sf_addrhi;
  881 };
  882 
  883 /* TX buffer descriptor type 3 is not defined. */
  884 
  885 /*
  886  * TX frame descriptor type 4, 32-bit addressing. This is a special
  887  * case of the type 0 descriptor, identical except that the fragment
  888  * address and length fields are ordered differently. This is done
  889  * to optimize copies in MS-DOS and OS/2 drivers.
  890  */
  891 struct sf_tx_bufdesc_type4 {
  892 #ifdef __i386__
  893         u_int32_t               sf_pad;
  894 #endif
  895         struct mbuf             *sf_mbuf;
  896         u_int32_t               sf_rsvd0:24,
  897                                 sf_crcen:1,
  898                                 sf_caltcp:1,
  899                                 sf_end:1,
  900                                 sf_intr:1,
  901                                 sf_id:4;
  902         u_int8_t                sf_fragcnt;
  903         u_int8_t                sf_rsvd2;
  904         u_int16_t               sf_rsvd1;
  905         struct sf_frag_msdos    sf_frags[14];
  906 };
  907 
  908 /*
  909  * Transmit completion queue descriptor formats.
  910  */
  911 
  912 /*
  913  * Transmit DMA completion descriptor, type 0.
  914  */
  915 #define SF_TXCMPTYPE_DMA        0x4
  916 struct sf_tx_cmpdesc_type0 {
  917         u_int32_t               sf_index:15,
  918                                 sf_priority:1,
  919                                 sf_timestamp:13,
  920                                 sf_type:3;
  921 };
  922 
  923 /*
  924  * Transmit completion descriptor, type 1.
  925  */
  926 #define SF_TXCMPTYPE_TX         0x5
  927 struct sf_tx_cmpdesc_type1 {
  928         u_int32_t               sf_index:15,
  929                                 sf_priority:1,
  930                                 sf_txstat:13,
  931                                 sf_type:3;
  932 };
  933 
  934 #define SF_TXSTAT_CRCERR        0x0001
  935 #define SF_TXSTAT_LENCHECKERR   0x0002
  936 #define SF_TXSTAT_LENRANGEERR   0x0004
  937 #define SF_TXSTAT_TX_OK         0x0008
  938 #define SF_TXSTAT_TX_DEFERED    0x0010
  939 #define SF_TXSTAT_EXCESS_DEFER  0x0020
  940 #define SF_TXSTAT_EXCESS_COLL   0x0040
  941 #define SF_TXSTAT_LATE_COLL     0x0080
  942 #define SF_TXSTAT_TOOBIG        0x0100
  943 #define SF_TXSTAT_TX_UNDERRUN   0x0200
  944 #define SF_TXSTAT_CTLFRAME_OK   0x0400
  945 #define SF_TXSTAT_PAUSEFRAME_OK 0x0800
  946 #define SF_TXSTAT_PAUSED        0x1000
  947 
  948 /* Statistics counters. */
  949 struct sf_stats {
  950         u_int32_t               sf_tx_frames;
  951         u_int32_t               sf_tx_single_colls;
  952         u_int32_t               sf_tx_multi_colls;
  953         u_int32_t               sf_tx_crcerrs;
  954         u_int32_t               sf_tx_bytes;
  955         u_int32_t               sf_tx_defered;
  956         u_int32_t               sf_tx_late_colls;
  957         u_int32_t               sf_tx_pause_frames;
  958         u_int32_t               sf_tx_control_frames;
  959         u_int32_t               sf_tx_excess_colls;
  960         u_int32_t               sf_tx_excess_defer;
  961         u_int32_t               sf_tx_mcast_frames;
  962         u_int32_t               sf_tx_bcast_frames;
  963         u_int32_t               sf_tx_frames_lost;
  964         u_int32_t               sf_rx_rx_frames;
  965         u_int32_t               sf_rx_crcerrs;
  966         u_int32_t               sf_rx_alignerrs;
  967         u_int32_t               sf_rx_bytes;
  968         u_int32_t               sf_rx_control_frames;
  969         u_int32_t               sf_rx_unsup_control_frames;
  970         u_int32_t               sf_rx_giants;
  971         u_int32_t               sf_rx_runts;
  972         u_int32_t               sf_rx_jabbererrs;
  973         u_int32_t               sf_rx_pkts_64;
  974         u_int32_t               sf_rx_pkts_65_127;
  975         u_int32_t               sf_rx_pkts_128_255;
  976         u_int32_t               sf_rx_pkts_256_511;
  977         u_int32_t               sf_rx_pkts_512_1023;
  978         u_int32_t               sf_rx_pkts_1024_1518;
  979         u_int32_t               sf_rx_frames_lost;
  980         u_int16_t               sf_tx_underruns;
  981         u_int16_t               sf_pad;
  982 };
  983 
  984 /*
  985  * register space access macros
  986  */
  987 #define CSR_WRITE_4(sc, reg, val)       \
  988         bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val)
  989 
  990 #define CSR_READ_4(sc, reg)             \
  991         bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg)
  992 
  993 #define CSR_READ_1(sc, reg)             \
  994         bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg)
  995 
  996 
  997 struct sf_type {
  998         u_int16_t               sf_vid;
  999         u_int16_t               sf_did;
 1000         char                    *sf_name;
 1001 };
 1002 
 1003 #define SF_INC(x, y)    (x) = (x + 1) % y
 1004 
 1005 #define ETHER_ALIGN 2
 1006 
 1007 /*
 1008  * Note: alignment is important here: each list must be aligned to
 1009  * a 256-byte boundary. It turns out that each ring is some multiple
 1010  * of 4K in length, so we can stack them all on top of each other
 1011  * and just worry about aligning the whole mess. There's one transmit
 1012  * buffer ring and two receive buffer rings: one RX ring is for small
 1013  * packets and the other is for large packets. Each buffer ring also
 1014  * has a companion completion queue.
 1015  */
 1016 struct sf_list_data {
 1017         struct sf_tx_bufdesc_type0      sf_tx_dlist[SF_TX_DLIST_CNT];
 1018         struct sf_tx_cmpdesc_type1      sf_tx_clist[SF_TX_CLIST_CNT];
 1019         struct sf_rx_bufdesc_type0      sf_rx_dlist_big[SF_RX_DLIST_CNT];
 1020 #ifdef notdef
 1021         /*
 1022          * Unfortunately, because the Starfire doesn't allow arbitrary
 1023          * byte alignment, we have to copy packets in the RX handler in
 1024          * order to align the payload correctly. This means that we
 1025          * don't gain anything by having separate large and small descriptor
 1026          * lists, so for now we don't bother with the small one.
 1027          */
 1028         struct sf_rx_bufdesc_type0      sf_rx_dlist_small[SF_RX_DLIST_CNT];
 1029 #endif
 1030         struct sf_rx_cmpdesc_type3      sf_rx_clist[SF_RX_CLIST_CNT];
 1031 };
 1032 
 1033 struct sf_softc {
 1034         struct ifnet            *sf_ifp;        /* interface info */
 1035         device_t                sf_dev;         /* device info */
 1036         bus_space_handle_t      sf_bhandle;     /* bus space handle */
 1037         bus_space_tag_t         sf_btag;        /* bus space tag */
 1038         void                    *sf_intrhand;   /* interrupt handler cookie */
 1039         struct resource         *sf_irq;        /* irq resource descriptor */
 1040         struct resource         *sf_res;        /* mem/ioport resource */
 1041         struct sf_type          *sf_info;       /* Starfire adapter info */
 1042         device_t                sf_miibus;
 1043         struct sf_list_data     *sf_ldata;
 1044         int                     sf_tx_cnt;
 1045         u_int8_t                sf_link;
 1046         int                     sf_if_flags;
 1047         struct callout          sf_stat_callout;
 1048         struct mtx              sf_mtx;
 1049 #ifdef DEVICE_POLLING
 1050         int                     rxcycles;
 1051 #endif /* DEVICE_POLLING */
 1052 };
 1053 
 1054 
 1055 #define SF_LOCK(_sc)            mtx_lock(&(_sc)->sf_mtx)
 1056 #define SF_UNLOCK(_sc)          mtx_unlock(&(_sc)->sf_mtx)
 1057 #define SF_LOCK_ASSERT(_sc)     mtx_assert(&(_sc)->sf_mtx, MA_OWNED)
 1058 
 1059 #define SF_TIMEOUT      1000

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