Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sis.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/sysctl.h> 68 69 #include <net/if.h> 70 #include <net/if_arp.h> 71 #include <net/ethernet.h> 72 #include <net/if_dl.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_vlan_var.h> 76 77 #include <net/bpf.h> 78 79 #include <vm/vm.h> /* for vtophys */ 80 #include <vm/pmap.h> /* for vtophys */ 81 #include <machine/clock.h> /* for DELAY */ 82 #include <machine/bus_pio.h> 83 #include <machine/bus_memio.h> 84 #include <machine/bus.h> 85 #include <machine/resource.h> 86 #include <sys/bus.h> 87 #include <sys/rman.h> 88 89 #include <dev/mii/mii.h> 90 #include <dev/mii/miivar.h> 91 92 #include <pci/pcireg.h> 93 #include <pci/pcivar.h> 94 95 #define SIS_USEIOSPACE 96 97 #include <pci/if_sisreg.h> 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 #ifndef lint 103 static const char rcsid[] = 104 "$FreeBSD$"; 105 #endif 106 107 /* 108 * Various supported device vendors/types and their names. 109 */ 110 static struct sis_type sis_devs[] = { 111 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 112 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 113 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 114 { 0, 0, NULL } 115 }; 116 117 static int sis_probe __P((device_t)); 118 static int sis_attach __P((device_t)); 119 static int sis_detach __P((device_t)); 120 121 static int sis_newbuf __P((struct sis_softc *, 122 struct sis_desc *, 123 struct mbuf *)); 124 static int sis_encap __P((struct sis_softc *, 125 struct mbuf **, u_int32_t *)); 126 static void sis_rxeof __P((struct sis_softc *)); 127 static void sis_rxeoc __P((struct sis_softc *)); 128 static void sis_txeof __P((struct sis_softc *)); 129 static void sis_intr __P((void *)); 130 static void sis_tick __P((void *)); 131 static void sis_start __P((struct ifnet *)); 132 static int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 133 static void sis_init __P((void *)); 134 static void sis_stop __P((struct sis_softc *)); 135 static void sis_watchdog __P((struct ifnet *)); 136 static void sis_shutdown __P((device_t)); 137 static int sis_ifmedia_upd __P((struct ifnet *)); 138 static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 139 140 static u_int16_t sis_reverse __P((u_int16_t)); 141 static void sis_delay __P((struct sis_softc *)); 142 static void sis_eeprom_idle __P((struct sis_softc *)); 143 static void sis_eeprom_putbyte __P((struct sis_softc *, int)); 144 static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 145 static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, 146 int, int)); 147 #ifdef __i386__ 148 static void sis_read_cmos __P((struct sis_softc *, device_t, caddr_t, 149 int, int)); 150 static void sis_read_mac __P((struct sis_softc *, device_t, caddr_t)); 151 static device_t sis_find_bridge __P((device_t)); 152 #endif 153 154 static void sis_mii_sync __P((struct sis_softc *)); 155 static void sis_mii_send __P((struct sis_softc *, u_int32_t, int)); 156 static int sis_mii_readreg __P((struct sis_softc *, struct sis_mii_frame *)); 157 static int sis_mii_writereg __P((struct sis_softc *, struct sis_mii_frame *)); 158 static int sis_miibus_readreg __P((device_t, int, int)); 159 static int sis_miibus_writereg __P((device_t, int, int, int)); 160 static void sis_miibus_statchg __P((device_t)); 161 162 static void sis_setmulti_sis __P((struct sis_softc *)); 163 static void sis_setmulti_ns __P((struct sis_softc *)); 164 static u_int32_t sis_crc __P((struct sis_softc *, caddr_t)); 165 static void sis_reset __P((struct sis_softc *)); 166 static int sis_list_rx_init __P((struct sis_softc *)); 167 static int sis_list_tx_init __P((struct sis_softc *)); 168 169 #ifdef SIS_USEIOSPACE 170 #define SIS_RES SYS_RES_IOPORT 171 #define SIS_RID SIS_PCI_LOIO 172 #else 173 #define SIS_RES SYS_RES_MEMORY 174 #define SIS_RID SIS_PCI_LOMEM 175 #endif 176 177 static device_method_t sis_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, sis_probe), 180 DEVMETHOD(device_attach, sis_attach), 181 DEVMETHOD(device_detach, sis_detach), 182 DEVMETHOD(device_shutdown, sis_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 190 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 191 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 192 193 { 0, 0 } 194 }; 195 196 static driver_t sis_driver = { 197 "sis", 198 sis_methods, 199 sizeof(struct sis_softc) 200 }; 201 202 static devclass_t sis_devclass; 203 204 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 205 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 206 207 #define SIS_SETBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, \ 209 CSR_READ_4(sc, reg) | (x)) 210 211 #define SIS_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_4(sc, reg, \ 213 CSR_READ_4(sc, reg) & ~(x)) 214 215 #define SIO_SET(x) \ 216 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 217 218 #define SIO_CLR(x) \ 219 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 220 221 /* 222 * Routine to reverse the bits in a word. Stolen almost 223 * verbatim from /usr/games/fortune. 224 */ 225 static u_int16_t sis_reverse(n) 226 u_int16_t n; 227 { 228 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 229 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 230 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 231 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 232 233 return(n); 234 } 235 236 static void sis_delay(sc) 237 struct sis_softc *sc; 238 { 239 int idx; 240 241 for (idx = (300 / 33) + 1; idx > 0; idx--) 242 CSR_READ_4(sc, SIS_CSR); 243 244 return; 245 } 246 247 static void sis_eeprom_idle(sc) 248 struct sis_softc *sc; 249 { 250 register int i; 251 252 SIO_SET(SIS_EECTL_CSEL); 253 sis_delay(sc); 254 SIO_SET(SIS_EECTL_CLK); 255 sis_delay(sc); 256 257 for (i = 0; i < 25; i++) { 258 SIO_CLR(SIS_EECTL_CLK); 259 sis_delay(sc); 260 SIO_SET(SIS_EECTL_CLK); 261 sis_delay(sc); 262 } 263 264 SIO_CLR(SIS_EECTL_CLK); 265 sis_delay(sc); 266 SIO_CLR(SIS_EECTL_CSEL); 267 sis_delay(sc); 268 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 269 270 return; 271 } 272 273 /* 274 * Send a read command and address to the EEPROM, check for ACK. 275 */ 276 static void sis_eeprom_putbyte(sc, addr) 277 struct sis_softc *sc; 278 int addr; 279 { 280 register int d, i; 281 282 d = addr | SIS_EECMD_READ; 283 284 /* 285 * Feed in each bit and stobe the clock. 286 */ 287 for (i = 0x400; i; i >>= 1) { 288 if (d & i) { 289 SIO_SET(SIS_EECTL_DIN); 290 } else { 291 SIO_CLR(SIS_EECTL_DIN); 292 } 293 sis_delay(sc); 294 SIO_SET(SIS_EECTL_CLK); 295 sis_delay(sc); 296 SIO_CLR(SIS_EECTL_CLK); 297 sis_delay(sc); 298 } 299 300 return; 301 } 302 303 /* 304 * Read a word of data stored in the EEPROM at address 'addr.' 305 */ 306 static void sis_eeprom_getword(sc, addr, dest) 307 struct sis_softc *sc; 308 int addr; 309 u_int16_t *dest; 310 { 311 register int i; 312 u_int16_t word = 0; 313 314 /* Force EEPROM to idle state. */ 315 sis_eeprom_idle(sc); 316 317 /* Enter EEPROM access mode. */ 318 sis_delay(sc); 319 SIO_CLR(SIS_EECTL_CLK); 320 sis_delay(sc); 321 SIO_SET(SIS_EECTL_CSEL); 322 sis_delay(sc); 323 324 /* 325 * Send address of word we want to read. 326 */ 327 sis_eeprom_putbyte(sc, addr); 328 329 /* 330 * Start reading bits from EEPROM. 331 */ 332 for (i = 0x8000; i; i >>= 1) { 333 SIO_SET(SIS_EECTL_CLK); 334 sis_delay(sc); 335 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 336 word |= i; 337 sis_delay(sc); 338 SIO_CLR(SIS_EECTL_CLK); 339 sis_delay(sc); 340 } 341 342 /* Turn off EEPROM access mode. */ 343 sis_eeprom_idle(sc); 344 345 *dest = word; 346 347 return; 348 } 349 350 /* 351 * Read a sequence of words from the EEPROM. 352 */ 353 static void sis_read_eeprom(sc, dest, off, cnt, swap) 354 struct sis_softc *sc; 355 caddr_t dest; 356 int off; 357 int cnt; 358 int swap; 359 { 360 int i; 361 u_int16_t word = 0, *ptr; 362 363 for (i = 0; i < cnt; i++) { 364 sis_eeprom_getword(sc, off + i, &word); 365 ptr = (u_int16_t *)(dest + (i * 2)); 366 if (swap) 367 *ptr = ntohs(word); 368 else 369 *ptr = word; 370 } 371 372 return; 373 } 374 375 #ifdef __i386__ 376 static device_t sis_find_bridge(dev) 377 device_t dev; 378 { 379 devclass_t pci_devclass; 380 device_t *pci_devices; 381 int pci_count = 0; 382 device_t *pci_children; 383 int pci_childcount = 0; 384 device_t *busp, *childp; 385 device_t child = NULL; 386 int i, j; 387 388 if ((pci_devclass = devclass_find("pci")) == NULL) 389 return(NULL); 390 391 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 392 393 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 394 pci_childcount = 0; 395 device_get_children(*busp, &pci_children, &pci_childcount); 396 for (j = 0, childp = pci_children; 397 j < pci_childcount; j++, childp++) { 398 if (pci_get_vendor(*childp) == SIS_VENDORID && 399 pci_get_device(*childp) == 0x0008) { 400 child = *childp; 401 goto done; 402 } 403 } 404 } 405 406 done: 407 free(pci_devices, M_TEMP); 408 free(pci_children, M_TEMP); 409 return(child); 410 } 411 412 static void sis_read_cmos(sc, dev, dest, off, cnt) 413 struct sis_softc *sc; 414 device_t dev; 415 caddr_t dest; 416 int off; 417 int cnt; 418 { 419 device_t bridge; 420 u_int8_t reg; 421 int i; 422 bus_space_tag_t btag; 423 424 bridge = sis_find_bridge(dev); 425 if (bridge == NULL) 426 return; 427 reg = pci_read_config(bridge, 0x48, 1); 428 pci_write_config(bridge, 0x48, reg|0x40, 1); 429 430 /* XXX */ 431 btag = I386_BUS_SPACE_IO; 432 433 for (i = 0; i < cnt; i++) { 434 bus_space_write_1(btag, 0x0, 0x70, i + off); 435 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 436 } 437 438 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 439 return; 440 } 441 442 static void sis_read_mac(sc, dev, dest) 443 struct sis_softc *sc; 444 device_t dev; 445 caddr_t dest; 446 { 447 u_int32_t filtsave, csrsave; 448 449 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 450 csrsave = CSR_READ_4(sc, SIS_CSR); 451 452 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 453 CSR_WRITE_4(sc, SIS_CSR, 0); 454 455 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 456 457 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 458 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 459 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 460 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 461 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 462 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 463 464 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 465 CSR_WRITE_4(sc, SIS_CSR, csrsave); 466 return; 467 } 468 #endif 469 470 /* 471 * Sync the PHYs by setting data bit and strobing the clock 32 times. 472 */ 473 static void sis_mii_sync(sc) 474 struct sis_softc *sc; 475 { 476 register int i; 477 478 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 479 480 for (i = 0; i < 32; i++) { 481 SIO_SET(SIS_MII_CLK); 482 DELAY(1); 483 SIO_CLR(SIS_MII_CLK); 484 DELAY(1); 485 } 486 487 return; 488 } 489 490 /* 491 * Clock a series of bits through the MII. 492 */ 493 static void sis_mii_send(sc, bits, cnt) 494 struct sis_softc *sc; 495 u_int32_t bits; 496 int cnt; 497 { 498 int i; 499 500 SIO_CLR(SIS_MII_CLK); 501 502 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 503 if (bits & i) { 504 SIO_SET(SIS_MII_DATA); 505 } else { 506 SIO_CLR(SIS_MII_DATA); 507 } 508 DELAY(1); 509 SIO_CLR(SIS_MII_CLK); 510 DELAY(1); 511 SIO_SET(SIS_MII_CLK); 512 } 513 } 514 515 /* 516 * Read an PHY register through the MII. 517 */ 518 static int sis_mii_readreg(sc, frame) 519 struct sis_softc *sc; 520 struct sis_mii_frame *frame; 521 522 { 523 int i, ack, s; 524 525 s = splimp(); 526 527 /* 528 * Set up frame for RX. 529 */ 530 frame->mii_stdelim = SIS_MII_STARTDELIM; 531 frame->mii_opcode = SIS_MII_READOP; 532 frame->mii_turnaround = 0; 533 frame->mii_data = 0; 534 535 /* 536 * Turn on data xmit. 537 */ 538 SIO_SET(SIS_MII_DIR); 539 540 sis_mii_sync(sc); 541 542 /* 543 * Send command/address info. 544 */ 545 sis_mii_send(sc, frame->mii_stdelim, 2); 546 sis_mii_send(sc, frame->mii_opcode, 2); 547 sis_mii_send(sc, frame->mii_phyaddr, 5); 548 sis_mii_send(sc, frame->mii_regaddr, 5); 549 550 /* Idle bit */ 551 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 552 DELAY(1); 553 SIO_SET(SIS_MII_CLK); 554 DELAY(1); 555 556 /* Turn off xmit. */ 557 SIO_CLR(SIS_MII_DIR); 558 559 /* Check for ack */ 560 SIO_CLR(SIS_MII_CLK); 561 DELAY(1); 562 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 563 SIO_SET(SIS_MII_CLK); 564 DELAY(1); 565 566 /* 567 * Now try reading data bits. If the ack failed, we still 568 * need to clock through 16 cycles to keep the PHY(s) in sync. 569 */ 570 if (ack) { 571 for(i = 0; i < 16; i++) { 572 SIO_CLR(SIS_MII_CLK); 573 DELAY(1); 574 SIO_SET(SIS_MII_CLK); 575 DELAY(1); 576 } 577 goto fail; 578 } 579 580 for (i = 0x8000; i; i >>= 1) { 581 SIO_CLR(SIS_MII_CLK); 582 DELAY(1); 583 if (!ack) { 584 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 585 frame->mii_data |= i; 586 DELAY(1); 587 } 588 SIO_SET(SIS_MII_CLK); 589 DELAY(1); 590 } 591 592 fail: 593 594 SIO_CLR(SIS_MII_CLK); 595 DELAY(1); 596 SIO_SET(SIS_MII_CLK); 597 DELAY(1); 598 599 splx(s); 600 601 if (ack) 602 return(1); 603 return(0); 604 } 605 606 /* 607 * Write to a PHY register through the MII. 608 */ 609 static int sis_mii_writereg(sc, frame) 610 struct sis_softc *sc; 611 struct sis_mii_frame *frame; 612 613 { 614 int s; 615 616 s = splimp(); 617 /* 618 * Set up frame for TX. 619 */ 620 621 frame->mii_stdelim = SIS_MII_STARTDELIM; 622 frame->mii_opcode = SIS_MII_WRITEOP; 623 frame->mii_turnaround = SIS_MII_TURNAROUND; 624 625 /* 626 * Turn on data output. 627 */ 628 SIO_SET(SIS_MII_DIR); 629 630 sis_mii_sync(sc); 631 632 sis_mii_send(sc, frame->mii_stdelim, 2); 633 sis_mii_send(sc, frame->mii_opcode, 2); 634 sis_mii_send(sc, frame->mii_phyaddr, 5); 635 sis_mii_send(sc, frame->mii_regaddr, 5); 636 sis_mii_send(sc, frame->mii_turnaround, 2); 637 sis_mii_send(sc, frame->mii_data, 16); 638 639 /* Idle bit. */ 640 SIO_SET(SIS_MII_CLK); 641 DELAY(1); 642 SIO_CLR(SIS_MII_CLK); 643 DELAY(1); 644 645 /* 646 * Turn off xmit. 647 */ 648 SIO_CLR(SIS_MII_DIR); 649 650 splx(s); 651 652 return(0); 653 } 654 655 static int sis_miibus_readreg(dev, phy, reg) 656 device_t dev; 657 int phy, reg; 658 { 659 struct sis_softc *sc; 660 int i, val = 0; 661 struct sis_mii_frame frame; 662 663 sc = device_get_softc(dev); 664 665 if (sc->sis_type == SIS_TYPE_83815) { 666 if (phy != 0) 667 return(0); 668 /* 669 * The NatSemi chip can take a while after 670 * a reset to come ready, during which the BMSR 671 * returns a value of 0. This is *never* supposed 672 * to happen: some of the BMSR bits are meant to 673 * be hardwired in the on position, and this can 674 * confuse the miibus code a bit during the probe 675 * and attach phase. So we make an effort to check 676 * for this condition and wait for it to clear. 677 */ 678 if (!CSR_READ_4(sc, NS_BMSR)) 679 DELAY(1000); 680 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 681 } 682 /* 683 * Chipsets < SIS_635 seem not to be able to read/write 684 * through mdio. Use the enhanced PHY access register 685 * again for them. 686 */ 687 if (sc->sis_type == SIS_TYPE_900 && 688 sc->sis_rev < SIS_REV_635) { 689 690 if (phy != 0) 691 return(0); 692 693 CSR_WRITE_4(sc, SIS_PHYCTL, 694 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 695 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 696 697 for (i = 0; i < SIS_TIMEOUT; i++) { 698 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 699 break; 700 } 701 702 if (i == SIS_TIMEOUT) { 703 printf("sis%d: PHY failed to come ready\n", 704 sc->sis_unit); 705 return(0); 706 } 707 708 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 709 710 if (val == 0xFFFF) 711 return(0); 712 713 return(val); 714 } else { 715 bzero((char *)&frame, sizeof(frame)); 716 frame.mii_phyaddr = phy; 717 frame.mii_regaddr = reg; 718 sis_mii_readreg(sc, &frame); 719 return(frame.mii_data); 720 } 721 } 722 723 static int sis_miibus_writereg(dev, phy, reg, data) 724 device_t dev; 725 int phy, reg, data; 726 { 727 struct sis_softc *sc; 728 int i; 729 struct sis_mii_frame frame; 730 731 sc = device_get_softc(dev); 732 733 if (sc->sis_type == SIS_TYPE_83815) { 734 if (phy != 0) 735 return(0); 736 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 737 return(0); 738 } 739 740 if (sc->sis_type == SIS_TYPE_900 && 741 sc->sis_rev < SIS_REV_635) { 742 743 if (phy != 0) 744 return(0); 745 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 746 (reg << 6) | SIS_PHYOP_WRITE); 747 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 748 749 for (i = 0; i < SIS_TIMEOUT; i++) { 750 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 751 break; 752 } 753 754 if (i == SIS_TIMEOUT) 755 printf("sis%d: PHY failed to come ready\n", 756 sc->sis_unit); 757 } else { 758 bzero((char *)&frame, sizeof(frame)); 759 760 frame.mii_phyaddr = phy; 761 frame.mii_regaddr = reg; 762 frame.mii_data = data; 763 sis_mii_writereg(sc, &frame); 764 } 765 return(0); 766 } 767 768 static void sis_miibus_statchg(dev) 769 device_t dev; 770 { 771 struct sis_softc *sc; 772 773 sc = device_get_softc(dev); 774 sis_init(sc); 775 776 return; 777 } 778 779 static u_int32_t sis_crc(sc, addr) 780 struct sis_softc *sc; 781 caddr_t addr; 782 { 783 u_int32_t crc, carry; 784 int i, j; 785 u_int8_t c; 786 787 /* Compute CRC for the address value. */ 788 crc = 0xFFFFFFFF; /* initial value */ 789 790 for (i = 0; i < 6; i++) { 791 c = *(addr + i); 792 for (j = 0; j < 8; j++) { 793 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 794 crc <<= 1; 795 c >>= 1; 796 if (carry) 797 crc = (crc ^ 0x04c11db6) | carry; 798 } 799 } 800 801 /* 802 * return the filter bit position 803 * 804 * The NatSemi chip has a 512-bit filter, which is 805 * different than the SiS, so we special-case it. 806 */ 807 if (sc->sis_type == SIS_TYPE_83815) 808 return (crc >> 23); 809 else if (sc->sis_rev >= SIS_REV_635 || 810 sc->sis_rev == SIS_REV_900B) 811 return (crc >> 24); 812 else 813 return (crc >> 25); 814 } 815 816 static void sis_setmulti_ns(sc) 817 struct sis_softc *sc; 818 { 819 struct ifnet *ifp; 820 struct ifmultiaddr *ifma; 821 u_int32_t h = 0, i, filtsave; 822 int bit, index; 823 824 ifp = &sc->arpcom.ac_if; 825 826 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 827 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 828 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 829 return; 830 } 831 832 /* 833 * We have to explicitly enable the multicast hash table 834 * on the NatSemi chip if we want to use it, which we do. 835 */ 836 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 837 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 838 839 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 840 841 /* first, zot all the existing hash bits */ 842 for (i = 0; i < 32; i++) { 843 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 844 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 845 } 846 847 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 848 ifma = ifma->ifma_link.le_next) { 849 if (ifma->ifma_addr->sa_family != AF_LINK) 850 continue; 851 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 852 index = h >> 3; 853 bit = h & 0x1F; 854 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 855 if (bit > 0xF) 856 bit -= 0x10; 857 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 858 } 859 860 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 861 862 return; 863 } 864 865 static void sis_setmulti_sis(sc) 866 struct sis_softc *sc; 867 { 868 struct ifnet *ifp; 869 struct ifmultiaddr *ifma; 870 u_int32_t h, i, n, ctl; 871 u_int16_t hashes[16]; 872 873 ifp = &sc->arpcom.ac_if; 874 875 /* hash table size */ 876 if (sc->sis_rev >= SIS_REV_635 || 877 sc->sis_rev == SIS_REV_900B) 878 n = 16; 879 else 880 n = 8; 881 882 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 883 884 if (ifp->if_flags & IFF_BROADCAST) 885 ctl |= SIS_RXFILTCTL_BROAD; 886 887 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 888 ctl |= SIS_RXFILTCTL_ALLMULTI; 889 if (ifp->if_flags & IFF_PROMISC) 890 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 891 for (i = 0; i < n; i++) 892 hashes[i] = ~0; 893 } else { 894 for (i = 0; i < n; i++) 895 hashes[i] = 0; 896 i = 0; 897 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 898 if (ifma->ifma_addr->sa_family != AF_LINK) 899 continue; 900 h = sis_crc(sc, 901 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 902 hashes[h >> 4] |= 1 << (h & 0xf); 903 i++; 904 } 905 if (i > n) { 906 ctl |= SIS_RXFILTCTL_ALLMULTI; 907 for (i = 0; i < n; i++) 908 hashes[i] = ~0; 909 } 910 } 911 912 for (i = 0; i < n; i++) { 913 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 914 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 915 } 916 917 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 918 } 919 920 static void sis_reset(sc) 921 struct sis_softc *sc; 922 { 923 register int i; 924 925 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 926 927 for (i = 0; i < SIS_TIMEOUT; i++) { 928 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 929 break; 930 } 931 932 if (i == SIS_TIMEOUT) 933 printf("sis%d: reset never completed\n", sc->sis_unit); 934 935 /* Wait a little while for the chip to get its brains in order. */ 936 DELAY(1000); 937 938 /* 939 * If this is a NetSemi chip, make sure to clear 940 * PME mode. 941 */ 942 if (sc->sis_type == SIS_TYPE_83815) { 943 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 944 CSR_WRITE_4(sc, NS_CLKRUN, 0); 945 } 946 947 return; 948 } 949 950 /* 951 * Probe for an SiS chip. Check the PCI vendor and device 952 * IDs against our list and return a device name if we find a match. 953 */ 954 static int sis_probe(dev) 955 device_t dev; 956 { 957 struct sis_type *t; 958 959 t = sis_devs; 960 961 while(t->sis_name != NULL) { 962 if ((pci_get_vendor(dev) == t->sis_vid) && 963 (pci_get_device(dev) == t->sis_did)) { 964 device_set_desc(dev, t->sis_name); 965 return(0); 966 } 967 t++; 968 } 969 970 return(ENXIO); 971 } 972 973 /* 974 * Attach the interface. Allocate softc structures, do ifmedia 975 * setup and ethernet/BPF attach. 976 */ 977 static int sis_attach(dev) 978 device_t dev; 979 { 980 int s; 981 u_char eaddr[ETHER_ADDR_LEN]; 982 u_int32_t command; 983 struct sis_softc *sc; 984 struct ifnet *ifp; 985 int unit, error, rid, waittime; 986 987 s = splimp(); 988 989 error = waittime = 0; 990 sc = device_get_softc(dev); 991 unit = device_get_unit(dev); 992 bzero(sc, sizeof(struct sis_softc)); 993 994 if (pci_get_device(dev) == SIS_DEVICEID_900) 995 sc->sis_type = SIS_TYPE_900; 996 if (pci_get_device(dev) == SIS_DEVICEID_7016) 997 sc->sis_type = SIS_TYPE_7016; 998 if (pci_get_vendor(dev) == NS_VENDORID) 999 sc->sis_type = SIS_TYPE_83815; 1000 1001 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1002 1003 /* 1004 * Handle power management nonsense. 1005 */ 1006 1007 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 1008 if (command == 0x01) { 1009 1010 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 1011 if (command & SIS_PSTATE_MASK) { 1012 u_int32_t iobase, membase, irq; 1013 1014 /* Save important PCI config data. */ 1015 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 1016 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 1017 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 1018 1019 /* Reset the power state. */ 1020 printf("sis%d: chip is in D%d power mode " 1021 "-- setting to D0\n", unit, command & SIS_PSTATE_MASK); 1022 command &= 0xFFFFFFFC; 1023 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 1024 1025 /* Restore PCI config data. */ 1026 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1027 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1028 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1029 } 1030 } 1031 1032 /* 1033 * Map control/status registers. 1034 */ 1035 command = pci_read_config(dev, PCIR_COMMAND, 4); 1036 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1037 pci_write_config(dev, PCIR_COMMAND, command, 4); 1038 command = pci_read_config(dev, PCIR_COMMAND, 4); 1039 1040 #ifdef SIS_USEIOSPACE 1041 if (!(command & PCIM_CMD_PORTEN)) { 1042 printf("sis%d: failed to enable I/O ports!\n", unit); 1043 error = ENXIO;; 1044 goto fail; 1045 } 1046 #else 1047 if (!(command & PCIM_CMD_MEMEN)) { 1048 printf("sis%d: failed to enable memory mapping!\n", unit); 1049 error = ENXIO;; 1050 goto fail; 1051 } 1052 #endif 1053 1054 rid = SIS_RID; 1055 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1056 0, ~0, 1, RF_ACTIVE); 1057 1058 if (sc->sis_res == NULL) { 1059 printf("sis%d: couldn't map ports/memory\n", unit); 1060 error = ENXIO; 1061 goto fail; 1062 } 1063 1064 sc->sis_btag = rman_get_bustag(sc->sis_res); 1065 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1066 1067 /* Allocate interrupt */ 1068 rid = 0; 1069 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1070 RF_SHAREABLE | RF_ACTIVE); 1071 1072 if (sc->sis_irq == NULL) { 1073 printf("sis%d: couldn't map interrupt\n", unit); 1074 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1075 error = ENXIO; 1076 goto fail; 1077 } 1078 1079 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1080 sis_intr, sc, &sc->sis_intrhand); 1081 1082 if (error) { 1083 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1084 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1085 printf("sis%d: couldn't set up irq\n", unit); 1086 goto fail; 1087 } 1088 1089 /* Reset the adapter. */ 1090 sis_reset(sc); 1091 1092 if (sc->sis_type == SIS_TYPE_900 && 1093 (sc->sis_rev == SIS_REV_635 || 1094 sc->sis_rev == SIS_REV_900B)) { 1095 SIO_SET(SIS_CFG_RND_CNT); 1096 SIO_SET(SIS_CFG_PERR_DETECT); 1097 } 1098 1099 /* 1100 * Get station address from the EEPROM. 1101 */ 1102 switch (pci_get_vendor(dev)) { 1103 case NS_VENDORID: 1104 /* 1105 * Reading the MAC address out of the EEPROM on 1106 * the NatSemi chip takes a bit more work than 1107 * you'd expect. The address spans 4 16-bit words, 1108 * with the first word containing only a single bit. 1109 * You have to shift everything over one bit to 1110 * get it aligned properly. Also, the bits are 1111 * stored backwards (the LSB is really the MSB, 1112 * and so on) so you have to reverse them in order 1113 * to get the MAC address into the form we want. 1114 * Why? Who the hell knows. 1115 */ 1116 { 1117 u_int16_t tmp[4]; 1118 1119 sis_read_eeprom(sc, (caddr_t)&tmp, 1120 NS_EE_NODEADDR, 4, 0); 1121 1122 /* Shift everything over one bit. */ 1123 tmp[3] = tmp[3] >> 1; 1124 tmp[3] |= tmp[2] << 15; 1125 tmp[2] = tmp[2] >> 1; 1126 tmp[2] |= tmp[1] << 15; 1127 tmp[1] = tmp[1] >> 1; 1128 tmp[1] |= tmp[0] << 15; 1129 1130 /* Now reverse all the bits. */ 1131 tmp[3] = sis_reverse(tmp[3]); 1132 tmp[2] = sis_reverse(tmp[2]); 1133 tmp[1] = sis_reverse(tmp[1]); 1134 1135 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1136 } 1137 break; 1138 case SIS_VENDORID: 1139 default: 1140 #ifdef __i386__ 1141 /* 1142 * If this is a SiS 630E chipset with an embedded 1143 * SiS 900 controller, we have to read the MAC address 1144 * from the APC CMOS RAM. Our method for doing this 1145 * is very ugly since we have to reach out and grab 1146 * ahold of hardware for which we cannot properly 1147 * allocate resources. This code is only compiled on 1148 * the i386 architecture since the SiS 630E chipset 1149 * is for x86 motherboards only. Note that there are 1150 * a lot of magic numbers in this hack. These are 1151 * taken from SiS's Linux driver. I'd like to replace 1152 * them with proper symbolic definitions, but that 1153 * requires some datasheets that I don't have access 1154 * to at the moment. 1155 */ 1156 if (sc->sis_rev == SIS_REV_630S || 1157 sc->sis_rev == SIS_REV_630E || 1158 sc->sis_rev == SIS_REV_630EA1) 1159 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1160 1161 else if (sc->sis_rev == SIS_REV_635 || 1162 sc->sis_rev == SIS_REV_630ET) 1163 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1164 else if (sc->sis_rev == SIS_REV_96x) { 1165 /* 1166 * Allow to read EEPROM from LAN. It is shared 1167 * between a 1394 controller and the NIC and each 1168 * time we access it, we need to set SIS_EECMD_REQ. 1169 */ 1170 SIO_SET(SIS_EECMD_REQ); 1171 for (waittime = 0; waittime < SIS_TIMEOUT; 1172 waittime++) { 1173 /* Force EEPROM to idle state. */ 1174 sis_eeprom_idle(sc); 1175 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1176 sis_read_eeprom(sc, (caddr_t)&eaddr, 1177 SIS_EE_NODEADDR, 3, 0); 1178 break; 1179 } 1180 DELAY(1); 1181 } 1182 /* 1183 * Set SIS_EECTL_CLK to high, so a other master 1184 * can operate on the i2c bus. 1185 */ 1186 SIO_SET(SIS_EECTL_CLK); 1187 /* Refuse EEPROM access by LAN */ 1188 SIO_SET(SIS_EECMD_DONE); 1189 } else 1190 #endif 1191 sis_read_eeprom(sc, (caddr_t)&eaddr, 1192 SIS_EE_NODEADDR, 3, 0); 1193 break; 1194 } 1195 1196 /* 1197 * A SiS chip was detected. Inform the world. 1198 */ 1199 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1200 1201 sc->sis_unit = unit; 1202 callout_handle_init(&sc->sis_stat_ch); 1203 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1204 1205 sc->sis_ldata = contigmalloc(sizeof(struct sis_list_data), M_DEVBUF, 1206 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1207 1208 if (sc->sis_ldata == NULL) { 1209 printf("sis%d: no memory for list buffers!\n", unit); 1210 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1211 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1212 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1213 error = ENXIO; 1214 goto fail; 1215 } 1216 bzero(sc->sis_ldata, sizeof(struct sis_list_data)); 1217 1218 ifp = &sc->arpcom.ac_if; 1219 ifp->if_softc = sc; 1220 ifp->if_unit = unit; 1221 ifp->if_name = "sis"; 1222 ifp->if_mtu = ETHERMTU; 1223 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1224 ifp->if_ioctl = sis_ioctl; 1225 ifp->if_output = ether_output; 1226 ifp->if_start = sis_start; 1227 ifp->if_watchdog = sis_watchdog; 1228 ifp->if_init = sis_init; 1229 ifp->if_baudrate = 10000000; 1230 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1231 1232 /* 1233 * Do MII setup. 1234 */ 1235 if (mii_phy_probe(dev, &sc->sis_miibus, 1236 sis_ifmedia_upd, sis_ifmedia_sts)) { 1237 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1238 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), 1239 M_DEVBUF); 1240 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1241 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1242 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1243 error = ENXIO; 1244 goto fail; 1245 } 1246 1247 /* 1248 * Call MI attach routine. 1249 */ 1250 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1251 1252 /* 1253 * Tell the upper layer(s) we support long frames. 1254 */ 1255 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1256 1257 #ifdef DEVICE_POLLING 1258 ifp->if_capabilities |= IFCAP_POLLING; 1259 #endif 1260 ifp->if_capenable = ifp->if_capabilities; 1261 1262 callout_handle_init(&sc->sis_stat_ch); 1263 1264 fail: 1265 splx(s); 1266 return(error); 1267 } 1268 1269 static int sis_detach(dev) 1270 device_t dev; 1271 { 1272 struct sis_softc *sc; 1273 struct ifnet *ifp; 1274 int s; 1275 1276 s = splimp(); 1277 1278 sc = device_get_softc(dev); 1279 ifp = &sc->arpcom.ac_if; 1280 1281 sis_reset(sc); 1282 sis_stop(sc); 1283 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1284 1285 bus_generic_detach(dev); 1286 device_delete_child(dev, sc->sis_miibus); 1287 1288 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1289 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1290 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1291 1292 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), M_DEVBUF); 1293 1294 splx(s); 1295 1296 return(0); 1297 } 1298 1299 /* 1300 * Initialize the transmit descriptors. 1301 */ 1302 static int sis_list_tx_init(sc) 1303 struct sis_softc *sc; 1304 { 1305 struct sis_list_data *ld; 1306 struct sis_ring_data *cd; 1307 int i, nexti; 1308 1309 cd = &sc->sis_cdata; 1310 ld = sc->sis_ldata; 1311 1312 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1313 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1314 ld->sis_tx_list[i].sis_nextdesc = 1315 &ld->sis_tx_list[nexti]; 1316 ld->sis_tx_list[i].sis_next = 1317 vtophys(&ld->sis_tx_list[nexti]); 1318 ld->sis_tx_list[i].sis_mbuf = NULL; 1319 ld->sis_tx_list[i].sis_ptr = 0; 1320 ld->sis_tx_list[i].sis_ctl = 0; 1321 } 1322 1323 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1324 1325 return(0); 1326 } 1327 1328 1329 /* 1330 * Initialize the RX descriptors and allocate mbufs for them. Note that 1331 * we arrange the descriptors in a closed ring, so that the last descriptor 1332 * points back to the first. 1333 */ 1334 static int sis_list_rx_init(sc) 1335 struct sis_softc *sc; 1336 { 1337 struct sis_list_data *ld; 1338 struct sis_ring_data *cd; 1339 int i, nexti; 1340 1341 ld = sc->sis_ldata; 1342 cd = &sc->sis_cdata; 1343 1344 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1345 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1346 return(ENOBUFS); 1347 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1348 ld->sis_rx_list[i].sis_nextdesc = 1349 &ld->sis_rx_list[nexti]; 1350 ld->sis_rx_list[i].sis_next = 1351 vtophys(&ld->sis_rx_list[nexti]); 1352 } 1353 1354 cd->sis_rx_prod = 0; 1355 1356 return(0); 1357 } 1358 1359 /* 1360 * Initialize an RX descriptor and attach an MBUF cluster. 1361 */ 1362 static int sis_newbuf(sc, c, m) 1363 struct sis_softc *sc; 1364 struct sis_desc *c; 1365 struct mbuf *m; 1366 { 1367 1368 if (m == NULL) { 1369 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1370 if (m == NULL) 1371 return(ENOBUFS); 1372 } else { 1373 m->m_data = m->m_ext.ext_buf; 1374 } 1375 1376 c->sis_mbuf = m; 1377 c->sis_ptr = vtophys(mtod(m, caddr_t)); 1378 c->sis_ctl = SIS_RXLEN; 1379 1380 return(0); 1381 } 1382 1383 /* 1384 * A frame has been uploaded: pass the resulting mbuf chain up to 1385 * the higher level protocols. 1386 */ 1387 static void sis_rxeof(sc) 1388 struct sis_softc *sc; 1389 { 1390 struct mbuf *m; 1391 struct ifnet *ifp; 1392 struct sis_desc *cur_rx; 1393 int i, total_len = 0; 1394 u_int32_t rxstat; 1395 1396 ifp = &sc->arpcom.ac_if; 1397 i = sc->sis_cdata.sis_rx_prod; 1398 1399 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) { 1400 1401 #ifdef DEVICE_POLLING 1402 if (ifp->if_ipending & IFF_POLLING) { 1403 if (sc->rxcycles <= 0) 1404 break; 1405 sc->rxcycles--; 1406 } 1407 #endif /* DEVICE_POLLING */ 1408 cur_rx = &sc->sis_ldata->sis_rx_list[i]; 1409 rxstat = cur_rx->sis_rxstat; 1410 m = cur_rx->sis_mbuf; 1411 cur_rx->sis_mbuf = NULL; 1412 total_len = SIS_RXBYTES(cur_rx); 1413 SIS_INC(i, SIS_RX_LIST_CNT); 1414 1415 /* 1416 * If an error occurs, update stats, clear the 1417 * status word and leave the mbuf cluster in place: 1418 * it should simply get re-used next time this descriptor 1419 * comes up in the ring. 1420 */ 1421 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1422 ifp->if_ierrors++; 1423 if (rxstat & SIS_RXSTAT_COLL) 1424 ifp->if_collisions++; 1425 sis_newbuf(sc, cur_rx, m); 1426 continue; 1427 } 1428 1429 /* No errors; receive the packet. */ 1430 #ifdef __i386__ 1431 /* 1432 * On the x86 we do not have alignment problems, so try to 1433 * allocate a new buffer for the receive ring, and pass up 1434 * the one where the packet is already, saving the expensive 1435 * copy done in m_devget(). 1436 * If we are on an architecture with alignment problems, or 1437 * if the allocation fails, then use m_devget and leave the 1438 * existing buffer in the receive ring. 1439 */ 1440 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1441 m->m_pkthdr.len = m->m_len = total_len; 1442 else 1443 #endif 1444 { 1445 struct mbuf *m0; 1446 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1447 total_len + ETHER_ALIGN, 0, ifp, NULL); 1448 sis_newbuf(sc, cur_rx, m); 1449 if (m0 == NULL) { 1450 ifp->if_ierrors++; 1451 continue; 1452 } 1453 m_adj(m0, ETHER_ALIGN); 1454 m = m0; 1455 } 1456 1457 ifp->if_ipackets++; 1458 ether_input(ifp, NULL, m); 1459 } 1460 1461 sc->sis_cdata.sis_rx_prod = i; 1462 1463 return; 1464 } 1465 1466 void sis_rxeoc(sc) 1467 struct sis_softc *sc; 1468 { 1469 sis_rxeof(sc); 1470 /* sis_init(sc); */ 1471 return; 1472 } 1473 1474 /* 1475 * A frame was downloaded to the chip. It's safe for us to clean up 1476 * the list buffers. 1477 */ 1478 1479 static void sis_txeof(sc) 1480 struct sis_softc *sc; 1481 { 1482 struct sis_desc *cur_tx = NULL; 1483 struct ifnet *ifp; 1484 u_int32_t idx; 1485 1486 ifp = &sc->arpcom.ac_if; 1487 1488 /* 1489 * Go through our tx list and free mbufs for those 1490 * frames that have been transmitted. 1491 */ 1492 idx = sc->sis_cdata.sis_tx_cons; 1493 while (idx != sc->sis_cdata.sis_tx_prod) { 1494 cur_tx = &sc->sis_ldata->sis_tx_list[idx]; 1495 1496 if (SIS_OWNDESC(cur_tx)) 1497 break; 1498 1499 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1500 sc->sis_cdata.sis_tx_cnt--; 1501 SIS_INC(idx, SIS_TX_LIST_CNT); 1502 continue; 1503 } 1504 1505 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1506 ifp->if_oerrors++; 1507 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1508 ifp->if_collisions++; 1509 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1510 ifp->if_collisions++; 1511 } 1512 1513 ifp->if_collisions += 1514 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1515 1516 ifp->if_opackets++; 1517 if (cur_tx->sis_mbuf != NULL) { 1518 m_freem(cur_tx->sis_mbuf); 1519 cur_tx->sis_mbuf = NULL; 1520 } 1521 1522 sc->sis_cdata.sis_tx_cnt--; 1523 SIS_INC(idx, SIS_TX_LIST_CNT); 1524 ifp->if_timer = 0; 1525 } 1526 1527 if (idx != sc->sis_cdata.sis_tx_cons) { 1528 sc->sis_cdata.sis_tx_cons = idx; 1529 ifp->if_flags &= ~IFF_OACTIVE; 1530 } 1531 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1532 return; 1533 } 1534 1535 static void sis_tick(xsc) 1536 void *xsc; 1537 { 1538 struct sis_softc *sc; 1539 struct mii_data *mii; 1540 struct ifnet *ifp; 1541 int s; 1542 1543 s = splimp(); 1544 1545 sc = xsc; 1546 ifp = &sc->arpcom.ac_if; 1547 1548 mii = device_get_softc(sc->sis_miibus); 1549 mii_tick(mii); 1550 1551 if (!sc->sis_link) { 1552 mii_pollstat(mii); 1553 if (mii->mii_media_status & IFM_ACTIVE && 1554 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1555 sc->sis_link++; 1556 if (ifp->if_snd.ifq_head != NULL) 1557 sis_start(ifp); 1558 } 1559 1560 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1561 1562 splx(s); 1563 1564 return; 1565 } 1566 1567 #ifdef DEVICE_POLLING 1568 static poll_handler_t sis_poll; 1569 1570 static void 1571 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1572 { 1573 struct sis_softc *sc = ifp->if_softc; 1574 1575 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1576 ether_poll_deregister(ifp); 1577 cmd = POLL_DEREGISTER; 1578 } 1579 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1580 CSR_WRITE_4(sc, SIS_IER, 1); 1581 return; 1582 } 1583 1584 /* 1585 * On the sis, reading the status register also clears it. 1586 * So before returning to intr mode we must make sure that all 1587 * possible pending sources of interrupts have been served. 1588 * In practice this means run to completion the *eof routines, 1589 * and then call the interrupt routine 1590 */ 1591 sc->rxcycles = count; 1592 sis_rxeof(sc); 1593 sis_txeof(sc); 1594 if (ifp->if_snd.ifq_head != NULL) 1595 sis_start(ifp); 1596 1597 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1598 u_int32_t status; 1599 1600 /* Reading the ISR register clears all interrupts. */ 1601 status = CSR_READ_4(sc, SIS_ISR); 1602 1603 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1604 sis_rxeoc(sc); 1605 1606 if (status & (SIS_ISR_RX_IDLE)) 1607 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1608 1609 if (status & SIS_ISR_SYSERR) { 1610 sis_reset(sc); 1611 sis_init(sc); 1612 } 1613 } 1614 } 1615 #endif /* DEVICE_POLLING */ 1616 1617 static void sis_intr(arg) 1618 void *arg; 1619 { 1620 struct sis_softc *sc; 1621 struct ifnet *ifp; 1622 u_int32_t status; 1623 1624 sc = arg; 1625 ifp = &sc->arpcom.ac_if; 1626 1627 #ifdef DEVICE_POLLING 1628 if (ifp->if_ipending & IFF_POLLING) 1629 return; 1630 if ((ifp->if_capenable & IFCAP_POLLING) && 1631 ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1632 CSR_WRITE_4(sc, SIS_IER, 0); 1633 sis_poll(ifp, 0, 1); 1634 return; 1635 } 1636 #endif /* DEVICE_POLLING */ 1637 1638 /* Supress unwanted interrupts */ 1639 if (!(ifp->if_flags & IFF_UP)) { 1640 sis_stop(sc); 1641 return; 1642 } 1643 1644 /* Disable interrupts. */ 1645 CSR_WRITE_4(sc, SIS_IER, 0); 1646 1647 for (;;) { 1648 /* Reading the ISR register clears all interrupts. */ 1649 status = CSR_READ_4(sc, SIS_ISR); 1650 1651 if ((status & SIS_INTRS) == 0) 1652 break; 1653 1654 if (status & 1655 (SIS_ISR_TX_DESC_OK|SIS_ISR_TX_ERR| 1656 SIS_ISR_TX_OK|SIS_ISR_TX_IDLE) ) 1657 sis_txeof(sc); 1658 1659 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1660 sis_rxeof(sc); 1661 1662 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1663 sis_rxeoc(sc); 1664 1665 if (status & (SIS_ISR_RX_IDLE)) 1666 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1667 1668 if (status & SIS_ISR_SYSERR) { 1669 sis_reset(sc); 1670 sis_init(sc); 1671 } 1672 } 1673 1674 /* Re-enable interrupts. */ 1675 CSR_WRITE_4(sc, SIS_IER, 1); 1676 1677 if (ifp->if_snd.ifq_head != NULL) 1678 sis_start(ifp); 1679 1680 return; 1681 } 1682 1683 /* 1684 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1685 * pointers to the fragment pointers. 1686 */ 1687 static int sis_encap(sc, m_head, txidx) 1688 struct sis_softc *sc; 1689 struct mbuf **m_head; 1690 u_int32_t *txidx; 1691 { 1692 struct sis_desc *f = NULL; 1693 struct mbuf *m; 1694 int frag, cur, cnt = 0, chainlen = 0; 1695 1696 /* 1697 * If there's no way we can send any packets, return now. 1698 */ 1699 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1700 return (ENOBUFS); 1701 1702 /* 1703 * Count the number of frags in this chain to see if 1704 * we need to m_defrag. Since the descriptor list is shared 1705 * by all packets, we'll m_defrag long chains so that they 1706 * do not use up the entire list, even if they would fit. 1707 */ 1708 1709 for (m = *m_head; m != NULL; m = m->m_next) 1710 chainlen++; 1711 1712 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1713 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { 1714 m = m_defrag(*m_head, M_DONTWAIT); 1715 if (m == NULL) 1716 return (ENOBUFS); 1717 *m_head = m; 1718 } 1719 1720 /* 1721 * Start packing the mbufs in this chain into 1722 * the fragment pointers. Stop when we run out 1723 * of fragments or hit the end of the mbuf chain. 1724 */ 1725 m = *m_head; 1726 cur = frag = *txidx; 1727 1728 for (m = *m_head; m != NULL; m = m->m_next) { 1729 if (m->m_len != 0) { 1730 if ((SIS_TX_LIST_CNT - 1731 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1732 return(ENOBUFS); 1733 f = &sc->sis_ldata->sis_tx_list[frag]; 1734 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1735 f->sis_ptr = vtophys(mtod(m, vm_offset_t)); 1736 if (cnt != 0) 1737 f->sis_ctl |= SIS_CMDSTS_OWN; 1738 cur = frag; 1739 SIS_INC(frag, SIS_TX_LIST_CNT); 1740 cnt++; 1741 } 1742 } 1743 1744 if (m != NULL) 1745 return(ENOBUFS); 1746 1747 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = *m_head; 1748 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1749 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1750 sc->sis_cdata.sis_tx_cnt += cnt; 1751 *txidx = frag; 1752 1753 return(0); 1754 } 1755 1756 /* 1757 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1758 * to the mbuf data regions directly in the transmit lists. We also save a 1759 * copy of the pointers since the transmit list fragment pointers are 1760 * physical addresses. 1761 */ 1762 1763 static void sis_start(ifp) 1764 struct ifnet *ifp; 1765 { 1766 struct sis_softc *sc; 1767 struct mbuf *m_head = NULL; 1768 u_int32_t idx; 1769 1770 sc = ifp->if_softc; 1771 1772 if (!sc->sis_link) 1773 return; 1774 1775 idx = sc->sis_cdata.sis_tx_prod; 1776 1777 if (ifp->if_flags & IFF_OACTIVE) 1778 return; 1779 1780 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) { 1781 IF_DEQUEUE(&ifp->if_snd, m_head); 1782 if (m_head == NULL) 1783 break; 1784 1785 if (sis_encap(sc, &m_head, &idx)) { 1786 IF_PREPEND(&ifp->if_snd, m_head); 1787 ifp->if_flags |= IFF_OACTIVE; 1788 break; 1789 } 1790 1791 /* 1792 * If there's a BPF listener, bounce a copy of this frame 1793 * to him. 1794 */ 1795 if (ifp->if_bpf) 1796 bpf_mtap(ifp, m_head); 1797 1798 } 1799 1800 /* Transmit */ 1801 sc->sis_cdata.sis_tx_prod = idx; 1802 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1803 1804 /* 1805 * Set a timeout in case the chip goes out to lunch. 1806 */ 1807 ifp->if_timer = 5; 1808 1809 return; 1810 } 1811 1812 static void sis_init(xsc) 1813 void *xsc; 1814 { 1815 struct sis_softc *sc = xsc; 1816 struct ifnet *ifp = &sc->arpcom.ac_if; 1817 struct mii_data *mii; 1818 int s; 1819 1820 s = splimp(); 1821 1822 /* 1823 * Cancel pending I/O and free all RX/TX buffers. 1824 */ 1825 sis_stop(sc); 1826 1827 mii = device_get_softc(sc->sis_miibus); 1828 1829 /* Set MAC address */ 1830 if (sc->sis_type == SIS_TYPE_83815) { 1831 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1832 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1833 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1834 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1835 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1836 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1837 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1838 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1839 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1840 } else { 1841 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1842 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1843 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1844 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1845 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1846 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1847 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1848 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1849 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1850 } 1851 1852 /* Init circular RX list. */ 1853 if (sis_list_rx_init(sc) == ENOBUFS) { 1854 printf("sis%d: initialization failed: no " 1855 "memory for rx buffers\n", sc->sis_unit); 1856 sis_stop(sc); 1857 (void)splx(s); 1858 return; 1859 } 1860 1861 /* 1862 * Init tx descriptors. 1863 */ 1864 sis_list_tx_init(sc); 1865 1866 /* 1867 * For the NatSemi chip, we have to explicitly enable the 1868 * reception of ARP frames, as well as turn on the 'perfect 1869 * match' filter where we store the station address, otherwise 1870 * we won't receive unicasts meant for this host. 1871 */ 1872 if (sc->sis_type == SIS_TYPE_83815) { 1873 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1874 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1875 } 1876 1877 /* If we want promiscuous mode, set the allframes bit. */ 1878 if (ifp->if_flags & IFF_PROMISC) { 1879 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1880 } else { 1881 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1882 } 1883 1884 /* 1885 * Set the capture broadcast bit to capture broadcast frames. 1886 */ 1887 if (ifp->if_flags & IFF_BROADCAST) { 1888 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1889 } else { 1890 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1891 } 1892 1893 /* 1894 * Load the multicast filter. 1895 */ 1896 if (sc->sis_type == SIS_TYPE_83815) 1897 sis_setmulti_ns(sc); 1898 else 1899 sis_setmulti_sis(sc); 1900 1901 /* Turn the receive filter on */ 1902 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1903 1904 /* 1905 * Load the address of the RX and TX lists. 1906 */ 1907 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 1908 vtophys(&sc->sis_ldata->sis_rx_list[0])); 1909 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 1910 vtophys(&sc->sis_ldata->sis_tx_list[0])); 1911 1912 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1913 * the PCI bus. When this bit is set, the Max DMA Burst Size 1914 * for TX/RX DMA should be no larger than 16 double words. 1915 */ 1916 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 1917 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1918 } else { 1919 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1920 } 1921 1922 /* Accept Long Packets for VLAN support */ 1923 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1924 1925 /* Set TX configuration */ 1926 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1927 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1928 } else { 1929 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1930 } 1931 1932 /* Set full/half duplex mode. */ 1933 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1934 SIS_SETBIT(sc, SIS_TX_CFG, 1935 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1936 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1937 } else { 1938 SIS_CLRBIT(sc, SIS_TX_CFG, 1939 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1940 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1941 } 1942 1943 if (sc->sis_type == SIS_TYPE_83815 && 1944 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1945 uint32_t reg; 1946 1947 /* 1948 * Some DP83815s experience problems when used with short 1949 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 1950 * sequence adjusts the DSP's signal attenuation to fix the 1951 * problem. 1952 */ 1953 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1954 1955 reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 1956 CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 1957 DELAY(100); 1958 reg = CSR_READ_4(sc, NS_PHY_TDATA); 1959 if ((reg & 0x0080) == 0 || (reg & 0xff) >= 0xd8) { 1960 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 1961 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 1962 } 1963 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 1964 } 1965 1966 /* 1967 * Enable interrupts. 1968 */ 1969 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1970 #ifdef DEVICE_POLLING 1971 /* 1972 * ... only enable interrupts if we are not polling, make sure 1973 * they are off otherwise. 1974 */ 1975 if (ifp->if_ipending & IFF_POLLING) 1976 CSR_WRITE_4(sc, SIS_IER, 0); 1977 else 1978 #endif /* DEVICE_POLLING */ 1979 CSR_WRITE_4(sc, SIS_IER, 1); 1980 1981 /* Enable receiver and transmitter. */ 1982 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1983 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1984 1985 #ifdef notdef 1986 mii_mediachg(mii); 1987 #endif 1988 1989 /* 1990 * Page 75 of the DP83815 manual recommends the 1991 * following register settings "for optimum 1992 * performance." Note however that at least three 1993 * of the registers are listed as "reserved" in 1994 * the register map, so who knows what they do. 1995 */ 1996 if (sc->sis_type == SIS_TYPE_83815) { 1997 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1998 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1999 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2000 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2001 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2002 } 2003 2004 ifp->if_flags |= IFF_RUNNING; 2005 ifp->if_flags &= ~IFF_OACTIVE; 2006 2007 (void)splx(s); 2008 2009 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 2010 2011 return; 2012 } 2013 2014 /* 2015 * Set media options. 2016 */ 2017 static int sis_ifmedia_upd(ifp) 2018 struct ifnet *ifp; 2019 { 2020 struct sis_softc *sc; 2021 struct mii_data *mii; 2022 2023 sc = ifp->if_softc; 2024 2025 mii = device_get_softc(sc->sis_miibus); 2026 sc->sis_link = 0; 2027 if (mii->mii_instance) { 2028 struct mii_softc *miisc; 2029 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2030 miisc = LIST_NEXT(miisc, mii_list)) 2031 mii_phy_reset(miisc); 2032 } 2033 mii_mediachg(mii); 2034 2035 return(0); 2036 } 2037 2038 /* 2039 * Report current media status. 2040 */ 2041 static void sis_ifmedia_sts(ifp, ifmr) 2042 struct ifnet *ifp; 2043 struct ifmediareq *ifmr; 2044 { 2045 struct sis_softc *sc; 2046 struct mii_data *mii; 2047 2048 sc = ifp->if_softc; 2049 2050 mii = device_get_softc(sc->sis_miibus); 2051 mii_pollstat(mii); 2052 ifmr->ifm_active = mii->mii_media_active; 2053 ifmr->ifm_status = mii->mii_media_status; 2054 2055 return; 2056 } 2057 2058 static int sis_ioctl(ifp, command, data) 2059 struct ifnet *ifp; 2060 u_long command; 2061 caddr_t data; 2062 { 2063 struct sis_softc *sc = ifp->if_softc; 2064 struct ifreq *ifr = (struct ifreq *) data; 2065 struct mii_data *mii; 2066 int s, error = 0; 2067 2068 s = splimp(); 2069 2070 switch(command) { 2071 case SIOCSIFADDR: 2072 case SIOCGIFADDR: 2073 case SIOCSIFMTU: 2074 error = ether_ioctl(ifp, command, data); 2075 break; 2076 case SIOCSIFFLAGS: 2077 if (ifp->if_flags & IFF_UP) { 2078 sis_init(sc); 2079 } else { 2080 if (ifp->if_flags & IFF_RUNNING) 2081 sis_stop(sc); 2082 } 2083 error = 0; 2084 break; 2085 case SIOCADDMULTI: 2086 case SIOCDELMULTI: 2087 if (sc->sis_type == SIS_TYPE_83815) 2088 sis_setmulti_ns(sc); 2089 else 2090 sis_setmulti_sis(sc); 2091 error = 0; 2092 break; 2093 case SIOCGIFMEDIA: 2094 case SIOCSIFMEDIA: 2095 mii = device_get_softc(sc->sis_miibus); 2096 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2097 break; 2098 case SIOCSIFCAP: 2099 ifp->if_capenable = ifr->ifr_reqcap; 2100 break; 2101 default: 2102 error = EINVAL; 2103 break; 2104 } 2105 2106 (void)splx(s); 2107 2108 return(error); 2109 } 2110 2111 static void sis_watchdog(ifp) 2112 struct ifnet *ifp; 2113 { 2114 struct sis_softc *sc; 2115 2116 sc = ifp->if_softc; 2117 2118 ifp->if_oerrors++; 2119 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2120 2121 sis_stop(sc); 2122 sis_reset(sc); 2123 sis_init(sc); 2124 2125 if (ifp->if_snd.ifq_head != NULL) 2126 sis_start(ifp); 2127 2128 return; 2129 } 2130 2131 /* 2132 * Stop the adapter and free any mbufs allocated to the 2133 * RX and TX lists. 2134 */ 2135 static void sis_stop(sc) 2136 struct sis_softc *sc; 2137 { 2138 register int i; 2139 struct ifnet *ifp; 2140 2141 ifp = &sc->arpcom.ac_if; 2142 ifp->if_timer = 0; 2143 2144 untimeout(sis_tick, sc, sc->sis_stat_ch); 2145 2146 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2147 #ifdef DEVICE_POLLING 2148 ether_poll_deregister(ifp); 2149 #endif 2150 CSR_WRITE_4(sc, SIS_IER, 0); 2151 CSR_WRITE_4(sc, SIS_IMR, 0); 2152 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2153 DELAY(1000); 2154 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2155 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2156 2157 sc->sis_link = 0; 2158 2159 /* 2160 * Free data in the RX lists. 2161 */ 2162 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2163 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) { 2164 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf); 2165 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL; 2166 } 2167 } 2168 bzero((char *)&sc->sis_ldata->sis_rx_list, 2169 sizeof(sc->sis_ldata->sis_rx_list)); 2170 2171 /* 2172 * Free the TX list buffers. 2173 */ 2174 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2175 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) { 2176 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf); 2177 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL; 2178 } 2179 } 2180 2181 bzero((char *)&sc->sis_ldata->sis_tx_list, 2182 sizeof(sc->sis_ldata->sis_tx_list)); 2183 2184 return; 2185 } 2186 2187 /* 2188 * Stop all chip I/O so that the kernel's probe routines don't 2189 * get confused by errant DMAs when rebooting. 2190 */ 2191 static void sis_shutdown(dev) 2192 device_t dev; 2193 { 2194 struct sis_softc *sc; 2195 2196 sc = device_get_softc(dev); 2197 2198 sis_reset(sc); 2199 sis_stop(sc); 2200 2201 return; 2202 }
Cache object: 366ac9d3fbf40746fbdafa8957822575
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]