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sys/pci/if_sis.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: releng/5.0/sys/pci/if_sis.c 106936 2002-11-14 23:49:09Z sam $ 33 */ 34 35 /* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/sysctl.h> 68 69 #include <net/if.h> 70 #include <net/if_arp.h> 71 #include <net/ethernet.h> 72 #include <net/if_dl.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_vlan_var.h> 76 77 #include <net/bpf.h> 78 79 #include <machine/bus_pio.h> 80 #include <machine/bus_memio.h> 81 #include <machine/bus.h> 82 #include <machine/resource.h> 83 #include <sys/bus.h> 84 #include <sys/rman.h> 85 86 #include <dev/mii/mii.h> 87 #include <dev/mii/miivar.h> 88 89 #include <pci/pcireg.h> 90 #include <pci/pcivar.h> 91 92 #define SIS_USEIOSPACE 93 94 #include <pci/if_sisreg.h> 95 96 MODULE_DEPEND(sis, miibus, 1, 1, 1); 97 98 /* "controller miibus0" required. See GENERIC if you get errors here. */ 99 #include "miibus_if.h" 100 101 #ifndef lint 102 static const char rcsid[] = 103 "$FreeBSD: releng/5.0/sys/pci/if_sis.c 106936 2002-11-14 23:49:09Z sam $"; 104 #endif 105 106 /* 107 * Various supported device vendors/types and their names. 108 */ 109 static struct sis_type sis_devs[] = { 110 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 111 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 112 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 113 { 0, 0, NULL } 114 }; 115 116 static int sis_probe (device_t); 117 static int sis_attach (device_t); 118 static int sis_detach (device_t); 119 120 static int sis_newbuf (struct sis_softc *, 121 struct sis_desc *, struct mbuf *); 122 static int sis_encap (struct sis_softc *, 123 struct mbuf *, u_int32_t *); 124 static void sis_rxeof (struct sis_softc *); 125 static void sis_rxeoc (struct sis_softc *); 126 static void sis_txeof (struct sis_softc *); 127 static void sis_intr (void *); 128 static void sis_tick (void *); 129 static void sis_start (struct ifnet *); 130 static int sis_ioctl (struct ifnet *, u_long, caddr_t); 131 static void sis_init (void *); 132 static void sis_stop (struct sis_softc *); 133 static void sis_watchdog (struct ifnet *); 134 static void sis_shutdown (device_t); 135 static int sis_ifmedia_upd (struct ifnet *); 136 static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 137 138 static u_int16_t sis_reverse (u_int16_t); 139 static void sis_delay (struct sis_softc *); 140 static void sis_eeprom_idle (struct sis_softc *); 141 static void sis_eeprom_putbyte (struct sis_softc *, int); 142 static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 143 static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 144 #ifdef __i386__ 145 static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 146 int, int); 147 static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 148 static device_t sis_find_bridge (device_t); 149 #endif 150 151 static int sis_miibus_readreg (device_t, int, int); 152 static int sis_miibus_writereg (device_t, int, int, int); 153 static void sis_miibus_statchg (device_t); 154 155 static void sis_setmulti_sis (struct sis_softc *); 156 static void sis_setmulti_ns (struct sis_softc *); 157 static u_int32_t sis_crc (struct sis_softc *, caddr_t); 158 static void sis_reset (struct sis_softc *); 159 static int sis_list_rx_init (struct sis_softc *); 160 static int sis_list_tx_init (struct sis_softc *); 161 162 static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 163 static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 164 static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 165 #ifdef SIS_USEIOSPACE 166 #define SIS_RES SYS_RES_IOPORT 167 #define SIS_RID SIS_PCI_LOIO 168 #else 169 #define SIS_RES SYS_RES_MEMORY 170 #define SIS_RID SIS_PCI_LOMEM 171 #endif 172 173 static device_method_t sis_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, sis_probe), 176 DEVMETHOD(device_attach, sis_attach), 177 DEVMETHOD(device_detach, sis_detach), 178 DEVMETHOD(device_shutdown, sis_shutdown), 179 180 /* bus interface */ 181 DEVMETHOD(bus_print_child, bus_generic_print_child), 182 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 186 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 187 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 188 189 { 0, 0 } 190 }; 191 192 static driver_t sis_driver = { 193 "sis", 194 sis_methods, 195 sizeof(struct sis_softc) 196 }; 197 198 static devclass_t sis_devclass; 199 200 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 201 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 202 203 #define SIS_SETBIT(sc, reg, x) \ 204 CSR_WRITE_4(sc, reg, \ 205 CSR_READ_4(sc, reg) | (x)) 206 207 #define SIS_CLRBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, \ 209 CSR_READ_4(sc, reg) & ~(x)) 210 211 #define SIO_SET(x) \ 212 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 213 214 #define SIO_CLR(x) \ 215 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 216 217 static void 218 sis_dma_map_desc_next(arg, segs, nseg, error) 219 void *arg; 220 bus_dma_segment_t *segs; 221 int nseg, error; 222 { 223 struct sis_desc *r; 224 225 r = arg; 226 r->sis_next = segs->ds_addr; 227 228 return; 229 } 230 231 static void 232 sis_dma_map_desc_ptr(arg, segs, nseg, error) 233 void *arg; 234 bus_dma_segment_t *segs; 235 int nseg, error; 236 { 237 struct sis_desc *r; 238 239 r = arg; 240 r->sis_ptr = segs->ds_addr; 241 242 return; 243 } 244 245 static void 246 sis_dma_map_ring(arg, segs, nseg, error) 247 void *arg; 248 bus_dma_segment_t *segs; 249 int nseg, error; 250 { 251 u_int32_t *p; 252 253 p = arg; 254 *p = segs->ds_addr; 255 256 return; 257 } 258 259 /* 260 * Routine to reverse the bits in a word. Stolen almost 261 * verbatim from /usr/games/fortune. 262 */ 263 static u_int16_t 264 sis_reverse(n) 265 u_int16_t n; 266 { 267 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 268 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 269 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 270 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 271 272 return(n); 273 } 274 275 static void 276 sis_delay(sc) 277 struct sis_softc *sc; 278 { 279 int idx; 280 281 for (idx = (300 / 33) + 1; idx > 0; idx--) 282 CSR_READ_4(sc, SIS_CSR); 283 284 return; 285 } 286 287 static void 288 sis_eeprom_idle(sc) 289 struct sis_softc *sc; 290 { 291 register int i; 292 293 SIO_SET(SIS_EECTL_CSEL); 294 sis_delay(sc); 295 SIO_SET(SIS_EECTL_CLK); 296 sis_delay(sc); 297 298 for (i = 0; i < 25; i++) { 299 SIO_CLR(SIS_EECTL_CLK); 300 sis_delay(sc); 301 SIO_SET(SIS_EECTL_CLK); 302 sis_delay(sc); 303 } 304 305 SIO_CLR(SIS_EECTL_CLK); 306 sis_delay(sc); 307 SIO_CLR(SIS_EECTL_CSEL); 308 sis_delay(sc); 309 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 310 311 return; 312 } 313 314 /* 315 * Send a read command and address to the EEPROM, check for ACK. 316 */ 317 static void 318 sis_eeprom_putbyte(sc, addr) 319 struct sis_softc *sc; 320 int addr; 321 { 322 register int d, i; 323 324 d = addr | SIS_EECMD_READ; 325 326 /* 327 * Feed in each bit and stobe the clock. 328 */ 329 for (i = 0x400; i; i >>= 1) { 330 if (d & i) { 331 SIO_SET(SIS_EECTL_DIN); 332 } else { 333 SIO_CLR(SIS_EECTL_DIN); 334 } 335 sis_delay(sc); 336 SIO_SET(SIS_EECTL_CLK); 337 sis_delay(sc); 338 SIO_CLR(SIS_EECTL_CLK); 339 sis_delay(sc); 340 } 341 342 return; 343 } 344 345 /* 346 * Read a word of data stored in the EEPROM at address 'addr.' 347 */ 348 static void 349 sis_eeprom_getword(sc, addr, dest) 350 struct sis_softc *sc; 351 int addr; 352 u_int16_t *dest; 353 { 354 register int i; 355 u_int16_t word = 0; 356 357 /* Force EEPROM to idle state. */ 358 sis_eeprom_idle(sc); 359 360 /* Enter EEPROM access mode. */ 361 sis_delay(sc); 362 SIO_CLR(SIS_EECTL_CLK); 363 sis_delay(sc); 364 SIO_SET(SIS_EECTL_CSEL); 365 sis_delay(sc); 366 367 /* 368 * Send address of word we want to read. 369 */ 370 sis_eeprom_putbyte(sc, addr); 371 372 /* 373 * Start reading bits from EEPROM. 374 */ 375 for (i = 0x8000; i; i >>= 1) { 376 SIO_SET(SIS_EECTL_CLK); 377 sis_delay(sc); 378 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 379 word |= i; 380 sis_delay(sc); 381 SIO_CLR(SIS_EECTL_CLK); 382 sis_delay(sc); 383 } 384 385 /* Turn off EEPROM access mode. */ 386 sis_eeprom_idle(sc); 387 388 *dest = word; 389 390 return; 391 } 392 393 /* 394 * Read a sequence of words from the EEPROM. 395 */ 396 static void 397 sis_read_eeprom(sc, dest, off, cnt, swap) 398 struct sis_softc *sc; 399 caddr_t dest; 400 int off; 401 int cnt; 402 int swap; 403 { 404 int i; 405 u_int16_t word = 0, *ptr; 406 407 for (i = 0; i < cnt; i++) { 408 sis_eeprom_getword(sc, off + i, &word); 409 ptr = (u_int16_t *)(dest + (i * 2)); 410 if (swap) 411 *ptr = ntohs(word); 412 else 413 *ptr = word; 414 } 415 416 return; 417 } 418 419 #ifdef __i386__ 420 static device_t 421 sis_find_bridge(dev) 422 device_t dev; 423 { 424 devclass_t pci_devclass; 425 device_t *pci_devices; 426 int pci_count = 0; 427 device_t *pci_children; 428 int pci_childcount = 0; 429 device_t *busp, *childp; 430 device_t child = NULL; 431 int i, j; 432 433 if ((pci_devclass = devclass_find("pci")) == NULL) 434 return(NULL); 435 436 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 437 438 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 439 pci_childcount = 0; 440 device_get_children(*busp, &pci_children, &pci_childcount); 441 for (j = 0, childp = pci_children; 442 j < pci_childcount; j++, childp++) { 443 if (pci_get_vendor(*childp) == SIS_VENDORID && 444 pci_get_device(*childp) == 0x0008) { 445 child = *childp; 446 goto done; 447 } 448 } 449 } 450 451 done: 452 free(pci_devices, M_TEMP); 453 free(pci_children, M_TEMP); 454 return(child); 455 } 456 457 static void 458 sis_read_cmos(sc, dev, dest, off, cnt) 459 struct sis_softc *sc; 460 device_t dev; 461 caddr_t dest; 462 int off; 463 int cnt; 464 { 465 device_t bridge; 466 u_int8_t reg; 467 int i; 468 bus_space_tag_t btag; 469 470 bridge = sis_find_bridge(dev); 471 if (bridge == NULL) 472 return; 473 reg = pci_read_config(bridge, 0x48, 1); 474 pci_write_config(bridge, 0x48, reg|0x40, 1); 475 476 /* XXX */ 477 btag = I386_BUS_SPACE_IO; 478 479 for (i = 0; i < cnt; i++) { 480 bus_space_write_1(btag, 0x0, 0x70, i + off); 481 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 482 } 483 484 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 485 return; 486 } 487 488 static void 489 sis_read_mac(sc, dev, dest) 490 struct sis_softc *sc; 491 device_t dev; 492 caddr_t dest; 493 { 494 u_int32_t filtsave, csrsave; 495 496 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 497 csrsave = CSR_READ_4(sc, SIS_CSR); 498 499 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 500 CSR_WRITE_4(sc, SIS_CSR, 0); 501 502 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 503 504 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 505 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 507 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 509 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 511 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 512 CSR_WRITE_4(sc, SIS_CSR, csrsave); 513 return; 514 } 515 #endif 516 517 static int 518 sis_miibus_readreg(dev, phy, reg) 519 device_t dev; 520 int phy, reg; 521 { 522 struct sis_softc *sc; 523 int i, val = 0; 524 525 sc = device_get_softc(dev); 526 527 if (sc->sis_type == SIS_TYPE_83815) { 528 if (phy != 0) 529 return(0); 530 /* 531 * The NatSemi chip can take a while after 532 * a reset to come ready, during which the BMSR 533 * returns a value of 0. This is *never* supposed 534 * to happen: some of the BMSR bits are meant to 535 * be hardwired in the on position, and this can 536 * confuse the miibus code a bit during the probe 537 * and attach phase. So we make an effort to check 538 * for this condition and wait for it to clear. 539 */ 540 if (!CSR_READ_4(sc, NS_BMSR)) 541 DELAY(1000); 542 val = CSR_READ_4(sc, NS_BMCR + (reg * 4)); 543 return(val); 544 } 545 546 if (sc->sis_type == SIS_TYPE_900 && 547 sc->sis_rev < SIS_REV_635 && phy != 0) 548 return(0); 549 550 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 551 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 552 553 for (i = 0; i < SIS_TIMEOUT; i++) { 554 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 555 break; 556 } 557 558 if (i == SIS_TIMEOUT) { 559 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 560 return(0); 561 } 562 563 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 564 565 if (val == 0xFFFF) 566 return(0); 567 568 return(val); 569 } 570 571 static int 572 sis_miibus_writereg(dev, phy, reg, data) 573 device_t dev; 574 int phy, reg, data; 575 { 576 struct sis_softc *sc; 577 int i; 578 579 sc = device_get_softc(dev); 580 581 if (sc->sis_type == SIS_TYPE_83815) { 582 if (phy != 0) 583 return(0); 584 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 585 return(0); 586 } 587 588 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 589 return(0); 590 591 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 592 (reg << 6) | SIS_PHYOP_WRITE); 593 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 594 595 for (i = 0; i < SIS_TIMEOUT; i++) { 596 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 597 break; 598 } 599 600 if (i == SIS_TIMEOUT) 601 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 602 603 return(0); 604 } 605 606 static void 607 sis_miibus_statchg(dev) 608 device_t dev; 609 { 610 struct sis_softc *sc; 611 612 sc = device_get_softc(dev); 613 sis_init(sc); 614 615 return; 616 } 617 618 static u_int32_t 619 sis_crc(sc, addr) 620 struct sis_softc *sc; 621 caddr_t addr; 622 { 623 u_int32_t crc, carry; 624 int i, j; 625 u_int8_t c; 626 627 /* Compute CRC for the address value. */ 628 crc = 0xFFFFFFFF; /* initial value */ 629 630 for (i = 0; i < 6; i++) { 631 c = *(addr + i); 632 for (j = 0; j < 8; j++) { 633 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 634 crc <<= 1; 635 c >>= 1; 636 if (carry) 637 crc = (crc ^ 0x04c11db6) | carry; 638 } 639 } 640 641 /* 642 * return the filter bit position 643 * 644 * The NatSemi chip has a 512-bit filter, which is 645 * different than the SiS, so we special-case it. 646 */ 647 if (sc->sis_type == SIS_TYPE_83815) 648 return((crc >> 23) & 0x1FF); 649 650 return((crc >> 25) & 0x0000007F); 651 } 652 653 static void 654 sis_setmulti_ns(sc) 655 struct sis_softc *sc; 656 { 657 struct ifnet *ifp; 658 struct ifmultiaddr *ifma; 659 u_int32_t h = 0, i, filtsave; 660 int bit, index; 661 662 ifp = &sc->arpcom.ac_if; 663 664 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 665 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 666 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 667 return; 668 } 669 670 /* 671 * We have to explicitly enable the multicast hash table 672 * on the NatSemi chip if we want to use it, which we do. 673 */ 674 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 675 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 676 677 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 678 679 /* first, zot all the existing hash bits */ 680 for (i = 0; i < 32; i++) { 681 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 682 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 683 } 684 685 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 686 if (ifma->ifma_addr->sa_family != AF_LINK) 687 continue; 688 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 689 index = h >> 3; 690 bit = h & 0x1F; 691 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 692 if (bit > 0xF) 693 bit -= 0x10; 694 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 695 } 696 697 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 698 699 return; 700 } 701 702 static void 703 sis_setmulti_sis(sc) 704 struct sis_softc *sc; 705 { 706 struct ifnet *ifp; 707 struct ifmultiaddr *ifma; 708 u_int32_t h = 0, i, filtsave; 709 710 ifp = &sc->arpcom.ac_if; 711 712 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 713 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 714 return; 715 } 716 717 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 718 719 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 720 721 /* first, zot all the existing hash bits */ 722 for (i = 0; i < 8; i++) { 723 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 724 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 725 } 726 727 /* now program new ones */ 728 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 729 if (ifma->ifma_addr->sa_family != AF_LINK) 730 continue; 731 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 732 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 733 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 734 } 735 736 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 737 738 return; 739 } 740 741 static void 742 sis_reset(sc) 743 struct sis_softc *sc; 744 { 745 register int i; 746 747 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 748 749 for (i = 0; i < SIS_TIMEOUT; i++) { 750 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 751 break; 752 } 753 754 if (i == SIS_TIMEOUT) 755 printf("sis%d: reset never completed\n", sc->sis_unit); 756 757 /* Wait a little while for the chip to get its brains in order. */ 758 DELAY(1000); 759 760 /* 761 * If this is a NetSemi chip, make sure to clear 762 * PME mode. 763 */ 764 if (sc->sis_type == SIS_TYPE_83815) { 765 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 766 CSR_WRITE_4(sc, NS_CLKRUN, 0); 767 } 768 769 return; 770 } 771 772 /* 773 * Probe for an SiS chip. Check the PCI vendor and device 774 * IDs against our list and return a device name if we find a match. 775 */ 776 static int 777 sis_probe(dev) 778 device_t dev; 779 { 780 struct sis_type *t; 781 782 t = sis_devs; 783 784 while(t->sis_name != NULL) { 785 if ((pci_get_vendor(dev) == t->sis_vid) && 786 (pci_get_device(dev) == t->sis_did)) { 787 device_set_desc(dev, t->sis_name); 788 return(0); 789 } 790 t++; 791 } 792 793 return(ENXIO); 794 } 795 796 /* 797 * Attach the interface. Allocate softc structures, do ifmedia 798 * setup and ethernet/BPF attach. 799 */ 800 static int 801 sis_attach(dev) 802 device_t dev; 803 { 804 u_char eaddr[ETHER_ADDR_LEN]; 805 u_int32_t command; 806 struct sis_softc *sc; 807 struct ifnet *ifp; 808 int unit, error = 0, rid; 809 810 sc = device_get_softc(dev); 811 unit = device_get_unit(dev); 812 bzero(sc, sizeof(struct sis_softc)); 813 814 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 815 MTX_DEF | MTX_RECURSE); 816 817 if (pci_get_device(dev) == SIS_DEVICEID_900) 818 sc->sis_type = SIS_TYPE_900; 819 if (pci_get_device(dev) == SIS_DEVICEID_7016) 820 sc->sis_type = SIS_TYPE_7016; 821 if (pci_get_vendor(dev) == NS_VENDORID) 822 sc->sis_type = SIS_TYPE_83815; 823 824 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 825 826 /* 827 * Handle power management nonsense. 828 */ 829 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 830 u_int32_t iobase, membase, irq; 831 832 /* Save important PCI config data. */ 833 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 834 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 835 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 836 837 /* Reset the power state. */ 838 printf("sis%d: chip is in D%d power mode " 839 "-- setting to D0\n", unit, 840 pci_get_powerstate(dev)); 841 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 842 843 /* Restore PCI config data. */ 844 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 845 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 846 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 847 } 848 849 /* 850 * Map control/status registers. 851 */ 852 pci_enable_busmaster(dev); 853 pci_enable_io(dev, SYS_RES_IOPORT); 854 pci_enable_io(dev, SYS_RES_MEMORY); 855 command = pci_read_config(dev, PCIR_COMMAND, 4); 856 857 #ifdef SIS_USEIOSPACE 858 if (!(command & PCIM_CMD_PORTEN)) { 859 printf("sis%d: failed to enable I/O ports!\n", unit); 860 error = ENXIO;; 861 goto fail; 862 } 863 #else 864 if (!(command & PCIM_CMD_MEMEN)) { 865 printf("sis%d: failed to enable memory mapping!\n", unit); 866 error = ENXIO;; 867 goto fail; 868 } 869 #endif 870 871 rid = SIS_RID; 872 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 873 0, ~0, 1, RF_ACTIVE); 874 875 if (sc->sis_res == NULL) { 876 printf("sis%d: couldn't map ports/memory\n", unit); 877 error = ENXIO; 878 goto fail; 879 } 880 881 sc->sis_btag = rman_get_bustag(sc->sis_res); 882 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 883 884 /* Allocate interrupt */ 885 rid = 0; 886 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 887 RF_SHAREABLE | RF_ACTIVE); 888 889 if (sc->sis_irq == NULL) { 890 printf("sis%d: couldn't map interrupt\n", unit); 891 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 892 error = ENXIO; 893 goto fail; 894 } 895 896 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 897 sis_intr, sc, &sc->sis_intrhand); 898 899 if (error) { 900 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 901 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 902 printf("sis%d: couldn't set up irq\n", unit); 903 goto fail; 904 } 905 906 /* Reset the adapter. */ 907 sis_reset(sc); 908 909 /* 910 * Get station address from the EEPROM. 911 */ 912 switch (pci_get_vendor(dev)) { 913 case NS_VENDORID: 914 /* 915 * Reading the MAC address out of the EEPROM on 916 * the NatSemi chip takes a bit more work than 917 * you'd expect. The address spans 4 16-bit words, 918 * with the first word containing only a single bit. 919 * You have to shift everything over one bit to 920 * get it aligned properly. Also, the bits are 921 * stored backwards (the LSB is really the MSB, 922 * and so on) so you have to reverse them in order 923 * to get the MAC address into the form we want. 924 * Why? Who the hell knows. 925 */ 926 { 927 u_int16_t tmp[4]; 928 929 sis_read_eeprom(sc, (caddr_t)&tmp, 930 NS_EE_NODEADDR, 4, 0); 931 932 /* Shift everything over one bit. */ 933 tmp[3] = tmp[3] >> 1; 934 tmp[3] |= tmp[2] << 15; 935 tmp[2] = tmp[2] >> 1; 936 tmp[2] |= tmp[1] << 15; 937 tmp[1] = tmp[1] >> 1; 938 tmp[1] |= tmp[0] << 15; 939 940 /* Now reverse all the bits. */ 941 tmp[3] = sis_reverse(tmp[3]); 942 tmp[2] = sis_reverse(tmp[2]); 943 tmp[1] = sis_reverse(tmp[1]); 944 945 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 946 } 947 break; 948 case SIS_VENDORID: 949 default: 950 #ifdef __i386__ 951 /* 952 * If this is a SiS 630E chipset with an embedded 953 * SiS 900 controller, we have to read the MAC address 954 * from the APC CMOS RAM. Our method for doing this 955 * is very ugly since we have to reach out and grab 956 * ahold of hardware for which we cannot properly 957 * allocate resources. This code is only compiled on 958 * the i386 architecture since the SiS 630E chipset 959 * is for x86 motherboards only. Note that there are 960 * a lot of magic numbers in this hack. These are 961 * taken from SiS's Linux driver. I'd like to replace 962 * them with proper symbolic definitions, but that 963 * requires some datasheets that I don't have access 964 * to at the moment. 965 */ 966 if (sc->sis_rev == SIS_REV_630S || 967 sc->sis_rev == SIS_REV_630E || 968 sc->sis_rev == SIS_REV_630EA1) 969 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 970 971 else if (sc->sis_rev == SIS_REV_635 || 972 sc->sis_rev == SIS_REV_630ET) 973 sis_read_mac(sc, dev, (caddr_t)&eaddr); 974 else 975 #endif 976 sis_read_eeprom(sc, (caddr_t)&eaddr, 977 SIS_EE_NODEADDR, 3, 0); 978 break; 979 } 980 981 /* 982 * A SiS chip was detected. Inform the world. 983 */ 984 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 985 986 sc->sis_unit = unit; 987 callout_handle_init(&sc->sis_stat_ch); 988 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 989 990 /* 991 * Allocate the parent bus DMA tag appropriate for PCI. 992 */ 993 #define SIS_NSEG_NEW 32 994 error = bus_dma_tag_create(NULL, /* parent */ 995 1, 0, /* alignment, boundary */ 996 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 997 BUS_SPACE_MAXADDR, /* highaddr */ 998 NULL, NULL, /* filter, filterarg */ 999 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1000 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1001 BUS_DMA_ALLOCNOW, /* flags */ 1002 &sc->sis_parent_tag); 1003 1004 /* 1005 * Now allocate a tag for the DMA descriptor lists. 1006 * All of our lists are allocated as a contiguous block 1007 * of memory. 1008 */ 1009 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1010 1, 0, /* alignment, boundary */ 1011 BUS_SPACE_MAXADDR, /* lowaddr */ 1012 BUS_SPACE_MAXADDR, /* highaddr */ 1013 NULL, NULL, /* filter, filterarg */ 1014 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1015 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1016 0, /* flags */ 1017 &sc->sis_ldata.sis_rx_tag); 1018 1019 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1020 1, 0, /* alignment, boundary */ 1021 BUS_SPACE_MAXADDR, /* lowaddr */ 1022 BUS_SPACE_MAXADDR, /* highaddr */ 1023 NULL, NULL, /* filter, filterarg */ 1024 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1025 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1026 0, /* flags */ 1027 &sc->sis_ldata.sis_tx_tag); 1028 1029 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1030 1, 0, /* alignment, boundary */ 1031 BUS_SPACE_MAXADDR, /* lowaddr */ 1032 BUS_SPACE_MAXADDR, /* highaddr */ 1033 NULL, NULL, /* filter, filterarg */ 1034 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1035 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1036 0, /* flags */ 1037 &sc->sis_tag); 1038 1039 /* 1040 * Now allocate a chunk of DMA-able memory based on the 1041 * tag we just created. 1042 */ 1043 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1044 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 1045 &sc->sis_ldata.sis_tx_dmamap); 1046 1047 if (error) { 1048 printf("sis%d: no memory for list buffers!\n", unit); 1049 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1050 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1051 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1052 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1053 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1054 error = ENXIO; 1055 goto fail; 1056 } 1057 1058 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1059 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 1060 &sc->sis_ldata.sis_rx_dmamap); 1061 1062 if (error) { 1063 printf("sis%d: no memory for list buffers!\n", unit); 1064 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1065 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1066 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1067 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1068 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1069 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1070 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1071 error = ENXIO; 1072 goto fail; 1073 } 1074 1075 1076 bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 1077 bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 1078 1079 /* 1080 * Obtain the physical addresses of the RX and TX 1081 * rings which we'll need later in the init routine. 1082 */ 1083 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1084 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1085 sizeof(struct sis_desc), sis_dma_map_ring, 1086 &sc->sis_cdata.sis_tx_paddr, 0); 1087 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1088 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1089 sizeof(struct sis_desc), sis_dma_map_ring, 1090 &sc->sis_cdata.sis_rx_paddr, 0); 1091 1092 ifp = &sc->arpcom.ac_if; 1093 ifp->if_softc = sc; 1094 ifp->if_unit = unit; 1095 ifp->if_name = "sis"; 1096 ifp->if_mtu = ETHERMTU; 1097 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1098 ifp->if_ioctl = sis_ioctl; 1099 ifp->if_output = ether_output; 1100 ifp->if_start = sis_start; 1101 ifp->if_watchdog = sis_watchdog; 1102 ifp->if_init = sis_init; 1103 ifp->if_baudrate = 10000000; 1104 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1105 1106 /* 1107 * Do MII setup. 1108 */ 1109 if (mii_phy_probe(dev, &sc->sis_miibus, 1110 sis_ifmedia_upd, sis_ifmedia_sts)) { 1111 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1112 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1113 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1114 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1115 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1116 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1117 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1118 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1119 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1120 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1121 error = ENXIO; 1122 goto fail; 1123 } 1124 1125 /* 1126 * Call MI attach routine. 1127 */ 1128 ether_ifattach(ifp, eaddr); 1129 1130 /* 1131 * Tell the upper layer(s) we support long frames. 1132 */ 1133 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1134 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1135 1136 callout_handle_init(&sc->sis_stat_ch); 1137 return(0); 1138 1139 fail: 1140 mtx_destroy(&sc->sis_mtx); 1141 return(error); 1142 } 1143 1144 static int 1145 sis_detach(dev) 1146 device_t dev; 1147 { 1148 struct sis_softc *sc; 1149 struct ifnet *ifp; 1150 1151 1152 sc = device_get_softc(dev); 1153 SIS_LOCK(sc); 1154 ifp = &sc->arpcom.ac_if; 1155 1156 sis_reset(sc); 1157 sis_stop(sc); 1158 ether_ifdetach(ifp); 1159 1160 bus_generic_detach(dev); 1161 device_delete_child(dev, sc->sis_miibus); 1162 1163 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1164 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1165 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1166 1167 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1168 sc->sis_ldata.sis_rx_dmamap); 1169 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1170 sc->sis_ldata.sis_tx_dmamap); 1171 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1172 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1173 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1174 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1175 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1176 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1177 bus_dma_tag_destroy(sc->sis_parent_tag); 1178 1179 SIS_UNLOCK(sc); 1180 mtx_destroy(&sc->sis_mtx); 1181 1182 return(0); 1183 } 1184 1185 /* 1186 * Initialize the transmit descriptors. 1187 */ 1188 static int 1189 sis_list_tx_init(sc) 1190 struct sis_softc *sc; 1191 { 1192 struct sis_list_data *ld; 1193 struct sis_ring_data *cd; 1194 int i, nexti; 1195 1196 cd = &sc->sis_cdata; 1197 ld = &sc->sis_ldata; 1198 1199 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1200 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1201 ld->sis_tx_list[i].sis_nextdesc = 1202 &ld->sis_tx_list[nexti]; 1203 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1204 sc->sis_ldata.sis_tx_dmamap, 1205 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1206 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1207 ld->sis_tx_list[i].sis_mbuf = NULL; 1208 ld->sis_tx_list[i].sis_ptr = 0; 1209 ld->sis_tx_list[i].sis_ctl = 0; 1210 } 1211 1212 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1213 1214 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1215 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1216 1217 return(0); 1218 } 1219 1220 /* 1221 * Initialize the RX descriptors and allocate mbufs for them. Note that 1222 * we arrange the descriptors in a closed ring, so that the last descriptor 1223 * points back to the first. 1224 */ 1225 static int 1226 sis_list_rx_init(sc) 1227 struct sis_softc *sc; 1228 { 1229 struct sis_list_data *ld; 1230 struct sis_ring_data *cd; 1231 int i,nexti; 1232 1233 ld = &sc->sis_ldata; 1234 cd = &sc->sis_cdata; 1235 1236 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1237 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1238 return(ENOBUFS); 1239 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1240 ld->sis_rx_list[i].sis_nextdesc = 1241 &ld->sis_rx_list[nexti]; 1242 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1243 sc->sis_ldata.sis_rx_dmamap, 1244 &ld->sis_rx_list[nexti], 1245 sizeof(struct sis_desc), sis_dma_map_desc_next, 1246 &ld->sis_rx_list[i], 0); 1247 } 1248 1249 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1250 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1251 1252 cd->sis_rx_prod = 0; 1253 1254 return(0); 1255 } 1256 1257 /* 1258 * Initialize an RX descriptor and attach an MBUF cluster. 1259 */ 1260 static int 1261 sis_newbuf(sc, c, m) 1262 struct sis_softc *sc; 1263 struct sis_desc *c; 1264 struct mbuf *m; 1265 { 1266 1267 if (c == NULL) 1268 return(EINVAL); 1269 1270 if (m == NULL) { 1271 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1272 if (m == NULL) 1273 return(ENOBUFS); 1274 } else 1275 m->m_data = m->m_ext.ext_buf; 1276 1277 c->sis_mbuf = m; 1278 c->sis_ctl = SIS_RXLEN; 1279 1280 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1281 bus_dmamap_load(sc->sis_tag, c->sis_map, 1282 mtod(m, void *), MCLBYTES, 1283 sis_dma_map_desc_ptr, c, 0); 1284 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1285 1286 return(0); 1287 } 1288 1289 /* 1290 * A frame has been uploaded: pass the resulting mbuf chain up to 1291 * the higher level protocols. 1292 */ 1293 static void 1294 sis_rxeof(sc) 1295 struct sis_softc *sc; 1296 { 1297 struct mbuf *m; 1298 struct ifnet *ifp; 1299 struct sis_desc *cur_rx; 1300 int i, total_len = 0; 1301 u_int32_t rxstat; 1302 1303 ifp = &sc->arpcom.ac_if; 1304 i = sc->sis_cdata.sis_rx_prod; 1305 1306 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1307 1308 #ifdef DEVICE_POLLING 1309 if (ifp->if_flags & IFF_POLLING) { 1310 if (sc->rxcycles <= 0) 1311 break; 1312 sc->rxcycles--; 1313 } 1314 #endif /* DEVICE_POLLING */ 1315 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1316 rxstat = cur_rx->sis_rxstat; 1317 bus_dmamap_sync(sc->sis_tag, 1318 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1319 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1320 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1321 m = cur_rx->sis_mbuf; 1322 cur_rx->sis_mbuf = NULL; 1323 total_len = SIS_RXBYTES(cur_rx); 1324 SIS_INC(i, SIS_RX_LIST_CNT); 1325 1326 /* 1327 * If an error occurs, update stats, clear the 1328 * status word and leave the mbuf cluster in place: 1329 * it should simply get re-used next time this descriptor 1330 * comes up in the ring. 1331 */ 1332 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1333 ifp->if_ierrors++; 1334 if (rxstat & SIS_RXSTAT_COLL) 1335 ifp->if_collisions++; 1336 sis_newbuf(sc, cur_rx, m); 1337 continue; 1338 } 1339 1340 /* No errors; receive the packet. */ 1341 #ifdef __i386__ 1342 /* 1343 * On the x86 we do not have alignment problems, so try to 1344 * allocate a new buffer for the receive ring, and pass up 1345 * the one where the packet is already, saving the expensive 1346 * copy done in m_devget(). 1347 * If we are on an architecture with alignment problems, or 1348 * if the allocation fails, then use m_devget and leave the 1349 * existing buffer in the receive ring. 1350 */ 1351 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1352 m->m_pkthdr.len = m->m_len = total_len; 1353 else 1354 #endif 1355 { 1356 struct mbuf *m0; 1357 m0 = m_devget(mtod(m, char *), total_len, 1358 ETHER_ALIGN, ifp, NULL); 1359 sis_newbuf(sc, cur_rx, m); 1360 if (m0 == NULL) { 1361 ifp->if_ierrors++; 1362 continue; 1363 } 1364 m = m0; 1365 } 1366 1367 ifp->if_ipackets++; 1368 m->m_pkthdr.rcvif = ifp; 1369 1370 (*ifp->if_input)(ifp, m); 1371 } 1372 1373 sc->sis_cdata.sis_rx_prod = i; 1374 1375 return; 1376 } 1377 1378 static void 1379 sis_rxeoc(sc) 1380 struct sis_softc *sc; 1381 { 1382 sis_rxeof(sc); 1383 sis_init(sc); 1384 return; 1385 } 1386 1387 /* 1388 * A frame was downloaded to the chip. It's safe for us to clean up 1389 * the list buffers. 1390 */ 1391 1392 static void 1393 sis_txeof(sc) 1394 struct sis_softc *sc; 1395 { 1396 struct ifnet *ifp; 1397 u_int32_t idx; 1398 1399 ifp = &sc->arpcom.ac_if; 1400 1401 /* 1402 * Go through our tx list and free mbufs for those 1403 * frames that have been transmitted. 1404 */ 1405 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1406 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1407 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1408 1409 if (SIS_OWNDESC(cur_tx)) 1410 break; 1411 1412 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1413 continue; 1414 1415 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1416 ifp->if_oerrors++; 1417 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1418 ifp->if_collisions++; 1419 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1420 ifp->if_collisions++; 1421 } 1422 1423 ifp->if_collisions += 1424 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1425 1426 ifp->if_opackets++; 1427 if (cur_tx->sis_mbuf != NULL) { 1428 m_freem(cur_tx->sis_mbuf); 1429 cur_tx->sis_mbuf = NULL; 1430 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1431 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1432 } 1433 } 1434 1435 if (idx != sc->sis_cdata.sis_tx_cons) { 1436 /* we freed up some buffers */ 1437 sc->sis_cdata.sis_tx_cons = idx; 1438 ifp->if_flags &= ~IFF_OACTIVE; 1439 } 1440 1441 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1442 1443 return; 1444 } 1445 1446 static void 1447 sis_tick(xsc) 1448 void *xsc; 1449 { 1450 struct sis_softc *sc; 1451 struct mii_data *mii; 1452 struct ifnet *ifp; 1453 1454 sc = xsc; 1455 SIS_LOCK(sc); 1456 ifp = &sc->arpcom.ac_if; 1457 1458 mii = device_get_softc(sc->sis_miibus); 1459 mii_tick(mii); 1460 1461 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1462 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1463 sc->sis_link++; 1464 if (ifp->if_snd.ifq_head != NULL) 1465 sis_start(ifp); 1466 } 1467 1468 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1469 1470 SIS_UNLOCK(sc); 1471 1472 return; 1473 } 1474 1475 #ifdef DEVICE_POLLING 1476 static poll_handler_t sis_poll; 1477 1478 static void 1479 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1480 { 1481 struct sis_softc *sc = ifp->if_softc; 1482 1483 SIS_LOCK(sc); 1484 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1485 CSR_WRITE_4(sc, SIS_IER, 1); 1486 goto done; 1487 } 1488 1489 /* 1490 * On the sis, reading the status register also clears it. 1491 * So before returning to intr mode we must make sure that all 1492 * possible pending sources of interrupts have been served. 1493 * In practice this means run to completion the *eof routines, 1494 * and then call the interrupt routine 1495 */ 1496 sc->rxcycles = count; 1497 sis_rxeof(sc); 1498 sis_txeof(sc); 1499 if (ifp->if_snd.ifq_head != NULL) 1500 sis_start(ifp); 1501 1502 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1503 u_int32_t status; 1504 1505 /* Reading the ISR register clears all interrupts. */ 1506 status = CSR_READ_4(sc, SIS_ISR); 1507 1508 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1509 sis_rxeoc(sc); 1510 1511 if (status & (SIS_ISR_RX_IDLE)) 1512 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1513 1514 if (status & SIS_ISR_SYSERR) { 1515 sis_reset(sc); 1516 sis_init(sc); 1517 } 1518 } 1519 done: 1520 SIS_UNLOCK(sc); 1521 return; 1522 } 1523 #endif /* DEVICE_POLLING */ 1524 1525 static void 1526 sis_intr(arg) 1527 void *arg; 1528 { 1529 struct sis_softc *sc; 1530 struct ifnet *ifp; 1531 u_int32_t status; 1532 1533 sc = arg; 1534 ifp = &sc->arpcom.ac_if; 1535 1536 SIS_LOCK(sc); 1537 #ifdef DEVICE_POLLING 1538 if (ifp->if_flags & IFF_POLLING) 1539 goto done; 1540 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1541 CSR_WRITE_4(sc, SIS_IER, 0); 1542 goto done; 1543 } 1544 #endif /* DEVICE_POLLING */ 1545 1546 /* Supress unwanted interrupts */ 1547 if (!(ifp->if_flags & IFF_UP)) { 1548 sis_stop(sc); 1549 goto done; 1550 } 1551 1552 /* Disable interrupts. */ 1553 CSR_WRITE_4(sc, SIS_IER, 0); 1554 1555 for (;;) { 1556 /* Reading the ISR register clears all interrupts. */ 1557 status = CSR_READ_4(sc, SIS_ISR); 1558 1559 if ((status & SIS_INTRS) == 0) 1560 break; 1561 1562 if (status & 1563 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1564 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1565 sis_txeof(sc); 1566 1567 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1568 sis_rxeof(sc); 1569 1570 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1571 sis_rxeoc(sc); 1572 1573 if (status & (SIS_ISR_RX_IDLE)) 1574 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1575 1576 if (status & SIS_ISR_SYSERR) { 1577 sis_reset(sc); 1578 sis_init(sc); 1579 } 1580 } 1581 1582 /* Re-enable interrupts. */ 1583 CSR_WRITE_4(sc, SIS_IER, 1); 1584 1585 if (ifp->if_snd.ifq_head != NULL) 1586 sis_start(ifp); 1587 done: 1588 SIS_UNLOCK(sc); 1589 1590 return; 1591 } 1592 1593 /* 1594 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1595 * pointers to the fragment pointers. 1596 */ 1597 static int 1598 sis_encap(sc, m_head, txidx) 1599 struct sis_softc *sc; 1600 struct mbuf *m_head; 1601 u_int32_t *txidx; 1602 { 1603 struct sis_desc *f = NULL; 1604 struct mbuf *m; 1605 int frag, cur, cnt = 0; 1606 1607 /* 1608 * Start packing the mbufs in this chain into 1609 * the fragment pointers. Stop when we run out 1610 * of fragments or hit the end of the mbuf chain. 1611 */ 1612 m = m_head; 1613 cur = frag = *txidx; 1614 1615 for (m = m_head; m != NULL; m = m->m_next) { 1616 if (m->m_len != 0) { 1617 if ((SIS_TX_LIST_CNT - 1618 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1619 return(ENOBUFS); 1620 f = &sc->sis_ldata.sis_tx_list[frag]; 1621 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1622 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1623 bus_dmamap_load(sc->sis_tag, f->sis_map, 1624 mtod(m, void *), m->m_len, 1625 sis_dma_map_desc_ptr, f, 0); 1626 bus_dmamap_sync(sc->sis_tag, 1627 f->sis_map, BUS_DMASYNC_PREREAD); 1628 if (cnt != 0) 1629 f->sis_ctl |= SIS_CMDSTS_OWN; 1630 cur = frag; 1631 SIS_INC(frag, SIS_TX_LIST_CNT); 1632 cnt++; 1633 } 1634 } 1635 1636 if (m != NULL) 1637 return(ENOBUFS); 1638 1639 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1640 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1641 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1642 sc->sis_cdata.sis_tx_cnt += cnt; 1643 *txidx = frag; 1644 1645 return(0); 1646 } 1647 1648 /* 1649 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1650 * to the mbuf data regions directly in the transmit lists. We also save a 1651 * copy of the pointers since the transmit list fragment pointers are 1652 * physical addresses. 1653 */ 1654 1655 static void 1656 sis_start(ifp) 1657 struct ifnet *ifp; 1658 { 1659 struct sis_softc *sc; 1660 struct mbuf *m_head = NULL; 1661 u_int32_t idx; 1662 1663 sc = ifp->if_softc; 1664 SIS_LOCK(sc); 1665 1666 if (!sc->sis_link) { 1667 SIS_UNLOCK(sc); 1668 return; 1669 } 1670 1671 idx = sc->sis_cdata.sis_tx_prod; 1672 1673 if (ifp->if_flags & IFF_OACTIVE) { 1674 SIS_UNLOCK(sc); 1675 return; 1676 } 1677 1678 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1679 IF_DEQUEUE(&ifp->if_snd, m_head); 1680 if (m_head == NULL) 1681 break; 1682 1683 if (sis_encap(sc, m_head, &idx)) { 1684 IF_PREPEND(&ifp->if_snd, m_head); 1685 ifp->if_flags |= IFF_OACTIVE; 1686 break; 1687 } 1688 1689 /* 1690 * If there's a BPF listener, bounce a copy of this frame 1691 * to him. 1692 */ 1693 BPF_MTAP(ifp, m_head); 1694 1695 } 1696 1697 /* Transmit */ 1698 sc->sis_cdata.sis_tx_prod = idx; 1699 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1700 1701 /* 1702 * Set a timeout in case the chip goes out to lunch. 1703 */ 1704 ifp->if_timer = 5; 1705 1706 SIS_UNLOCK(sc); 1707 1708 return; 1709 } 1710 1711 static void 1712 sis_init(xsc) 1713 void *xsc; 1714 { 1715 struct sis_softc *sc = xsc; 1716 struct ifnet *ifp = &sc->arpcom.ac_if; 1717 struct mii_data *mii; 1718 1719 SIS_LOCK(sc); 1720 1721 /* 1722 * Cancel pending I/O and free all RX/TX buffers. 1723 */ 1724 sis_stop(sc); 1725 1726 mii = device_get_softc(sc->sis_miibus); 1727 1728 /* Set MAC address */ 1729 if (sc->sis_type == SIS_TYPE_83815) { 1730 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1731 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1732 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1733 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1734 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1735 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1736 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1737 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1738 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1739 } else { 1740 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1741 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1742 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1743 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1744 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1745 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1746 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1747 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1748 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1749 } 1750 1751 /* Init circular RX list. */ 1752 if (sis_list_rx_init(sc) == ENOBUFS) { 1753 printf("sis%d: initialization failed: no " 1754 "memory for rx buffers\n", sc->sis_unit); 1755 sis_stop(sc); 1756 SIS_UNLOCK(sc); 1757 return; 1758 } 1759 1760 /* 1761 * Init tx descriptors. 1762 */ 1763 sis_list_tx_init(sc); 1764 1765 /* 1766 * For the NatSemi chip, we have to explicitly enable the 1767 * reception of ARP frames, as well as turn on the 'perfect 1768 * match' filter where we store the station address, otherwise 1769 * we won't receive unicasts meant for this host. 1770 */ 1771 if (sc->sis_type == SIS_TYPE_83815) { 1772 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1773 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1774 } 1775 1776 /* If we want promiscuous mode, set the allframes bit. */ 1777 if (ifp->if_flags & IFF_PROMISC) { 1778 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1779 } else { 1780 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1781 } 1782 1783 /* 1784 * Set the capture broadcast bit to capture broadcast frames. 1785 */ 1786 if (ifp->if_flags & IFF_BROADCAST) { 1787 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1788 } else { 1789 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1790 } 1791 1792 /* 1793 * Load the multicast filter. 1794 */ 1795 if (sc->sis_type == SIS_TYPE_83815) 1796 sis_setmulti_ns(sc); 1797 else 1798 sis_setmulti_sis(sc); 1799 1800 /* Turn the receive filter on */ 1801 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1802 1803 /* 1804 * Load the address of the RX and TX lists. 1805 */ 1806 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1807 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1808 1809 /* Set RX configuration */ 1810 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1811 1812 /* Accept Long Packets for VLAN support */ 1813 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1814 1815 /* Set TX configuration */ 1816 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1817 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1818 } else { 1819 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1820 } 1821 1822 /* Set full/half duplex mode. */ 1823 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1824 SIS_SETBIT(sc, SIS_TX_CFG, 1825 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1826 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1827 } else { 1828 SIS_CLRBIT(sc, SIS_TX_CFG, 1829 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1830 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1831 } 1832 1833 /* 1834 * Enable interrupts. 1835 */ 1836 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1837 #ifdef DEVICE_POLLING 1838 /* 1839 * ... only enable interrupts if we are not polling, make sure 1840 * they are off otherwise. 1841 */ 1842 if (ifp->if_flags & IFF_POLLING) 1843 CSR_WRITE_4(sc, SIS_IER, 0); 1844 else 1845 #endif /* DEVICE_POLLING */ 1846 CSR_WRITE_4(sc, SIS_IER, 1); 1847 1848 /* Enable receiver and transmitter. */ 1849 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1850 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1851 1852 #ifdef notdef 1853 mii_mediachg(mii); 1854 #endif 1855 1856 /* 1857 * Page 75 of the DP83815 manual recommends the 1858 * following register settings "for optimum 1859 * performance." Note however that at least three 1860 * of the registers are listed as "reserved" in 1861 * the register map, so who knows what they do. 1862 */ 1863 if (sc->sis_type == SIS_TYPE_83815) { 1864 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1865 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1866 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1867 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1868 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1869 } 1870 1871 ifp->if_flags |= IFF_RUNNING; 1872 ifp->if_flags &= ~IFF_OACTIVE; 1873 1874 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1875 1876 SIS_UNLOCK(sc); 1877 1878 return; 1879 } 1880 1881 /* 1882 * Set media options. 1883 */ 1884 static int 1885 sis_ifmedia_upd(ifp) 1886 struct ifnet *ifp; 1887 { 1888 struct sis_softc *sc; 1889 struct mii_data *mii; 1890 1891 sc = ifp->if_softc; 1892 1893 mii = device_get_softc(sc->sis_miibus); 1894 sc->sis_link = 0; 1895 if (mii->mii_instance) { 1896 struct mii_softc *miisc; 1897 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1898 mii_phy_reset(miisc); 1899 } 1900 mii_mediachg(mii); 1901 1902 return(0); 1903 } 1904 1905 /* 1906 * Report current media status. 1907 */ 1908 static void 1909 sis_ifmedia_sts(ifp, ifmr) 1910 struct ifnet *ifp; 1911 struct ifmediareq *ifmr; 1912 { 1913 struct sis_softc *sc; 1914 struct mii_data *mii; 1915 1916 sc = ifp->if_softc; 1917 1918 mii = device_get_softc(sc->sis_miibus); 1919 mii_pollstat(mii); 1920 ifmr->ifm_active = mii->mii_media_active; 1921 ifmr->ifm_status = mii->mii_media_status; 1922 1923 return; 1924 } 1925 1926 static int 1927 sis_ioctl(ifp, command, data) 1928 struct ifnet *ifp; 1929 u_long command; 1930 caddr_t data; 1931 { 1932 struct sis_softc *sc = ifp->if_softc; 1933 struct ifreq *ifr = (struct ifreq *) data; 1934 struct mii_data *mii; 1935 int error = 0; 1936 1937 switch(command) { 1938 case SIOCSIFFLAGS: 1939 if (ifp->if_flags & IFF_UP) { 1940 sis_init(sc); 1941 } else { 1942 if (ifp->if_flags & IFF_RUNNING) 1943 sis_stop(sc); 1944 } 1945 error = 0; 1946 break; 1947 case SIOCADDMULTI: 1948 case SIOCDELMULTI: 1949 SIS_LOCK(sc); 1950 if (sc->sis_type == SIS_TYPE_83815) 1951 sis_setmulti_ns(sc); 1952 else 1953 sis_setmulti_sis(sc); 1954 SIS_UNLOCK(sc); 1955 error = 0; 1956 break; 1957 case SIOCGIFMEDIA: 1958 case SIOCSIFMEDIA: 1959 mii = device_get_softc(sc->sis_miibus); 1960 SIS_LOCK(sc); 1961 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1962 SIS_UNLOCK(sc); 1963 break; 1964 default: 1965 error = ether_ioctl(ifp, command, data); 1966 break; 1967 } 1968 1969 return(error); 1970 } 1971 1972 static void 1973 sis_watchdog(ifp) 1974 struct ifnet *ifp; 1975 { 1976 struct sis_softc *sc; 1977 1978 sc = ifp->if_softc; 1979 1980 SIS_LOCK(sc); 1981 1982 ifp->if_oerrors++; 1983 printf("sis%d: watchdog timeout\n", sc->sis_unit); 1984 1985 sis_stop(sc); 1986 sis_reset(sc); 1987 sis_init(sc); 1988 1989 if (ifp->if_snd.ifq_head != NULL) 1990 sis_start(ifp); 1991 1992 SIS_UNLOCK(sc); 1993 1994 return; 1995 } 1996 1997 /* 1998 * Stop the adapter and free any mbufs allocated to the 1999 * RX and TX lists. 2000 */ 2001 static void 2002 sis_stop(sc) 2003 struct sis_softc *sc; 2004 { 2005 register int i; 2006 struct ifnet *ifp; 2007 2008 SIS_LOCK(sc); 2009 ifp = &sc->arpcom.ac_if; 2010 ifp->if_timer = 0; 2011 2012 untimeout(sis_tick, sc, sc->sis_stat_ch); 2013 2014 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2015 #ifdef DEVICE_POLLING 2016 ether_poll_deregister(ifp); 2017 #endif 2018 CSR_WRITE_4(sc, SIS_IER, 0); 2019 CSR_WRITE_4(sc, SIS_IMR, 0); 2020 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2021 DELAY(1000); 2022 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2023 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2024 2025 sc->sis_link = 0; 2026 2027 /* 2028 * Free data in the RX lists. 2029 */ 2030 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2031 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2032 bus_dmamap_unload(sc->sis_tag, 2033 sc->sis_ldata.sis_rx_list[i].sis_map); 2034 bus_dmamap_destroy(sc->sis_tag, 2035 sc->sis_ldata.sis_rx_list[i].sis_map); 2036 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2037 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2038 } 2039 } 2040 bzero(sc->sis_ldata.sis_rx_list, 2041 sizeof(sc->sis_ldata.sis_rx_list)); 2042 2043 /* 2044 * Free the TX list buffers. 2045 */ 2046 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2047 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2048 bus_dmamap_unload(sc->sis_tag, 2049 sc->sis_ldata.sis_tx_list[i].sis_map); 2050 bus_dmamap_destroy(sc->sis_tag, 2051 sc->sis_ldata.sis_tx_list[i].sis_map); 2052 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2053 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2054 } 2055 } 2056 2057 bzero(sc->sis_ldata.sis_tx_list, 2058 sizeof(sc->sis_ldata.sis_tx_list)); 2059 2060 SIS_UNLOCK(sc); 2061 2062 return; 2063 } 2064 2065 /* 2066 * Stop all chip I/O so that the kernel's probe routines don't 2067 * get confused by errant DMAs when rebooting. 2068 */ 2069 static void 2070 sis_shutdown(dev) 2071 device_t dev; 2072 { 2073 struct sis_softc *sc; 2074 2075 sc = device_get_softc(dev); 2076 SIS_LOCK(sc); 2077 sis_reset(sc); 2078 sis_stop(sc); 2079 SIS_UNLOCK(sc); 2080 2081 return; 2082 }
Cache object: fc1aa83023adaf591282ec2cfe7b82c9
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