The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sis.c

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 /*
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/5.1/sys/pci/if_sis.c 114770 2003-05-06 02:00:01Z cognet $
   33  */
   34 
   35 /*
   36  * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
   37  * available from http://www.sis.com.tw.
   38  *
   39  * This driver also supports the NatSemi DP83815. Datasheets are
   40  * available from http://www.national.com.
   41  *
   42  * Written by Bill Paul <wpaul@ee.columbia.edu>
   43  * Electrical Engineering Department
   44  * Columbia University, New York City
   45  */
   46 
   47 /*
   48  * The SiS 900 is a fairly simple chip. It uses bus master DMA with
   49  * simple TX and RX descriptors of 3 longwords in size. The receiver
   50  * has a single perfect filter entry for the station address and a
   51  * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
   52  * transceiver while the 7016 requires an external transceiver chip.
   53  * Both chips offer the standard bit-bang MII interface as well as
   54  * an enchanced PHY interface which simplifies accessing MII registers.
   55  *
   56  * The only downside to this chipset is that RX descriptors must be
   57  * longword aligned.
   58  */
   59 
   60 #include <sys/cdefs.h>
   61 __FBSDID("$FreeBSD: releng/5.1/sys/pci/if_sis.c 114770 2003-05-06 02:00:01Z cognet $");
   62 
   63 #include <sys/param.h>
   64 #include <sys/systm.h>
   65 #include <sys/sockio.h>
   66 #include <sys/mbuf.h>
   67 #include <sys/malloc.h>
   68 #include <sys/kernel.h>
   69 #include <sys/socket.h>
   70 #include <sys/sysctl.h>
   71 
   72 #include <net/if.h>
   73 #include <net/if_arp.h>
   74 #include <net/ethernet.h>
   75 #include <net/if_dl.h>
   76 #include <net/if_media.h>
   77 #include <net/if_types.h>
   78 #include <net/if_vlan_var.h>
   79 
   80 #include <net/bpf.h>
   81 
   82 #include <machine/bus_pio.h>
   83 #include <machine/bus_memio.h>
   84 #include <machine/bus.h>
   85 #include <machine/resource.h>
   86 #include <sys/bus.h>
   87 #include <sys/rman.h>
   88 
   89 #include <dev/mii/mii.h>
   90 #include <dev/mii/miivar.h>
   91 
   92 #include <pci/pcireg.h>
   93 #include <pci/pcivar.h>
   94 
   95 #define SIS_USEIOSPACE
   96 
   97 #include <pci/if_sisreg.h>
   98 
   99 MODULE_DEPEND(sis, pci, 1, 1, 1);
  100 MODULE_DEPEND(sis, ether, 1, 1, 1);
  101 MODULE_DEPEND(sis, miibus, 1, 1, 1);
  102 
  103 /* "controller miibus0" required.  See GENERIC if you get errors here. */
  104 #include "miibus_if.h"
  105 
  106 /*
  107  * Various supported device vendors/types and their names.
  108  */
  109 static struct sis_type sis_devs[] = {
  110         { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
  111         { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
  112         { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" },
  113         { 0, 0, NULL }
  114 };
  115 
  116 static int sis_probe            (device_t);
  117 static int sis_attach           (device_t);
  118 static int sis_detach           (device_t);
  119 
  120 static int sis_newbuf           (struct sis_softc *,
  121                                         struct sis_desc *, struct mbuf *);
  122 static int sis_encap            (struct sis_softc *,
  123                                         struct mbuf *, u_int32_t *);
  124 static void sis_rxeof           (struct sis_softc *);
  125 static void sis_rxeoc           (struct sis_softc *);
  126 static void sis_txeof           (struct sis_softc *);
  127 static void sis_intr            (void *);
  128 static void sis_tick            (void *);
  129 static void sis_start           (struct ifnet *);
  130 static int sis_ioctl            (struct ifnet *, u_long, caddr_t);
  131 static void sis_init            (void *);
  132 static void sis_stop            (struct sis_softc *);
  133 static void sis_watchdog                (struct ifnet *);
  134 static void sis_shutdown                (device_t);
  135 static int sis_ifmedia_upd      (struct ifnet *);
  136 static void sis_ifmedia_sts     (struct ifnet *, struct ifmediareq *);
  137 
  138 static u_int16_t sis_reverse    (u_int16_t);
  139 static void sis_delay           (struct sis_softc *);
  140 static void sis_eeprom_idle     (struct sis_softc *);
  141 static void sis_eeprom_putbyte  (struct sis_softc *, int);
  142 static void sis_eeprom_getword  (struct sis_softc *, int, u_int16_t *);
  143 static void sis_read_eeprom     (struct sis_softc *, caddr_t, int, int, int);
  144 #ifdef __i386__
  145 static void sis_read_cmos       (struct sis_softc *, device_t, caddr_t,
  146                                                         int, int);
  147 static void sis_read_mac        (struct sis_softc *, device_t, caddr_t);
  148 static device_t sis_find_bridge (device_t);
  149 #endif
  150 
  151 static void sis_mii_sync        (struct sis_softc *);
  152 static void sis_mii_send        (struct sis_softc *, u_int32_t, int);
  153 static int sis_mii_readreg      (struct sis_softc *, struct sis_mii_frame *);
  154 static int sis_mii_writereg     (struct sis_softc *, struct sis_mii_frame *);
  155 static int sis_miibus_readreg   (device_t, int, int);
  156 static int sis_miibus_writereg  (device_t, int, int, int);
  157 static void sis_miibus_statchg  (device_t);
  158 
  159 static void sis_setmulti_sis    (struct sis_softc *);
  160 static void sis_setmulti_ns     (struct sis_softc *);
  161 static u_int32_t sis_crc        (struct sis_softc *, caddr_t);
  162 static void sis_reset           (struct sis_softc *);
  163 static int sis_list_rx_init     (struct sis_softc *);
  164 static int sis_list_tx_init     (struct sis_softc *);
  165 
  166 static void sis_dma_map_desc_ptr        (void *, bus_dma_segment_t *, int, int);
  167 static void sis_dma_map_desc_next       (void *, bus_dma_segment_t *, int, int);
  168 static void sis_dma_map_ring            (void *, bus_dma_segment_t *, int, int);
  169 #ifdef SIS_USEIOSPACE
  170 #define SIS_RES                 SYS_RES_IOPORT
  171 #define SIS_RID                 SIS_PCI_LOIO
  172 #else
  173 #define SIS_RES                 SYS_RES_MEMORY
  174 #define SIS_RID                 SIS_PCI_LOMEM
  175 #endif
  176 
  177 static device_method_t sis_methods[] = {
  178         /* Device interface */
  179         DEVMETHOD(device_probe,         sis_probe),
  180         DEVMETHOD(device_attach,        sis_attach),
  181         DEVMETHOD(device_detach,        sis_detach),
  182         DEVMETHOD(device_shutdown,      sis_shutdown),
  183 
  184         /* bus interface */
  185         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  186         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  187 
  188         /* MII interface */
  189         DEVMETHOD(miibus_readreg,       sis_miibus_readreg),
  190         DEVMETHOD(miibus_writereg,      sis_miibus_writereg),
  191         DEVMETHOD(miibus_statchg,       sis_miibus_statchg),
  192 
  193         { 0, 0 }
  194 };
  195 
  196 static driver_t sis_driver = {
  197         "sis",
  198         sis_methods,
  199         sizeof(struct sis_softc)
  200 };
  201 
  202 static devclass_t sis_devclass;
  203 
  204 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
  205 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
  206 
  207 #define SIS_SETBIT(sc, reg, x)                          \
  208         CSR_WRITE_4(sc, reg,                            \
  209                 CSR_READ_4(sc, reg) | (x))
  210 
  211 #define SIS_CLRBIT(sc, reg, x)                          \
  212         CSR_WRITE_4(sc, reg,                            \
  213                 CSR_READ_4(sc, reg) & ~(x))
  214 
  215 #define SIO_SET(x)                                      \
  216         CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
  217 
  218 #define SIO_CLR(x)                                      \
  219         CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
  220 
  221 static void
  222 sis_dma_map_desc_next(arg, segs, nseg, error)
  223         void *arg;
  224         bus_dma_segment_t *segs;
  225         int nseg, error;
  226 {
  227         struct sis_desc *r;
  228 
  229         r = arg;
  230         r->sis_next = segs->ds_addr;
  231 
  232         return;
  233 }
  234 
  235 static void
  236 sis_dma_map_desc_ptr(arg, segs, nseg, error)
  237         void *arg;
  238         bus_dma_segment_t *segs;
  239         int nseg, error;
  240 {
  241         struct sis_desc *r;
  242 
  243         r = arg;
  244         r->sis_ptr = segs->ds_addr;
  245 
  246         return;
  247 }
  248 
  249 static void
  250 sis_dma_map_ring(arg, segs, nseg, error)
  251         void *arg;
  252         bus_dma_segment_t *segs;
  253         int nseg, error;
  254 {
  255         u_int32_t *p;
  256 
  257         p = arg;
  258         *p = segs->ds_addr;
  259 
  260         return;
  261 }
  262 
  263 /*
  264  * Routine to reverse the bits in a word. Stolen almost
  265  * verbatim from /usr/games/fortune.
  266  */
  267 static u_int16_t
  268 sis_reverse(n)
  269         u_int16_t               n;
  270 {
  271         n = ((n >>  1) & 0x5555) | ((n <<  1) & 0xaaaa);
  272         n = ((n >>  2) & 0x3333) | ((n <<  2) & 0xcccc);
  273         n = ((n >>  4) & 0x0f0f) | ((n <<  4) & 0xf0f0);
  274         n = ((n >>  8) & 0x00ff) | ((n <<  8) & 0xff00);
  275 
  276         return(n);
  277 }
  278 
  279 static void
  280 sis_delay(sc)
  281         struct sis_softc        *sc;
  282 {
  283         int                     idx;
  284 
  285         for (idx = (300 / 33) + 1; idx > 0; idx--)
  286                 CSR_READ_4(sc, SIS_CSR);
  287 
  288         return;
  289 }
  290 
  291 static void
  292 sis_eeprom_idle(sc)
  293         struct sis_softc        *sc;
  294 {
  295         register int            i;
  296 
  297         SIO_SET(SIS_EECTL_CSEL);
  298         sis_delay(sc);
  299         SIO_SET(SIS_EECTL_CLK);
  300         sis_delay(sc);
  301 
  302         for (i = 0; i < 25; i++) {
  303                 SIO_CLR(SIS_EECTL_CLK);
  304                 sis_delay(sc);
  305                 SIO_SET(SIS_EECTL_CLK);
  306                 sis_delay(sc);
  307         }
  308 
  309         SIO_CLR(SIS_EECTL_CLK);
  310         sis_delay(sc);
  311         SIO_CLR(SIS_EECTL_CSEL);
  312         sis_delay(sc);
  313         CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
  314 
  315         return;
  316 }
  317 
  318 /*
  319  * Send a read command and address to the EEPROM, check for ACK.
  320  */
  321 static void
  322 sis_eeprom_putbyte(sc, addr)
  323         struct sis_softc        *sc;
  324         int                     addr;
  325 {
  326         register int            d, i;
  327 
  328         d = addr | SIS_EECMD_READ;
  329 
  330         /*
  331          * Feed in each bit and stobe the clock.
  332          */
  333         for (i = 0x400; i; i >>= 1) {
  334                 if (d & i) {
  335                         SIO_SET(SIS_EECTL_DIN);
  336                 } else {
  337                         SIO_CLR(SIS_EECTL_DIN);
  338                 }
  339                 sis_delay(sc);
  340                 SIO_SET(SIS_EECTL_CLK);
  341                 sis_delay(sc);
  342                 SIO_CLR(SIS_EECTL_CLK);
  343                 sis_delay(sc);
  344         }
  345 
  346         return;
  347 }
  348 
  349 /*
  350  * Read a word of data stored in the EEPROM at address 'addr.'
  351  */
  352 static void
  353 sis_eeprom_getword(sc, addr, dest)
  354         struct sis_softc        *sc;
  355         int                     addr;
  356         u_int16_t               *dest;
  357 {
  358         register int            i;
  359         u_int16_t               word = 0;
  360 
  361         /* Force EEPROM to idle state. */
  362         sis_eeprom_idle(sc);
  363 
  364         /* Enter EEPROM access mode. */
  365         sis_delay(sc);
  366         SIO_CLR(SIS_EECTL_CLK);
  367         sis_delay(sc);
  368         SIO_SET(SIS_EECTL_CSEL);
  369         sis_delay(sc);
  370 
  371         /*
  372          * Send address of word we want to read.
  373          */
  374         sis_eeprom_putbyte(sc, addr);
  375 
  376         /*
  377          * Start reading bits from EEPROM.
  378          */
  379         for (i = 0x8000; i; i >>= 1) {
  380                 SIO_SET(SIS_EECTL_CLK);
  381                 sis_delay(sc);
  382                 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
  383                         word |= i;
  384                 sis_delay(sc);
  385                 SIO_CLR(SIS_EECTL_CLK);
  386                 sis_delay(sc);
  387         }
  388 
  389         /* Turn off EEPROM access mode. */
  390         sis_eeprom_idle(sc);
  391 
  392         *dest = word;
  393 
  394         return;
  395 }
  396 
  397 /*
  398  * Read a sequence of words from the EEPROM.
  399  */
  400 static void
  401 sis_read_eeprom(sc, dest, off, cnt, swap)
  402         struct sis_softc        *sc;
  403         caddr_t                 dest;
  404         int                     off;
  405         int                     cnt;
  406         int                     swap;
  407 {
  408         int                     i;
  409         u_int16_t               word = 0, *ptr;
  410 
  411         for (i = 0; i < cnt; i++) {
  412                 sis_eeprom_getword(sc, off + i, &word);
  413                 ptr = (u_int16_t *)(dest + (i * 2));
  414                 if (swap)
  415                         *ptr = ntohs(word);
  416                 else
  417                         *ptr = word;
  418         }
  419 
  420         return;
  421 }
  422 
  423 #ifdef __i386__
  424 static device_t
  425 sis_find_bridge(dev)
  426         device_t                dev;
  427 {
  428         devclass_t              pci_devclass;
  429         device_t                *pci_devices;
  430         int                     pci_count = 0;
  431         device_t                *pci_children;
  432         int                     pci_childcount = 0;
  433         device_t                *busp, *childp;
  434         device_t                child = NULL;
  435         int                     i, j;
  436 
  437         if ((pci_devclass = devclass_find("pci")) == NULL)
  438                 return(NULL);
  439 
  440         devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
  441 
  442         for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
  443                 pci_childcount = 0;
  444                 device_get_children(*busp, &pci_children, &pci_childcount);
  445                 for (j = 0, childp = pci_children;
  446                     j < pci_childcount; j++, childp++) {
  447                         if (pci_get_vendor(*childp) == SIS_VENDORID &&
  448                             pci_get_device(*childp) == 0x0008) {
  449                                 child = *childp;
  450                                 goto done;
  451                         }
  452                 }
  453         }
  454 
  455 done:
  456         free(pci_devices, M_TEMP);
  457         free(pci_children, M_TEMP);
  458         return(child);
  459 }
  460 
  461 static void
  462 sis_read_cmos(sc, dev, dest, off, cnt)
  463         struct sis_softc        *sc;
  464         device_t                dev;
  465         caddr_t                 dest;
  466         int                     off;
  467         int                     cnt;
  468 {
  469         device_t                bridge;
  470         u_int8_t                reg;
  471         int                     i;
  472         bus_space_tag_t         btag;
  473 
  474         bridge = sis_find_bridge(dev);
  475         if (bridge == NULL)
  476                 return;
  477         reg = pci_read_config(bridge, 0x48, 1);
  478         pci_write_config(bridge, 0x48, reg|0x40, 1);
  479 
  480         /* XXX */
  481         btag = I386_BUS_SPACE_IO;
  482 
  483         for (i = 0; i < cnt; i++) {
  484                 bus_space_write_1(btag, 0x0, 0x70, i + off);
  485                 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
  486         }
  487 
  488         pci_write_config(bridge, 0x48, reg & ~0x40, 1);
  489         return;
  490 }
  491 
  492 static void
  493 sis_read_mac(sc, dev, dest)
  494         struct sis_softc        *sc;
  495         device_t                dev;
  496         caddr_t                 dest;
  497 {
  498         u_int32_t               filtsave, csrsave;
  499 
  500         filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
  501         csrsave = CSR_READ_4(sc, SIS_CSR);
  502 
  503         CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
  504         CSR_WRITE_4(sc, SIS_CSR, 0);
  505                 
  506         CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
  507 
  508         CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
  509         ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
  510         CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
  511         ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
  512         CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
  513         ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
  514 
  515         CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
  516         CSR_WRITE_4(sc, SIS_CSR, csrsave);
  517         return;
  518 }
  519 #endif
  520 
  521 /*
  522  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  523  */
  524 static void sis_mii_sync(sc)
  525         struct sis_softc        *sc;
  526 {
  527         register int            i;
  528  
  529         SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
  530  
  531         for (i = 0; i < 32; i++) {
  532                 SIO_SET(SIS_MII_CLK);
  533                 DELAY(1);
  534                 SIO_CLR(SIS_MII_CLK);
  535                 DELAY(1);
  536         }
  537  
  538         return;
  539 }
  540  
  541 /*
  542  * Clock a series of bits through the MII.
  543  */
  544 static void sis_mii_send(sc, bits, cnt)
  545         struct sis_softc        *sc;
  546         u_int32_t               bits;
  547         int                     cnt;
  548 {
  549         int                     i;
  550  
  551         SIO_CLR(SIS_MII_CLK);
  552  
  553         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  554                 if (bits & i) {
  555                         SIO_SET(SIS_MII_DATA);
  556                 } else {
  557                         SIO_CLR(SIS_MII_DATA);
  558                 }
  559                 DELAY(1);
  560                 SIO_CLR(SIS_MII_CLK);
  561                 DELAY(1);
  562                 SIO_SET(SIS_MII_CLK);
  563         }
  564 }
  565  
  566 /*
  567  * Read an PHY register through the MII.
  568  */
  569 static int sis_mii_readreg(sc, frame)
  570         struct sis_softc        *sc;
  571         struct sis_mii_frame    *frame;
  572         
  573 {
  574         int                     i, ack, s;
  575  
  576         s = splimp();
  577  
  578         /*
  579          * Set up frame for RX.
  580          */
  581         frame->mii_stdelim = SIS_MII_STARTDELIM;
  582         frame->mii_opcode = SIS_MII_READOP;
  583         frame->mii_turnaround = 0;
  584         frame->mii_data = 0;
  585         
  586         /*
  587          * Turn on data xmit.
  588          */
  589         SIO_SET(SIS_MII_DIR);
  590 
  591         sis_mii_sync(sc);
  592  
  593         /*
  594          * Send command/address info.
  595          */
  596         sis_mii_send(sc, frame->mii_stdelim, 2);
  597         sis_mii_send(sc, frame->mii_opcode, 2);
  598         sis_mii_send(sc, frame->mii_phyaddr, 5);
  599         sis_mii_send(sc, frame->mii_regaddr, 5);
  600  
  601         /* Idle bit */
  602         SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
  603         DELAY(1);
  604         SIO_SET(SIS_MII_CLK);
  605         DELAY(1);
  606  
  607         /* Turn off xmit. */
  608         SIO_CLR(SIS_MII_DIR);
  609  
  610         /* Check for ack */
  611         SIO_CLR(SIS_MII_CLK);
  612         DELAY(1);
  613         ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
  614         SIO_SET(SIS_MII_CLK);
  615         DELAY(1);
  616  
  617         /*
  618          * Now try reading data bits. If the ack failed, we still
  619          * need to clock through 16 cycles to keep the PHY(s) in sync.
  620          */
  621         if (ack) {
  622                 for(i = 0; i < 16; i++) {
  623                         SIO_CLR(SIS_MII_CLK);
  624                         DELAY(1);
  625                         SIO_SET(SIS_MII_CLK);
  626                         DELAY(1);
  627                 }
  628                 goto fail;
  629         }
  630  
  631         for (i = 0x8000; i; i >>= 1) {
  632                 SIO_CLR(SIS_MII_CLK);
  633                 DELAY(1);
  634                 if (!ack) {
  635                         if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
  636                                 frame->mii_data |= i;
  637                         DELAY(1);
  638                 }
  639                 SIO_SET(SIS_MII_CLK);
  640                 DELAY(1);
  641         }
  642 
  643 fail:
  644 
  645         SIO_CLR(SIS_MII_CLK);
  646         DELAY(1);
  647         SIO_SET(SIS_MII_CLK);
  648         DELAY(1);
  649 
  650         splx(s);
  651 
  652         if (ack)
  653                 return(1);
  654         return(0);
  655 }
  656  
  657 /*
  658  * Write to a PHY register through the MII.
  659  */
  660 static int sis_mii_writereg(sc, frame)
  661         struct sis_softc        *sc;
  662         struct sis_mii_frame    *frame;
  663         
  664 {
  665         int                     s;
  666  
  667          s = splimp();
  668         /*
  669          * Set up frame for TX.
  670          */
  671  
  672         frame->mii_stdelim = SIS_MII_STARTDELIM;
  673         frame->mii_opcode = SIS_MII_WRITEOP;
  674         frame->mii_turnaround = SIS_MII_TURNAROUND;
  675         
  676         /*
  677          * Turn on data output.
  678          */
  679         SIO_SET(SIS_MII_DIR);
  680  
  681         sis_mii_sync(sc);
  682  
  683         sis_mii_send(sc, frame->mii_stdelim, 2);
  684         sis_mii_send(sc, frame->mii_opcode, 2);
  685         sis_mii_send(sc, frame->mii_phyaddr, 5);
  686         sis_mii_send(sc, frame->mii_regaddr, 5);
  687         sis_mii_send(sc, frame->mii_turnaround, 2);
  688         sis_mii_send(sc, frame->mii_data, 16);
  689  
  690         /* Idle bit. */
  691         SIO_SET(SIS_MII_CLK);
  692         DELAY(1);
  693         SIO_CLR(SIS_MII_CLK);
  694         DELAY(1);
  695  
  696         /*
  697          * Turn off xmit.
  698          */
  699         SIO_CLR(SIS_MII_DIR);
  700  
  701         splx(s);
  702  
  703         return(0);
  704 }
  705 
  706 static int
  707 sis_miibus_readreg(dev, phy, reg)
  708         device_t                dev;
  709         int                     phy, reg;
  710 {
  711         struct sis_softc        *sc;
  712         struct sis_mii_frame    frame;
  713 
  714         sc = device_get_softc(dev);
  715 
  716         if (sc->sis_type == SIS_TYPE_83815) {
  717                 if (phy != 0)
  718                         return(0);
  719                 /*
  720                  * The NatSemi chip can take a while after
  721                  * a reset to come ready, during which the BMSR
  722                  * returns a value of 0. This is *never* supposed
  723                  * to happen: some of the BMSR bits are meant to
  724                  * be hardwired in the on position, and this can
  725                  * confuse the miibus code a bit during the probe
  726                  * and attach phase. So we make an effort to check
  727                  * for this condition and wait for it to clear.
  728                  */
  729                 if (!CSR_READ_4(sc, NS_BMSR))
  730                         DELAY(1000);
  731                 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
  732         }
  733 
  734         /*
  735          * Chipsets < SIS_635 seem not to be able to read/write
  736          * through mdio. Use the enhanced PHY access register
  737          * again for them.
  738          */
  739         if (sc->sis_type == SIS_TYPE_900 &&
  740             sc->sis_rev < SIS_REV_635) {
  741                 int i, val = 0;
  742 
  743                 if (phy != 0)
  744                         return(0);
  745 
  746                 CSR_WRITE_4(sc, SIS_PHYCTL,
  747                     (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
  748                 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
  749 
  750                 for (i = 0; i < SIS_TIMEOUT; i++) {
  751                         if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
  752                                 break;
  753                 }
  754 
  755                 if (i == SIS_TIMEOUT) {
  756                         printf("sis%d: PHY failed to come ready\n",
  757                             sc->sis_unit);
  758                         return(0);
  759                 }
  760 
  761                 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
  762 
  763                 if (val == 0xFFFF)
  764                         return(0);
  765 
  766                 return(val);
  767         } else {
  768                 bzero((char *)&frame, sizeof(frame));
  769 
  770                 frame.mii_phyaddr = phy;
  771                 frame.mii_regaddr = reg;
  772                 sis_mii_readreg(sc, &frame);
  773 
  774                 return(frame.mii_data);
  775         }
  776 }
  777 
  778 static int
  779 sis_miibus_writereg(dev, phy, reg, data)
  780         device_t                dev;
  781         int                     phy, reg, data;
  782 {
  783         struct sis_softc        *sc;
  784         struct sis_mii_frame    frame;
  785 
  786         sc = device_get_softc(dev);
  787 
  788         if (sc->sis_type == SIS_TYPE_83815) {
  789                 if (phy != 0)
  790                         return(0);
  791                 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
  792                 return(0);
  793         }
  794 
  795         /*
  796          * Chipsets < SIS_635 seem not to be able to read/write
  797          * through mdio. Use the enhanced PHY access register
  798          * again for them.
  799          */
  800         if (sc->sis_type == SIS_TYPE_900 &&
  801             sc->sis_rev < SIS_REV_635) {
  802                 int i;
  803 
  804                 if (phy != 0)
  805                         return(0);
  806 
  807                 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
  808                     (reg << 6) | SIS_PHYOP_WRITE);
  809                 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
  810 
  811                 for (i = 0; i < SIS_TIMEOUT; i++) {
  812                         if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
  813                                 break;
  814                 }
  815 
  816                 if (i == SIS_TIMEOUT)
  817                         printf("sis%d: PHY failed to come ready\n",
  818                             sc->sis_unit);
  819         } else {
  820                 bzero((char *)&frame, sizeof(frame));
  821 
  822                 frame.mii_phyaddr = phy;
  823                 frame.mii_regaddr = reg;
  824                 frame.mii_data = data;
  825                 sis_mii_writereg(sc, &frame);
  826         }
  827         return(0);
  828 }
  829 
  830 static void
  831 sis_miibus_statchg(dev)
  832         device_t                dev;
  833 {
  834         struct sis_softc        *sc;
  835 
  836         sc = device_get_softc(dev);
  837         sis_init(sc);
  838 
  839         return;
  840 }
  841 
  842 static u_int32_t
  843 sis_crc(sc, addr)
  844         struct sis_softc        *sc;
  845         caddr_t                 addr;
  846 {
  847         u_int32_t               crc, carry; 
  848         int                     i, j;
  849         u_int8_t                c;
  850 
  851         /* Compute CRC for the address value. */
  852         crc = 0xFFFFFFFF; /* initial value */
  853 
  854         for (i = 0; i < 6; i++) {
  855                 c = *(addr + i);
  856                 for (j = 0; j < 8; j++) {
  857                         carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
  858                         crc <<= 1;
  859                         c >>= 1;
  860                         if (carry)
  861                                 crc = (crc ^ 0x04c11db6) | carry;
  862                 }
  863         }
  864 
  865         /*
  866          * return the filter bit position
  867          *
  868          * The NatSemi chip has a 512-bit filter, which is
  869          * different than the SiS, so we special-case it.
  870          */
  871         if (sc->sis_type == SIS_TYPE_83815)
  872                 return (crc >> 23);
  873         else if (sc->sis_rev >= SIS_REV_635 ||
  874             sc->sis_rev == SIS_REV_900B)
  875                 return (crc >> 24);
  876         else
  877                 return (crc >> 25);
  878 }
  879 
  880 static void
  881 sis_setmulti_ns(sc)
  882         struct sis_softc        *sc;
  883 {
  884         struct ifnet            *ifp;
  885         struct ifmultiaddr      *ifma;
  886         u_int32_t               h = 0, i, filtsave;
  887         int                     bit, index;
  888 
  889         ifp = &sc->arpcom.ac_if;
  890 
  891         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  892                 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
  893                 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
  894                 return;
  895         }
  896 
  897         /*
  898          * We have to explicitly enable the multicast hash table
  899          * on the NatSemi chip if we want to use it, which we do.
  900          */
  901         SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
  902         SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
  903 
  904         filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
  905 
  906         /* first, zot all the existing hash bits */
  907         for (i = 0; i < 32; i++) {
  908                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
  909                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
  910         }
  911 
  912         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  913                 if (ifma->ifma_addr->sa_family != AF_LINK)
  914                         continue;
  915                 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  916                 index = h >> 3;
  917                 bit = h & 0x1F;
  918                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
  919                 if (bit > 0xF)
  920                         bit -= 0x10;
  921                 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
  922         }
  923 
  924         CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
  925 
  926         return;
  927 }
  928 
  929 static void
  930 sis_setmulti_sis(sc)
  931         struct sis_softc        *sc;
  932 {
  933         struct ifnet            *ifp;
  934         struct ifmultiaddr      *ifma;
  935         u_int32_t               h, i, n, ctl;
  936         u_int16_t               hashes[16];
  937 
  938         ifp = &sc->arpcom.ac_if;
  939 
  940         /* hash table size */
  941         if (sc->sis_rev >= SIS_REV_635 ||
  942             sc->sis_rev == SIS_REV_900B)
  943                 n = 16;
  944         else
  945                 n = 8;
  946 
  947         ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
  948 
  949         if (ifp->if_flags & IFF_BROADCAST)
  950                 ctl |= SIS_RXFILTCTL_BROAD;
  951 
  952         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  953                 ctl |= SIS_RXFILTCTL_ALLMULTI;
  954                 if (ifp->if_flags & IFF_PROMISC)
  955                         ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
  956                 for (i = 0; i < n; i++)
  957                         hashes[i] = ~0;
  958         } else {
  959                 for (i = 0; i < n; i++)
  960                         hashes[i] = 0;
  961                 i = 0;
  962                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  963                         if (ifma->ifma_addr->sa_family != AF_LINK)
  964                         continue;
  965                         h = sis_crc(sc,
  966                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  967                         hashes[h >> 4] |= 1 << (h & 0xf);
  968                         i++;
  969                 }
  970                 if (i > n) {
  971                         ctl |= SIS_RXFILTCTL_ALLMULTI;
  972                         for (i = 0; i < n; i++)
  973                                 hashes[i] = ~0;
  974                 }
  975         }
  976 
  977         for (i = 0; i < n; i++) {
  978                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
  979                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
  980         }
  981 
  982         CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
  983 }
  984 
  985 static void
  986 sis_reset(sc)
  987         struct sis_softc        *sc;
  988 {
  989         register int            i;
  990 
  991         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
  992 
  993         for (i = 0; i < SIS_TIMEOUT; i++) {
  994                 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
  995                         break;
  996         }
  997 
  998         if (i == SIS_TIMEOUT)
  999                 printf("sis%d: reset never completed\n", sc->sis_unit);
 1000 
 1001         /* Wait a little while for the chip to get its brains in order. */
 1002         DELAY(1000);
 1003 
 1004         /*
 1005          * If this is a NetSemi chip, make sure to clear
 1006          * PME mode.
 1007          */
 1008         if (sc->sis_type == SIS_TYPE_83815) {
 1009                 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
 1010                 CSR_WRITE_4(sc, NS_CLKRUN, 0);
 1011         }
 1012 
 1013         return;
 1014 }
 1015 
 1016 /*
 1017  * Probe for an SiS chip. Check the PCI vendor and device
 1018  * IDs against our list and return a device name if we find a match.
 1019  */
 1020 static int
 1021 sis_probe(dev)
 1022         device_t                dev;
 1023 {
 1024         struct sis_type         *t;
 1025 
 1026         t = sis_devs;
 1027 
 1028         while(t->sis_name != NULL) {
 1029                 if ((pci_get_vendor(dev) == t->sis_vid) &&
 1030                     (pci_get_device(dev) == t->sis_did)) {
 1031                         device_set_desc(dev, t->sis_name);
 1032                         return(0);
 1033                 }
 1034                 t++;
 1035         }
 1036 
 1037         return(ENXIO);
 1038 }
 1039 
 1040 /*
 1041  * Attach the interface. Allocate softc structures, do ifmedia
 1042  * setup and ethernet/BPF attach.
 1043  */
 1044 static int
 1045 sis_attach(dev)
 1046         device_t                dev;
 1047 {
 1048         u_char                  eaddr[ETHER_ADDR_LEN];
 1049         struct sis_softc        *sc;
 1050         struct ifnet            *ifp;
 1051         int                     unit, error = 0, rid, waittime = 0;
 1052 
 1053         waittime = 0;
 1054         sc = device_get_softc(dev);
 1055         unit = device_get_unit(dev);
 1056 
 1057         mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 1058             MTX_DEF | MTX_RECURSE);
 1059 
 1060         if (pci_get_device(dev) == SIS_DEVICEID_900)
 1061                 sc->sis_type = SIS_TYPE_900;
 1062         if (pci_get_device(dev) == SIS_DEVICEID_7016)
 1063                 sc->sis_type = SIS_TYPE_7016;
 1064         if (pci_get_vendor(dev) == NS_VENDORID)
 1065                 sc->sis_type = SIS_TYPE_83815;
 1066 
 1067         sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
 1068 
 1069         /*
 1070          * Handle power management nonsense.
 1071          */
 1072         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 1073                 u_int32_t               iobase, membase, irq;
 1074 
 1075                 /* Save important PCI config data. */
 1076                 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
 1077                 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
 1078                 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
 1079 
 1080                 /* Reset the power state. */
 1081                 printf("sis%d: chip is in D%d power mode "
 1082                     "-- setting to D0\n", unit,
 1083                     pci_get_powerstate(dev));
 1084                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 1085 
 1086                 /* Restore PCI config data. */
 1087                 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
 1088                 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
 1089                 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
 1090         }
 1091 
 1092         /*
 1093          * Map control/status registers.
 1094          */
 1095         pci_enable_busmaster(dev);
 1096 
 1097         rid = SIS_RID;
 1098         sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid,
 1099             0, ~0, 1, RF_ACTIVE);
 1100 
 1101         if (sc->sis_res == NULL) {
 1102                 printf("sis%d: couldn't map ports/memory\n", unit);
 1103                 error = ENXIO;
 1104                 goto fail;
 1105         }
 1106 
 1107         sc->sis_btag = rman_get_bustag(sc->sis_res);
 1108         sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
 1109 
 1110         /* Allocate interrupt */
 1111         rid = 0;
 1112         sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
 1113             RF_SHAREABLE | RF_ACTIVE);
 1114 
 1115         if (sc->sis_irq == NULL) {
 1116                 printf("sis%d: couldn't map interrupt\n", unit);
 1117                 error = ENXIO;
 1118                 goto fail;
 1119         }
 1120 
 1121         /* Reset the adapter. */
 1122         sis_reset(sc);
 1123 
 1124         if (sc->sis_type == SIS_TYPE_900 &&
 1125             (sc->sis_rev == SIS_REV_635 ||
 1126             sc->sis_rev == SIS_REV_900B)) {
 1127                 SIO_SET(SIS_CFG_RND_CNT);
 1128                 SIO_SET(SIS_CFG_PERR_DETECT);
 1129         }
 1130 
 1131         /*
 1132          * Get station address from the EEPROM.
 1133          */
 1134         switch (pci_get_vendor(dev)) {
 1135         case NS_VENDORID:
 1136                 /*
 1137                  * Reading the MAC address out of the EEPROM on
 1138                  * the NatSemi chip takes a bit more work than
 1139                  * you'd expect. The address spans 4 16-bit words,
 1140                  * with the first word containing only a single bit.
 1141                  * You have to shift everything over one bit to
 1142                  * get it aligned properly. Also, the bits are
 1143                  * stored backwards (the LSB is really the MSB,
 1144                  * and so on) so you have to reverse them in order
 1145                  * to get the MAC address into the form we want.
 1146                  * Why? Who the hell knows.
 1147                  */
 1148                 {
 1149                         u_int16_t               tmp[4];
 1150 
 1151                         sis_read_eeprom(sc, (caddr_t)&tmp,
 1152                             NS_EE_NODEADDR, 4, 0);
 1153 
 1154                         /* Shift everything over one bit. */
 1155                         tmp[3] = tmp[3] >> 1;
 1156                         tmp[3] |= tmp[2] << 15;
 1157                         tmp[2] = tmp[2] >> 1;
 1158                         tmp[2] |= tmp[1] << 15;
 1159                         tmp[1] = tmp[1] >> 1;
 1160                         tmp[1] |= tmp[0] << 15;
 1161 
 1162                         /* Now reverse all the bits. */
 1163                         tmp[3] = sis_reverse(tmp[3]);
 1164                         tmp[2] = sis_reverse(tmp[2]);
 1165                         tmp[1] = sis_reverse(tmp[1]);
 1166 
 1167                         bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
 1168                 }
 1169                 break;
 1170         case SIS_VENDORID:
 1171         default:
 1172 #ifdef __i386__
 1173                 /*
 1174                  * If this is a SiS 630E chipset with an embedded
 1175                  * SiS 900 controller, we have to read the MAC address
 1176                  * from the APC CMOS RAM. Our method for doing this
 1177                  * is very ugly since we have to reach out and grab
 1178                  * ahold of hardware for which we cannot properly
 1179                  * allocate resources. This code is only compiled on
 1180                  * the i386 architecture since the SiS 630E chipset
 1181                  * is for x86 motherboards only. Note that there are
 1182                  * a lot of magic numbers in this hack. These are
 1183                  * taken from SiS's Linux driver. I'd like to replace
 1184                  * them with proper symbolic definitions, but that
 1185                  * requires some datasheets that I don't have access
 1186                  * to at the moment.
 1187                  */
 1188                 if (sc->sis_rev == SIS_REV_630S ||
 1189                     sc->sis_rev == SIS_REV_630E ||
 1190                     sc->sis_rev == SIS_REV_630EA1)
 1191                         sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
 1192 
 1193                 else if (sc->sis_rev == SIS_REV_635 ||
 1194                          sc->sis_rev == SIS_REV_630ET)
 1195                         sis_read_mac(sc, dev, (caddr_t)&eaddr);
 1196                 else if (sc->sis_rev == SIS_REV_96x) {
 1197                         /* Allow to read EEPROM from LAN. It is shared
 1198                          * between a 1394 controller and the NIC and each
 1199                          * time we access it, we need to set SIS_EECMD_REQ.
 1200                          */
 1201                         SIO_SET(SIS_EECMD_REQ);
 1202                         for (waittime = 0; waittime < SIS_TIMEOUT;
 1203                             waittime++) {
 1204                                 /* Force EEPROM to idle state. */
 1205                                 sis_eeprom_idle(sc);
 1206                                 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
 1207                                         sis_read_eeprom(sc, (caddr_t)&eaddr,
 1208                                             SIS_EE_NODEADDR, 3, 0);
 1209                                         break;
 1210                                 }
 1211                                 DELAY(1);
 1212                         }
 1213                         /*
 1214                          * Set SIS_EECTL_CLK to high, so a other master
 1215                          * can operate on the i2c bus.
 1216                          */
 1217                         SIO_SET(SIS_EECTL_CLK);
 1218                         /* Refuse EEPROM access by LAN */
 1219                         SIO_SET(SIS_EECMD_DONE);
 1220                 } else
 1221 #endif
 1222                         sis_read_eeprom(sc, (caddr_t)&eaddr,
 1223                             SIS_EE_NODEADDR, 3, 0);
 1224                 break;
 1225         }
 1226 
 1227         /*
 1228          * A SiS chip was detected. Inform the world.
 1229          */
 1230         printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":");
 1231 
 1232         sc->sis_unit = unit;
 1233         callout_handle_init(&sc->sis_stat_ch);
 1234         bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
 1235 
 1236         /*
 1237          * Allocate the parent bus DMA tag appropriate for PCI.
 1238          */
 1239 #define SIS_NSEG_NEW 32
 1240          error = bus_dma_tag_create(NULL,       /* parent */ 
 1241                         1, 0,                   /* alignment, boundary */
 1242                         BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
 1243                         BUS_SPACE_MAXADDR,      /* highaddr */
 1244                         NULL, NULL,             /* filter, filterarg */
 1245                         MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
 1246                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 
 1247                         BUS_DMA_ALLOCNOW,       /* flags */
 1248                         &sc->sis_parent_tag);
 1249         if (error)
 1250                 goto fail;
 1251 
 1252         /*
 1253          * Now allocate a tag for the DMA descriptor lists and a chunk
 1254          * of DMA-able memory based on the tag.  Also obtain the physical
 1255          * addresses of the RX and TX ring, which we'll need later.
 1256          * All of our lists are allocated as a contiguous block
 1257          * of memory.
 1258          */
 1259         error = bus_dma_tag_create(sc->sis_parent_tag,  /* parent */
 1260                         1, 0,                   /* alignment, boundary */
 1261                         BUS_SPACE_MAXADDR,      /* lowaddr */
 1262                         BUS_SPACE_MAXADDR,      /* highaddr */
 1263                         NULL, NULL,             /* filter, filterarg */
 1264                         SIS_RX_LIST_SZ, 1,      /* maxsize,nsegments */
 1265                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
 1266                         0,                      /* flags */
 1267                         &sc->sis_ldata.sis_rx_tag);
 1268         if (error)
 1269                 goto fail;
 1270 
 1271         error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
 1272             (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT,
 1273             &sc->sis_ldata.sis_rx_dmamap);
 1274 
 1275         if (error) {
 1276                 printf("sis%d: no memory for rx list buffers!\n", unit);
 1277                 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
 1278                 sc->sis_ldata.sis_rx_tag = NULL;
 1279                 goto fail;
 1280         }
 1281 
 1282         error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
 1283             sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]),
 1284             sizeof(struct sis_desc), sis_dma_map_ring,
 1285             &sc->sis_cdata.sis_rx_paddr, 0);
 1286 
 1287         if (error) {
 1288                 printf("sis%d: cannot get address of the rx ring!\n", unit);
 1289                 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
 1290                     sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap);
 1291                 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
 1292                 sc->sis_ldata.sis_rx_tag = NULL;
 1293                 goto fail;
 1294         }
 1295 
 1296         error = bus_dma_tag_create(sc->sis_parent_tag,  /* parent */
 1297                         1, 0,                   /* alignment, boundary */
 1298                         BUS_SPACE_MAXADDR,      /* lowaddr */
 1299                         BUS_SPACE_MAXADDR,      /* highaddr */
 1300                         NULL, NULL,             /* filter, filterarg */
 1301                         SIS_TX_LIST_SZ, 1,      /* maxsize,nsegments */
 1302                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
 1303                         0,                      /* flags */
 1304                         &sc->sis_ldata.sis_tx_tag);
 1305         if (error)
 1306                 goto fail;
 1307 
 1308         error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
 1309             (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT,
 1310             &sc->sis_ldata.sis_tx_dmamap);
 1311 
 1312         if (error) {
 1313                 printf("sis%d: no memory for tx list buffers!\n", unit);
 1314                 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
 1315                 sc->sis_ldata.sis_tx_tag = NULL;
 1316                 goto fail;
 1317         }
 1318 
 1319         error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
 1320             sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]),
 1321             sizeof(struct sis_desc), sis_dma_map_ring,
 1322             &sc->sis_cdata.sis_tx_paddr, 0);
 1323 
 1324         if (error) {
 1325                 printf("sis%d: cannot get address of the tx ring!\n", unit);
 1326                 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
 1327                     sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap);
 1328                 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
 1329                 sc->sis_ldata.sis_tx_tag = NULL;
 1330                 goto fail;
 1331         }
 1332 
 1333         error = bus_dma_tag_create(sc->sis_parent_tag,  /* parent */
 1334                         1, 0,                   /* alignment, boundary */
 1335                         BUS_SPACE_MAXADDR,      /* lowaddr */
 1336                         BUS_SPACE_MAXADDR,      /* highaddr */
 1337                         NULL, NULL,             /* filter, filterarg */
 1338                         MCLBYTES, 1,            /* maxsize,nsegments */
 1339                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
 1340                         0,                      /* flags */
 1341                         &sc->sis_tag);
 1342         if (error)
 1343                 goto fail;
 1344 
 1345         bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ);
 1346         bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ);
 1347 
 1348         /*
 1349          * Obtain the physical addresses of the RX and TX
 1350          * rings which we'll need later in the init routine.
 1351          */
 1352 
 1353         ifp = &sc->arpcom.ac_if;
 1354         ifp->if_softc = sc;
 1355         ifp->if_unit = unit;
 1356         ifp->if_name = "sis";
 1357         ifp->if_mtu = ETHERMTU;
 1358         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1359         ifp->if_ioctl = sis_ioctl;
 1360         ifp->if_output = ether_output;
 1361         ifp->if_start = sis_start;
 1362         ifp->if_watchdog = sis_watchdog;
 1363         ifp->if_init = sis_init;
 1364         ifp->if_baudrate = 10000000;
 1365         ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1;
 1366 
 1367         /*
 1368          * Do MII setup.
 1369          */
 1370         if (mii_phy_probe(dev, &sc->sis_miibus,
 1371             sis_ifmedia_upd, sis_ifmedia_sts)) {
 1372                 printf("sis%d: MII without any PHY!\n", sc->sis_unit);
 1373                 error = ENXIO;
 1374                 goto fail;
 1375         }
 1376 
 1377         /*
 1378          * Call MI attach routine.
 1379          */
 1380         ether_ifattach(ifp, eaddr);
 1381         
 1382         /*
 1383          * Tell the upper layer(s) we support long frames.
 1384          */
 1385         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 1386         ifp->if_capabilities |= IFCAP_VLAN_MTU;
 1387 
 1388         /* Hook interrupt last to avoid having to lock softc */
 1389         error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET,
 1390             sis_intr, sc, &sc->sis_intrhand);
 1391 
 1392         if (error) {
 1393                 printf("sis%d: couldn't set up irq\n", unit);
 1394                 ether_ifdetach(ifp);
 1395                 goto fail;
 1396         }
 1397 
 1398 fail:
 1399         if (error)
 1400                 sis_detach(dev);
 1401 
 1402         return(error);
 1403 }
 1404 
 1405 /*
 1406  * Shutdown hardware and free up resources. This can be called any
 1407  * time after the mutex has been initialized. It is called in both
 1408  * the error case in attach and the normal detach case so it needs
 1409  * to be careful about only freeing resources that have actually been
 1410  * allocated.
 1411  */
 1412 static int
 1413 sis_detach(dev)
 1414         device_t                dev;
 1415 {
 1416         struct sis_softc        *sc;
 1417         struct ifnet            *ifp;
 1418 
 1419         sc = device_get_softc(dev);
 1420         KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
 1421         SIS_LOCK(sc);
 1422         ifp = &sc->arpcom.ac_if;
 1423 
 1424         /* These should only be active if attach succeeded */
 1425         if (device_is_attached(dev)) {
 1426                 sis_reset(sc);
 1427                 sis_stop(sc);
 1428                 ether_ifdetach(ifp);
 1429         }
 1430         if (sc->sis_miibus)
 1431                 device_delete_child(dev, sc->sis_miibus);
 1432         bus_generic_detach(dev);
 1433 
 1434         if (sc->sis_intrhand)
 1435                 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
 1436         if (sc->sis_irq)
 1437                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
 1438         if (sc->sis_res)
 1439                 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
 1440 
 1441         if (sc->sis_ldata.sis_rx_tag) {
 1442                 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
 1443                     sc->sis_ldata.sis_rx_dmamap);
 1444                 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
 1445                     sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap);
 1446                 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
 1447         }
 1448         if (sc->sis_ldata.sis_tx_tag) {
 1449                 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
 1450                     sc->sis_ldata.sis_tx_dmamap);
 1451                 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
 1452                     sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap);
 1453                 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
 1454         }
 1455         if (sc->sis_parent_tag)
 1456                 bus_dma_tag_destroy(sc->sis_parent_tag);
 1457         if (sc->sis_tag)
 1458                 bus_dma_tag_destroy(sc->sis_tag);
 1459 
 1460         SIS_UNLOCK(sc);
 1461         mtx_destroy(&sc->sis_mtx);
 1462 
 1463         return(0);
 1464 }
 1465 
 1466 /*
 1467  * Initialize the transmit descriptors.
 1468  */
 1469 static int
 1470 sis_list_tx_init(sc)
 1471         struct sis_softc        *sc;
 1472 {
 1473         struct sis_list_data    *ld;
 1474         struct sis_ring_data    *cd;
 1475         int                     i, nexti;
 1476 
 1477         cd = &sc->sis_cdata;
 1478         ld = &sc->sis_ldata;
 1479 
 1480         for (i = 0; i < SIS_TX_LIST_CNT; i++) {
 1481                 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
 1482                         ld->sis_tx_list[i].sis_nextdesc =
 1483                             &ld->sis_tx_list[nexti];
 1484                         bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
 1485                             sc->sis_ldata.sis_tx_dmamap,
 1486                             &ld->sis_tx_list[nexti], sizeof(struct sis_desc),
 1487                             sis_dma_map_desc_next, &ld->sis_tx_list[i], 0);
 1488                 ld->sis_tx_list[i].sis_mbuf = NULL;
 1489                 ld->sis_tx_list[i].sis_ptr = 0;
 1490                 ld->sis_tx_list[i].sis_ctl = 0;
 1491         }
 1492 
 1493         cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
 1494 
 1495         bus_dmamap_sync(sc->sis_ldata.sis_tx_tag,
 1496             sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE);
 1497 
 1498         return(0);
 1499 }
 1500 
 1501 /*
 1502  * Initialize the RX descriptors and allocate mbufs for them. Note that
 1503  * we arrange the descriptors in a closed ring, so that the last descriptor
 1504  * points back to the first.
 1505  */
 1506 static int
 1507 sis_list_rx_init(sc)
 1508         struct sis_softc        *sc;
 1509 {
 1510         struct sis_list_data    *ld;
 1511         struct sis_ring_data    *cd;
 1512         int                     i,nexti;
 1513 
 1514         ld = &sc->sis_ldata;
 1515         cd = &sc->sis_cdata;
 1516 
 1517         for (i = 0; i < SIS_RX_LIST_CNT; i++) {
 1518                 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
 1519                         return(ENOBUFS);
 1520                 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
 1521                         ld->sis_rx_list[i].sis_nextdesc =
 1522                             &ld->sis_rx_list[nexti];
 1523                         bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
 1524                             sc->sis_ldata.sis_rx_dmamap,
 1525                             &ld->sis_rx_list[nexti],
 1526                             sizeof(struct sis_desc), sis_dma_map_desc_next,
 1527                             &ld->sis_rx_list[i], 0);
 1528                 }
 1529 
 1530         bus_dmamap_sync(sc->sis_ldata.sis_rx_tag,
 1531             sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE);
 1532 
 1533         cd->sis_rx_prod = 0;
 1534 
 1535         return(0);
 1536 }
 1537 
 1538 /*
 1539  * Initialize an RX descriptor and attach an MBUF cluster.
 1540  */
 1541 static int
 1542 sis_newbuf(sc, c, m)
 1543         struct sis_softc        *sc;
 1544         struct sis_desc         *c;
 1545         struct mbuf             *m;
 1546 {
 1547 
 1548         if (c == NULL)
 1549                 return(EINVAL);
 1550 
 1551         if (m == NULL) {
 1552                 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 1553                 if (m == NULL)
 1554                         return(ENOBUFS);
 1555         } else
 1556                 m->m_data = m->m_ext.ext_buf;
 1557 
 1558         c->sis_mbuf = m;
 1559         c->sis_ctl = SIS_RXLEN;
 1560 
 1561         bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
 1562         bus_dmamap_load(sc->sis_tag, c->sis_map,
 1563             mtod(m, void *), MCLBYTES,
 1564             sis_dma_map_desc_ptr, c, 0);
 1565         bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
 1566 
 1567         return(0);
 1568 }
 1569 
 1570 /*
 1571  * A frame has been uploaded: pass the resulting mbuf chain up to
 1572  * the higher level protocols.
 1573  */
 1574 static void
 1575 sis_rxeof(sc)
 1576         struct sis_softc        *sc;
 1577 {
 1578         struct mbuf             *m;
 1579         struct ifnet            *ifp;
 1580         struct sis_desc         *cur_rx;
 1581         int                     i, total_len = 0;
 1582         u_int32_t               rxstat;
 1583 
 1584         ifp = &sc->arpcom.ac_if;
 1585         i = sc->sis_cdata.sis_rx_prod;
 1586 
 1587         while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
 1588 
 1589 #ifdef DEVICE_POLLING
 1590                 if (ifp->if_flags & IFF_POLLING) {
 1591                         if (sc->rxcycles <= 0)
 1592                                 break;
 1593                         sc->rxcycles--;
 1594                 }
 1595 #endif /* DEVICE_POLLING */
 1596                 cur_rx = &sc->sis_ldata.sis_rx_list[i];
 1597                 rxstat = cur_rx->sis_rxstat;
 1598                 bus_dmamap_sync(sc->sis_tag,
 1599                     cur_rx->sis_map, BUS_DMASYNC_POSTWRITE);
 1600                 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
 1601                 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
 1602                 m = cur_rx->sis_mbuf;
 1603                 cur_rx->sis_mbuf = NULL;
 1604                 total_len = SIS_RXBYTES(cur_rx);
 1605                 SIS_INC(i, SIS_RX_LIST_CNT);
 1606 
 1607                 /*
 1608                  * If an error occurs, update stats, clear the
 1609                  * status word and leave the mbuf cluster in place:
 1610                  * it should simply get re-used next time this descriptor
 1611                  * comes up in the ring.
 1612                  */
 1613                 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
 1614                         ifp->if_ierrors++;
 1615                         if (rxstat & SIS_RXSTAT_COLL)
 1616                                 ifp->if_collisions++;
 1617                         sis_newbuf(sc, cur_rx, m);
 1618                         continue;
 1619                 }
 1620 
 1621                 /* No errors; receive the packet. */    
 1622 #ifdef __i386__
 1623                 /*
 1624                  * On the x86 we do not have alignment problems, so try to
 1625                  * allocate a new buffer for the receive ring, and pass up
 1626                  * the one where the packet is already, saving the expensive
 1627                  * copy done in m_devget().
 1628                  * If we are on an architecture with alignment problems, or
 1629                  * if the allocation fails, then use m_devget and leave the
 1630                  * existing buffer in the receive ring.
 1631                  */
 1632                 if (sis_newbuf(sc, cur_rx, NULL) == 0)
 1633                         m->m_pkthdr.len = m->m_len = total_len;
 1634                 else
 1635 #endif
 1636                 {
 1637                         struct mbuf             *m0;
 1638                         m0 = m_devget(mtod(m, char *), total_len,
 1639                                 ETHER_ALIGN, ifp, NULL);
 1640                         sis_newbuf(sc, cur_rx, m);
 1641                         if (m0 == NULL) {
 1642                                 ifp->if_ierrors++;
 1643                                 continue;
 1644                         }
 1645                         m = m0;
 1646                 }
 1647 
 1648                 ifp->if_ipackets++;
 1649                 m->m_pkthdr.rcvif = ifp;
 1650 
 1651                 (*ifp->if_input)(ifp, m);
 1652         }
 1653 
 1654         sc->sis_cdata.sis_rx_prod = i;
 1655 
 1656         return;
 1657 }
 1658 
 1659 static void
 1660 sis_rxeoc(sc)
 1661         struct sis_softc        *sc;
 1662 {
 1663         sis_rxeof(sc);
 1664         sis_init(sc);
 1665         return;
 1666 }
 1667 
 1668 /*
 1669  * A frame was downloaded to the chip. It's safe for us to clean up
 1670  * the list buffers.
 1671  */
 1672 
 1673 static void
 1674 sis_txeof(sc)
 1675         struct sis_softc        *sc;
 1676 {
 1677         struct ifnet            *ifp;
 1678         u_int32_t               idx;
 1679 
 1680         ifp = &sc->arpcom.ac_if;
 1681 
 1682         /*
 1683          * Go through our tx list and free mbufs for those
 1684          * frames that have been transmitted.
 1685          */
 1686         for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
 1687             sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
 1688                 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx];
 1689 
 1690                 if (SIS_OWNDESC(cur_tx))
 1691                         break;
 1692 
 1693                 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
 1694                         continue;
 1695 
 1696                 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
 1697                         ifp->if_oerrors++;
 1698                         if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
 1699                                 ifp->if_collisions++;
 1700                         if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
 1701                                 ifp->if_collisions++;
 1702                 }
 1703 
 1704                 ifp->if_collisions +=
 1705                     (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
 1706 
 1707                 ifp->if_opackets++;
 1708                 if (cur_tx->sis_mbuf != NULL) {
 1709                         m_freem(cur_tx->sis_mbuf);
 1710                         cur_tx->sis_mbuf = NULL;
 1711                         bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
 1712                         bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
 1713                 }
 1714         }
 1715 
 1716         if (idx != sc->sis_cdata.sis_tx_cons) {
 1717                 /* we freed up some buffers */
 1718                 sc->sis_cdata.sis_tx_cons = idx;
 1719                 ifp->if_flags &= ~IFF_OACTIVE;
 1720         }
 1721 
 1722         ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
 1723 
 1724         return;
 1725 }
 1726 
 1727 static void
 1728 sis_tick(xsc)
 1729         void                    *xsc;
 1730 {
 1731         struct sis_softc        *sc;
 1732         struct mii_data         *mii;
 1733         struct ifnet            *ifp;
 1734 
 1735         sc = xsc;
 1736         SIS_LOCK(sc);
 1737         ifp = &sc->arpcom.ac_if;
 1738 
 1739         mii = device_get_softc(sc->sis_miibus);
 1740         mii_tick(mii);
 1741 
 1742         if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE &&
 1743             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 1744                 sc->sis_link++;
 1745                 if (ifp->if_snd.ifq_head != NULL)
 1746                         sis_start(ifp);
 1747         }
 1748 
 1749         SIS_UNLOCK(sc);
 1750 
 1751         return;
 1752 }
 1753 
 1754 #ifdef DEVICE_POLLING
 1755 static poll_handler_t sis_poll;
 1756 
 1757 static void
 1758 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
 1759 {
 1760         struct  sis_softc *sc = ifp->if_softc;
 1761 
 1762         SIS_LOCK(sc);
 1763         if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
 1764                 CSR_WRITE_4(sc, SIS_IER, 1);
 1765                 goto done;
 1766         }
 1767 
 1768         /*
 1769          * On the sis, reading the status register also clears it.
 1770          * So before returning to intr mode we must make sure that all
 1771          * possible pending sources of interrupts have been served.
 1772          * In practice this means run to completion the *eof routines,
 1773          * and then call the interrupt routine
 1774          */
 1775         sc->rxcycles = count;
 1776         sis_rxeof(sc);
 1777         sis_txeof(sc);
 1778         if (ifp->if_snd.ifq_head != NULL)
 1779                 sis_start(ifp);
 1780 
 1781         if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
 1782                 u_int32_t       status;
 1783 
 1784                 /* Reading the ISR register clears all interrupts. */
 1785                 status = CSR_READ_4(sc, SIS_ISR);
 1786 
 1787                 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
 1788                         sis_rxeoc(sc);
 1789 
 1790                 if (status & (SIS_ISR_RX_IDLE))
 1791                         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
 1792 
 1793                 if (status & SIS_ISR_SYSERR) {
 1794                         sis_reset(sc);
 1795                         sis_init(sc);
 1796                 }
 1797         }
 1798 done:
 1799         SIS_UNLOCK(sc);
 1800         return;
 1801 }
 1802 #endif /* DEVICE_POLLING */
 1803 
 1804 static void
 1805 sis_intr(arg)
 1806         void                    *arg;
 1807 {
 1808         struct sis_softc        *sc;
 1809         struct ifnet            *ifp;
 1810         u_int32_t               status;
 1811 
 1812         sc = arg;
 1813         ifp = &sc->arpcom.ac_if;
 1814 
 1815         SIS_LOCK(sc);
 1816 #ifdef DEVICE_POLLING
 1817         if (ifp->if_flags & IFF_POLLING)
 1818                 goto done;
 1819         if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */
 1820                 CSR_WRITE_4(sc, SIS_IER, 0);
 1821                 goto done;
 1822         }
 1823 #endif /* DEVICE_POLLING */
 1824 
 1825         /* Supress unwanted interrupts */
 1826         if (!(ifp->if_flags & IFF_UP)) {
 1827                 sis_stop(sc);
 1828                 goto done;
 1829         }
 1830 
 1831         /* Disable interrupts. */
 1832         CSR_WRITE_4(sc, SIS_IER, 0);
 1833 
 1834         for (;;) {
 1835                 /* Reading the ISR register clears all interrupts. */
 1836                 status = CSR_READ_4(sc, SIS_ISR);
 1837 
 1838                 if ((status & SIS_INTRS) == 0)
 1839                         break;
 1840 
 1841                 if (status &
 1842                     (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
 1843                      SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
 1844                         sis_txeof(sc);
 1845 
 1846                 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE))
 1847                         sis_rxeof(sc);
 1848 
 1849                 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
 1850                         sis_rxeoc(sc);
 1851 
 1852                 if (status & (SIS_ISR_RX_IDLE))
 1853                         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
 1854 
 1855                 if (status & SIS_ISR_SYSERR) {
 1856                         sis_reset(sc);
 1857                         sis_init(sc);
 1858                 }
 1859         }
 1860 
 1861         /* Re-enable interrupts. */
 1862         CSR_WRITE_4(sc, SIS_IER, 1);
 1863 
 1864         if (ifp->if_snd.ifq_head != NULL)
 1865                 sis_start(ifp);
 1866 done:
 1867         SIS_UNLOCK(sc);
 1868 
 1869         return;
 1870 }
 1871 
 1872 /*
 1873  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1874  * pointers to the fragment pointers.
 1875  */
 1876 static int
 1877 sis_encap(sc, m_head, txidx)
 1878         struct sis_softc        *sc;
 1879         struct mbuf             *m_head;
 1880         u_int32_t               *txidx;
 1881 {
 1882         struct sis_desc         *f = NULL;
 1883         struct mbuf             *m;
 1884         int                     frag, cur, cnt = 0, chainlen = 0;
 1885 
 1886         /*
 1887          * If there's no way we can send any packets, return now.
 1888          */
 1889         if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2)
 1890                 return (ENOBUFS);
 1891 
 1892         /*
 1893          * Count the number of frags in this chain to see if
 1894          * we need to m_defrag.  Since the descriptor list is shared
 1895          * by all packets, we'll m_defrag long chains so that they
 1896          * do not use up the entire list, even if they would fit.
 1897          */
 1898 
 1899         for (m = m_head; m != NULL; m = m->m_next)
 1900                 chainlen++;
 1901 
 1902         if ((chainlen > SIS_TX_LIST_CNT / 4) ||
 1903             ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) {
 1904                 m = m_defrag(m_head, M_DONTWAIT);
 1905                 if (m == NULL)
 1906                         return (ENOBUFS);
 1907                 m_head = m;
 1908         }
 1909         
 1910         /*
 1911          * Start packing the mbufs in this chain into
 1912          * the fragment pointers. Stop when we run out
 1913          * of fragments or hit the end of the mbuf chain.
 1914          */
 1915         m = m_head;
 1916         cur = frag = *txidx;
 1917 
 1918         for (m = m_head; m != NULL; m = m->m_next) {
 1919                 if (m->m_len != 0) {
 1920                         if ((SIS_TX_LIST_CNT -
 1921                             (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
 1922                                 return(ENOBUFS);
 1923                         f = &sc->sis_ldata.sis_tx_list[frag];
 1924                         f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
 1925                         bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
 1926                         bus_dmamap_load(sc->sis_tag, f->sis_map,
 1927                             mtod(m, void *), m->m_len,
 1928                             sis_dma_map_desc_ptr, f, 0);
 1929                         bus_dmamap_sync(sc->sis_tag,
 1930                             f->sis_map, BUS_DMASYNC_PREREAD);
 1931                         if (cnt != 0)
 1932                                 f->sis_ctl |= SIS_CMDSTS_OWN;
 1933                         cur = frag;
 1934                         SIS_INC(frag, SIS_TX_LIST_CNT);
 1935                         cnt++;
 1936                 }
 1937         }
 1938 
 1939         if (m != NULL)
 1940                 return(ENOBUFS);
 1941 
 1942         sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head;
 1943         sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
 1944         sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
 1945         sc->sis_cdata.sis_tx_cnt += cnt;
 1946         *txidx = frag;
 1947 
 1948         return(0);
 1949 }
 1950 
 1951 /*
 1952  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 1953  * to the mbuf data regions directly in the transmit lists. We also save a
 1954  * copy of the pointers since the transmit list fragment pointers are
 1955  * physical addresses.
 1956  */
 1957 
 1958 static void
 1959 sis_start(ifp)
 1960         struct ifnet            *ifp;
 1961 {
 1962         struct sis_softc        *sc;
 1963         struct mbuf             *m_head = NULL;
 1964         u_int32_t               idx;
 1965 
 1966         sc = ifp->if_softc;
 1967         SIS_LOCK(sc);
 1968 
 1969         if (!sc->sis_link) {
 1970                 SIS_UNLOCK(sc);
 1971                 return;
 1972         }
 1973 
 1974         idx = sc->sis_cdata.sis_tx_prod;
 1975 
 1976         if (ifp->if_flags & IFF_OACTIVE) {
 1977                 SIS_UNLOCK(sc);
 1978                 return;
 1979         }
 1980 
 1981         while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
 1982                 IF_DEQUEUE(&ifp->if_snd, m_head);
 1983                 if (m_head == NULL)
 1984                         break;
 1985 
 1986                 if (sis_encap(sc, m_head, &idx)) {
 1987                         IF_PREPEND(&ifp->if_snd, m_head);
 1988                         ifp->if_flags |= IFF_OACTIVE;
 1989                         break;
 1990                 }
 1991 
 1992                 /*
 1993                  * If there's a BPF listener, bounce a copy of this frame
 1994                  * to him.
 1995                  */
 1996                 BPF_MTAP(ifp, m_head);
 1997 
 1998         }
 1999 
 2000         /* Transmit */
 2001         sc->sis_cdata.sis_tx_prod = idx;
 2002         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
 2003 
 2004         /*
 2005          * Set a timeout in case the chip goes out to lunch.
 2006          */
 2007         ifp->if_timer = 5;
 2008 
 2009         SIS_UNLOCK(sc);
 2010 
 2011         return;
 2012 }
 2013 
 2014 static void
 2015 sis_init(xsc)
 2016         void                    *xsc;
 2017 {
 2018         struct sis_softc        *sc = xsc;
 2019         struct ifnet            *ifp = &sc->arpcom.ac_if;
 2020         struct mii_data         *mii;
 2021 
 2022         SIS_LOCK(sc);
 2023 
 2024         /*
 2025          * Cancel pending I/O and free all RX/TX buffers.
 2026          */
 2027         sis_stop(sc);
 2028 
 2029         mii = device_get_softc(sc->sis_miibus);
 2030 
 2031         /* Set MAC address */
 2032         if (sc->sis_type == SIS_TYPE_83815) {
 2033                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
 2034                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 2035                     ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
 2036                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
 2037                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 2038                     ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
 2039                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
 2040                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 2041                     ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
 2042         } else {
 2043                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
 2044                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 2045                     ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
 2046                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
 2047                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 2048                     ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
 2049                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
 2050                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 2051                     ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
 2052         }
 2053 
 2054         /* Init circular RX list. */
 2055         if (sis_list_rx_init(sc) == ENOBUFS) {
 2056                 printf("sis%d: initialization failed: no "
 2057                         "memory for rx buffers\n", sc->sis_unit);
 2058                 sis_stop(sc);
 2059                 SIS_UNLOCK(sc);
 2060                 return;
 2061         }
 2062 
 2063         /*
 2064          * Init tx descriptors.
 2065          */
 2066         sis_list_tx_init(sc);
 2067 
 2068         /*
 2069          * For the NatSemi chip, we have to explicitly enable the
 2070          * reception of ARP frames, as well as turn on the 'perfect
 2071          * match' filter where we store the station address, otherwise
 2072          * we won't receive unicasts meant for this host.
 2073          */
 2074         if (sc->sis_type == SIS_TYPE_83815) {
 2075                 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
 2076                 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
 2077         }
 2078 
 2079          /* If we want promiscuous mode, set the allframes bit. */
 2080         if (ifp->if_flags & IFF_PROMISC) {
 2081                 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
 2082         } else {
 2083                 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
 2084         }
 2085 
 2086         /*
 2087          * Set the capture broadcast bit to capture broadcast frames.
 2088          */
 2089         if (ifp->if_flags & IFF_BROADCAST) {
 2090                 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
 2091         } else {
 2092                 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
 2093         }
 2094 
 2095         /*
 2096          * Load the multicast filter.
 2097          */
 2098         if (sc->sis_type == SIS_TYPE_83815)
 2099                 sis_setmulti_ns(sc);
 2100         else
 2101                 sis_setmulti_sis(sc);
 2102 
 2103         /* Turn the receive filter on */
 2104         SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
 2105 
 2106         /*
 2107          * Load the address of the RX and TX lists.
 2108          */
 2109         CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
 2110         CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
 2111 
 2112         /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
 2113          * the PCI bus. When this bit is set, the Max DMA Burst Size
 2114          * for TX/RX DMA should be no larger than 16 double words.
 2115          */
 2116         if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
 2117                 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
 2118         } else {
 2119                 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
 2120         }
 2121 
 2122 
 2123         /* Accept Long Packets for VLAN support */
 2124         SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
 2125 
 2126         /* Set TX configuration */
 2127         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
 2128                 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
 2129         } else {
 2130                 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
 2131         }
 2132 
 2133         /* Set full/half duplex mode. */
 2134         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 2135                 SIS_SETBIT(sc, SIS_TX_CFG,
 2136                     (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
 2137                 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
 2138         } else {
 2139                 SIS_CLRBIT(sc, SIS_TX_CFG,
 2140                     (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
 2141                 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
 2142         }
 2143 
 2144         /*
 2145          * Enable interrupts.
 2146          */
 2147         CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
 2148 #ifdef DEVICE_POLLING
 2149         /*
 2150          * ... only enable interrupts if we are not polling, make sure
 2151          * they are off otherwise.
 2152          */
 2153         if (ifp->if_flags & IFF_POLLING)
 2154                 CSR_WRITE_4(sc, SIS_IER, 0);
 2155         else
 2156 #endif /* DEVICE_POLLING */
 2157         CSR_WRITE_4(sc, SIS_IER, 1);
 2158 
 2159         /* Enable receiver and transmitter. */
 2160         SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
 2161         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
 2162 
 2163 #ifdef notdef
 2164         mii_mediachg(mii);
 2165 #endif
 2166 
 2167         /*
 2168          * Page 75 of the DP83815 manual recommends the
 2169          * following register settings "for optimum
 2170          * performance." Note however that at least three
 2171          * of the registers are listed as "reserved" in
 2172          * the register map, so who knows what they do.
 2173          */
 2174         if (sc->sis_type == SIS_TYPE_83815) {
 2175                 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
 2176                 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
 2177                 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
 2178                 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
 2179                 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
 2180         }
 2181 
 2182         ifp->if_flags |= IFF_RUNNING;
 2183         ifp->if_flags &= ~IFF_OACTIVE;
 2184 
 2185         sc->sis_stat_ch = timeout(sis_tick, sc, hz);
 2186 
 2187         SIS_UNLOCK(sc);
 2188 
 2189         return;
 2190 }
 2191 
 2192 /*
 2193  * Set media options.
 2194  */
 2195 static int
 2196 sis_ifmedia_upd(ifp)
 2197         struct ifnet            *ifp;
 2198 {
 2199         struct sis_softc        *sc;
 2200         struct mii_data         *mii;
 2201 
 2202         sc = ifp->if_softc;
 2203 
 2204         mii = device_get_softc(sc->sis_miibus);
 2205         sc->sis_link = 0;
 2206         if (mii->mii_instance) {
 2207                 struct mii_softc        *miisc;
 2208                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 2209                         mii_phy_reset(miisc);
 2210         }
 2211         mii_mediachg(mii);
 2212 
 2213         return(0);
 2214 }
 2215 
 2216 /*
 2217  * Report current media status.
 2218  */
 2219 static void
 2220 sis_ifmedia_sts(ifp, ifmr)
 2221         struct ifnet            *ifp;
 2222         struct ifmediareq       *ifmr;
 2223 {
 2224         struct sis_softc        *sc;
 2225         struct mii_data         *mii;
 2226 
 2227         sc = ifp->if_softc;
 2228 
 2229         mii = device_get_softc(sc->sis_miibus);
 2230         mii_pollstat(mii);
 2231         ifmr->ifm_active = mii->mii_media_active;
 2232         ifmr->ifm_status = mii->mii_media_status;
 2233 
 2234         return;
 2235 }
 2236 
 2237 static int
 2238 sis_ioctl(ifp, command, data)
 2239         struct ifnet            *ifp;
 2240         u_long                  command;
 2241         caddr_t                 data;
 2242 {
 2243         struct sis_softc        *sc = ifp->if_softc;
 2244         struct ifreq            *ifr = (struct ifreq *) data;
 2245         struct mii_data         *mii;
 2246         int                     error = 0;
 2247 
 2248         switch(command) {
 2249         case SIOCSIFFLAGS:
 2250                 if (ifp->if_flags & IFF_UP) {
 2251                         sis_init(sc);
 2252                 } else {
 2253                         if (ifp->if_flags & IFF_RUNNING)
 2254                                 sis_stop(sc);
 2255                 }
 2256                 error = 0;
 2257                 break;
 2258         case SIOCADDMULTI:
 2259         case SIOCDELMULTI:
 2260                 SIS_LOCK(sc);
 2261                 if (sc->sis_type == SIS_TYPE_83815)
 2262                         sis_setmulti_ns(sc);
 2263                 else
 2264                         sis_setmulti_sis(sc);
 2265                 SIS_UNLOCK(sc);
 2266                 error = 0;
 2267                 break;
 2268         case SIOCGIFMEDIA:
 2269         case SIOCSIFMEDIA:
 2270                 mii = device_get_softc(sc->sis_miibus);
 2271                 SIS_LOCK(sc);
 2272                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 2273                 SIS_UNLOCK(sc);
 2274                 break;
 2275         default:
 2276                 error = ether_ioctl(ifp, command, data);
 2277                 break;
 2278         }
 2279 
 2280         return(error);
 2281 }
 2282 
 2283 static void
 2284 sis_watchdog(ifp)
 2285         struct ifnet            *ifp;
 2286 {
 2287         struct sis_softc        *sc;
 2288 
 2289         sc = ifp->if_softc;
 2290 
 2291         SIS_LOCK(sc);
 2292 
 2293         ifp->if_oerrors++;
 2294         printf("sis%d: watchdog timeout\n", sc->sis_unit);
 2295 
 2296         sis_stop(sc);
 2297         sis_reset(sc);
 2298         sis_init(sc);
 2299 
 2300         if (ifp->if_snd.ifq_head != NULL)
 2301                 sis_start(ifp);
 2302 
 2303         SIS_UNLOCK(sc);
 2304 
 2305         return;
 2306 }
 2307 
 2308 /*
 2309  * Stop the adapter and free any mbufs allocated to the
 2310  * RX and TX lists.
 2311  */
 2312 static void
 2313 sis_stop(sc)
 2314         struct sis_softc        *sc;
 2315 {
 2316         register int            i;
 2317         struct ifnet            *ifp;
 2318 
 2319         SIS_LOCK(sc);
 2320         ifp = &sc->arpcom.ac_if;
 2321         ifp->if_timer = 0;
 2322 
 2323         untimeout(sis_tick, sc, sc->sis_stat_ch);
 2324 
 2325         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 2326 #ifdef DEVICE_POLLING
 2327         ether_poll_deregister(ifp);
 2328 #endif
 2329         CSR_WRITE_4(sc, SIS_IER, 0);
 2330         CSR_WRITE_4(sc, SIS_IMR, 0);
 2331         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
 2332         DELAY(1000);
 2333         CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
 2334         CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
 2335 
 2336         sc->sis_link = 0;
 2337 
 2338         /*
 2339          * Free data in the RX lists.
 2340          */
 2341         for (i = 0; i < SIS_RX_LIST_CNT; i++) {
 2342                 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
 2343                         bus_dmamap_unload(sc->sis_tag,
 2344                             sc->sis_ldata.sis_rx_list[i].sis_map);
 2345                         bus_dmamap_destroy(sc->sis_tag,
 2346                             sc->sis_ldata.sis_rx_list[i].sis_map);
 2347                         m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
 2348                         sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
 2349                 }
 2350         }
 2351         bzero(sc->sis_ldata.sis_rx_list,
 2352                 sizeof(sc->sis_ldata.sis_rx_list));
 2353 
 2354         /*
 2355          * Free the TX list buffers.
 2356          */
 2357         for (i = 0; i < SIS_TX_LIST_CNT; i++) {
 2358                 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
 2359                         bus_dmamap_unload(sc->sis_tag,
 2360                             sc->sis_ldata.sis_tx_list[i].sis_map);
 2361                         bus_dmamap_destroy(sc->sis_tag,
 2362                             sc->sis_ldata.sis_tx_list[i].sis_map);
 2363                         m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
 2364                         sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
 2365                 }
 2366         }
 2367 
 2368         bzero(sc->sis_ldata.sis_tx_list,
 2369                 sizeof(sc->sis_ldata.sis_tx_list));
 2370 
 2371         SIS_UNLOCK(sc);
 2372 
 2373         return;
 2374 }
 2375 
 2376 /*
 2377  * Stop all chip I/O so that the kernel's probe routines don't
 2378  * get confused by errant DMAs when rebooting.
 2379  */
 2380 static void
 2381 sis_shutdown(dev)
 2382         device_t                dev;
 2383 {
 2384         struct sis_softc        *sc;
 2385 
 2386         sc = device_get_softc(dev);
 2387         SIS_LOCK(sc);
 2388         sis_reset(sc);
 2389         sis_stop(sc);
 2390         SIS_UNLOCK(sc);
 2391 
 2392         return;
 2393 }

Cache object: 1d82844e6a103a5b6cb1e8b6ddc87ac4


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.