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sys/pci/if_sis.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/5.4/sys/pci/if_sis.c 143087 2005-03-03 04:16:17Z avatar $"); 35 36 /* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/module.h> 67 #include <sys/socket.h> 68 #include <sys/sysctl.h> 69 70 #include <net/if.h> 71 #include <net/if_arp.h> 72 #include <net/ethernet.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 #include <net/if_vlan_var.h> 77 78 #include <net/bpf.h> 79 80 #include <machine/bus_pio.h> 81 #include <machine/bus_memio.h> 82 #include <machine/bus.h> 83 #include <machine/resource.h> 84 #include <sys/bus.h> 85 #include <sys/rman.h> 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <dev/pci/pcireg.h> 91 #include <dev/pci/pcivar.h> 92 93 #define SIS_USEIOSPACE 94 95 #include <pci/if_sisreg.h> 96 97 MODULE_DEPEND(sis, pci, 1, 1, 1); 98 MODULE_DEPEND(sis, ether, 1, 1, 1); 99 MODULE_DEPEND(sis, miibus, 1, 1, 1); 100 101 /* "controller miibus0" required. See GENERIC if you get errors here. */ 102 #include "miibus_if.h" 103 104 /* 105 * Various supported device vendors/types and their names. 106 */ 107 static struct sis_type sis_devs[] = { 108 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 109 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 110 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 111 { 0, 0, NULL } 112 }; 113 114 static int sis_probe (device_t); 115 static int sis_attach (device_t); 116 static int sis_detach (device_t); 117 118 static int sis_newbuf (struct sis_softc *, 119 struct sis_desc *, struct mbuf *); 120 static int sis_encap (struct sis_softc *, 121 struct mbuf **, u_int32_t *); 122 static void sis_rxeof (struct sis_softc *); 123 static void sis_rxeoc (struct sis_softc *); 124 static void sis_txeof (struct sis_softc *); 125 static void sis_intr (void *); 126 static void sis_tick (void *); 127 static void sis_start (struct ifnet *); 128 static int sis_ioctl (struct ifnet *, u_long, caddr_t); 129 static void sis_init (void *); 130 static void sis_stop (struct sis_softc *); 131 static void sis_watchdog (struct ifnet *); 132 static void sis_shutdown (device_t); 133 static int sis_ifmedia_upd (struct ifnet *); 134 static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 135 136 static u_int16_t sis_reverse (u_int16_t); 137 static void sis_delay (struct sis_softc *); 138 static void sis_eeprom_idle (struct sis_softc *); 139 static void sis_eeprom_putbyte (struct sis_softc *, int); 140 static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 141 static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 142 #ifdef __i386__ 143 static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 144 int, int); 145 static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 146 static device_t sis_find_bridge (device_t); 147 #endif 148 149 static void sis_mii_sync (struct sis_softc *); 150 static void sis_mii_send (struct sis_softc *, u_int32_t, int); 151 static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 152 static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 153 static int sis_miibus_readreg (device_t, int, int); 154 static int sis_miibus_writereg (device_t, int, int, int); 155 static void sis_miibus_statchg (device_t); 156 157 static void sis_setmulti_sis (struct sis_softc *); 158 static void sis_setmulti_ns (struct sis_softc *); 159 static uint32_t sis_mchash (struct sis_softc *, const uint8_t *); 160 static void sis_reset (struct sis_softc *); 161 static int sis_list_rx_init (struct sis_softc *); 162 static int sis_list_tx_init (struct sis_softc *); 163 164 static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 165 static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 166 static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 167 #ifdef SIS_USEIOSPACE 168 #define SIS_RES SYS_RES_IOPORT 169 #define SIS_RID SIS_PCI_LOIO 170 #else 171 #define SIS_RES SYS_RES_MEMORY 172 #define SIS_RID SIS_PCI_LOMEM 173 #endif 174 175 static device_method_t sis_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, sis_probe), 178 DEVMETHOD(device_attach, sis_attach), 179 DEVMETHOD(device_detach, sis_detach), 180 DEVMETHOD(device_shutdown, sis_shutdown), 181 182 /* bus interface */ 183 DEVMETHOD(bus_print_child, bus_generic_print_child), 184 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 185 186 /* MII interface */ 187 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 188 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 189 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 190 191 { 0, 0 } 192 }; 193 194 static driver_t sis_driver = { 195 "sis", 196 sis_methods, 197 sizeof(struct sis_softc) 198 }; 199 200 static devclass_t sis_devclass; 201 202 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 203 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 204 205 #define SIS_SETBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, \ 207 CSR_READ_4(sc, reg) | (x)) 208 209 #define SIS_CLRBIT(sc, reg, x) \ 210 CSR_WRITE_4(sc, reg, \ 211 CSR_READ_4(sc, reg) & ~(x)) 212 213 #define SIO_SET(x) \ 214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 215 216 #define SIO_CLR(x) \ 217 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 218 219 static void 220 sis_dma_map_desc_next(arg, segs, nseg, error) 221 void *arg; 222 bus_dma_segment_t *segs; 223 int nseg, error; 224 { 225 struct sis_desc *r; 226 227 r = arg; 228 r->sis_next = segs->ds_addr; 229 230 return; 231 } 232 233 static void 234 sis_dma_map_desc_ptr(arg, segs, nseg, error) 235 void *arg; 236 bus_dma_segment_t *segs; 237 int nseg, error; 238 { 239 struct sis_desc *r; 240 241 r = arg; 242 r->sis_ptr = segs->ds_addr; 243 244 return; 245 } 246 247 static void 248 sis_dma_map_ring(arg, segs, nseg, error) 249 void *arg; 250 bus_dma_segment_t *segs; 251 int nseg, error; 252 { 253 u_int32_t *p; 254 255 p = arg; 256 *p = segs->ds_addr; 257 258 return; 259 } 260 261 /* 262 * Routine to reverse the bits in a word. Stolen almost 263 * verbatim from /usr/games/fortune. 264 */ 265 static u_int16_t 266 sis_reverse(n) 267 u_int16_t n; 268 { 269 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 270 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 271 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 272 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 273 274 return(n); 275 } 276 277 static void 278 sis_delay(sc) 279 struct sis_softc *sc; 280 { 281 int idx; 282 283 for (idx = (300 / 33) + 1; idx > 0; idx--) 284 CSR_READ_4(sc, SIS_CSR); 285 286 return; 287 } 288 289 static void 290 sis_eeprom_idle(sc) 291 struct sis_softc *sc; 292 { 293 register int i; 294 295 SIO_SET(SIS_EECTL_CSEL); 296 sis_delay(sc); 297 SIO_SET(SIS_EECTL_CLK); 298 sis_delay(sc); 299 300 for (i = 0; i < 25; i++) { 301 SIO_CLR(SIS_EECTL_CLK); 302 sis_delay(sc); 303 SIO_SET(SIS_EECTL_CLK); 304 sis_delay(sc); 305 } 306 307 SIO_CLR(SIS_EECTL_CLK); 308 sis_delay(sc); 309 SIO_CLR(SIS_EECTL_CSEL); 310 sis_delay(sc); 311 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 312 313 return; 314 } 315 316 /* 317 * Send a read command and address to the EEPROM, check for ACK. 318 */ 319 static void 320 sis_eeprom_putbyte(sc, addr) 321 struct sis_softc *sc; 322 int addr; 323 { 324 register int d, i; 325 326 d = addr | SIS_EECMD_READ; 327 328 /* 329 * Feed in each bit and stobe the clock. 330 */ 331 for (i = 0x400; i; i >>= 1) { 332 if (d & i) { 333 SIO_SET(SIS_EECTL_DIN); 334 } else { 335 SIO_CLR(SIS_EECTL_DIN); 336 } 337 sis_delay(sc); 338 SIO_SET(SIS_EECTL_CLK); 339 sis_delay(sc); 340 SIO_CLR(SIS_EECTL_CLK); 341 sis_delay(sc); 342 } 343 344 return; 345 } 346 347 /* 348 * Read a word of data stored in the EEPROM at address 'addr.' 349 */ 350 static void 351 sis_eeprom_getword(sc, addr, dest) 352 struct sis_softc *sc; 353 int addr; 354 u_int16_t *dest; 355 { 356 register int i; 357 u_int16_t word = 0; 358 359 /* Force EEPROM to idle state. */ 360 sis_eeprom_idle(sc); 361 362 /* Enter EEPROM access mode. */ 363 sis_delay(sc); 364 SIO_CLR(SIS_EECTL_CLK); 365 sis_delay(sc); 366 SIO_SET(SIS_EECTL_CSEL); 367 sis_delay(sc); 368 369 /* 370 * Send address of word we want to read. 371 */ 372 sis_eeprom_putbyte(sc, addr); 373 374 /* 375 * Start reading bits from EEPROM. 376 */ 377 for (i = 0x8000; i; i >>= 1) { 378 SIO_SET(SIS_EECTL_CLK); 379 sis_delay(sc); 380 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 381 word |= i; 382 sis_delay(sc); 383 SIO_CLR(SIS_EECTL_CLK); 384 sis_delay(sc); 385 } 386 387 /* Turn off EEPROM access mode. */ 388 sis_eeprom_idle(sc); 389 390 *dest = word; 391 392 return; 393 } 394 395 /* 396 * Read a sequence of words from the EEPROM. 397 */ 398 static void 399 sis_read_eeprom(sc, dest, off, cnt, swap) 400 struct sis_softc *sc; 401 caddr_t dest; 402 int off; 403 int cnt; 404 int swap; 405 { 406 int i; 407 u_int16_t word = 0, *ptr; 408 409 for (i = 0; i < cnt; i++) { 410 sis_eeprom_getword(sc, off + i, &word); 411 ptr = (u_int16_t *)(dest + (i * 2)); 412 if (swap) 413 *ptr = ntohs(word); 414 else 415 *ptr = word; 416 } 417 418 return; 419 } 420 421 #ifdef __i386__ 422 static device_t 423 sis_find_bridge(dev) 424 device_t dev; 425 { 426 devclass_t pci_devclass; 427 device_t *pci_devices; 428 int pci_count = 0; 429 device_t *pci_children; 430 int pci_childcount = 0; 431 device_t *busp, *childp; 432 device_t child = NULL; 433 int i, j; 434 435 if ((pci_devclass = devclass_find("pci")) == NULL) 436 return(NULL); 437 438 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 439 440 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 441 pci_childcount = 0; 442 device_get_children(*busp, &pci_children, &pci_childcount); 443 for (j = 0, childp = pci_children; 444 j < pci_childcount; j++, childp++) { 445 if (pci_get_vendor(*childp) == SIS_VENDORID && 446 pci_get_device(*childp) == 0x0008) { 447 child = *childp; 448 goto done; 449 } 450 } 451 } 452 453 done: 454 free(pci_devices, M_TEMP); 455 free(pci_children, M_TEMP); 456 return(child); 457 } 458 459 static void 460 sis_read_cmos(sc, dev, dest, off, cnt) 461 struct sis_softc *sc; 462 device_t dev; 463 caddr_t dest; 464 int off; 465 int cnt; 466 { 467 device_t bridge; 468 u_int8_t reg; 469 int i; 470 bus_space_tag_t btag; 471 472 bridge = sis_find_bridge(dev); 473 if (bridge == NULL) 474 return; 475 reg = pci_read_config(bridge, 0x48, 1); 476 pci_write_config(bridge, 0x48, reg|0x40, 1); 477 478 /* XXX */ 479 btag = I386_BUS_SPACE_IO; 480 481 for (i = 0; i < cnt; i++) { 482 bus_space_write_1(btag, 0x0, 0x70, i + off); 483 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 484 } 485 486 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 487 return; 488 } 489 490 static void 491 sis_read_mac(sc, dev, dest) 492 struct sis_softc *sc; 493 device_t dev; 494 caddr_t dest; 495 { 496 u_int32_t filtsave, csrsave; 497 498 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 499 csrsave = CSR_READ_4(sc, SIS_CSR); 500 501 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 502 CSR_WRITE_4(sc, SIS_CSR, 0); 503 504 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 507 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 509 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 511 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 513 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 514 CSR_WRITE_4(sc, SIS_CSR, csrsave); 515 return; 516 } 517 #endif 518 519 /* 520 * Sync the PHYs by setting data bit and strobing the clock 32 times. 521 */ 522 static void sis_mii_sync(sc) 523 struct sis_softc *sc; 524 { 525 register int i; 526 527 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 528 529 for (i = 0; i < 32; i++) { 530 SIO_SET(SIS_MII_CLK); 531 DELAY(1); 532 SIO_CLR(SIS_MII_CLK); 533 DELAY(1); 534 } 535 536 return; 537 } 538 539 /* 540 * Clock a series of bits through the MII. 541 */ 542 static void sis_mii_send(sc, bits, cnt) 543 struct sis_softc *sc; 544 u_int32_t bits; 545 int cnt; 546 { 547 int i; 548 549 SIO_CLR(SIS_MII_CLK); 550 551 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 552 if (bits & i) { 553 SIO_SET(SIS_MII_DATA); 554 } else { 555 SIO_CLR(SIS_MII_DATA); 556 } 557 DELAY(1); 558 SIO_CLR(SIS_MII_CLK); 559 DELAY(1); 560 SIO_SET(SIS_MII_CLK); 561 } 562 } 563 564 /* 565 * Read an PHY register through the MII. 566 */ 567 static int sis_mii_readreg(sc, frame) 568 struct sis_softc *sc; 569 struct sis_mii_frame *frame; 570 571 { 572 int i, ack, s; 573 574 s = splimp(); 575 576 /* 577 * Set up frame for RX. 578 */ 579 frame->mii_stdelim = SIS_MII_STARTDELIM; 580 frame->mii_opcode = SIS_MII_READOP; 581 frame->mii_turnaround = 0; 582 frame->mii_data = 0; 583 584 /* 585 * Turn on data xmit. 586 */ 587 SIO_SET(SIS_MII_DIR); 588 589 sis_mii_sync(sc); 590 591 /* 592 * Send command/address info. 593 */ 594 sis_mii_send(sc, frame->mii_stdelim, 2); 595 sis_mii_send(sc, frame->mii_opcode, 2); 596 sis_mii_send(sc, frame->mii_phyaddr, 5); 597 sis_mii_send(sc, frame->mii_regaddr, 5); 598 599 /* Idle bit */ 600 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 601 DELAY(1); 602 SIO_SET(SIS_MII_CLK); 603 DELAY(1); 604 605 /* Turn off xmit. */ 606 SIO_CLR(SIS_MII_DIR); 607 608 /* Check for ack */ 609 SIO_CLR(SIS_MII_CLK); 610 DELAY(1); 611 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 612 SIO_SET(SIS_MII_CLK); 613 DELAY(1); 614 615 /* 616 * Now try reading data bits. If the ack failed, we still 617 * need to clock through 16 cycles to keep the PHY(s) in sync. 618 */ 619 if (ack) { 620 for(i = 0; i < 16; i++) { 621 SIO_CLR(SIS_MII_CLK); 622 DELAY(1); 623 SIO_SET(SIS_MII_CLK); 624 DELAY(1); 625 } 626 goto fail; 627 } 628 629 for (i = 0x8000; i; i >>= 1) { 630 SIO_CLR(SIS_MII_CLK); 631 DELAY(1); 632 if (!ack) { 633 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 634 frame->mii_data |= i; 635 DELAY(1); 636 } 637 SIO_SET(SIS_MII_CLK); 638 DELAY(1); 639 } 640 641 fail: 642 643 SIO_CLR(SIS_MII_CLK); 644 DELAY(1); 645 SIO_SET(SIS_MII_CLK); 646 DELAY(1); 647 648 splx(s); 649 650 if (ack) 651 return(1); 652 return(0); 653 } 654 655 /* 656 * Write to a PHY register through the MII. 657 */ 658 static int sis_mii_writereg(sc, frame) 659 struct sis_softc *sc; 660 struct sis_mii_frame *frame; 661 662 { 663 int s; 664 665 s = splimp(); 666 /* 667 * Set up frame for TX. 668 */ 669 670 frame->mii_stdelim = SIS_MII_STARTDELIM; 671 frame->mii_opcode = SIS_MII_WRITEOP; 672 frame->mii_turnaround = SIS_MII_TURNAROUND; 673 674 /* 675 * Turn on data output. 676 */ 677 SIO_SET(SIS_MII_DIR); 678 679 sis_mii_sync(sc); 680 681 sis_mii_send(sc, frame->mii_stdelim, 2); 682 sis_mii_send(sc, frame->mii_opcode, 2); 683 sis_mii_send(sc, frame->mii_phyaddr, 5); 684 sis_mii_send(sc, frame->mii_regaddr, 5); 685 sis_mii_send(sc, frame->mii_turnaround, 2); 686 sis_mii_send(sc, frame->mii_data, 16); 687 688 /* Idle bit. */ 689 SIO_SET(SIS_MII_CLK); 690 DELAY(1); 691 SIO_CLR(SIS_MII_CLK); 692 DELAY(1); 693 694 /* 695 * Turn off xmit. 696 */ 697 SIO_CLR(SIS_MII_DIR); 698 699 splx(s); 700 701 return(0); 702 } 703 704 static int 705 sis_miibus_readreg(dev, phy, reg) 706 device_t dev; 707 int phy, reg; 708 { 709 struct sis_softc *sc; 710 struct sis_mii_frame frame; 711 712 sc = device_get_softc(dev); 713 714 if (sc->sis_type == SIS_TYPE_83815) { 715 if (phy != 0) 716 return(0); 717 /* 718 * The NatSemi chip can take a while after 719 * a reset to come ready, during which the BMSR 720 * returns a value of 0. This is *never* supposed 721 * to happen: some of the BMSR bits are meant to 722 * be hardwired in the on position, and this can 723 * confuse the miibus code a bit during the probe 724 * and attach phase. So we make an effort to check 725 * for this condition and wait for it to clear. 726 */ 727 if (!CSR_READ_4(sc, NS_BMSR)) 728 DELAY(1000); 729 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 730 } 731 732 /* 733 * Chipsets < SIS_635 seem not to be able to read/write 734 * through mdio. Use the enhanced PHY access register 735 * again for them. 736 */ 737 if (sc->sis_type == SIS_TYPE_900 && 738 sc->sis_rev < SIS_REV_635) { 739 int i, val = 0; 740 741 if (phy != 0) 742 return(0); 743 744 CSR_WRITE_4(sc, SIS_PHYCTL, 745 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 746 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 747 748 for (i = 0; i < SIS_TIMEOUT; i++) { 749 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 750 break; 751 } 752 753 if (i == SIS_TIMEOUT) { 754 printf("sis%d: PHY failed to come ready\n", 755 sc->sis_unit); 756 return(0); 757 } 758 759 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 760 761 if (val == 0xFFFF) 762 return(0); 763 764 return(val); 765 } else { 766 bzero((char *)&frame, sizeof(frame)); 767 768 frame.mii_phyaddr = phy; 769 frame.mii_regaddr = reg; 770 sis_mii_readreg(sc, &frame); 771 772 return(frame.mii_data); 773 } 774 } 775 776 static int 777 sis_miibus_writereg(dev, phy, reg, data) 778 device_t dev; 779 int phy, reg, data; 780 { 781 struct sis_softc *sc; 782 struct sis_mii_frame frame; 783 784 sc = device_get_softc(dev); 785 786 if (sc->sis_type == SIS_TYPE_83815) { 787 if (phy != 0) 788 return(0); 789 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 790 return(0); 791 } 792 793 /* 794 * Chipsets < SIS_635 seem not to be able to read/write 795 * through mdio. Use the enhanced PHY access register 796 * again for them. 797 */ 798 if (sc->sis_type == SIS_TYPE_900 && 799 sc->sis_rev < SIS_REV_635) { 800 int i; 801 802 if (phy != 0) 803 return(0); 804 805 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 806 (reg << 6) | SIS_PHYOP_WRITE); 807 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 808 809 for (i = 0; i < SIS_TIMEOUT; i++) { 810 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 811 break; 812 } 813 814 if (i == SIS_TIMEOUT) 815 printf("sis%d: PHY failed to come ready\n", 816 sc->sis_unit); 817 } else { 818 bzero((char *)&frame, sizeof(frame)); 819 820 frame.mii_phyaddr = phy; 821 frame.mii_regaddr = reg; 822 frame.mii_data = data; 823 sis_mii_writereg(sc, &frame); 824 } 825 return(0); 826 } 827 828 static void 829 sis_miibus_statchg(dev) 830 device_t dev; 831 { 832 struct sis_softc *sc; 833 834 sc = device_get_softc(dev); 835 sis_init(sc); 836 837 return; 838 } 839 840 static u_int32_t 841 sis_mchash(sc, addr) 842 struct sis_softc *sc; 843 const uint8_t *addr; 844 { 845 uint32_t crc; 846 847 /* Compute CRC for the address value. */ 848 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 849 850 /* 851 * return the filter bit position 852 * 853 * The NatSemi chip has a 512-bit filter, which is 854 * different than the SiS, so we special-case it. 855 */ 856 if (sc->sis_type == SIS_TYPE_83815) 857 return (crc >> 23); 858 else if (sc->sis_rev >= SIS_REV_635 || 859 sc->sis_rev == SIS_REV_900B) 860 return (crc >> 24); 861 else 862 return (crc >> 25); 863 } 864 865 static void 866 sis_setmulti_ns(sc) 867 struct sis_softc *sc; 868 { 869 struct ifnet *ifp; 870 struct ifmultiaddr *ifma; 871 u_int32_t h = 0, i, filtsave; 872 int bit, index; 873 874 ifp = &sc->arpcom.ac_if; 875 876 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 877 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 878 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 879 return; 880 } 881 882 /* 883 * We have to explicitly enable the multicast hash table 884 * on the NatSemi chip if we want to use it, which we do. 885 */ 886 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 887 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 888 889 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 890 891 /* first, zot all the existing hash bits */ 892 for (i = 0; i < 32; i++) { 893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 894 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 895 } 896 897 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 898 if (ifma->ifma_addr->sa_family != AF_LINK) 899 continue; 900 h = sis_mchash(sc, 901 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 902 index = h >> 3; 903 bit = h & 0x1F; 904 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 905 if (bit > 0xF) 906 bit -= 0x10; 907 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 908 } 909 910 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 911 912 return; 913 } 914 915 static void 916 sis_setmulti_sis(sc) 917 struct sis_softc *sc; 918 { 919 struct ifnet *ifp; 920 struct ifmultiaddr *ifma; 921 u_int32_t h, i, n, ctl; 922 u_int16_t hashes[16]; 923 924 ifp = &sc->arpcom.ac_if; 925 926 /* hash table size */ 927 if (sc->sis_rev >= SIS_REV_635 || 928 sc->sis_rev == SIS_REV_900B) 929 n = 16; 930 else 931 n = 8; 932 933 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 934 935 if (ifp->if_flags & IFF_BROADCAST) 936 ctl |= SIS_RXFILTCTL_BROAD; 937 938 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 939 ctl |= SIS_RXFILTCTL_ALLMULTI; 940 if (ifp->if_flags & IFF_PROMISC) 941 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 942 for (i = 0; i < n; i++) 943 hashes[i] = ~0; 944 } else { 945 for (i = 0; i < n; i++) 946 hashes[i] = 0; 947 i = 0; 948 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 949 if (ifma->ifma_addr->sa_family != AF_LINK) 950 continue; 951 h = sis_mchash(sc, 952 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 953 hashes[h >> 4] |= 1 << (h & 0xf); 954 i++; 955 } 956 if (i > n) { 957 ctl |= SIS_RXFILTCTL_ALLMULTI; 958 for (i = 0; i < n; i++) 959 hashes[i] = ~0; 960 } 961 } 962 963 for (i = 0; i < n; i++) { 964 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 965 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 966 } 967 968 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 969 } 970 971 static void 972 sis_reset(sc) 973 struct sis_softc *sc; 974 { 975 register int i; 976 977 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 978 979 for (i = 0; i < SIS_TIMEOUT; i++) { 980 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 981 break; 982 } 983 984 if (i == SIS_TIMEOUT) 985 printf("sis%d: reset never completed\n", sc->sis_unit); 986 987 /* Wait a little while for the chip to get its brains in order. */ 988 DELAY(1000); 989 990 /* 991 * If this is a NetSemi chip, make sure to clear 992 * PME mode. 993 */ 994 if (sc->sis_type == SIS_TYPE_83815) { 995 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 996 CSR_WRITE_4(sc, NS_CLKRUN, 0); 997 } 998 999 return; 1000 } 1001 1002 /* 1003 * Probe for an SiS chip. Check the PCI vendor and device 1004 * IDs against our list and return a device name if we find a match. 1005 */ 1006 static int 1007 sis_probe(dev) 1008 device_t dev; 1009 { 1010 struct sis_type *t; 1011 1012 t = sis_devs; 1013 1014 while(t->sis_name != NULL) { 1015 if ((pci_get_vendor(dev) == t->sis_vid) && 1016 (pci_get_device(dev) == t->sis_did)) { 1017 device_set_desc(dev, t->sis_name); 1018 return(0); 1019 } 1020 t++; 1021 } 1022 1023 return(ENXIO); 1024 } 1025 1026 /* 1027 * Attach the interface. Allocate softc structures, do ifmedia 1028 * setup and ethernet/BPF attach. 1029 */ 1030 static int 1031 sis_attach(dev) 1032 device_t dev; 1033 { 1034 u_char eaddr[ETHER_ADDR_LEN]; 1035 struct sis_softc *sc; 1036 struct ifnet *ifp; 1037 int unit, error = 0, rid, waittime = 0; 1038 1039 waittime = 0; 1040 sc = device_get_softc(dev); 1041 unit = device_get_unit(dev); 1042 1043 sc->sis_self = dev; 1044 1045 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1046 MTX_DEF | MTX_RECURSE); 1047 1048 if (pci_get_device(dev) == SIS_DEVICEID_900) 1049 sc->sis_type = SIS_TYPE_900; 1050 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1051 sc->sis_type = SIS_TYPE_7016; 1052 if (pci_get_vendor(dev) == NS_VENDORID) 1053 sc->sis_type = SIS_TYPE_83815; 1054 1055 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1056 /* 1057 * Map control/status registers. 1058 */ 1059 pci_enable_busmaster(dev); 1060 1061 rid = SIS_RID; 1062 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 1063 1064 if (sc->sis_res == NULL) { 1065 printf("sis%d: couldn't map ports/memory\n", unit); 1066 error = ENXIO; 1067 goto fail; 1068 } 1069 1070 sc->sis_btag = rman_get_bustag(sc->sis_res); 1071 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1072 1073 /* Allocate interrupt */ 1074 rid = 0; 1075 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1076 RF_SHAREABLE | RF_ACTIVE); 1077 1078 if (sc->sis_irq == NULL) { 1079 printf("sis%d: couldn't map interrupt\n", unit); 1080 error = ENXIO; 1081 goto fail; 1082 } 1083 1084 /* Reset the adapter. */ 1085 sis_reset(sc); 1086 1087 if (sc->sis_type == SIS_TYPE_900 && 1088 (sc->sis_rev == SIS_REV_635 || 1089 sc->sis_rev == SIS_REV_900B)) { 1090 SIO_SET(SIS_CFG_RND_CNT); 1091 SIO_SET(SIS_CFG_PERR_DETECT); 1092 } 1093 1094 /* 1095 * Get station address from the EEPROM. 1096 */ 1097 switch (pci_get_vendor(dev)) { 1098 case NS_VENDORID: 1099 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1100 1101 /* We can't update the device description, so spew */ 1102 if (sc->sis_srr == NS_SRR_15C) 1103 device_printf(dev, "Silicon Revision: DP83815C\n"); 1104 else if (sc->sis_srr == NS_SRR_15D) 1105 device_printf(dev, "Silicon Revision: DP83815D\n"); 1106 else if (sc->sis_srr == NS_SRR_16A) 1107 device_printf(dev, "Silicon Revision: DP83816A\n"); 1108 else 1109 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1110 1111 /* 1112 * Reading the MAC address out of the EEPROM on 1113 * the NatSemi chip takes a bit more work than 1114 * you'd expect. The address spans 4 16-bit words, 1115 * with the first word containing only a single bit. 1116 * You have to shift everything over one bit to 1117 * get it aligned properly. Also, the bits are 1118 * stored backwards (the LSB is really the MSB, 1119 * and so on) so you have to reverse them in order 1120 * to get the MAC address into the form we want. 1121 * Why? Who the hell knows. 1122 */ 1123 { 1124 u_int16_t tmp[4]; 1125 1126 sis_read_eeprom(sc, (caddr_t)&tmp, 1127 NS_EE_NODEADDR, 4, 0); 1128 1129 /* Shift everything over one bit. */ 1130 tmp[3] = tmp[3] >> 1; 1131 tmp[3] |= tmp[2] << 15; 1132 tmp[2] = tmp[2] >> 1; 1133 tmp[2] |= tmp[1] << 15; 1134 tmp[1] = tmp[1] >> 1; 1135 tmp[1] |= tmp[0] << 15; 1136 1137 /* Now reverse all the bits. */ 1138 tmp[3] = sis_reverse(tmp[3]); 1139 tmp[2] = sis_reverse(tmp[2]); 1140 tmp[1] = sis_reverse(tmp[1]); 1141 1142 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1143 } 1144 break; 1145 case SIS_VENDORID: 1146 default: 1147 #ifdef __i386__ 1148 /* 1149 * If this is a SiS 630E chipset with an embedded 1150 * SiS 900 controller, we have to read the MAC address 1151 * from the APC CMOS RAM. Our method for doing this 1152 * is very ugly since we have to reach out and grab 1153 * ahold of hardware for which we cannot properly 1154 * allocate resources. This code is only compiled on 1155 * the i386 architecture since the SiS 630E chipset 1156 * is for x86 motherboards only. Note that there are 1157 * a lot of magic numbers in this hack. These are 1158 * taken from SiS's Linux driver. I'd like to replace 1159 * them with proper symbolic definitions, but that 1160 * requires some datasheets that I don't have access 1161 * to at the moment. 1162 */ 1163 if (sc->sis_rev == SIS_REV_630S || 1164 sc->sis_rev == SIS_REV_630E || 1165 sc->sis_rev == SIS_REV_630EA1) 1166 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1167 1168 else if (sc->sis_rev == SIS_REV_635 || 1169 sc->sis_rev == SIS_REV_630ET) 1170 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1171 else if (sc->sis_rev == SIS_REV_96x) { 1172 /* Allow to read EEPROM from LAN. It is shared 1173 * between a 1394 controller and the NIC and each 1174 * time we access it, we need to set SIS_EECMD_REQ. 1175 */ 1176 SIO_SET(SIS_EECMD_REQ); 1177 for (waittime = 0; waittime < SIS_TIMEOUT; 1178 waittime++) { 1179 /* Force EEPROM to idle state. */ 1180 sis_eeprom_idle(sc); 1181 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1182 sis_read_eeprom(sc, (caddr_t)&eaddr, 1183 SIS_EE_NODEADDR, 3, 0); 1184 break; 1185 } 1186 DELAY(1); 1187 } 1188 /* 1189 * Set SIS_EECTL_CLK to high, so a other master 1190 * can operate on the i2c bus. 1191 */ 1192 SIO_SET(SIS_EECTL_CLK); 1193 /* Refuse EEPROM access by LAN */ 1194 SIO_SET(SIS_EECMD_DONE); 1195 } else 1196 #endif 1197 sis_read_eeprom(sc, (caddr_t)&eaddr, 1198 SIS_EE_NODEADDR, 3, 0); 1199 break; 1200 } 1201 1202 sc->sis_unit = unit; 1203 if (debug_mpsafenet) 1204 callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1205 else 1206 callout_init(&sc->sis_stat_ch, 0); 1207 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1208 1209 /* 1210 * Allocate the parent bus DMA tag appropriate for PCI. 1211 */ 1212 #define SIS_NSEG_NEW 32 1213 error = bus_dma_tag_create(NULL, /* parent */ 1214 1, 0, /* alignment, boundary */ 1215 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1216 BUS_SPACE_MAXADDR, /* highaddr */ 1217 NULL, NULL, /* filter, filterarg */ 1218 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1219 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1220 BUS_DMA_ALLOCNOW, /* flags */ 1221 NULL, NULL, /* lockfunc, lockarg */ 1222 &sc->sis_parent_tag); 1223 if (error) 1224 goto fail; 1225 1226 /* 1227 * Now allocate a tag for the DMA descriptor lists and a chunk 1228 * of DMA-able memory based on the tag. Also obtain the physical 1229 * addresses of the RX and TX ring, which we'll need later. 1230 * All of our lists are allocated as a contiguous block 1231 * of memory. 1232 */ 1233 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1234 1, 0, /* alignment, boundary */ 1235 BUS_SPACE_MAXADDR, /* lowaddr */ 1236 BUS_SPACE_MAXADDR, /* highaddr */ 1237 NULL, NULL, /* filter, filterarg */ 1238 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1239 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1240 0, /* flags */ 1241 busdma_lock_mutex, /* lockfunc */ 1242 &Giant, /* lockarg */ 1243 &sc->sis_ldata.sis_rx_tag); 1244 if (error) 1245 goto fail; 1246 1247 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1248 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1249 &sc->sis_ldata.sis_rx_dmamap); 1250 1251 if (error) { 1252 printf("sis%d: no memory for rx list buffers!\n", unit); 1253 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1254 sc->sis_ldata.sis_rx_tag = NULL; 1255 goto fail; 1256 } 1257 1258 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1259 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1260 sizeof(struct sis_desc), sis_dma_map_ring, 1261 &sc->sis_cdata.sis_rx_paddr, 0); 1262 1263 if (error) { 1264 printf("sis%d: cannot get address of the rx ring!\n", unit); 1265 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1266 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1267 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1268 sc->sis_ldata.sis_rx_tag = NULL; 1269 goto fail; 1270 } 1271 1272 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1273 1, 0, /* alignment, boundary */ 1274 BUS_SPACE_MAXADDR, /* lowaddr */ 1275 BUS_SPACE_MAXADDR, /* highaddr */ 1276 NULL, NULL, /* filter, filterarg */ 1277 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1278 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1279 0, /* flags */ 1280 busdma_lock_mutex, /* lockfunc */ 1281 &Giant, /* lockarg */ 1282 &sc->sis_ldata.sis_tx_tag); 1283 if (error) 1284 goto fail; 1285 1286 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1287 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1288 &sc->sis_ldata.sis_tx_dmamap); 1289 1290 if (error) { 1291 printf("sis%d: no memory for tx list buffers!\n", unit); 1292 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1293 sc->sis_ldata.sis_tx_tag = NULL; 1294 goto fail; 1295 } 1296 1297 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1298 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1299 sizeof(struct sis_desc), sis_dma_map_ring, 1300 &sc->sis_cdata.sis_tx_paddr, 0); 1301 1302 if (error) { 1303 printf("sis%d: cannot get address of the tx ring!\n", unit); 1304 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1305 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1306 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1307 sc->sis_ldata.sis_tx_tag = NULL; 1308 goto fail; 1309 } 1310 1311 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1312 1, 0, /* alignment, boundary */ 1313 BUS_SPACE_MAXADDR, /* lowaddr */ 1314 BUS_SPACE_MAXADDR, /* highaddr */ 1315 NULL, NULL, /* filter, filterarg */ 1316 MCLBYTES, 1, /* maxsize,nsegments */ 1317 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1318 0, /* flags */ 1319 busdma_lock_mutex, /* lockfunc */ 1320 &Giant, /* lockarg */ 1321 &sc->sis_tag); 1322 if (error) 1323 goto fail; 1324 1325 /* 1326 * Obtain the physical addresses of the RX and TX 1327 * rings which we'll need later in the init routine. 1328 */ 1329 1330 ifp = &sc->arpcom.ac_if; 1331 ifp->if_softc = sc; 1332 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1333 ifp->if_mtu = ETHERMTU; 1334 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1335 ifp->if_ioctl = sis_ioctl; 1336 ifp->if_start = sis_start; 1337 ifp->if_watchdog = sis_watchdog; 1338 ifp->if_init = sis_init; 1339 ifp->if_baudrate = 10000000; 1340 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1341 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1342 IFQ_SET_READY(&ifp->if_snd); 1343 1344 /* 1345 * Do MII setup. 1346 */ 1347 if (mii_phy_probe(dev, &sc->sis_miibus, 1348 sis_ifmedia_upd, sis_ifmedia_sts)) { 1349 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1350 error = ENXIO; 1351 goto fail; 1352 } 1353 1354 /* 1355 * Call MI attach routine. 1356 */ 1357 ether_ifattach(ifp, eaddr); 1358 1359 /* 1360 * Tell the upper layer(s) we support long frames. 1361 */ 1362 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1363 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1364 1365 #ifdef DEVICE_POLLING 1366 ifp->if_capabilities |= IFCAP_POLLING; 1367 #endif 1368 ifp->if_capenable = ifp->if_capabilities; 1369 1370 /* Hook interrupt last to avoid having to lock softc */ 1371 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, 1372 sis_intr, sc, &sc->sis_intrhand); 1373 1374 if (error) { 1375 printf("sis%d: couldn't set up irq\n", unit); 1376 ether_ifdetach(ifp); 1377 goto fail; 1378 } 1379 1380 fail: 1381 if (error) 1382 sis_detach(dev); 1383 1384 return(error); 1385 } 1386 1387 /* 1388 * Shutdown hardware and free up resources. This can be called any 1389 * time after the mutex has been initialized. It is called in both 1390 * the error case in attach and the normal detach case so it needs 1391 * to be careful about only freeing resources that have actually been 1392 * allocated. 1393 */ 1394 static int 1395 sis_detach(dev) 1396 device_t dev; 1397 { 1398 struct sis_softc *sc; 1399 struct ifnet *ifp; 1400 1401 sc = device_get_softc(dev); 1402 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1403 SIS_LOCK(sc); 1404 ifp = &sc->arpcom.ac_if; 1405 1406 /* These should only be active if attach succeeded. */ 1407 if (device_is_attached(dev)) { 1408 sis_reset(sc); 1409 sis_stop(sc); 1410 ether_ifdetach(ifp); 1411 } 1412 if (sc->sis_miibus) 1413 device_delete_child(dev, sc->sis_miibus); 1414 bus_generic_detach(dev); 1415 1416 if (sc->sis_intrhand) 1417 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1418 if (sc->sis_irq) 1419 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1420 if (sc->sis_res) 1421 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1422 1423 if (sc->sis_ldata.sis_rx_tag) { 1424 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1425 sc->sis_ldata.sis_rx_dmamap); 1426 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1427 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1428 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1429 } 1430 if (sc->sis_ldata.sis_tx_tag) { 1431 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1432 sc->sis_ldata.sis_tx_dmamap); 1433 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1434 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1435 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1436 } 1437 if (sc->sis_parent_tag) 1438 bus_dma_tag_destroy(sc->sis_parent_tag); 1439 if (sc->sis_tag) 1440 bus_dma_tag_destroy(sc->sis_tag); 1441 1442 SIS_UNLOCK(sc); 1443 mtx_destroy(&sc->sis_mtx); 1444 1445 return(0); 1446 } 1447 1448 /* 1449 * Initialize the transmit descriptors. 1450 */ 1451 static int 1452 sis_list_tx_init(sc) 1453 struct sis_softc *sc; 1454 { 1455 struct sis_list_data *ld; 1456 struct sis_ring_data *cd; 1457 int i, nexti; 1458 1459 cd = &sc->sis_cdata; 1460 ld = &sc->sis_ldata; 1461 1462 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1463 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1464 ld->sis_tx_list[i].sis_nextdesc = 1465 &ld->sis_tx_list[nexti]; 1466 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1467 sc->sis_ldata.sis_tx_dmamap, 1468 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1469 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1470 ld->sis_tx_list[i].sis_mbuf = NULL; 1471 ld->sis_tx_list[i].sis_ptr = 0; 1472 ld->sis_tx_list[i].sis_ctl = 0; 1473 } 1474 1475 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1476 1477 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1478 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1479 1480 return(0); 1481 } 1482 1483 /* 1484 * Initialize the RX descriptors and allocate mbufs for them. Note that 1485 * we arrange the descriptors in a closed ring, so that the last descriptor 1486 * points back to the first. 1487 */ 1488 static int 1489 sis_list_rx_init(sc) 1490 struct sis_softc *sc; 1491 { 1492 struct sis_list_data *ld; 1493 struct sis_ring_data *cd; 1494 int i,nexti; 1495 1496 ld = &sc->sis_ldata; 1497 cd = &sc->sis_cdata; 1498 1499 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1500 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1501 return(ENOBUFS); 1502 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1503 ld->sis_rx_list[i].sis_nextdesc = 1504 &ld->sis_rx_list[nexti]; 1505 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1506 sc->sis_ldata.sis_rx_dmamap, 1507 &ld->sis_rx_list[nexti], 1508 sizeof(struct sis_desc), sis_dma_map_desc_next, 1509 &ld->sis_rx_list[i], 0); 1510 } 1511 1512 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1513 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1514 1515 cd->sis_rx_prod = 0; 1516 1517 return(0); 1518 } 1519 1520 /* 1521 * Initialize an RX descriptor and attach an MBUF cluster. 1522 */ 1523 static int 1524 sis_newbuf(sc, c, m) 1525 struct sis_softc *sc; 1526 struct sis_desc *c; 1527 struct mbuf *m; 1528 { 1529 1530 if (c == NULL) 1531 return(EINVAL); 1532 1533 if (m == NULL) { 1534 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1535 if (m == NULL) 1536 return(ENOBUFS); 1537 } else 1538 m->m_data = m->m_ext.ext_buf; 1539 1540 c->sis_mbuf = m; 1541 c->sis_ctl = SIS_RXLEN; 1542 1543 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1544 bus_dmamap_load(sc->sis_tag, c->sis_map, 1545 mtod(m, void *), MCLBYTES, 1546 sis_dma_map_desc_ptr, c, 0); 1547 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD); 1548 1549 return(0); 1550 } 1551 1552 /* 1553 * A frame has been uploaded: pass the resulting mbuf chain up to 1554 * the higher level protocols. 1555 */ 1556 static void 1557 sis_rxeof(sc) 1558 struct sis_softc *sc; 1559 { 1560 struct mbuf *m; 1561 struct ifnet *ifp; 1562 struct sis_desc *cur_rx; 1563 int i, total_len = 0; 1564 u_int32_t rxstat; 1565 1566 SIS_LOCK_ASSERT(sc); 1567 1568 ifp = &sc->arpcom.ac_if; 1569 i = sc->sis_cdata.sis_rx_prod; 1570 1571 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1572 1573 #ifdef DEVICE_POLLING 1574 if (ifp->if_flags & IFF_POLLING) { 1575 if (sc->rxcycles <= 0) 1576 break; 1577 sc->rxcycles--; 1578 } 1579 #endif /* DEVICE_POLLING */ 1580 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1581 rxstat = cur_rx->sis_rxstat; 1582 bus_dmamap_sync(sc->sis_tag, 1583 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1584 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1585 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1586 m = cur_rx->sis_mbuf; 1587 cur_rx->sis_mbuf = NULL; 1588 total_len = SIS_RXBYTES(cur_rx); 1589 SIS_INC(i, SIS_RX_LIST_CNT); 1590 1591 /* 1592 * If an error occurs, update stats, clear the 1593 * status word and leave the mbuf cluster in place: 1594 * it should simply get re-used next time this descriptor 1595 * comes up in the ring. 1596 */ 1597 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1598 ifp->if_ierrors++; 1599 if (rxstat & SIS_RXSTAT_COLL) 1600 ifp->if_collisions++; 1601 sis_newbuf(sc, cur_rx, m); 1602 continue; 1603 } 1604 1605 /* No errors; receive the packet. */ 1606 #ifdef __i386__ 1607 /* 1608 * On the x86 we do not have alignment problems, so try to 1609 * allocate a new buffer for the receive ring, and pass up 1610 * the one where the packet is already, saving the expensive 1611 * copy done in m_devget(). 1612 * If we are on an architecture with alignment problems, or 1613 * if the allocation fails, then use m_devget and leave the 1614 * existing buffer in the receive ring. 1615 */ 1616 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1617 m->m_pkthdr.len = m->m_len = total_len; 1618 else 1619 #endif 1620 { 1621 struct mbuf *m0; 1622 m0 = m_devget(mtod(m, char *), total_len, 1623 ETHER_ALIGN, ifp, NULL); 1624 sis_newbuf(sc, cur_rx, m); 1625 if (m0 == NULL) { 1626 ifp->if_ierrors++; 1627 continue; 1628 } 1629 m = m0; 1630 } 1631 1632 ifp->if_ipackets++; 1633 m->m_pkthdr.rcvif = ifp; 1634 1635 SIS_UNLOCK(sc); 1636 (*ifp->if_input)(ifp, m); 1637 SIS_LOCK(sc); 1638 } 1639 1640 sc->sis_cdata.sis_rx_prod = i; 1641 1642 return; 1643 } 1644 1645 static void 1646 sis_rxeoc(sc) 1647 struct sis_softc *sc; 1648 { 1649 sis_rxeof(sc); 1650 sis_init(sc); 1651 return; 1652 } 1653 1654 /* 1655 * A frame was downloaded to the chip. It's safe for us to clean up 1656 * the list buffers. 1657 */ 1658 1659 static void 1660 sis_txeof(sc) 1661 struct sis_softc *sc; 1662 { 1663 struct ifnet *ifp; 1664 u_int32_t idx; 1665 1666 ifp = &sc->arpcom.ac_if; 1667 1668 /* 1669 * Go through our tx list and free mbufs for those 1670 * frames that have been transmitted. 1671 */ 1672 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1673 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1674 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1675 1676 if (SIS_OWNDESC(cur_tx)) 1677 break; 1678 1679 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1680 continue; 1681 1682 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1683 ifp->if_oerrors++; 1684 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1685 ifp->if_collisions++; 1686 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1687 ifp->if_collisions++; 1688 } 1689 1690 ifp->if_collisions += 1691 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1692 1693 ifp->if_opackets++; 1694 if (cur_tx->sis_mbuf != NULL) { 1695 m_freem(cur_tx->sis_mbuf); 1696 cur_tx->sis_mbuf = NULL; 1697 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1698 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1699 } 1700 } 1701 1702 if (idx != sc->sis_cdata.sis_tx_cons) { 1703 /* we freed up some buffers */ 1704 sc->sis_cdata.sis_tx_cons = idx; 1705 ifp->if_flags &= ~IFF_OACTIVE; 1706 } 1707 1708 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1709 1710 return; 1711 } 1712 1713 static void 1714 sis_tick(xsc) 1715 void *xsc; 1716 { 1717 struct sis_softc *sc; 1718 struct mii_data *mii; 1719 struct ifnet *ifp; 1720 1721 sc = xsc; 1722 SIS_LOCK(sc); 1723 sc->in_tick = 1; 1724 ifp = &sc->arpcom.ac_if; 1725 1726 mii = device_get_softc(sc->sis_miibus); 1727 mii_tick(mii); 1728 1729 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1730 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1731 sc->sis_link++; 1732 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1733 sis_start(ifp); 1734 } 1735 1736 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1737 sc->in_tick = 0; 1738 SIS_UNLOCK(sc); 1739 1740 return; 1741 } 1742 1743 #ifdef DEVICE_POLLING 1744 static poll_handler_t sis_poll; 1745 1746 static void 1747 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1748 { 1749 struct sis_softc *sc = ifp->if_softc; 1750 1751 SIS_LOCK(sc); 1752 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1753 ether_poll_deregister(ifp); 1754 cmd = POLL_DEREGISTER; 1755 } 1756 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1757 CSR_WRITE_4(sc, SIS_IER, 1); 1758 goto done; 1759 } 1760 1761 /* 1762 * On the sis, reading the status register also clears it. 1763 * So before returning to intr mode we must make sure that all 1764 * possible pending sources of interrupts have been served. 1765 * In practice this means run to completion the *eof routines, 1766 * and then call the interrupt routine 1767 */ 1768 sc->rxcycles = count; 1769 sis_rxeof(sc); 1770 sis_txeof(sc); 1771 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1772 sis_start(ifp); 1773 1774 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1775 u_int32_t status; 1776 1777 /* Reading the ISR register clears all interrupts. */ 1778 status = CSR_READ_4(sc, SIS_ISR); 1779 1780 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1781 sis_rxeoc(sc); 1782 1783 if (status & (SIS_ISR_RX_IDLE)) 1784 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1785 1786 if (status & SIS_ISR_SYSERR) { 1787 sis_reset(sc); 1788 sis_init(sc); 1789 } 1790 } 1791 done: 1792 SIS_UNLOCK(sc); 1793 return; 1794 } 1795 #endif /* DEVICE_POLLING */ 1796 1797 static void 1798 sis_intr(arg) 1799 void *arg; 1800 { 1801 struct sis_softc *sc; 1802 struct ifnet *ifp; 1803 u_int32_t status; 1804 1805 sc = arg; 1806 ifp = &sc->arpcom.ac_if; 1807 1808 SIS_LOCK(sc); 1809 #ifdef DEVICE_POLLING 1810 if (ifp->if_flags & IFF_POLLING) 1811 goto done; 1812 if ((ifp->if_capenable & IFCAP_POLLING) && 1813 ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1814 CSR_WRITE_4(sc, SIS_IER, 0); 1815 goto done; 1816 } 1817 #endif /* DEVICE_POLLING */ 1818 1819 /* Supress unwanted interrupts */ 1820 if (!(ifp->if_flags & IFF_UP)) { 1821 sis_stop(sc); 1822 goto done; 1823 } 1824 1825 /* Disable interrupts. */ 1826 CSR_WRITE_4(sc, SIS_IER, 0); 1827 1828 for (;;) { 1829 /* Reading the ISR register clears all interrupts. */ 1830 status = CSR_READ_4(sc, SIS_ISR); 1831 1832 if ((status & SIS_INTRS) == 0) 1833 break; 1834 1835 if (status & 1836 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1837 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1838 sis_txeof(sc); 1839 1840 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1841 sis_rxeof(sc); 1842 1843 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1844 sis_rxeoc(sc); 1845 1846 if (status & (SIS_ISR_RX_IDLE)) 1847 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1848 1849 if (status & SIS_ISR_SYSERR) { 1850 sis_reset(sc); 1851 sis_init(sc); 1852 } 1853 } 1854 1855 /* Re-enable interrupts. */ 1856 CSR_WRITE_4(sc, SIS_IER, 1); 1857 1858 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1859 sis_start(ifp); 1860 done: 1861 SIS_UNLOCK(sc); 1862 1863 return; 1864 } 1865 1866 /* 1867 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1868 * pointers to the fragment pointers. 1869 */ 1870 static int 1871 sis_encap(sc, m_head, txidx) 1872 struct sis_softc *sc; 1873 struct mbuf **m_head; 1874 u_int32_t *txidx; 1875 { 1876 struct sis_desc *f = NULL; 1877 struct mbuf *m; 1878 int frag, cur, cnt = 0, chainlen = 0; 1879 1880 /* 1881 * If there's no way we can send any packets, return now. 1882 */ 1883 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1884 return (ENOBUFS); 1885 1886 /* 1887 * Count the number of frags in this chain to see if 1888 * we need to m_defrag. Since the descriptor list is shared 1889 * by all packets, we'll m_defrag long chains so that they 1890 * do not use up the entire list, even if they would fit. 1891 */ 1892 1893 for (m = *m_head; m != NULL; m = m->m_next) 1894 chainlen++; 1895 1896 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1897 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { 1898 m = m_defrag(*m_head, M_DONTWAIT); 1899 if (m == NULL) 1900 return (ENOBUFS); 1901 *m_head = m; 1902 } 1903 1904 /* 1905 * Start packing the mbufs in this chain into 1906 * the fragment pointers. Stop when we run out 1907 * of fragments or hit the end of the mbuf chain. 1908 */ 1909 cur = frag = *txidx; 1910 1911 for (m = *m_head; m != NULL; m = m->m_next) { 1912 if (m->m_len != 0) { 1913 if ((SIS_TX_LIST_CNT - 1914 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1915 return(ENOBUFS); 1916 f = &sc->sis_ldata.sis_tx_list[frag]; 1917 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1918 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1919 bus_dmamap_load(sc->sis_tag, f->sis_map, 1920 mtod(m, void *), m->m_len, 1921 sis_dma_map_desc_ptr, f, 0); 1922 bus_dmamap_sync(sc->sis_tag, 1923 f->sis_map, BUS_DMASYNC_PREREAD); 1924 if (cnt != 0) 1925 f->sis_ctl |= SIS_CMDSTS_OWN; 1926 cur = frag; 1927 SIS_INC(frag, SIS_TX_LIST_CNT); 1928 cnt++; 1929 } 1930 } 1931 1932 if (m != NULL) 1933 return(ENOBUFS); 1934 1935 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = *m_head; 1936 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1937 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1938 sc->sis_cdata.sis_tx_cnt += cnt; 1939 *txidx = frag; 1940 1941 return(0); 1942 } 1943 1944 /* 1945 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1946 * to the mbuf data regions directly in the transmit lists. We also save a 1947 * copy of the pointers since the transmit list fragment pointers are 1948 * physical addresses. 1949 */ 1950 1951 static void 1952 sis_start(ifp) 1953 struct ifnet *ifp; 1954 { 1955 struct sis_softc *sc; 1956 struct mbuf *m_head = NULL; 1957 u_int32_t idx, queued = 0; 1958 1959 sc = ifp->if_softc; 1960 SIS_LOCK(sc); 1961 1962 if (!sc->sis_link) { 1963 SIS_UNLOCK(sc); 1964 return; 1965 } 1966 1967 idx = sc->sis_cdata.sis_tx_prod; 1968 1969 if (ifp->if_flags & IFF_OACTIVE) { 1970 SIS_UNLOCK(sc); 1971 return; 1972 } 1973 1974 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1975 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1976 if (m_head == NULL) 1977 break; 1978 1979 if (sis_encap(sc, &m_head, &idx)) { 1980 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1981 ifp->if_flags |= IFF_OACTIVE; 1982 break; 1983 } 1984 1985 queued++; 1986 1987 /* 1988 * If there's a BPF listener, bounce a copy of this frame 1989 * to him. 1990 */ 1991 BPF_MTAP(ifp, m_head); 1992 1993 } 1994 1995 if (queued) { 1996 /* Transmit */ 1997 sc->sis_cdata.sis_tx_prod = idx; 1998 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1999 2000 /* 2001 * Set a timeout in case the chip goes out to lunch. 2002 */ 2003 ifp->if_timer = 5; 2004 } 2005 2006 SIS_UNLOCK(sc); 2007 2008 return; 2009 } 2010 2011 static void 2012 sis_init(xsc) 2013 void *xsc; 2014 { 2015 struct sis_softc *sc = xsc; 2016 struct ifnet *ifp = &sc->arpcom.ac_if; 2017 struct mii_data *mii; 2018 2019 SIS_LOCK(sc); 2020 2021 /* 2022 * Cancel pending I/O and free all RX/TX buffers. 2023 */ 2024 sis_stop(sc); 2025 sc->sis_stopped = 0; 2026 2027 #ifdef notyet 2028 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 2029 /* 2030 * Configure 400usec of interrupt holdoff. This is based 2031 * on emperical tests on a Soekris 4801. 2032 */ 2033 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 2034 } 2035 #endif 2036 2037 mii = device_get_softc(sc->sis_miibus); 2038 2039 /* Set MAC address */ 2040 if (sc->sis_type == SIS_TYPE_83815) { 2041 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2042 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2043 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2044 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2045 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2046 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2047 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2048 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2049 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2050 } else { 2051 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2052 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2053 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2054 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2055 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2056 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2057 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2058 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2059 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2060 } 2061 2062 /* Init circular RX list. */ 2063 if (sis_list_rx_init(sc) == ENOBUFS) { 2064 printf("sis%d: initialization failed: no " 2065 "memory for rx buffers\n", sc->sis_unit); 2066 sis_stop(sc); 2067 SIS_UNLOCK(sc); 2068 return; 2069 } 2070 2071 /* 2072 * Init tx descriptors. 2073 */ 2074 sis_list_tx_init(sc); 2075 2076 /* 2077 * Page 78 of the DP83815 data sheet (september 2002 version) 2078 * recommends the following register settings "for optimum 2079 * performance." for rev 15C. The driver from NS also sets 2080 * the PHY_CR register for later versions. 2081 */ 2082 if (sc->sis_type == SIS_TYPE_83815) { 2083 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2084 /* DC speed = 01 */ 2085 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2086 if (sc->sis_srr == NS_SRR_15C) { 2087 /* set val for c2 */ 2088 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2089 /* load/kill c2 */ 2090 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2091 /* rais SD off, from 4 to c */ 2092 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2093 } 2094 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2095 } 2096 2097 2098 /* 2099 * For the NatSemi chip, we have to explicitly enable the 2100 * reception of ARP frames, as well as turn on the 'perfect 2101 * match' filter where we store the station address, otherwise 2102 * we won't receive unicasts meant for this host. 2103 */ 2104 if (sc->sis_type == SIS_TYPE_83815) { 2105 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 2106 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 2107 } 2108 2109 /* If we want promiscuous mode, set the allframes bit. */ 2110 if (ifp->if_flags & IFF_PROMISC) { 2111 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2112 } else { 2113 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2114 } 2115 2116 /* 2117 * Set the capture broadcast bit to capture broadcast frames. 2118 */ 2119 if (ifp->if_flags & IFF_BROADCAST) { 2120 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2121 } else { 2122 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2123 } 2124 2125 /* 2126 * Load the multicast filter. 2127 */ 2128 if (sc->sis_type == SIS_TYPE_83815) 2129 sis_setmulti_ns(sc); 2130 else 2131 sis_setmulti_sis(sc); 2132 2133 /* Turn the receive filter on */ 2134 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2135 2136 /* 2137 * Load the address of the RX and TX lists. 2138 */ 2139 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 2140 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 2141 2142 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2143 * the PCI bus. When this bit is set, the Max DMA Burst Size 2144 * for TX/RX DMA should be no larger than 16 double words. 2145 */ 2146 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2147 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2148 } else { 2149 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2150 } 2151 2152 /* Accept Long Packets for VLAN support */ 2153 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2154 2155 /* Set TX configuration */ 2156 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2157 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2158 } else { 2159 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2160 } 2161 2162 /* Set full/half duplex mode. */ 2163 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2164 SIS_SETBIT(sc, SIS_TX_CFG, 2165 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2166 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2167 } else { 2168 SIS_CLRBIT(sc, SIS_TX_CFG, 2169 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2170 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2171 } 2172 2173 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2174 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2175 uint32_t reg; 2176 2177 /* 2178 * Some DP83815s experience problems when used with short 2179 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 2180 * sequence adjusts the DSP's signal attenuation to fix the 2181 * problem. 2182 */ 2183 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2184 2185 reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2186 /* Allow coefficient to be read */ 2187 CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 2188 DELAY(100); 2189 reg = CSR_READ_4(sc, NS_PHY_TDATA); 2190 if ((reg & 0x0080) == 0 || 2191 (reg > 0xd8 && reg <= 0xff)) { 2192 device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); 2193 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2194 /* Adjust coefficient and prevent change */ 2195 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2196 } 2197 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2198 } 2199 2200 /* 2201 * Enable interrupts. 2202 */ 2203 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2204 #ifdef DEVICE_POLLING 2205 /* 2206 * ... only enable interrupts if we are not polling, make sure 2207 * they are off otherwise. 2208 */ 2209 if (ifp->if_flags & IFF_POLLING) 2210 CSR_WRITE_4(sc, SIS_IER, 0); 2211 else 2212 #endif /* DEVICE_POLLING */ 2213 CSR_WRITE_4(sc, SIS_IER, 1); 2214 2215 /* Enable receiver and transmitter. */ 2216 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2217 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2218 2219 #ifdef notdef 2220 mii_mediachg(mii); 2221 #endif 2222 2223 ifp->if_flags |= IFF_RUNNING; 2224 ifp->if_flags &= ~IFF_OACTIVE; 2225 2226 if (!sc->in_tick) 2227 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2228 2229 SIS_UNLOCK(sc); 2230 2231 return; 2232 } 2233 2234 /* 2235 * Set media options. 2236 */ 2237 static int 2238 sis_ifmedia_upd(ifp) 2239 struct ifnet *ifp; 2240 { 2241 struct sis_softc *sc; 2242 struct mii_data *mii; 2243 2244 sc = ifp->if_softc; 2245 2246 mii = device_get_softc(sc->sis_miibus); 2247 sc->sis_link = 0; 2248 if (mii->mii_instance) { 2249 struct mii_softc *miisc; 2250 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2251 mii_phy_reset(miisc); 2252 } 2253 mii_mediachg(mii); 2254 2255 return(0); 2256 } 2257 2258 /* 2259 * Report current media status. 2260 */ 2261 static void 2262 sis_ifmedia_sts(ifp, ifmr) 2263 struct ifnet *ifp; 2264 struct ifmediareq *ifmr; 2265 { 2266 struct sis_softc *sc; 2267 struct mii_data *mii; 2268 2269 sc = ifp->if_softc; 2270 2271 mii = device_get_softc(sc->sis_miibus); 2272 mii_pollstat(mii); 2273 ifmr->ifm_active = mii->mii_media_active; 2274 ifmr->ifm_status = mii->mii_media_status; 2275 2276 return; 2277 } 2278 2279 static int 2280 sis_ioctl(ifp, command, data) 2281 struct ifnet *ifp; 2282 u_long command; 2283 caddr_t data; 2284 { 2285 struct sis_softc *sc = ifp->if_softc; 2286 struct ifreq *ifr = (struct ifreq *) data; 2287 struct mii_data *mii; 2288 int error = 0; 2289 2290 switch(command) { 2291 case SIOCSIFFLAGS: 2292 if (ifp->if_flags & IFF_UP) { 2293 sis_init(sc); 2294 } else { 2295 if (ifp->if_flags & IFF_RUNNING) 2296 sis_stop(sc); 2297 } 2298 error = 0; 2299 break; 2300 case SIOCADDMULTI: 2301 case SIOCDELMULTI: 2302 SIS_LOCK(sc); 2303 if (sc->sis_type == SIS_TYPE_83815) 2304 sis_setmulti_ns(sc); 2305 else 2306 sis_setmulti_sis(sc); 2307 SIS_UNLOCK(sc); 2308 error = 0; 2309 break; 2310 case SIOCGIFMEDIA: 2311 case SIOCSIFMEDIA: 2312 mii = device_get_softc(sc->sis_miibus); 2313 SIS_LOCK(sc); 2314 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2315 SIS_UNLOCK(sc); 2316 break; 2317 case SIOCSIFCAP: 2318 ifp->if_capenable &= ~IFCAP_POLLING; 2319 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2320 break; 2321 default: 2322 error = ether_ioctl(ifp, command, data); 2323 break; 2324 } 2325 2326 return(error); 2327 } 2328 2329 static void 2330 sis_watchdog(ifp) 2331 struct ifnet *ifp; 2332 { 2333 struct sis_softc *sc; 2334 2335 sc = ifp->if_softc; 2336 2337 SIS_LOCK(sc); 2338 2339 ifp->if_oerrors++; 2340 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2341 2342 sis_stop(sc); 2343 sis_reset(sc); 2344 sis_init(sc); 2345 2346 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2347 sis_start(ifp); 2348 2349 SIS_UNLOCK(sc); 2350 2351 return; 2352 } 2353 2354 /* 2355 * Stop the adapter and free any mbufs allocated to the 2356 * RX and TX lists. 2357 */ 2358 static void 2359 sis_stop(sc) 2360 struct sis_softc *sc; 2361 { 2362 register int i; 2363 struct ifnet *ifp; 2364 2365 if (sc->sis_stopped) 2366 return; 2367 SIS_LOCK(sc); 2368 ifp = &sc->arpcom.ac_if; 2369 ifp->if_timer = 0; 2370 2371 callout_stop(&sc->sis_stat_ch); 2372 2373 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2374 #ifdef DEVICE_POLLING 2375 ether_poll_deregister(ifp); 2376 #endif 2377 CSR_WRITE_4(sc, SIS_IER, 0); 2378 CSR_WRITE_4(sc, SIS_IMR, 0); 2379 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2380 DELAY(1000); 2381 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2382 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2383 2384 sc->sis_link = 0; 2385 2386 /* 2387 * Free data in the RX lists. 2388 */ 2389 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2390 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2391 bus_dmamap_unload(sc->sis_tag, 2392 sc->sis_ldata.sis_rx_list[i].sis_map); 2393 bus_dmamap_destroy(sc->sis_tag, 2394 sc->sis_ldata.sis_rx_list[i].sis_map); 2395 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2396 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2397 } 2398 } 2399 bzero(sc->sis_ldata.sis_rx_list, 2400 sizeof(sc->sis_ldata.sis_rx_list)); 2401 2402 /* 2403 * Free the TX list buffers. 2404 */ 2405 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2406 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2407 bus_dmamap_unload(sc->sis_tag, 2408 sc->sis_ldata.sis_tx_list[i].sis_map); 2409 bus_dmamap_destroy(sc->sis_tag, 2410 sc->sis_ldata.sis_tx_list[i].sis_map); 2411 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2412 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2413 } 2414 } 2415 2416 bzero(sc->sis_ldata.sis_tx_list, 2417 sizeof(sc->sis_ldata.sis_tx_list)); 2418 2419 sc->sis_stopped = 1; 2420 SIS_UNLOCK(sc); 2421 2422 return; 2423 } 2424 2425 /* 2426 * Stop all chip I/O so that the kernel's probe routines don't 2427 * get confused by errant DMAs when rebooting. 2428 */ 2429 static void 2430 sis_shutdown(dev) 2431 device_t dev; 2432 { 2433 struct sis_softc *sc; 2434 2435 sc = device_get_softc(dev); 2436 SIS_LOCK(sc); 2437 sis_reset(sc); 2438 sis_stop(sc); 2439 SIS_UNLOCK(sc); 2440 2441 return; 2442 }
Cache object: c206f65e935ca1ec176f4e71fee058c6
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