Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sis.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/module.h> 67 #include <sys/socket.h> 68 #include <sys/sysctl.h> 69 70 #include <net/if.h> 71 #include <net/if_arp.h> 72 #include <net/ethernet.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 #include <net/if_vlan_var.h> 77 78 #include <net/bpf.h> 79 80 #include <machine/bus_pio.h> 81 #include <machine/bus_memio.h> 82 #include <machine/bus.h> 83 #include <machine/resource.h> 84 #include <sys/bus.h> 85 #include <sys/rman.h> 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <dev/pci/pcireg.h> 91 #include <dev/pci/pcivar.h> 92 93 #define SIS_USEIOSPACE 94 95 #include <pci/if_sisreg.h> 96 97 MODULE_DEPEND(sis, pci, 1, 1, 1); 98 MODULE_DEPEND(sis, ether, 1, 1, 1); 99 MODULE_DEPEND(sis, miibus, 1, 1, 1); 100 101 /* "controller miibus0" required. See GENERIC if you get errors here. */ 102 #include "miibus_if.h" 103 104 /* 105 * Various supported device vendors/types and their names. 106 */ 107 static struct sis_type sis_devs[] = { 108 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 109 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 110 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 111 { 0, 0, NULL } 112 }; 113 114 static int sis_probe (device_t); 115 static int sis_attach (device_t); 116 static int sis_detach (device_t); 117 118 static int sis_newbuf (struct sis_softc *, 119 struct sis_desc *, struct mbuf *); 120 static int sis_encap (struct sis_softc *, 121 struct mbuf **, u_int32_t *); 122 static void sis_rxeof (struct sis_softc *); 123 static void sis_rxeoc (struct sis_softc *); 124 static void sis_txeof (struct sis_softc *); 125 static void sis_intr (void *); 126 static void sis_tick (void *); 127 static void sis_start (struct ifnet *); 128 static int sis_ioctl (struct ifnet *, u_long, caddr_t); 129 static void sis_init (void *); 130 static void sis_stop (struct sis_softc *); 131 static void sis_watchdog (struct ifnet *); 132 static void sis_shutdown (device_t); 133 static int sis_ifmedia_upd (struct ifnet *); 134 static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 135 136 static u_int16_t sis_reverse (u_int16_t); 137 static void sis_delay (struct sis_softc *); 138 static void sis_eeprom_idle (struct sis_softc *); 139 static void sis_eeprom_putbyte (struct sis_softc *, int); 140 static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 141 static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 142 #ifdef __i386__ 143 static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 144 int, int); 145 static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 146 static device_t sis_find_bridge (device_t); 147 #endif 148 149 static void sis_mii_sync (struct sis_softc *); 150 static void sis_mii_send (struct sis_softc *, u_int32_t, int); 151 static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 152 static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 153 static int sis_miibus_readreg (device_t, int, int); 154 static int sis_miibus_writereg (device_t, int, int, int); 155 static void sis_miibus_statchg (device_t); 156 157 static void sis_setmulti_sis (struct sis_softc *); 158 static void sis_setmulti_ns (struct sis_softc *); 159 static uint32_t sis_mchash (struct sis_softc *, const uint8_t *); 160 static void sis_reset (struct sis_softc *); 161 static int sis_list_rx_init (struct sis_softc *); 162 static int sis_list_tx_init (struct sis_softc *); 163 164 static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 165 static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 166 static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 167 #ifdef SIS_USEIOSPACE 168 #define SIS_RES SYS_RES_IOPORT 169 #define SIS_RID SIS_PCI_LOIO 170 #else 171 #define SIS_RES SYS_RES_MEMORY 172 #define SIS_RID SIS_PCI_LOMEM 173 #endif 174 175 static device_method_t sis_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, sis_probe), 178 DEVMETHOD(device_attach, sis_attach), 179 DEVMETHOD(device_detach, sis_detach), 180 DEVMETHOD(device_shutdown, sis_shutdown), 181 182 /* bus interface */ 183 DEVMETHOD(bus_print_child, bus_generic_print_child), 184 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 185 186 /* MII interface */ 187 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 188 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 189 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 190 191 { 0, 0 } 192 }; 193 194 static driver_t sis_driver = { 195 "sis", 196 sis_methods, 197 sizeof(struct sis_softc) 198 }; 199 200 static devclass_t sis_devclass; 201 202 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 203 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 204 205 #define SIS_SETBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, \ 207 CSR_READ_4(sc, reg) | (x)) 208 209 #define SIS_CLRBIT(sc, reg, x) \ 210 CSR_WRITE_4(sc, reg, \ 211 CSR_READ_4(sc, reg) & ~(x)) 212 213 #define SIO_SET(x) \ 214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 215 216 #define SIO_CLR(x) \ 217 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 218 219 static void 220 sis_dma_map_desc_next(arg, segs, nseg, error) 221 void *arg; 222 bus_dma_segment_t *segs; 223 int nseg, error; 224 { 225 struct sis_desc *r; 226 227 r = arg; 228 r->sis_next = segs->ds_addr; 229 230 return; 231 } 232 233 static void 234 sis_dma_map_desc_ptr(arg, segs, nseg, error) 235 void *arg; 236 bus_dma_segment_t *segs; 237 int nseg, error; 238 { 239 struct sis_desc *r; 240 241 r = arg; 242 r->sis_ptr = segs->ds_addr; 243 244 return; 245 } 246 247 static void 248 sis_dma_map_ring(arg, segs, nseg, error) 249 void *arg; 250 bus_dma_segment_t *segs; 251 int nseg, error; 252 { 253 u_int32_t *p; 254 255 p = arg; 256 *p = segs->ds_addr; 257 258 return; 259 } 260 261 /* 262 * Routine to reverse the bits in a word. Stolen almost 263 * verbatim from /usr/games/fortune. 264 */ 265 static u_int16_t 266 sis_reverse(n) 267 u_int16_t n; 268 { 269 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 270 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 271 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 272 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 273 274 return(n); 275 } 276 277 static void 278 sis_delay(sc) 279 struct sis_softc *sc; 280 { 281 int idx; 282 283 for (idx = (300 / 33) + 1; idx > 0; idx--) 284 CSR_READ_4(sc, SIS_CSR); 285 286 return; 287 } 288 289 static void 290 sis_eeprom_idle(sc) 291 struct sis_softc *sc; 292 { 293 register int i; 294 295 SIO_SET(SIS_EECTL_CSEL); 296 sis_delay(sc); 297 SIO_SET(SIS_EECTL_CLK); 298 sis_delay(sc); 299 300 for (i = 0; i < 25; i++) { 301 SIO_CLR(SIS_EECTL_CLK); 302 sis_delay(sc); 303 SIO_SET(SIS_EECTL_CLK); 304 sis_delay(sc); 305 } 306 307 SIO_CLR(SIS_EECTL_CLK); 308 sis_delay(sc); 309 SIO_CLR(SIS_EECTL_CSEL); 310 sis_delay(sc); 311 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 312 313 return; 314 } 315 316 /* 317 * Send a read command and address to the EEPROM, check for ACK. 318 */ 319 static void 320 sis_eeprom_putbyte(sc, addr) 321 struct sis_softc *sc; 322 int addr; 323 { 324 register int d, i; 325 326 d = addr | SIS_EECMD_READ; 327 328 /* 329 * Feed in each bit and stobe the clock. 330 */ 331 for (i = 0x400; i; i >>= 1) { 332 if (d & i) { 333 SIO_SET(SIS_EECTL_DIN); 334 } else { 335 SIO_CLR(SIS_EECTL_DIN); 336 } 337 sis_delay(sc); 338 SIO_SET(SIS_EECTL_CLK); 339 sis_delay(sc); 340 SIO_CLR(SIS_EECTL_CLK); 341 sis_delay(sc); 342 } 343 344 return; 345 } 346 347 /* 348 * Read a word of data stored in the EEPROM at address 'addr.' 349 */ 350 static void 351 sis_eeprom_getword(sc, addr, dest) 352 struct sis_softc *sc; 353 int addr; 354 u_int16_t *dest; 355 { 356 register int i; 357 u_int16_t word = 0; 358 359 /* Force EEPROM to idle state. */ 360 sis_eeprom_idle(sc); 361 362 /* Enter EEPROM access mode. */ 363 sis_delay(sc); 364 SIO_CLR(SIS_EECTL_CLK); 365 sis_delay(sc); 366 SIO_SET(SIS_EECTL_CSEL); 367 sis_delay(sc); 368 369 /* 370 * Send address of word we want to read. 371 */ 372 sis_eeprom_putbyte(sc, addr); 373 374 /* 375 * Start reading bits from EEPROM. 376 */ 377 for (i = 0x8000; i; i >>= 1) { 378 SIO_SET(SIS_EECTL_CLK); 379 sis_delay(sc); 380 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 381 word |= i; 382 sis_delay(sc); 383 SIO_CLR(SIS_EECTL_CLK); 384 sis_delay(sc); 385 } 386 387 /* Turn off EEPROM access mode. */ 388 sis_eeprom_idle(sc); 389 390 *dest = word; 391 392 return; 393 } 394 395 /* 396 * Read a sequence of words from the EEPROM. 397 */ 398 static void 399 sis_read_eeprom(sc, dest, off, cnt, swap) 400 struct sis_softc *sc; 401 caddr_t dest; 402 int off; 403 int cnt; 404 int swap; 405 { 406 int i; 407 u_int16_t word = 0, *ptr; 408 409 for (i = 0; i < cnt; i++) { 410 sis_eeprom_getword(sc, off + i, &word); 411 ptr = (u_int16_t *)(dest + (i * 2)); 412 if (swap) 413 *ptr = ntohs(word); 414 else 415 *ptr = word; 416 } 417 418 return; 419 } 420 421 #ifdef __i386__ 422 static device_t 423 sis_find_bridge(dev) 424 device_t dev; 425 { 426 devclass_t pci_devclass; 427 device_t *pci_devices; 428 int pci_count = 0; 429 device_t *pci_children; 430 int pci_childcount = 0; 431 device_t *busp, *childp; 432 device_t child = NULL; 433 int i, j; 434 435 if ((pci_devclass = devclass_find("pci")) == NULL) 436 return(NULL); 437 438 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 439 440 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 441 pci_childcount = 0; 442 device_get_children(*busp, &pci_children, &pci_childcount); 443 for (j = 0, childp = pci_children; 444 j < pci_childcount; j++, childp++) { 445 if (pci_get_vendor(*childp) == SIS_VENDORID && 446 pci_get_device(*childp) == 0x0008) { 447 child = *childp; 448 goto done; 449 } 450 } 451 } 452 453 done: 454 free(pci_devices, M_TEMP); 455 free(pci_children, M_TEMP); 456 return(child); 457 } 458 459 static void 460 sis_read_cmos(sc, dev, dest, off, cnt) 461 struct sis_softc *sc; 462 device_t dev; 463 caddr_t dest; 464 int off; 465 int cnt; 466 { 467 device_t bridge; 468 u_int8_t reg; 469 int i; 470 bus_space_tag_t btag; 471 472 bridge = sis_find_bridge(dev); 473 if (bridge == NULL) 474 return; 475 reg = pci_read_config(bridge, 0x48, 1); 476 pci_write_config(bridge, 0x48, reg|0x40, 1); 477 478 /* XXX */ 479 btag = I386_BUS_SPACE_IO; 480 481 for (i = 0; i < cnt; i++) { 482 bus_space_write_1(btag, 0x0, 0x70, i + off); 483 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 484 } 485 486 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 487 return; 488 } 489 490 static void 491 sis_read_mac(sc, dev, dest) 492 struct sis_softc *sc; 493 device_t dev; 494 caddr_t dest; 495 { 496 u_int32_t filtsave, csrsave; 497 498 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 499 csrsave = CSR_READ_4(sc, SIS_CSR); 500 501 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 502 CSR_WRITE_4(sc, SIS_CSR, 0); 503 504 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 507 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 509 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 511 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 513 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 514 CSR_WRITE_4(sc, SIS_CSR, csrsave); 515 return; 516 } 517 #endif 518 519 /* 520 * Sync the PHYs by setting data bit and strobing the clock 32 times. 521 */ 522 static void sis_mii_sync(sc) 523 struct sis_softc *sc; 524 { 525 register int i; 526 527 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 528 529 for (i = 0; i < 32; i++) { 530 SIO_SET(SIS_MII_CLK); 531 DELAY(1); 532 SIO_CLR(SIS_MII_CLK); 533 DELAY(1); 534 } 535 536 return; 537 } 538 539 /* 540 * Clock a series of bits through the MII. 541 */ 542 static void sis_mii_send(sc, bits, cnt) 543 struct sis_softc *sc; 544 u_int32_t bits; 545 int cnt; 546 { 547 int i; 548 549 SIO_CLR(SIS_MII_CLK); 550 551 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 552 if (bits & i) { 553 SIO_SET(SIS_MII_DATA); 554 } else { 555 SIO_CLR(SIS_MII_DATA); 556 } 557 DELAY(1); 558 SIO_CLR(SIS_MII_CLK); 559 DELAY(1); 560 SIO_SET(SIS_MII_CLK); 561 } 562 } 563 564 /* 565 * Read an PHY register through the MII. 566 */ 567 static int sis_mii_readreg(sc, frame) 568 struct sis_softc *sc; 569 struct sis_mii_frame *frame; 570 571 { 572 int i, ack, s; 573 574 s = splimp(); 575 576 /* 577 * Set up frame for RX. 578 */ 579 frame->mii_stdelim = SIS_MII_STARTDELIM; 580 frame->mii_opcode = SIS_MII_READOP; 581 frame->mii_turnaround = 0; 582 frame->mii_data = 0; 583 584 /* 585 * Turn on data xmit. 586 */ 587 SIO_SET(SIS_MII_DIR); 588 589 sis_mii_sync(sc); 590 591 /* 592 * Send command/address info. 593 */ 594 sis_mii_send(sc, frame->mii_stdelim, 2); 595 sis_mii_send(sc, frame->mii_opcode, 2); 596 sis_mii_send(sc, frame->mii_phyaddr, 5); 597 sis_mii_send(sc, frame->mii_regaddr, 5); 598 599 /* Idle bit */ 600 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 601 DELAY(1); 602 SIO_SET(SIS_MII_CLK); 603 DELAY(1); 604 605 /* Turn off xmit. */ 606 SIO_CLR(SIS_MII_DIR); 607 608 /* Check for ack */ 609 SIO_CLR(SIS_MII_CLK); 610 DELAY(1); 611 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 612 SIO_SET(SIS_MII_CLK); 613 DELAY(1); 614 615 /* 616 * Now try reading data bits. If the ack failed, we still 617 * need to clock through 16 cycles to keep the PHY(s) in sync. 618 */ 619 if (ack) { 620 for(i = 0; i < 16; i++) { 621 SIO_CLR(SIS_MII_CLK); 622 DELAY(1); 623 SIO_SET(SIS_MII_CLK); 624 DELAY(1); 625 } 626 goto fail; 627 } 628 629 for (i = 0x8000; i; i >>= 1) { 630 SIO_CLR(SIS_MII_CLK); 631 DELAY(1); 632 if (!ack) { 633 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 634 frame->mii_data |= i; 635 DELAY(1); 636 } 637 SIO_SET(SIS_MII_CLK); 638 DELAY(1); 639 } 640 641 fail: 642 643 SIO_CLR(SIS_MII_CLK); 644 DELAY(1); 645 SIO_SET(SIS_MII_CLK); 646 DELAY(1); 647 648 splx(s); 649 650 if (ack) 651 return(1); 652 return(0); 653 } 654 655 /* 656 * Write to a PHY register through the MII. 657 */ 658 static int sis_mii_writereg(sc, frame) 659 struct sis_softc *sc; 660 struct sis_mii_frame *frame; 661 662 { 663 int s; 664 665 s = splimp(); 666 /* 667 * Set up frame for TX. 668 */ 669 670 frame->mii_stdelim = SIS_MII_STARTDELIM; 671 frame->mii_opcode = SIS_MII_WRITEOP; 672 frame->mii_turnaround = SIS_MII_TURNAROUND; 673 674 /* 675 * Turn on data output. 676 */ 677 SIO_SET(SIS_MII_DIR); 678 679 sis_mii_sync(sc); 680 681 sis_mii_send(sc, frame->mii_stdelim, 2); 682 sis_mii_send(sc, frame->mii_opcode, 2); 683 sis_mii_send(sc, frame->mii_phyaddr, 5); 684 sis_mii_send(sc, frame->mii_regaddr, 5); 685 sis_mii_send(sc, frame->mii_turnaround, 2); 686 sis_mii_send(sc, frame->mii_data, 16); 687 688 /* Idle bit. */ 689 SIO_SET(SIS_MII_CLK); 690 DELAY(1); 691 SIO_CLR(SIS_MII_CLK); 692 DELAY(1); 693 694 /* 695 * Turn off xmit. 696 */ 697 SIO_CLR(SIS_MII_DIR); 698 699 splx(s); 700 701 return(0); 702 } 703 704 static int 705 sis_miibus_readreg(dev, phy, reg) 706 device_t dev; 707 int phy, reg; 708 { 709 struct sis_softc *sc; 710 struct sis_mii_frame frame; 711 712 sc = device_get_softc(dev); 713 714 if (sc->sis_type == SIS_TYPE_83815) { 715 if (phy != 0) 716 return(0); 717 /* 718 * The NatSemi chip can take a while after 719 * a reset to come ready, during which the BMSR 720 * returns a value of 0. This is *never* supposed 721 * to happen: some of the BMSR bits are meant to 722 * be hardwired in the on position, and this can 723 * confuse the miibus code a bit during the probe 724 * and attach phase. So we make an effort to check 725 * for this condition and wait for it to clear. 726 */ 727 if (!CSR_READ_4(sc, NS_BMSR)) 728 DELAY(1000); 729 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 730 } 731 732 /* 733 * Chipsets < SIS_635 seem not to be able to read/write 734 * through mdio. Use the enhanced PHY access register 735 * again for them. 736 */ 737 if (sc->sis_type == SIS_TYPE_900 && 738 sc->sis_rev < SIS_REV_635) { 739 int i, val = 0; 740 741 if (phy != 0) 742 return(0); 743 744 CSR_WRITE_4(sc, SIS_PHYCTL, 745 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 746 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 747 748 for (i = 0; i < SIS_TIMEOUT; i++) { 749 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 750 break; 751 } 752 753 if (i == SIS_TIMEOUT) { 754 printf("sis%d: PHY failed to come ready\n", 755 sc->sis_unit); 756 return(0); 757 } 758 759 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 760 761 if (val == 0xFFFF) 762 return(0); 763 764 return(val); 765 } else { 766 bzero((char *)&frame, sizeof(frame)); 767 768 frame.mii_phyaddr = phy; 769 frame.mii_regaddr = reg; 770 sis_mii_readreg(sc, &frame); 771 772 return(frame.mii_data); 773 } 774 } 775 776 static int 777 sis_miibus_writereg(dev, phy, reg, data) 778 device_t dev; 779 int phy, reg, data; 780 { 781 struct sis_softc *sc; 782 struct sis_mii_frame frame; 783 784 sc = device_get_softc(dev); 785 786 if (sc->sis_type == SIS_TYPE_83815) { 787 if (phy != 0) 788 return(0); 789 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 790 return(0); 791 } 792 793 /* 794 * Chipsets < SIS_635 seem not to be able to read/write 795 * through mdio. Use the enhanced PHY access register 796 * again for them. 797 */ 798 if (sc->sis_type == SIS_TYPE_900 && 799 sc->sis_rev < SIS_REV_635) { 800 int i; 801 802 if (phy != 0) 803 return(0); 804 805 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 806 (reg << 6) | SIS_PHYOP_WRITE); 807 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 808 809 for (i = 0; i < SIS_TIMEOUT; i++) { 810 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 811 break; 812 } 813 814 if (i == SIS_TIMEOUT) 815 printf("sis%d: PHY failed to come ready\n", 816 sc->sis_unit); 817 } else { 818 bzero((char *)&frame, sizeof(frame)); 819 820 frame.mii_phyaddr = phy; 821 frame.mii_regaddr = reg; 822 frame.mii_data = data; 823 sis_mii_writereg(sc, &frame); 824 } 825 return(0); 826 } 827 828 static void 829 sis_miibus_statchg(dev) 830 device_t dev; 831 { 832 struct sis_softc *sc; 833 834 sc = device_get_softc(dev); 835 sis_init(sc); 836 837 return; 838 } 839 840 static u_int32_t 841 sis_mchash(sc, addr) 842 struct sis_softc *sc; 843 const uint8_t *addr; 844 { 845 uint32_t crc; 846 847 /* Compute CRC for the address value. */ 848 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 849 850 /* 851 * return the filter bit position 852 * 853 * The NatSemi chip has a 512-bit filter, which is 854 * different than the SiS, so we special-case it. 855 */ 856 if (sc->sis_type == SIS_TYPE_83815) 857 return (crc >> 23); 858 else if (sc->sis_rev >= SIS_REV_635 || 859 sc->sis_rev == SIS_REV_900B) 860 return (crc >> 24); 861 else 862 return (crc >> 25); 863 } 864 865 static void 866 sis_setmulti_ns(sc) 867 struct sis_softc *sc; 868 { 869 struct ifnet *ifp; 870 struct ifmultiaddr *ifma; 871 u_int32_t h = 0, i, filtsave; 872 int bit, index; 873 874 ifp = &sc->arpcom.ac_if; 875 876 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 877 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 878 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 879 return; 880 } 881 882 /* 883 * We have to explicitly enable the multicast hash table 884 * on the NatSemi chip if we want to use it, which we do. 885 */ 886 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 887 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 888 889 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 890 891 /* first, zot all the existing hash bits */ 892 for (i = 0; i < 32; i++) { 893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 894 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 895 } 896 897 IF_ADDR_LOCK(ifp); 898 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 899 if (ifma->ifma_addr->sa_family != AF_LINK) 900 continue; 901 h = sis_mchash(sc, 902 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 903 index = h >> 3; 904 bit = h & 0x1F; 905 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 906 if (bit > 0xF) 907 bit -= 0x10; 908 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 909 } 910 IF_ADDR_UNLOCK(ifp); 911 912 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 913 914 return; 915 } 916 917 static void 918 sis_setmulti_sis(sc) 919 struct sis_softc *sc; 920 { 921 struct ifnet *ifp; 922 struct ifmultiaddr *ifma; 923 u_int32_t h, i, n, ctl; 924 u_int16_t hashes[16]; 925 926 ifp = &sc->arpcom.ac_if; 927 928 /* hash table size */ 929 if (sc->sis_rev >= SIS_REV_635 || 930 sc->sis_rev == SIS_REV_900B) 931 n = 16; 932 else 933 n = 8; 934 935 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 936 937 if (ifp->if_flags & IFF_BROADCAST) 938 ctl |= SIS_RXFILTCTL_BROAD; 939 940 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 941 ctl |= SIS_RXFILTCTL_ALLMULTI; 942 if (ifp->if_flags & IFF_PROMISC) 943 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 944 for (i = 0; i < n; i++) 945 hashes[i] = ~0; 946 } else { 947 for (i = 0; i < n; i++) 948 hashes[i] = 0; 949 i = 0; 950 IF_ADDR_LOCK(ifp); 951 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 952 if (ifma->ifma_addr->sa_family != AF_LINK) 953 continue; 954 h = sis_mchash(sc, 955 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 956 hashes[h >> 4] |= 1 << (h & 0xf); 957 i++; 958 } 959 IF_ADDR_UNLOCK(ifp); 960 if (i > n) { 961 ctl |= SIS_RXFILTCTL_ALLMULTI; 962 for (i = 0; i < n; i++) 963 hashes[i] = ~0; 964 } 965 } 966 967 for (i = 0; i < n; i++) { 968 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 969 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 970 } 971 972 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 973 } 974 975 static void 976 sis_reset(sc) 977 struct sis_softc *sc; 978 { 979 register int i; 980 981 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 982 983 for (i = 0; i < SIS_TIMEOUT; i++) { 984 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 985 break; 986 } 987 988 if (i == SIS_TIMEOUT) 989 printf("sis%d: reset never completed\n", sc->sis_unit); 990 991 /* Wait a little while for the chip to get its brains in order. */ 992 DELAY(1000); 993 994 /* 995 * If this is a NetSemi chip, make sure to clear 996 * PME mode. 997 */ 998 if (sc->sis_type == SIS_TYPE_83815) { 999 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 1000 CSR_WRITE_4(sc, NS_CLKRUN, 0); 1001 } 1002 1003 return; 1004 } 1005 1006 /* 1007 * Probe for an SiS chip. Check the PCI vendor and device 1008 * IDs against our list and return a device name if we find a match. 1009 */ 1010 static int 1011 sis_probe(dev) 1012 device_t dev; 1013 { 1014 struct sis_type *t; 1015 1016 t = sis_devs; 1017 1018 while(t->sis_name != NULL) { 1019 if ((pci_get_vendor(dev) == t->sis_vid) && 1020 (pci_get_device(dev) == t->sis_did)) { 1021 device_set_desc(dev, t->sis_name); 1022 return(0); 1023 } 1024 t++; 1025 } 1026 1027 return(ENXIO); 1028 } 1029 1030 /* 1031 * Attach the interface. Allocate softc structures, do ifmedia 1032 * setup and ethernet/BPF attach. 1033 */ 1034 static int 1035 sis_attach(dev) 1036 device_t dev; 1037 { 1038 u_char eaddr[ETHER_ADDR_LEN]; 1039 struct sis_softc *sc; 1040 struct ifnet *ifp; 1041 int unit, error = 0, rid, waittime = 0; 1042 1043 waittime = 0; 1044 sc = device_get_softc(dev); 1045 unit = device_get_unit(dev); 1046 1047 sc->sis_self = dev; 1048 1049 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1050 MTX_DEF | MTX_RECURSE); 1051 1052 if (pci_get_device(dev) == SIS_DEVICEID_900) 1053 sc->sis_type = SIS_TYPE_900; 1054 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1055 sc->sis_type = SIS_TYPE_7016; 1056 if (pci_get_vendor(dev) == NS_VENDORID) 1057 sc->sis_type = SIS_TYPE_83815; 1058 1059 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1060 /* 1061 * Map control/status registers. 1062 */ 1063 pci_enable_busmaster(dev); 1064 1065 rid = SIS_RID; 1066 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 1067 1068 if (sc->sis_res == NULL) { 1069 printf("sis%d: couldn't map ports/memory\n", unit); 1070 error = ENXIO; 1071 goto fail; 1072 } 1073 1074 sc->sis_btag = rman_get_bustag(sc->sis_res); 1075 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1076 1077 /* Allocate interrupt */ 1078 rid = 0; 1079 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1080 RF_SHAREABLE | RF_ACTIVE); 1081 1082 if (sc->sis_irq == NULL) { 1083 printf("sis%d: couldn't map interrupt\n", unit); 1084 error = ENXIO; 1085 goto fail; 1086 } 1087 1088 /* Reset the adapter. */ 1089 sis_reset(sc); 1090 1091 if (sc->sis_type == SIS_TYPE_900 && 1092 (sc->sis_rev == SIS_REV_635 || 1093 sc->sis_rev == SIS_REV_900B)) { 1094 SIO_SET(SIS_CFG_RND_CNT); 1095 SIO_SET(SIS_CFG_PERR_DETECT); 1096 } 1097 1098 /* 1099 * Get station address from the EEPROM. 1100 */ 1101 switch (pci_get_vendor(dev)) { 1102 case NS_VENDORID: 1103 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1104 1105 /* We can't update the device description, so spew */ 1106 if (sc->sis_srr == NS_SRR_15C) 1107 device_printf(dev, "Silicon Revision: DP83815C\n"); 1108 else if (sc->sis_srr == NS_SRR_15D) 1109 device_printf(dev, "Silicon Revision: DP83815D\n"); 1110 else if (sc->sis_srr == NS_SRR_16A) 1111 device_printf(dev, "Silicon Revision: DP83816A\n"); 1112 else 1113 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1114 1115 /* 1116 * Reading the MAC address out of the EEPROM on 1117 * the NatSemi chip takes a bit more work than 1118 * you'd expect. The address spans 4 16-bit words, 1119 * with the first word containing only a single bit. 1120 * You have to shift everything over one bit to 1121 * get it aligned properly. Also, the bits are 1122 * stored backwards (the LSB is really the MSB, 1123 * and so on) so you have to reverse them in order 1124 * to get the MAC address into the form we want. 1125 * Why? Who the hell knows. 1126 */ 1127 { 1128 u_int16_t tmp[4]; 1129 1130 sis_read_eeprom(sc, (caddr_t)&tmp, 1131 NS_EE_NODEADDR, 4, 0); 1132 1133 /* Shift everything over one bit. */ 1134 tmp[3] = tmp[3] >> 1; 1135 tmp[3] |= tmp[2] << 15; 1136 tmp[2] = tmp[2] >> 1; 1137 tmp[2] |= tmp[1] << 15; 1138 tmp[1] = tmp[1] >> 1; 1139 tmp[1] |= tmp[0] << 15; 1140 1141 /* Now reverse all the bits. */ 1142 tmp[3] = sis_reverse(tmp[3]); 1143 tmp[2] = sis_reverse(tmp[2]); 1144 tmp[1] = sis_reverse(tmp[1]); 1145 1146 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1147 } 1148 break; 1149 case SIS_VENDORID: 1150 default: 1151 #ifdef __i386__ 1152 /* 1153 * If this is a SiS 630E chipset with an embedded 1154 * SiS 900 controller, we have to read the MAC address 1155 * from the APC CMOS RAM. Our method for doing this 1156 * is very ugly since we have to reach out and grab 1157 * ahold of hardware for which we cannot properly 1158 * allocate resources. This code is only compiled on 1159 * the i386 architecture since the SiS 630E chipset 1160 * is for x86 motherboards only. Note that there are 1161 * a lot of magic numbers in this hack. These are 1162 * taken from SiS's Linux driver. I'd like to replace 1163 * them with proper symbolic definitions, but that 1164 * requires some datasheets that I don't have access 1165 * to at the moment. 1166 */ 1167 if (sc->sis_rev == SIS_REV_630S || 1168 sc->sis_rev == SIS_REV_630E || 1169 sc->sis_rev == SIS_REV_630EA1) 1170 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1171 1172 else if (sc->sis_rev == SIS_REV_635 || 1173 sc->sis_rev == SIS_REV_630ET) 1174 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1175 else if (sc->sis_rev == SIS_REV_96x) { 1176 /* Allow to read EEPROM from LAN. It is shared 1177 * between a 1394 controller and the NIC and each 1178 * time we access it, we need to set SIS_EECMD_REQ. 1179 */ 1180 SIO_SET(SIS_EECMD_REQ); 1181 for (waittime = 0; waittime < SIS_TIMEOUT; 1182 waittime++) { 1183 /* Force EEPROM to idle state. */ 1184 sis_eeprom_idle(sc); 1185 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1186 sis_read_eeprom(sc, (caddr_t)&eaddr, 1187 SIS_EE_NODEADDR, 3, 0); 1188 break; 1189 } 1190 DELAY(1); 1191 } 1192 /* 1193 * Set SIS_EECTL_CLK to high, so a other master 1194 * can operate on the i2c bus. 1195 */ 1196 SIO_SET(SIS_EECTL_CLK); 1197 /* Refuse EEPROM access by LAN */ 1198 SIO_SET(SIS_EECMD_DONE); 1199 } else 1200 #endif 1201 sis_read_eeprom(sc, (caddr_t)&eaddr, 1202 SIS_EE_NODEADDR, 3, 0); 1203 break; 1204 } 1205 1206 sc->sis_unit = unit; 1207 if (debug_mpsafenet) 1208 callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1209 else 1210 callout_init(&sc->sis_stat_ch, 0); 1211 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1212 1213 /* 1214 * Allocate the parent bus DMA tag appropriate for PCI. 1215 */ 1216 #define SIS_NSEG_NEW 32 1217 error = bus_dma_tag_create(NULL, /* parent */ 1218 1, 0, /* alignment, boundary */ 1219 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1220 BUS_SPACE_MAXADDR, /* highaddr */ 1221 NULL, NULL, /* filter, filterarg */ 1222 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1223 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1224 BUS_DMA_ALLOCNOW, /* flags */ 1225 NULL, NULL, /* lockfunc, lockarg */ 1226 &sc->sis_parent_tag); 1227 if (error) 1228 goto fail; 1229 1230 /* 1231 * Now allocate a tag for the DMA descriptor lists and a chunk 1232 * of DMA-able memory based on the tag. Also obtain the physical 1233 * addresses of the RX and TX ring, which we'll need later. 1234 * All of our lists are allocated as a contiguous block 1235 * of memory. 1236 */ 1237 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1238 1, 0, /* alignment, boundary */ 1239 BUS_SPACE_MAXADDR, /* lowaddr */ 1240 BUS_SPACE_MAXADDR, /* highaddr */ 1241 NULL, NULL, /* filter, filterarg */ 1242 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1243 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1244 0, /* flags */ 1245 busdma_lock_mutex, /* lockfunc */ 1246 &Giant, /* lockarg */ 1247 &sc->sis_ldata.sis_rx_tag); 1248 if (error) 1249 goto fail; 1250 1251 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1252 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1253 &sc->sis_ldata.sis_rx_dmamap); 1254 1255 if (error) { 1256 printf("sis%d: no memory for rx list buffers!\n", unit); 1257 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1258 sc->sis_ldata.sis_rx_tag = NULL; 1259 goto fail; 1260 } 1261 1262 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1263 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1264 sizeof(struct sis_desc), sis_dma_map_ring, 1265 &sc->sis_cdata.sis_rx_paddr, 0); 1266 1267 if (error) { 1268 printf("sis%d: cannot get address of the rx ring!\n", unit); 1269 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1270 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1271 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1272 sc->sis_ldata.sis_rx_tag = NULL; 1273 goto fail; 1274 } 1275 1276 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1277 1, 0, /* alignment, boundary */ 1278 BUS_SPACE_MAXADDR, /* lowaddr */ 1279 BUS_SPACE_MAXADDR, /* highaddr */ 1280 NULL, NULL, /* filter, filterarg */ 1281 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1282 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1283 0, /* flags */ 1284 busdma_lock_mutex, /* lockfunc */ 1285 &Giant, /* lockarg */ 1286 &sc->sis_ldata.sis_tx_tag); 1287 if (error) 1288 goto fail; 1289 1290 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1291 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1292 &sc->sis_ldata.sis_tx_dmamap); 1293 1294 if (error) { 1295 printf("sis%d: no memory for tx list buffers!\n", unit); 1296 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1297 sc->sis_ldata.sis_tx_tag = NULL; 1298 goto fail; 1299 } 1300 1301 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1302 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1303 sizeof(struct sis_desc), sis_dma_map_ring, 1304 &sc->sis_cdata.sis_tx_paddr, 0); 1305 1306 if (error) { 1307 printf("sis%d: cannot get address of the tx ring!\n", unit); 1308 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1309 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1310 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1311 sc->sis_ldata.sis_tx_tag = NULL; 1312 goto fail; 1313 } 1314 1315 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1316 1, 0, /* alignment, boundary */ 1317 BUS_SPACE_MAXADDR, /* lowaddr */ 1318 BUS_SPACE_MAXADDR, /* highaddr */ 1319 NULL, NULL, /* filter, filterarg */ 1320 MCLBYTES, 1, /* maxsize,nsegments */ 1321 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1322 0, /* flags */ 1323 busdma_lock_mutex, /* lockfunc */ 1324 &Giant, /* lockarg */ 1325 &sc->sis_tag); 1326 if (error) 1327 goto fail; 1328 1329 /* 1330 * Obtain the physical addresses of the RX and TX 1331 * rings which we'll need later in the init routine. 1332 */ 1333 1334 ifp = &sc->arpcom.ac_if; 1335 ifp->if_softc = sc; 1336 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1337 ifp->if_mtu = ETHERMTU; 1338 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1339 ifp->if_ioctl = sis_ioctl; 1340 ifp->if_start = sis_start; 1341 ifp->if_watchdog = sis_watchdog; 1342 ifp->if_init = sis_init; 1343 ifp->if_baudrate = 10000000; 1344 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1345 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1346 IFQ_SET_READY(&ifp->if_snd); 1347 1348 /* 1349 * Do MII setup. 1350 */ 1351 if (mii_phy_probe(dev, &sc->sis_miibus, 1352 sis_ifmedia_upd, sis_ifmedia_sts)) { 1353 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1354 error = ENXIO; 1355 goto fail; 1356 } 1357 1358 /* 1359 * Call MI attach routine. 1360 */ 1361 ether_ifattach(ifp, eaddr); 1362 1363 /* 1364 * Tell the upper layer(s) we support long frames. 1365 */ 1366 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1367 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1368 1369 #ifdef DEVICE_POLLING 1370 ifp->if_capabilities |= IFCAP_POLLING; 1371 #endif 1372 ifp->if_capenable = ifp->if_capabilities; 1373 1374 /* Hook interrupt last to avoid having to lock softc */ 1375 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, 1376 sis_intr, sc, &sc->sis_intrhand); 1377 1378 if (error) { 1379 printf("sis%d: couldn't set up irq\n", unit); 1380 ether_ifdetach(ifp); 1381 goto fail; 1382 } 1383 1384 fail: 1385 if (error) 1386 sis_detach(dev); 1387 1388 return(error); 1389 } 1390 1391 /* 1392 * Shutdown hardware and free up resources. This can be called any 1393 * time after the mutex has been initialized. It is called in both 1394 * the error case in attach and the normal detach case so it needs 1395 * to be careful about only freeing resources that have actually been 1396 * allocated. 1397 */ 1398 static int 1399 sis_detach(dev) 1400 device_t dev; 1401 { 1402 struct sis_softc *sc; 1403 struct ifnet *ifp; 1404 1405 sc = device_get_softc(dev); 1406 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1407 SIS_LOCK(sc); 1408 ifp = &sc->arpcom.ac_if; 1409 1410 /* These should only be active if attach succeeded. */ 1411 if (device_is_attached(dev)) { 1412 sis_reset(sc); 1413 sis_stop(sc); 1414 ether_ifdetach(ifp); 1415 } 1416 if (sc->sis_miibus) 1417 device_delete_child(dev, sc->sis_miibus); 1418 bus_generic_detach(dev); 1419 1420 if (sc->sis_intrhand) 1421 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1422 if (sc->sis_irq) 1423 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1424 if (sc->sis_res) 1425 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1426 1427 if (sc->sis_ldata.sis_rx_tag) { 1428 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1429 sc->sis_ldata.sis_rx_dmamap); 1430 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1431 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1432 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1433 } 1434 if (sc->sis_ldata.sis_tx_tag) { 1435 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1436 sc->sis_ldata.sis_tx_dmamap); 1437 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1438 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1439 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1440 } 1441 if (sc->sis_parent_tag) 1442 bus_dma_tag_destroy(sc->sis_parent_tag); 1443 if (sc->sis_tag) 1444 bus_dma_tag_destroy(sc->sis_tag); 1445 1446 SIS_UNLOCK(sc); 1447 mtx_destroy(&sc->sis_mtx); 1448 1449 return(0); 1450 } 1451 1452 /* 1453 * Initialize the transmit descriptors. 1454 */ 1455 static int 1456 sis_list_tx_init(sc) 1457 struct sis_softc *sc; 1458 { 1459 struct sis_list_data *ld; 1460 struct sis_ring_data *cd; 1461 int i, nexti; 1462 1463 cd = &sc->sis_cdata; 1464 ld = &sc->sis_ldata; 1465 1466 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1467 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1468 ld->sis_tx_list[i].sis_nextdesc = 1469 &ld->sis_tx_list[nexti]; 1470 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1471 sc->sis_ldata.sis_tx_dmamap, 1472 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1473 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1474 ld->sis_tx_list[i].sis_mbuf = NULL; 1475 ld->sis_tx_list[i].sis_ptr = 0; 1476 ld->sis_tx_list[i].sis_ctl = 0; 1477 } 1478 1479 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1480 1481 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1482 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1483 1484 return(0); 1485 } 1486 1487 /* 1488 * Initialize the RX descriptors and allocate mbufs for them. Note that 1489 * we arrange the descriptors in a closed ring, so that the last descriptor 1490 * points back to the first. 1491 */ 1492 static int 1493 sis_list_rx_init(sc) 1494 struct sis_softc *sc; 1495 { 1496 struct sis_list_data *ld; 1497 struct sis_ring_data *cd; 1498 int i,nexti; 1499 1500 ld = &sc->sis_ldata; 1501 cd = &sc->sis_cdata; 1502 1503 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1504 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1505 return(ENOBUFS); 1506 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1507 ld->sis_rx_list[i].sis_nextdesc = 1508 &ld->sis_rx_list[nexti]; 1509 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1510 sc->sis_ldata.sis_rx_dmamap, 1511 &ld->sis_rx_list[nexti], 1512 sizeof(struct sis_desc), sis_dma_map_desc_next, 1513 &ld->sis_rx_list[i], 0); 1514 } 1515 1516 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1517 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1518 1519 cd->sis_rx_prod = 0; 1520 1521 return(0); 1522 } 1523 1524 /* 1525 * Initialize an RX descriptor and attach an MBUF cluster. 1526 */ 1527 static int 1528 sis_newbuf(sc, c, m) 1529 struct sis_softc *sc; 1530 struct sis_desc *c; 1531 struct mbuf *m; 1532 { 1533 1534 if (c == NULL) 1535 return(EINVAL); 1536 1537 if (m == NULL) { 1538 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1539 if (m == NULL) 1540 return(ENOBUFS); 1541 } else 1542 m->m_data = m->m_ext.ext_buf; 1543 1544 c->sis_mbuf = m; 1545 c->sis_ctl = SIS_RXLEN; 1546 1547 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1548 bus_dmamap_load(sc->sis_tag, c->sis_map, 1549 mtod(m, void *), MCLBYTES, 1550 sis_dma_map_desc_ptr, c, 0); 1551 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD); 1552 1553 return(0); 1554 } 1555 1556 /* 1557 * A frame has been uploaded: pass the resulting mbuf chain up to 1558 * the higher level protocols. 1559 */ 1560 static void 1561 sis_rxeof(sc) 1562 struct sis_softc *sc; 1563 { 1564 struct mbuf *m; 1565 struct ifnet *ifp; 1566 struct sis_desc *cur_rx; 1567 int i, total_len = 0; 1568 u_int32_t rxstat; 1569 1570 SIS_LOCK_ASSERT(sc); 1571 1572 ifp = &sc->arpcom.ac_if; 1573 i = sc->sis_cdata.sis_rx_prod; 1574 1575 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1576 1577 #ifdef DEVICE_POLLING 1578 if (ifp->if_flags & IFF_POLLING) { 1579 if (sc->rxcycles <= 0) 1580 break; 1581 sc->rxcycles--; 1582 } 1583 #endif /* DEVICE_POLLING */ 1584 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1585 rxstat = cur_rx->sis_rxstat; 1586 bus_dmamap_sync(sc->sis_tag, 1587 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1588 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1589 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1590 m = cur_rx->sis_mbuf; 1591 cur_rx->sis_mbuf = NULL; 1592 total_len = SIS_RXBYTES(cur_rx); 1593 SIS_INC(i, SIS_RX_LIST_CNT); 1594 1595 /* 1596 * If an error occurs, update stats, clear the 1597 * status word and leave the mbuf cluster in place: 1598 * it should simply get re-used next time this descriptor 1599 * comes up in the ring. 1600 */ 1601 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1602 ifp->if_ierrors++; 1603 if (rxstat & SIS_RXSTAT_COLL) 1604 ifp->if_collisions++; 1605 sis_newbuf(sc, cur_rx, m); 1606 continue; 1607 } 1608 1609 /* No errors; receive the packet. */ 1610 #ifdef __i386__ 1611 /* 1612 * On the x86 we do not have alignment problems, so try to 1613 * allocate a new buffer for the receive ring, and pass up 1614 * the one where the packet is already, saving the expensive 1615 * copy done in m_devget(). 1616 * If we are on an architecture with alignment problems, or 1617 * if the allocation fails, then use m_devget and leave the 1618 * existing buffer in the receive ring. 1619 */ 1620 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1621 m->m_pkthdr.len = m->m_len = total_len; 1622 else 1623 #endif 1624 { 1625 struct mbuf *m0; 1626 m0 = m_devget(mtod(m, char *), total_len, 1627 ETHER_ALIGN, ifp, NULL); 1628 sis_newbuf(sc, cur_rx, m); 1629 if (m0 == NULL) { 1630 ifp->if_ierrors++; 1631 continue; 1632 } 1633 m = m0; 1634 } 1635 1636 ifp->if_ipackets++; 1637 m->m_pkthdr.rcvif = ifp; 1638 1639 SIS_UNLOCK(sc); 1640 (*ifp->if_input)(ifp, m); 1641 SIS_LOCK(sc); 1642 } 1643 1644 sc->sis_cdata.sis_rx_prod = i; 1645 1646 return; 1647 } 1648 1649 static void 1650 sis_rxeoc(sc) 1651 struct sis_softc *sc; 1652 { 1653 sis_rxeof(sc); 1654 sis_init(sc); 1655 return; 1656 } 1657 1658 /* 1659 * A frame was downloaded to the chip. It's safe for us to clean up 1660 * the list buffers. 1661 */ 1662 1663 static void 1664 sis_txeof(sc) 1665 struct sis_softc *sc; 1666 { 1667 struct ifnet *ifp; 1668 u_int32_t idx; 1669 1670 ifp = &sc->arpcom.ac_if; 1671 1672 /* 1673 * Go through our tx list and free mbufs for those 1674 * frames that have been transmitted. 1675 */ 1676 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1677 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1678 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1679 1680 if (SIS_OWNDESC(cur_tx)) 1681 break; 1682 1683 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1684 continue; 1685 1686 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1687 ifp->if_oerrors++; 1688 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1689 ifp->if_collisions++; 1690 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1691 ifp->if_collisions++; 1692 } 1693 1694 ifp->if_collisions += 1695 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1696 1697 ifp->if_opackets++; 1698 if (cur_tx->sis_mbuf != NULL) { 1699 m_freem(cur_tx->sis_mbuf); 1700 cur_tx->sis_mbuf = NULL; 1701 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1702 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1703 } 1704 } 1705 1706 if (idx != sc->sis_cdata.sis_tx_cons) { 1707 /* we freed up some buffers */ 1708 sc->sis_cdata.sis_tx_cons = idx; 1709 ifp->if_flags &= ~IFF_OACTIVE; 1710 } 1711 1712 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1713 1714 return; 1715 } 1716 1717 static void 1718 sis_tick(xsc) 1719 void *xsc; 1720 { 1721 struct sis_softc *sc; 1722 struct mii_data *mii; 1723 struct ifnet *ifp; 1724 1725 sc = xsc; 1726 SIS_LOCK(sc); 1727 sc->in_tick = 1; 1728 ifp = &sc->arpcom.ac_if; 1729 1730 mii = device_get_softc(sc->sis_miibus); 1731 mii_tick(mii); 1732 1733 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1734 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1735 sc->sis_link++; 1736 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1737 sis_start(ifp); 1738 } 1739 1740 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1741 sc->in_tick = 0; 1742 SIS_UNLOCK(sc); 1743 1744 return; 1745 } 1746 1747 #ifdef DEVICE_POLLING 1748 static poll_handler_t sis_poll; 1749 1750 static void 1751 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1752 { 1753 struct sis_softc *sc = ifp->if_softc; 1754 1755 SIS_LOCK(sc); 1756 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1757 ether_poll_deregister(ifp); 1758 cmd = POLL_DEREGISTER; 1759 } 1760 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1761 CSR_WRITE_4(sc, SIS_IER, 1); 1762 goto done; 1763 } 1764 1765 /* 1766 * On the sis, reading the status register also clears it. 1767 * So before returning to intr mode we must make sure that all 1768 * possible pending sources of interrupts have been served. 1769 * In practice this means run to completion the *eof routines, 1770 * and then call the interrupt routine 1771 */ 1772 sc->rxcycles = count; 1773 sis_rxeof(sc); 1774 sis_txeof(sc); 1775 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1776 sis_start(ifp); 1777 1778 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1779 u_int32_t status; 1780 1781 /* Reading the ISR register clears all interrupts. */ 1782 status = CSR_READ_4(sc, SIS_ISR); 1783 1784 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1785 sis_rxeoc(sc); 1786 1787 if (status & (SIS_ISR_RX_IDLE)) 1788 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1789 1790 if (status & SIS_ISR_SYSERR) { 1791 sis_reset(sc); 1792 sis_init(sc); 1793 } 1794 } 1795 done: 1796 SIS_UNLOCK(sc); 1797 return; 1798 } 1799 #endif /* DEVICE_POLLING */ 1800 1801 static void 1802 sis_intr(arg) 1803 void *arg; 1804 { 1805 struct sis_softc *sc; 1806 struct ifnet *ifp; 1807 u_int32_t status; 1808 1809 sc = arg; 1810 ifp = &sc->arpcom.ac_if; 1811 1812 SIS_LOCK(sc); 1813 #ifdef DEVICE_POLLING 1814 if (ifp->if_flags & IFF_POLLING) 1815 goto done; 1816 if ((ifp->if_capenable & IFCAP_POLLING) && 1817 ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1818 CSR_WRITE_4(sc, SIS_IER, 0); 1819 goto done; 1820 } 1821 #endif /* DEVICE_POLLING */ 1822 1823 /* Supress unwanted interrupts */ 1824 if (!(ifp->if_flags & IFF_UP)) { 1825 sis_stop(sc); 1826 goto done; 1827 } 1828 1829 /* Disable interrupts. */ 1830 CSR_WRITE_4(sc, SIS_IER, 0); 1831 1832 for (;;) { 1833 /* Reading the ISR register clears all interrupts. */ 1834 status = CSR_READ_4(sc, SIS_ISR); 1835 1836 if ((status & SIS_INTRS) == 0) 1837 break; 1838 1839 if (status & 1840 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1841 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1842 sis_txeof(sc); 1843 1844 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1845 sis_rxeof(sc); 1846 1847 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1848 sis_rxeoc(sc); 1849 1850 if (status & (SIS_ISR_RX_IDLE)) 1851 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1852 1853 if (status & SIS_ISR_SYSERR) { 1854 sis_reset(sc); 1855 sis_init(sc); 1856 } 1857 } 1858 1859 /* Re-enable interrupts. */ 1860 CSR_WRITE_4(sc, SIS_IER, 1); 1861 1862 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1863 sis_start(ifp); 1864 done: 1865 SIS_UNLOCK(sc); 1866 1867 return; 1868 } 1869 1870 /* 1871 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1872 * pointers to the fragment pointers. 1873 */ 1874 static int 1875 sis_encap(sc, m_head, txidx) 1876 struct sis_softc *sc; 1877 struct mbuf **m_head; 1878 u_int32_t *txidx; 1879 { 1880 struct sis_desc *f = NULL; 1881 struct mbuf *m; 1882 int frag, cur, cnt = 0, chainlen = 0; 1883 1884 /* 1885 * If there's no way we can send any packets, return now. 1886 */ 1887 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1888 return (ENOBUFS); 1889 1890 /* 1891 * Count the number of frags in this chain to see if 1892 * we need to m_defrag. Since the descriptor list is shared 1893 * by all packets, we'll m_defrag long chains so that they 1894 * do not use up the entire list, even if they would fit. 1895 */ 1896 1897 for (m = *m_head; m != NULL; m = m->m_next) 1898 chainlen++; 1899 1900 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1901 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { 1902 m = m_defrag(*m_head, M_DONTWAIT); 1903 if (m == NULL) 1904 return (ENOBUFS); 1905 *m_head = m; 1906 } 1907 1908 /* 1909 * Start packing the mbufs in this chain into 1910 * the fragment pointers. Stop when we run out 1911 * of fragments or hit the end of the mbuf chain. 1912 */ 1913 cur = frag = *txidx; 1914 1915 for (m = *m_head; m != NULL; m = m->m_next) { 1916 if (m->m_len != 0) { 1917 if ((SIS_TX_LIST_CNT - 1918 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1919 return(ENOBUFS); 1920 f = &sc->sis_ldata.sis_tx_list[frag]; 1921 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1922 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1923 bus_dmamap_load(sc->sis_tag, f->sis_map, 1924 mtod(m, void *), m->m_len, 1925 sis_dma_map_desc_ptr, f, 0); 1926 bus_dmamap_sync(sc->sis_tag, 1927 f->sis_map, BUS_DMASYNC_PREREAD); 1928 if (cnt != 0) 1929 f->sis_ctl |= SIS_CMDSTS_OWN; 1930 cur = frag; 1931 SIS_INC(frag, SIS_TX_LIST_CNT); 1932 cnt++; 1933 } 1934 } 1935 1936 if (m != NULL) 1937 return(ENOBUFS); 1938 1939 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = *m_head; 1940 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1941 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1942 sc->sis_cdata.sis_tx_cnt += cnt; 1943 *txidx = frag; 1944 1945 return(0); 1946 } 1947 1948 /* 1949 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1950 * to the mbuf data regions directly in the transmit lists. We also save a 1951 * copy of the pointers since the transmit list fragment pointers are 1952 * physical addresses. 1953 */ 1954 1955 static void 1956 sis_start(ifp) 1957 struct ifnet *ifp; 1958 { 1959 struct sis_softc *sc; 1960 struct mbuf *m_head = NULL; 1961 u_int32_t idx, queued = 0; 1962 1963 sc = ifp->if_softc; 1964 SIS_LOCK(sc); 1965 1966 if (!sc->sis_link) { 1967 SIS_UNLOCK(sc); 1968 return; 1969 } 1970 1971 idx = sc->sis_cdata.sis_tx_prod; 1972 1973 if (ifp->if_flags & IFF_OACTIVE) { 1974 SIS_UNLOCK(sc); 1975 return; 1976 } 1977 1978 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1979 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1980 if (m_head == NULL) 1981 break; 1982 1983 if (sis_encap(sc, &m_head, &idx)) { 1984 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1985 ifp->if_flags |= IFF_OACTIVE; 1986 break; 1987 } 1988 1989 queued++; 1990 1991 /* 1992 * If there's a BPF listener, bounce a copy of this frame 1993 * to him. 1994 */ 1995 BPF_MTAP(ifp, m_head); 1996 1997 } 1998 1999 if (queued) { 2000 /* Transmit */ 2001 sc->sis_cdata.sis_tx_prod = idx; 2002 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 2003 2004 /* 2005 * Set a timeout in case the chip goes out to lunch. 2006 */ 2007 ifp->if_timer = 5; 2008 } 2009 2010 SIS_UNLOCK(sc); 2011 2012 return; 2013 } 2014 2015 static void 2016 sis_init(xsc) 2017 void *xsc; 2018 { 2019 struct sis_softc *sc = xsc; 2020 struct ifnet *ifp = &sc->arpcom.ac_if; 2021 struct mii_data *mii; 2022 2023 SIS_LOCK(sc); 2024 2025 /* 2026 * Cancel pending I/O and free all RX/TX buffers. 2027 */ 2028 sis_stop(sc); 2029 sc->sis_stopped = 0; 2030 2031 #ifdef notyet 2032 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 2033 /* 2034 * Configure 400usec of interrupt holdoff. This is based 2035 * on emperical tests on a Soekris 4801. 2036 */ 2037 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 2038 } 2039 #endif 2040 2041 mii = device_get_softc(sc->sis_miibus); 2042 2043 /* Set MAC address */ 2044 if (sc->sis_type == SIS_TYPE_83815) { 2045 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2046 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2047 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2048 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2049 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2050 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2051 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2052 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2053 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2054 } else { 2055 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2056 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2057 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2058 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2059 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2060 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2061 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2062 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2063 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2064 } 2065 2066 /* Init circular RX list. */ 2067 if (sis_list_rx_init(sc) == ENOBUFS) { 2068 printf("sis%d: initialization failed: no " 2069 "memory for rx buffers\n", sc->sis_unit); 2070 sis_stop(sc); 2071 SIS_UNLOCK(sc); 2072 return; 2073 } 2074 2075 /* 2076 * Init tx descriptors. 2077 */ 2078 sis_list_tx_init(sc); 2079 2080 /* 2081 * Page 78 of the DP83815 data sheet (september 2002 version) 2082 * recommends the following register settings "for optimum 2083 * performance." for rev 15C. The driver from NS also sets 2084 * the PHY_CR register for later versions. 2085 */ 2086 if (sc->sis_type == SIS_TYPE_83815) { 2087 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2088 /* DC speed = 01 */ 2089 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2090 if (sc->sis_srr == NS_SRR_15C) { 2091 /* set val for c2 */ 2092 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2093 /* load/kill c2 */ 2094 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2095 /* rais SD off, from 4 to c */ 2096 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2097 } 2098 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2099 } 2100 2101 2102 /* 2103 * For the NatSemi chip, we have to explicitly enable the 2104 * reception of ARP frames, as well as turn on the 'perfect 2105 * match' filter where we store the station address, otherwise 2106 * we won't receive unicasts meant for this host. 2107 */ 2108 if (sc->sis_type == SIS_TYPE_83815) { 2109 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 2110 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 2111 } 2112 2113 /* If we want promiscuous mode, set the allframes bit. */ 2114 if (ifp->if_flags & IFF_PROMISC) { 2115 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2116 } else { 2117 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2118 } 2119 2120 /* 2121 * Set the capture broadcast bit to capture broadcast frames. 2122 */ 2123 if (ifp->if_flags & IFF_BROADCAST) { 2124 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2125 } else { 2126 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2127 } 2128 2129 /* 2130 * Load the multicast filter. 2131 */ 2132 if (sc->sis_type == SIS_TYPE_83815) 2133 sis_setmulti_ns(sc); 2134 else 2135 sis_setmulti_sis(sc); 2136 2137 /* Turn the receive filter on */ 2138 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2139 2140 /* 2141 * Load the address of the RX and TX lists. 2142 */ 2143 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 2144 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 2145 2146 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2147 * the PCI bus. When this bit is set, the Max DMA Burst Size 2148 * for TX/RX DMA should be no larger than 16 double words. 2149 */ 2150 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2151 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2152 } else { 2153 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2154 } 2155 2156 /* Accept Long Packets for VLAN support */ 2157 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2158 2159 /* Set TX configuration */ 2160 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2161 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2162 } else { 2163 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2164 } 2165 2166 /* Set full/half duplex mode. */ 2167 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2168 SIS_SETBIT(sc, SIS_TX_CFG, 2169 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2170 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2171 } else { 2172 SIS_CLRBIT(sc, SIS_TX_CFG, 2173 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2174 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2175 } 2176 2177 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2178 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2179 uint32_t reg; 2180 2181 /* 2182 * Some DP83815s experience problems when used with short 2183 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 2184 * sequence adjusts the DSP's signal attenuation to fix the 2185 * problem. 2186 */ 2187 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2188 2189 reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2190 /* Allow coefficient to be read */ 2191 CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 2192 DELAY(100); 2193 reg = CSR_READ_4(sc, NS_PHY_TDATA); 2194 if ((reg & 0x0080) == 0 || 2195 (reg > 0xd8 && reg <= 0xff)) { 2196 device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); 2197 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2198 /* Adjust coefficient and prevent change */ 2199 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2200 } 2201 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2202 } 2203 2204 /* 2205 * Enable interrupts. 2206 */ 2207 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2208 #ifdef DEVICE_POLLING 2209 /* 2210 * ... only enable interrupts if we are not polling, make sure 2211 * they are off otherwise. 2212 */ 2213 if (ifp->if_flags & IFF_POLLING) 2214 CSR_WRITE_4(sc, SIS_IER, 0); 2215 else 2216 #endif /* DEVICE_POLLING */ 2217 CSR_WRITE_4(sc, SIS_IER, 1); 2218 2219 /* Enable receiver and transmitter. */ 2220 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2221 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2222 2223 #ifdef notdef 2224 mii_mediachg(mii); 2225 #endif 2226 2227 ifp->if_flags |= IFF_RUNNING; 2228 ifp->if_flags &= ~IFF_OACTIVE; 2229 2230 if (!sc->in_tick) 2231 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2232 2233 SIS_UNLOCK(sc); 2234 2235 return; 2236 } 2237 2238 /* 2239 * Set media options. 2240 */ 2241 static int 2242 sis_ifmedia_upd(ifp) 2243 struct ifnet *ifp; 2244 { 2245 struct sis_softc *sc; 2246 struct mii_data *mii; 2247 2248 sc = ifp->if_softc; 2249 2250 mii = device_get_softc(sc->sis_miibus); 2251 sc->sis_link = 0; 2252 if (mii->mii_instance) { 2253 struct mii_softc *miisc; 2254 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2255 mii_phy_reset(miisc); 2256 } 2257 mii_mediachg(mii); 2258 2259 return(0); 2260 } 2261 2262 /* 2263 * Report current media status. 2264 */ 2265 static void 2266 sis_ifmedia_sts(ifp, ifmr) 2267 struct ifnet *ifp; 2268 struct ifmediareq *ifmr; 2269 { 2270 struct sis_softc *sc; 2271 struct mii_data *mii; 2272 2273 sc = ifp->if_softc; 2274 2275 mii = device_get_softc(sc->sis_miibus); 2276 mii_pollstat(mii); 2277 ifmr->ifm_active = mii->mii_media_active; 2278 ifmr->ifm_status = mii->mii_media_status; 2279 2280 return; 2281 } 2282 2283 static int 2284 sis_ioctl(ifp, command, data) 2285 struct ifnet *ifp; 2286 u_long command; 2287 caddr_t data; 2288 { 2289 struct sis_softc *sc = ifp->if_softc; 2290 struct ifreq *ifr = (struct ifreq *) data; 2291 struct mii_data *mii; 2292 int error = 0; 2293 2294 switch(command) { 2295 case SIOCSIFFLAGS: 2296 if (ifp->if_flags & IFF_UP) { 2297 sis_init(sc); 2298 } else { 2299 if (ifp->if_flags & IFF_RUNNING) 2300 sis_stop(sc); 2301 } 2302 error = 0; 2303 break; 2304 case SIOCADDMULTI: 2305 case SIOCDELMULTI: 2306 SIS_LOCK(sc); 2307 if (sc->sis_type == SIS_TYPE_83815) 2308 sis_setmulti_ns(sc); 2309 else 2310 sis_setmulti_sis(sc); 2311 SIS_UNLOCK(sc); 2312 error = 0; 2313 break; 2314 case SIOCGIFMEDIA: 2315 case SIOCSIFMEDIA: 2316 mii = device_get_softc(sc->sis_miibus); 2317 SIS_LOCK(sc); 2318 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2319 SIS_UNLOCK(sc); 2320 break; 2321 case SIOCSIFCAP: 2322 ifp->if_capenable &= ~IFCAP_POLLING; 2323 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2324 break; 2325 default: 2326 error = ether_ioctl(ifp, command, data); 2327 break; 2328 } 2329 2330 return(error); 2331 } 2332 2333 static void 2334 sis_watchdog(ifp) 2335 struct ifnet *ifp; 2336 { 2337 struct sis_softc *sc; 2338 2339 sc = ifp->if_softc; 2340 2341 SIS_LOCK(sc); 2342 2343 ifp->if_oerrors++; 2344 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2345 2346 sis_stop(sc); 2347 sis_reset(sc); 2348 sis_init(sc); 2349 2350 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2351 sis_start(ifp); 2352 2353 SIS_UNLOCK(sc); 2354 2355 return; 2356 } 2357 2358 /* 2359 * Stop the adapter and free any mbufs allocated to the 2360 * RX and TX lists. 2361 */ 2362 static void 2363 sis_stop(sc) 2364 struct sis_softc *sc; 2365 { 2366 register int i; 2367 struct ifnet *ifp; 2368 2369 if (sc->sis_stopped) 2370 return; 2371 SIS_LOCK(sc); 2372 ifp = &sc->arpcom.ac_if; 2373 ifp->if_timer = 0; 2374 2375 callout_stop(&sc->sis_stat_ch); 2376 2377 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2378 #ifdef DEVICE_POLLING 2379 ether_poll_deregister(ifp); 2380 #endif 2381 CSR_WRITE_4(sc, SIS_IER, 0); 2382 CSR_WRITE_4(sc, SIS_IMR, 0); 2383 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2384 DELAY(1000); 2385 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2386 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2387 2388 sc->sis_link = 0; 2389 2390 /* 2391 * Free data in the RX lists. 2392 */ 2393 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2394 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2395 bus_dmamap_unload(sc->sis_tag, 2396 sc->sis_ldata.sis_rx_list[i].sis_map); 2397 bus_dmamap_destroy(sc->sis_tag, 2398 sc->sis_ldata.sis_rx_list[i].sis_map); 2399 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2400 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2401 } 2402 } 2403 bzero(sc->sis_ldata.sis_rx_list, 2404 sizeof(sc->sis_ldata.sis_rx_list)); 2405 2406 /* 2407 * Free the TX list buffers. 2408 */ 2409 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2410 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2411 bus_dmamap_unload(sc->sis_tag, 2412 sc->sis_ldata.sis_tx_list[i].sis_map); 2413 bus_dmamap_destroy(sc->sis_tag, 2414 sc->sis_ldata.sis_tx_list[i].sis_map); 2415 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2416 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2417 } 2418 } 2419 2420 bzero(sc->sis_ldata.sis_tx_list, 2421 sizeof(sc->sis_ldata.sis_tx_list)); 2422 2423 sc->sis_stopped = 1; 2424 SIS_UNLOCK(sc); 2425 2426 return; 2427 } 2428 2429 /* 2430 * Stop all chip I/O so that the kernel's probe routines don't 2431 * get confused by errant DMAs when rebooting. 2432 */ 2433 static void 2434 sis_shutdown(dev) 2435 device_t dev; 2436 { 2437 struct sis_softc *sc; 2438 2439 sc = device_get_softc(dev); 2440 SIS_LOCK(sc); 2441 sis_reset(sc); 2442 sis_stop(sc); 2443 SIS_UNLOCK(sc); 2444 2445 return; 2446 }
Cache object: 2cb06ac50a87e0dfe645708ed36d7acf
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]