The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sis.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
    3  * Copyright (c) 1997, 1998, 1999
    4  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. All advertising materials mentioning features or use of this software
   15  *    must display the following acknowledgement:
   16  *      This product includes software developed by Bill Paul.
   17  * 4. Neither the name of the author nor the names of any co-contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   31  * THE POSSIBILITY OF SUCH DAMAGE.
   32  */
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD: releng/6.0/sys/pci/if_sis.c 151140 2005-10-09 04:11:20Z delphij $");
   36 
   37 /*
   38  * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
   39  * available from http://www.sis.com.tw.
   40  *
   41  * This driver also supports the NatSemi DP83815. Datasheets are
   42  * available from http://www.national.com.
   43  *
   44  * Written by Bill Paul <wpaul@ee.columbia.edu>
   45  * Electrical Engineering Department
   46  * Columbia University, New York City
   47  */
   48 /*
   49  * The SiS 900 is a fairly simple chip. It uses bus master DMA with
   50  * simple TX and RX descriptors of 3 longwords in size. The receiver
   51  * has a single perfect filter entry for the station address and a
   52  * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
   53  * transceiver while the 7016 requires an external transceiver chip.
   54  * Both chips offer the standard bit-bang MII interface as well as
   55  * an enchanced PHY interface which simplifies accessing MII registers.
   56  *
   57  * The only downside to this chipset is that RX descriptors must be
   58  * longword aligned.
   59  */
   60 
   61 #ifdef HAVE_KERNEL_OPTION_HEADERS
   62 #include "opt_device_polling.h"
   63 #endif
   64 
   65 #include <sys/param.h>
   66 #include <sys/systm.h>
   67 #include <sys/sockio.h>
   68 #include <sys/mbuf.h>
   69 #include <sys/malloc.h>
   70 #include <sys/kernel.h>
   71 #include <sys/module.h>
   72 #include <sys/socket.h>
   73 #include <sys/sysctl.h>
   74 
   75 #include <net/if.h>
   76 #include <net/if_arp.h>
   77 #include <net/ethernet.h>
   78 #include <net/if_dl.h>
   79 #include <net/if_media.h>
   80 #include <net/if_types.h>
   81 #include <net/if_vlan_var.h>
   82 
   83 #include <net/bpf.h>
   84 
   85 #include <machine/bus.h>
   86 #include <machine/resource.h>
   87 #include <sys/bus.h>
   88 #include <sys/rman.h>
   89 
   90 #include <dev/mii/mii.h>
   91 #include <dev/mii/miivar.h>
   92 
   93 #include <dev/pci/pcireg.h>
   94 #include <dev/pci/pcivar.h>
   95 
   96 #define SIS_USEIOSPACE
   97 
   98 #include <pci/if_sisreg.h>
   99 
  100 MODULE_DEPEND(sis, pci, 1, 1, 1);
  101 MODULE_DEPEND(sis, ether, 1, 1, 1);
  102 MODULE_DEPEND(sis, miibus, 1, 1, 1);
  103 
  104 /* "controller miibus0" required.  See GENERIC if you get errors here. */
  105 #include "miibus_if.h"
  106 
  107 /*
  108  * Various supported device vendors/types and their names.
  109  */
  110 static struct sis_type sis_devs[] = {
  111         { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
  112         { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
  113         { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
  114         { 0, 0, NULL }
  115 };
  116 
  117 static int sis_detach(device_t);
  118 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  119 static int sis_ifmedia_upd(struct ifnet *);
  120 static void sis_init(void *);
  121 static void sis_initl(struct sis_softc *);
  122 static void sis_intr(void *);
  123 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
  124 static int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *);
  125 static void sis_start(struct ifnet *);
  126 static void sis_startl(struct ifnet *);
  127 static void sis_stop(struct sis_softc *);
  128 static void sis_watchdog(struct ifnet *);
  129 
  130 #ifdef SIS_USEIOSPACE
  131 #define SIS_RES                 SYS_RES_IOPORT
  132 #define SIS_RID                 SIS_PCI_LOIO
  133 #else
  134 #define SIS_RES                 SYS_RES_MEMORY
  135 #define SIS_RID                 SIS_PCI_LOMEM
  136 #endif
  137 
  138 #define SIS_SETBIT(sc, reg, x)                          \
  139         CSR_WRITE_4(sc, reg,                            \
  140                 CSR_READ_4(sc, reg) | (x))
  141 
  142 #define SIS_CLRBIT(sc, reg, x)                          \
  143         CSR_WRITE_4(sc, reg,                            \
  144                 CSR_READ_4(sc, reg) & ~(x))
  145 
  146 #define SIO_SET(x)                                      \
  147         CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
  148 
  149 #define SIO_CLR(x)                                      \
  150         CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
  151 
  152 static void
  153 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
  154 {
  155         struct sis_desc *r;
  156 
  157         r = arg;
  158         r->sis_next = segs->ds_addr;
  159 }
  160 
  161 static void
  162 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
  163 {
  164         struct sis_desc *r;
  165 
  166         r = arg;
  167         r->sis_ptr = segs->ds_addr;
  168 }
  169 
  170 static void
  171 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
  172 {
  173         u_int32_t *p;
  174 
  175         p = arg;
  176         *p = segs->ds_addr;
  177 }
  178 
  179 /*
  180  * Routine to reverse the bits in a word. Stolen almost
  181  * verbatim from /usr/games/fortune.
  182  */
  183 static uint16_t
  184 sis_reverse(uint16_t n)
  185 {
  186         n = ((n >>  1) & 0x5555) | ((n <<  1) & 0xaaaa);
  187         n = ((n >>  2) & 0x3333) | ((n <<  2) & 0xcccc);
  188         n = ((n >>  4) & 0x0f0f) | ((n <<  4) & 0xf0f0);
  189         n = ((n >>  8) & 0x00ff) | ((n <<  8) & 0xff00);
  190 
  191         return(n);
  192 }
  193 
  194 static void
  195 sis_delay(struct sis_softc *sc)
  196 {
  197         int                     idx;
  198 
  199         for (idx = (300 / 33) + 1; idx > 0; idx--)
  200                 CSR_READ_4(sc, SIS_CSR);
  201 }
  202 
  203 static void
  204 sis_eeprom_idle(struct sis_softc *sc)
  205 {
  206         int             i;
  207 
  208         SIO_SET(SIS_EECTL_CSEL);
  209         sis_delay(sc);
  210         SIO_SET(SIS_EECTL_CLK);
  211         sis_delay(sc);
  212 
  213         for (i = 0; i < 25; i++) {
  214                 SIO_CLR(SIS_EECTL_CLK);
  215                 sis_delay(sc);
  216                 SIO_SET(SIS_EECTL_CLK);
  217                 sis_delay(sc);
  218         }
  219 
  220         SIO_CLR(SIS_EECTL_CLK);
  221         sis_delay(sc);
  222         SIO_CLR(SIS_EECTL_CSEL);
  223         sis_delay(sc);
  224         CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
  225 }
  226 
  227 /*
  228  * Send a read command and address to the EEPROM, check for ACK.
  229  */
  230 static void
  231 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
  232 {
  233         int             d, i;
  234 
  235         d = addr | SIS_EECMD_READ;
  236 
  237         /*
  238          * Feed in each bit and stobe the clock.
  239          */
  240         for (i = 0x400; i; i >>= 1) {
  241                 if (d & i) {
  242                         SIO_SET(SIS_EECTL_DIN);
  243                 } else {
  244                         SIO_CLR(SIS_EECTL_DIN);
  245                 }
  246                 sis_delay(sc);
  247                 SIO_SET(SIS_EECTL_CLK);
  248                 sis_delay(sc);
  249                 SIO_CLR(SIS_EECTL_CLK);
  250                 sis_delay(sc);
  251         }
  252 }
  253 
  254 /*
  255  * Read a word of data stored in the EEPROM at address 'addr.'
  256  */
  257 static void
  258 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
  259 {
  260         int             i;
  261         u_int16_t               word = 0;
  262 
  263         /* Force EEPROM to idle state. */
  264         sis_eeprom_idle(sc);
  265 
  266         /* Enter EEPROM access mode. */
  267         sis_delay(sc);
  268         SIO_CLR(SIS_EECTL_CLK);
  269         sis_delay(sc);
  270         SIO_SET(SIS_EECTL_CSEL);
  271         sis_delay(sc);
  272 
  273         /*
  274          * Send address of word we want to read.
  275          */
  276         sis_eeprom_putbyte(sc, addr);
  277 
  278         /*
  279          * Start reading bits from EEPROM.
  280          */
  281         for (i = 0x8000; i; i >>= 1) {
  282                 SIO_SET(SIS_EECTL_CLK);
  283                 sis_delay(sc);
  284                 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
  285                         word |= i;
  286                 sis_delay(sc);
  287                 SIO_CLR(SIS_EECTL_CLK);
  288                 sis_delay(sc);
  289         }
  290 
  291         /* Turn off EEPROM access mode. */
  292         sis_eeprom_idle(sc);
  293 
  294         *dest = word;
  295 }
  296 
  297 /*
  298  * Read a sequence of words from the EEPROM.
  299  */
  300 static void
  301 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
  302 {
  303         int                     i;
  304         u_int16_t               word = 0, *ptr;
  305 
  306         for (i = 0; i < cnt; i++) {
  307                 sis_eeprom_getword(sc, off + i, &word);
  308                 ptr = (u_int16_t *)(dest + (i * 2));
  309                 if (swap)
  310                         *ptr = ntohs(word);
  311                 else
  312                         *ptr = word;
  313         }
  314 }
  315 
  316 #if defined(__i386__) || defined(__amd64__)
  317 static device_t
  318 sis_find_bridge(device_t dev)
  319 {
  320         devclass_t              pci_devclass;
  321         device_t                *pci_devices;
  322         int                     pci_count = 0;
  323         device_t                *pci_children;
  324         int                     pci_childcount = 0;
  325         device_t                *busp, *childp;
  326         device_t                child = NULL;
  327         int                     i, j;
  328 
  329         if ((pci_devclass = devclass_find("pci")) == NULL)
  330                 return(NULL);
  331 
  332         devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
  333 
  334         for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
  335                 pci_childcount = 0;
  336                 device_get_children(*busp, &pci_children, &pci_childcount);
  337                 for (j = 0, childp = pci_children;
  338                     j < pci_childcount; j++, childp++) {
  339                         if (pci_get_vendor(*childp) == SIS_VENDORID &&
  340                             pci_get_device(*childp) == 0x0008) {
  341                                 child = *childp;
  342                                 goto done;
  343                         }
  344                 }
  345         }
  346 
  347 done:
  348         free(pci_devices, M_TEMP);
  349         free(pci_children, M_TEMP);
  350         return(child);
  351 }
  352 
  353 static void
  354 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
  355 {
  356         device_t                bridge;
  357         u_int8_t                reg;
  358         int                     i;
  359         bus_space_tag_t         btag;
  360 
  361         bridge = sis_find_bridge(dev);
  362         if (bridge == NULL)
  363                 return;
  364         reg = pci_read_config(bridge, 0x48, 1);
  365         pci_write_config(bridge, 0x48, reg|0x40, 1);
  366 
  367         /* XXX */
  368 #if defined(__i386__)
  369         btag = I386_BUS_SPACE_IO;
  370 #elif defined(__amd64__)
  371         btag = AMD64_BUS_SPACE_IO;
  372 #endif
  373 
  374         for (i = 0; i < cnt; i++) {
  375                 bus_space_write_1(btag, 0x0, 0x70, i + off);
  376                 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
  377         }
  378 
  379         pci_write_config(bridge, 0x48, reg & ~0x40, 1);
  380         return;
  381 }
  382 
  383 static void
  384 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
  385 {
  386         u_int32_t               filtsave, csrsave;
  387 
  388         filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
  389         csrsave = CSR_READ_4(sc, SIS_CSR);
  390 
  391         CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
  392         CSR_WRITE_4(sc, SIS_CSR, 0);
  393                 
  394         CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
  395 
  396         CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
  397         ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
  398         CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
  399         ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
  400         CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
  401         ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
  402 
  403         CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
  404         CSR_WRITE_4(sc, SIS_CSR, csrsave);
  405         return;
  406 }
  407 #endif
  408 
  409 /*
  410  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  411  */
  412 static void
  413 sis_mii_sync(struct sis_softc *sc)
  414 {
  415         int             i;
  416  
  417         SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
  418  
  419         for (i = 0; i < 32; i++) {
  420                 SIO_SET(SIS_MII_CLK);
  421                 DELAY(1);
  422                 SIO_CLR(SIS_MII_CLK);
  423                 DELAY(1);
  424         }
  425 }
  426  
  427 /*
  428  * Clock a series of bits through the MII.
  429  */
  430 static void
  431 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
  432 {
  433         int                     i;
  434  
  435         SIO_CLR(SIS_MII_CLK);
  436  
  437         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  438                 if (bits & i) {
  439                         SIO_SET(SIS_MII_DATA);
  440                 } else {
  441                         SIO_CLR(SIS_MII_DATA);
  442                 }
  443                 DELAY(1);
  444                 SIO_CLR(SIS_MII_CLK);
  445                 DELAY(1);
  446                 SIO_SET(SIS_MII_CLK);
  447         }
  448 }
  449  
  450 /*
  451  * Read an PHY register through the MII.
  452  */
  453 static int
  454 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
  455 {
  456         int                     i, ack;
  457  
  458         /*
  459          * Set up frame for RX.
  460          */
  461         frame->mii_stdelim = SIS_MII_STARTDELIM;
  462         frame->mii_opcode = SIS_MII_READOP;
  463         frame->mii_turnaround = 0;
  464         frame->mii_data = 0;
  465         
  466         /*
  467          * Turn on data xmit.
  468          */
  469         SIO_SET(SIS_MII_DIR);
  470 
  471         sis_mii_sync(sc);
  472  
  473         /*
  474          * Send command/address info.
  475          */
  476         sis_mii_send(sc, frame->mii_stdelim, 2);
  477         sis_mii_send(sc, frame->mii_opcode, 2);
  478         sis_mii_send(sc, frame->mii_phyaddr, 5);
  479         sis_mii_send(sc, frame->mii_regaddr, 5);
  480  
  481         /* Idle bit */
  482         SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
  483         DELAY(1);
  484         SIO_SET(SIS_MII_CLK);
  485         DELAY(1);
  486  
  487         /* Turn off xmit. */
  488         SIO_CLR(SIS_MII_DIR);
  489  
  490         /* Check for ack */
  491         SIO_CLR(SIS_MII_CLK);
  492         DELAY(1);
  493         ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
  494         SIO_SET(SIS_MII_CLK);
  495         DELAY(1);
  496  
  497         /*
  498          * Now try reading data bits. If the ack failed, we still
  499          * need to clock through 16 cycles to keep the PHY(s) in sync.
  500          */
  501         if (ack) {
  502                 for(i = 0; i < 16; i++) {
  503                         SIO_CLR(SIS_MII_CLK);
  504                         DELAY(1);
  505                         SIO_SET(SIS_MII_CLK);
  506                         DELAY(1);
  507                 }
  508                 goto fail;
  509         }
  510  
  511         for (i = 0x8000; i; i >>= 1) {
  512                 SIO_CLR(SIS_MII_CLK);
  513                 DELAY(1);
  514                 if (!ack) {
  515                         if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
  516                                 frame->mii_data |= i;
  517                         DELAY(1);
  518                 }
  519                 SIO_SET(SIS_MII_CLK);
  520                 DELAY(1);
  521         }
  522 
  523 fail:
  524 
  525         SIO_CLR(SIS_MII_CLK);
  526         DELAY(1);
  527         SIO_SET(SIS_MII_CLK);
  528         DELAY(1);
  529 
  530         if (ack)
  531                 return(1);
  532         return(0);
  533 }
  534  
  535 /*
  536  * Write to a PHY register through the MII.
  537  */
  538 static int
  539 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
  540 {
  541  
  542         /*
  543          * Set up frame for TX.
  544          */
  545  
  546         frame->mii_stdelim = SIS_MII_STARTDELIM;
  547         frame->mii_opcode = SIS_MII_WRITEOP;
  548         frame->mii_turnaround = SIS_MII_TURNAROUND;
  549         
  550         /*
  551          * Turn on data output.
  552          */
  553         SIO_SET(SIS_MII_DIR);
  554  
  555         sis_mii_sync(sc);
  556  
  557         sis_mii_send(sc, frame->mii_stdelim, 2);
  558         sis_mii_send(sc, frame->mii_opcode, 2);
  559         sis_mii_send(sc, frame->mii_phyaddr, 5);
  560         sis_mii_send(sc, frame->mii_regaddr, 5);
  561         sis_mii_send(sc, frame->mii_turnaround, 2);
  562         sis_mii_send(sc, frame->mii_data, 16);
  563  
  564         /* Idle bit. */
  565         SIO_SET(SIS_MII_CLK);
  566         DELAY(1);
  567         SIO_CLR(SIS_MII_CLK);
  568         DELAY(1);
  569  
  570         /*
  571          * Turn off xmit.
  572          */
  573         SIO_CLR(SIS_MII_DIR);
  574  
  575         return(0);
  576 }
  577 
  578 static int
  579 sis_miibus_readreg(device_t dev, int phy, int reg)
  580 {
  581         struct sis_softc        *sc;
  582         struct sis_mii_frame    frame;
  583 
  584         sc = device_get_softc(dev);
  585 
  586         if (sc->sis_type == SIS_TYPE_83815) {
  587                 if (phy != 0)
  588                         return(0);
  589                 /*
  590                  * The NatSemi chip can take a while after
  591                  * a reset to come ready, during which the BMSR
  592                  * returns a value of 0. This is *never* supposed
  593                  * to happen: some of the BMSR bits are meant to
  594                  * be hardwired in the on position, and this can
  595                  * confuse the miibus code a bit during the probe
  596                  * and attach phase. So we make an effort to check
  597                  * for this condition and wait for it to clear.
  598                  */
  599                 if (!CSR_READ_4(sc, NS_BMSR))
  600                         DELAY(1000);
  601                 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
  602         }
  603 
  604         /*
  605          * Chipsets < SIS_635 seem not to be able to read/write
  606          * through mdio. Use the enhanced PHY access register
  607          * again for them.
  608          */
  609         if (sc->sis_type == SIS_TYPE_900 &&
  610             sc->sis_rev < SIS_REV_635) {
  611                 int i, val = 0;
  612 
  613                 if (phy != 0)
  614                         return(0);
  615 
  616                 CSR_WRITE_4(sc, SIS_PHYCTL,
  617                     (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
  618                 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
  619 
  620                 for (i = 0; i < SIS_TIMEOUT; i++) {
  621                         if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
  622                                 break;
  623                 }
  624 
  625                 if (i == SIS_TIMEOUT) {
  626                         if_printf(sc->sis_ifp, "PHY failed to come ready\n");
  627                         return(0);
  628                 }
  629 
  630                 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
  631 
  632                 if (val == 0xFFFF)
  633                         return(0);
  634 
  635                 return(val);
  636         } else {
  637                 bzero((char *)&frame, sizeof(frame));
  638 
  639                 frame.mii_phyaddr = phy;
  640                 frame.mii_regaddr = reg;
  641                 sis_mii_readreg(sc, &frame);
  642 
  643                 return(frame.mii_data);
  644         }
  645 }
  646 
  647 static int
  648 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
  649 {
  650         struct sis_softc        *sc;
  651         struct sis_mii_frame    frame;
  652 
  653         sc = device_get_softc(dev);
  654 
  655         if (sc->sis_type == SIS_TYPE_83815) {
  656                 if (phy != 0)
  657                         return(0);
  658                 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
  659                 return(0);
  660         }
  661 
  662         /*
  663          * Chipsets < SIS_635 seem not to be able to read/write
  664          * through mdio. Use the enhanced PHY access register
  665          * again for them.
  666          */
  667         if (sc->sis_type == SIS_TYPE_900 &&
  668             sc->sis_rev < SIS_REV_635) {
  669                 int i;
  670 
  671                 if (phy != 0)
  672                         return(0);
  673 
  674                 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
  675                     (reg << 6) | SIS_PHYOP_WRITE);
  676                 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
  677 
  678                 for (i = 0; i < SIS_TIMEOUT; i++) {
  679                         if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
  680                                 break;
  681                 }
  682 
  683                 if (i == SIS_TIMEOUT)
  684                         if_printf(sc->sis_ifp, "PHY failed to come ready\n");
  685         } else {
  686                 bzero((char *)&frame, sizeof(frame));
  687 
  688                 frame.mii_phyaddr = phy;
  689                 frame.mii_regaddr = reg;
  690                 frame.mii_data = data;
  691                 sis_mii_writereg(sc, &frame);
  692         }
  693         return(0);
  694 }
  695 
  696 static void
  697 sis_miibus_statchg(device_t dev)
  698 {
  699         struct sis_softc        *sc;
  700 
  701         sc = device_get_softc(dev);
  702         SIS_LOCK_ASSERT(sc);
  703         sis_initl(sc);
  704 }
  705 
  706 static uint32_t
  707 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
  708 {
  709         uint32_t                crc;
  710 
  711         /* Compute CRC for the address value. */
  712         crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
  713 
  714         /*
  715          * return the filter bit position
  716          *
  717          * The NatSemi chip has a 512-bit filter, which is
  718          * different than the SiS, so we special-case it.
  719          */
  720         if (sc->sis_type == SIS_TYPE_83815)
  721                 return (crc >> 23);
  722         else if (sc->sis_rev >= SIS_REV_635 ||
  723             sc->sis_rev == SIS_REV_900B)
  724                 return (crc >> 24);
  725         else
  726                 return (crc >> 25);
  727 }
  728 
  729 static void
  730 sis_setmulti_ns(struct sis_softc *sc)
  731 {
  732         struct ifnet            *ifp;
  733         struct ifmultiaddr      *ifma;
  734         u_int32_t               h = 0, i, filtsave;
  735         int                     bit, index;
  736 
  737         ifp = sc->sis_ifp;
  738 
  739         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  740                 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
  741                 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
  742                 return;
  743         }
  744 
  745         /*
  746          * We have to explicitly enable the multicast hash table
  747          * on the NatSemi chip if we want to use it, which we do.
  748          */
  749         SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
  750         SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
  751 
  752         filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
  753 
  754         /* first, zot all the existing hash bits */
  755         for (i = 0; i < 32; i++) {
  756                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
  757                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
  758         }
  759 
  760         IF_ADDR_LOCK(ifp);
  761         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  762                 if (ifma->ifma_addr->sa_family != AF_LINK)
  763                         continue;
  764                 h = sis_mchash(sc,
  765                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  766                 index = h >> 3;
  767                 bit = h & 0x1F;
  768                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
  769                 if (bit > 0xF)
  770                         bit -= 0x10;
  771                 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
  772         }
  773         IF_ADDR_UNLOCK(ifp);
  774 
  775         CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
  776 
  777         return;
  778 }
  779 
  780 static void
  781 sis_setmulti_sis(struct sis_softc *sc)
  782 {
  783         struct ifnet            *ifp;
  784         struct ifmultiaddr      *ifma;
  785         u_int32_t               h, i, n, ctl;
  786         u_int16_t               hashes[16];
  787 
  788         ifp = sc->sis_ifp;
  789 
  790         /* hash table size */
  791         if (sc->sis_rev >= SIS_REV_635 ||
  792             sc->sis_rev == SIS_REV_900B)
  793                 n = 16;
  794         else
  795                 n = 8;
  796 
  797         ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
  798 
  799         if (ifp->if_flags & IFF_BROADCAST)
  800                 ctl |= SIS_RXFILTCTL_BROAD;
  801 
  802         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  803                 ctl |= SIS_RXFILTCTL_ALLMULTI;
  804                 if (ifp->if_flags & IFF_PROMISC)
  805                         ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
  806                 for (i = 0; i < n; i++)
  807                         hashes[i] = ~0;
  808         } else {
  809                 for (i = 0; i < n; i++)
  810                         hashes[i] = 0;
  811                 i = 0;
  812                 IF_ADDR_LOCK(ifp);
  813                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  814                         if (ifma->ifma_addr->sa_family != AF_LINK)
  815                         continue;
  816                         h = sis_mchash(sc,
  817                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  818                         hashes[h >> 4] |= 1 << (h & 0xf);
  819                         i++;
  820                 }
  821                 IF_ADDR_UNLOCK(ifp);
  822                 if (i > n) {
  823                         ctl |= SIS_RXFILTCTL_ALLMULTI;
  824                         for (i = 0; i < n; i++)
  825                                 hashes[i] = ~0;
  826                 }
  827         }
  828 
  829         for (i = 0; i < n; i++) {
  830                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
  831                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
  832         }
  833 
  834         CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
  835 }
  836 
  837 static void
  838 sis_reset(struct sis_softc *sc)
  839 {
  840         int             i;
  841 
  842         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
  843 
  844         for (i = 0; i < SIS_TIMEOUT; i++) {
  845                 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
  846                         break;
  847         }
  848 
  849         if (i == SIS_TIMEOUT)
  850                 if_printf(sc->sis_ifp, "reset never completed\n");
  851 
  852         /* Wait a little while for the chip to get its brains in order. */
  853         DELAY(1000);
  854 
  855         /*
  856          * If this is a NetSemi chip, make sure to clear
  857          * PME mode.
  858          */
  859         if (sc->sis_type == SIS_TYPE_83815) {
  860                 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
  861                 CSR_WRITE_4(sc, NS_CLKRUN, 0);
  862         }
  863 
  864         return;
  865 }
  866 
  867 /*
  868  * Probe for an SiS chip. Check the PCI vendor and device
  869  * IDs against our list and return a device name if we find a match.
  870  */
  871 static int
  872 sis_probe(device_t dev)
  873 {
  874         struct sis_type         *t;
  875 
  876         t = sis_devs;
  877 
  878         while(t->sis_name != NULL) {
  879                 if ((pci_get_vendor(dev) == t->sis_vid) &&
  880                     (pci_get_device(dev) == t->sis_did)) {
  881                         device_set_desc(dev, t->sis_name);
  882                         return (BUS_PROBE_DEFAULT);
  883                 }
  884                 t++;
  885         }
  886 
  887         return(ENXIO);
  888 }
  889 
  890 /*
  891  * Attach the interface. Allocate softc structures, do ifmedia
  892  * setup and ethernet/BPF attach.
  893  */
  894 static int
  895 sis_attach(device_t dev)
  896 {
  897         u_char                  eaddr[ETHER_ADDR_LEN];
  898         struct sis_softc        *sc;
  899         struct ifnet            *ifp;
  900         int                     error = 0, rid, waittime = 0;
  901 
  902         waittime = 0;
  903         sc = device_get_softc(dev);
  904 
  905         sc->sis_self = dev;
  906 
  907         mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
  908             MTX_DEF);
  909         callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
  910 
  911         if (pci_get_device(dev) == SIS_DEVICEID_900)
  912                 sc->sis_type = SIS_TYPE_900;
  913         if (pci_get_device(dev) == SIS_DEVICEID_7016)
  914                 sc->sis_type = SIS_TYPE_7016;
  915         if (pci_get_vendor(dev) == NS_VENDORID)
  916                 sc->sis_type = SIS_TYPE_83815;
  917 
  918         sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
  919         /*
  920          * Map control/status registers.
  921          */
  922         pci_enable_busmaster(dev);
  923 
  924         rid = SIS_RID;
  925         sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
  926 
  927         if (sc->sis_res == NULL) {
  928                 device_printf(dev, "couldn't map ports/memory\n");
  929                 error = ENXIO;
  930                 goto fail;
  931         }
  932 
  933         sc->sis_btag = rman_get_bustag(sc->sis_res);
  934         sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
  935 
  936         /* Allocate interrupt */
  937         rid = 0;
  938         sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  939             RF_SHAREABLE | RF_ACTIVE);
  940 
  941         if (sc->sis_irq == NULL) {
  942                 device_printf(dev, "couldn't map interrupt\n");
  943                 error = ENXIO;
  944                 goto fail;
  945         }
  946 
  947         /* Reset the adapter. */
  948         sis_reset(sc);
  949 
  950         if (sc->sis_type == SIS_TYPE_900 &&
  951             (sc->sis_rev == SIS_REV_635 ||
  952             sc->sis_rev == SIS_REV_900B)) {
  953                 SIO_SET(SIS_CFG_RND_CNT);
  954                 SIO_SET(SIS_CFG_PERR_DETECT);
  955         }
  956 
  957         /*
  958          * Get station address from the EEPROM.
  959          */
  960         switch (pci_get_vendor(dev)) {
  961         case NS_VENDORID:
  962                 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
  963 
  964                 /* We can't update the device description, so spew */
  965                 if (sc->sis_srr == NS_SRR_15C)
  966                         device_printf(dev, "Silicon Revision: DP83815C\n");
  967                 else if (sc->sis_srr == NS_SRR_15D)
  968                         device_printf(dev, "Silicon Revision: DP83815D\n");
  969                 else if (sc->sis_srr == NS_SRR_16A)
  970                         device_printf(dev, "Silicon Revision: DP83816A\n");
  971                 else
  972                         device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
  973 
  974                 /*
  975                  * Reading the MAC address out of the EEPROM on
  976                  * the NatSemi chip takes a bit more work than
  977                  * you'd expect. The address spans 4 16-bit words,
  978                  * with the first word containing only a single bit.
  979                  * You have to shift everything over one bit to
  980                  * get it aligned properly. Also, the bits are
  981                  * stored backwards (the LSB is really the MSB,
  982                  * and so on) so you have to reverse them in order
  983                  * to get the MAC address into the form we want.
  984                  * Why? Who the hell knows.
  985                  */
  986                 {
  987                         u_int16_t               tmp[4];
  988 
  989                         sis_read_eeprom(sc, (caddr_t)&tmp,
  990                             NS_EE_NODEADDR, 4, 0);
  991 
  992                         /* Shift everything over one bit. */
  993                         tmp[3] = tmp[3] >> 1;
  994                         tmp[3] |= tmp[2] << 15;
  995                         tmp[2] = tmp[2] >> 1;
  996                         tmp[2] |= tmp[1] << 15;
  997                         tmp[1] = tmp[1] >> 1;
  998                         tmp[1] |= tmp[0] << 15;
  999 
 1000                         /* Now reverse all the bits. */
 1001                         tmp[3] = sis_reverse(tmp[3]);
 1002                         tmp[2] = sis_reverse(tmp[2]);
 1003                         tmp[1] = sis_reverse(tmp[1]);
 1004 
 1005                         bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
 1006                 }
 1007                 break;
 1008         case SIS_VENDORID:
 1009         default:
 1010 #if defined(__i386__) || defined(__amd64__)
 1011                 /*
 1012                  * If this is a SiS 630E chipset with an embedded
 1013                  * SiS 900 controller, we have to read the MAC address
 1014                  * from the APC CMOS RAM. Our method for doing this
 1015                  * is very ugly since we have to reach out and grab
 1016                  * ahold of hardware for which we cannot properly
 1017                  * allocate resources. This code is only compiled on
 1018                  * the i386 architecture since the SiS 630E chipset
 1019                  * is for x86 motherboards only. Note that there are
 1020                  * a lot of magic numbers in this hack. These are
 1021                  * taken from SiS's Linux driver. I'd like to replace
 1022                  * them with proper symbolic definitions, but that
 1023                  * requires some datasheets that I don't have access
 1024                  * to at the moment.
 1025                  */
 1026                 if (sc->sis_rev == SIS_REV_630S ||
 1027                     sc->sis_rev == SIS_REV_630E ||
 1028                     sc->sis_rev == SIS_REV_630EA1)
 1029                         sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
 1030 
 1031                 else if (sc->sis_rev == SIS_REV_635 ||
 1032                          sc->sis_rev == SIS_REV_630ET)
 1033                         sis_read_mac(sc, dev, (caddr_t)&eaddr);
 1034                 else if (sc->sis_rev == SIS_REV_96x) {
 1035                         /* Allow to read EEPROM from LAN. It is shared
 1036                          * between a 1394 controller and the NIC and each
 1037                          * time we access it, we need to set SIS_EECMD_REQ.
 1038                          */
 1039                         SIO_SET(SIS_EECMD_REQ);
 1040                         for (waittime = 0; waittime < SIS_TIMEOUT;
 1041                             waittime++) {
 1042                                 /* Force EEPROM to idle state. */
 1043                                 sis_eeprom_idle(sc);
 1044                                 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
 1045                                         sis_read_eeprom(sc, (caddr_t)&eaddr,
 1046                                             SIS_EE_NODEADDR, 3, 0);
 1047                                         break;
 1048                                 }
 1049                                 DELAY(1);
 1050                         }
 1051                         /*
 1052                          * Set SIS_EECTL_CLK to high, so a other master
 1053                          * can operate on the i2c bus.
 1054                          */
 1055                         SIO_SET(SIS_EECTL_CLK);
 1056                         /* Refuse EEPROM access by LAN */
 1057                         SIO_SET(SIS_EECMD_DONE);
 1058                 } else
 1059 #endif
 1060                         sis_read_eeprom(sc, (caddr_t)&eaddr,
 1061                             SIS_EE_NODEADDR, 3, 0);
 1062                 break;
 1063         }
 1064 
 1065         /*
 1066          * Allocate the parent bus DMA tag appropriate for PCI.
 1067          */
 1068 #define SIS_NSEG_NEW 32
 1069          error = bus_dma_tag_create(NULL,       /* parent */ 
 1070                         1, 0,                   /* alignment, boundary */
 1071                         BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
 1072                         BUS_SPACE_MAXADDR,      /* highaddr */
 1073                         NULL, NULL,             /* filter, filterarg */
 1074                         MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
 1075                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 
 1076                         BUS_DMA_ALLOCNOW,       /* flags */
 1077                         NULL, NULL,             /* lockfunc, lockarg */
 1078                         &sc->sis_parent_tag);
 1079         if (error)
 1080                 goto fail;
 1081 
 1082         /*
 1083          * Now allocate a tag for the DMA descriptor lists and a chunk
 1084          * of DMA-able memory based on the tag.  Also obtain the physical
 1085          * addresses of the RX and TX ring, which we'll need later.
 1086          * All of our lists are allocated as a contiguous block
 1087          * of memory.
 1088          */
 1089         error = bus_dma_tag_create(sc->sis_parent_tag,  /* parent */
 1090                         1, 0,                   /* alignment, boundary */
 1091                         BUS_SPACE_MAXADDR,      /* lowaddr */
 1092                         BUS_SPACE_MAXADDR,      /* highaddr */
 1093                         NULL, NULL,             /* filter, filterarg */
 1094                         SIS_RX_LIST_SZ, 1,      /* maxsize,nsegments */
 1095                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
 1096                         0,                      /* flags */
 1097                         busdma_lock_mutex,      /* lockfunc */
 1098                         &Giant,                 /* lockarg */
 1099                         &sc->sis_rx_tag);
 1100         if (error)
 1101                 goto fail;
 1102 
 1103         error = bus_dmamem_alloc(sc->sis_rx_tag,
 1104             (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
 1105             &sc->sis_rx_dmamap);
 1106 
 1107         if (error) {
 1108                 device_printf(dev, "no memory for rx list buffers!\n");
 1109                 bus_dma_tag_destroy(sc->sis_rx_tag);
 1110                 sc->sis_rx_tag = NULL;
 1111                 goto fail;
 1112         }
 1113 
 1114         error = bus_dmamap_load(sc->sis_rx_tag,
 1115             sc->sis_rx_dmamap, &(sc->sis_rx_list[0]),
 1116             sizeof(struct sis_desc), sis_dma_map_ring,
 1117             &sc->sis_rx_paddr, 0);
 1118 
 1119         if (error) {
 1120                 device_printf(dev, "cannot get address of the rx ring!\n");
 1121                 bus_dmamem_free(sc->sis_rx_tag,
 1122                     sc->sis_rx_list, sc->sis_rx_dmamap);
 1123                 bus_dma_tag_destroy(sc->sis_rx_tag);
 1124                 sc->sis_rx_tag = NULL;
 1125                 goto fail;
 1126         }
 1127 
 1128         error = bus_dma_tag_create(sc->sis_parent_tag,  /* parent */
 1129                         1, 0,                   /* alignment, boundary */
 1130                         BUS_SPACE_MAXADDR,      /* lowaddr */
 1131                         BUS_SPACE_MAXADDR,      /* highaddr */
 1132                         NULL, NULL,             /* filter, filterarg */
 1133                         SIS_TX_LIST_SZ, 1,      /* maxsize,nsegments */
 1134                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
 1135                         0,                      /* flags */
 1136                         busdma_lock_mutex,      /* lockfunc */
 1137                         &Giant,                 /* lockarg */
 1138                         &sc->sis_tx_tag);
 1139         if (error)
 1140                 goto fail;
 1141 
 1142         error = bus_dmamem_alloc(sc->sis_tx_tag,
 1143             (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
 1144             &sc->sis_tx_dmamap);
 1145 
 1146         if (error) {
 1147                 device_printf(dev, "no memory for tx list buffers!\n");
 1148                 bus_dma_tag_destroy(sc->sis_tx_tag);
 1149                 sc->sis_tx_tag = NULL;
 1150                 goto fail;
 1151         }
 1152 
 1153         error = bus_dmamap_load(sc->sis_tx_tag,
 1154             sc->sis_tx_dmamap, &(sc->sis_tx_list[0]),
 1155             sizeof(struct sis_desc), sis_dma_map_ring,
 1156             &sc->sis_tx_paddr, 0);
 1157 
 1158         if (error) {
 1159                 device_printf(dev, "cannot get address of the tx ring!\n");
 1160                 bus_dmamem_free(sc->sis_tx_tag,
 1161                     sc->sis_tx_list, sc->sis_tx_dmamap);
 1162                 bus_dma_tag_destroy(sc->sis_tx_tag);
 1163                 sc->sis_tx_tag = NULL;
 1164                 goto fail;
 1165         }
 1166 
 1167         error = bus_dma_tag_create(sc->sis_parent_tag,  /* parent */
 1168                         1, 0,                   /* alignment, boundary */
 1169                         BUS_SPACE_MAXADDR,      /* lowaddr */
 1170                         BUS_SPACE_MAXADDR,      /* highaddr */
 1171                         NULL, NULL,             /* filter, filterarg */
 1172                         MCLBYTES, 1,            /* maxsize,nsegments */
 1173                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
 1174                         0,                      /* flags */
 1175                         busdma_lock_mutex,      /* lockfunc */
 1176                         &Giant,                 /* lockarg */
 1177                         &sc->sis_tag);
 1178         if (error)
 1179                 goto fail;
 1180 
 1181         /*
 1182          * Obtain the physical addresses of the RX and TX
 1183          * rings which we'll need later in the init routine.
 1184          */
 1185 
 1186         ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
 1187         if (ifp == NULL) {
 1188                 device_printf(dev, "can not if_alloc()\n");
 1189                 error = ENOSPC;
 1190                 goto fail;
 1191         }
 1192         ifp->if_softc = sc;
 1193         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 1194         ifp->if_mtu = ETHERMTU;
 1195         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1196         ifp->if_ioctl = sis_ioctl;
 1197         ifp->if_start = sis_start;
 1198         ifp->if_watchdog = sis_watchdog;
 1199         ifp->if_init = sis_init;
 1200         ifp->if_baudrate = 10000000;
 1201         IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
 1202         ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
 1203         IFQ_SET_READY(&ifp->if_snd);
 1204 
 1205         /*
 1206          * Do MII setup.
 1207          */
 1208         if (mii_phy_probe(dev, &sc->sis_miibus,
 1209             sis_ifmedia_upd, sis_ifmedia_sts)) {
 1210                 device_printf(dev, "MII without any PHY!\n");
 1211                 if_free(ifp);
 1212                 error = ENXIO;
 1213                 goto fail;
 1214         }
 1215 
 1216         /*
 1217          * Call MI attach routine.
 1218          */
 1219         ether_ifattach(ifp, eaddr);
 1220         
 1221         /*
 1222          * Tell the upper layer(s) we support long frames.
 1223          */
 1224         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 1225         ifp->if_capabilities |= IFCAP_VLAN_MTU;
 1226         ifp->if_capenable = ifp->if_capabilities;
 1227 #ifdef DEVICE_POLLING
 1228         ifp->if_capabilities |= IFCAP_POLLING;
 1229 #endif
 1230 
 1231         /* Hook interrupt last to avoid having to lock softc */
 1232         error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE,
 1233             sis_intr, sc, &sc->sis_intrhand);
 1234 
 1235         if (error) {
 1236                 device_printf(dev, "couldn't set up irq\n");
 1237                 ether_ifdetach(ifp);
 1238                 goto fail;
 1239         }
 1240 
 1241 fail:
 1242         if (error)
 1243                 sis_detach(dev);
 1244 
 1245         return(error);
 1246 }
 1247 
 1248 /*
 1249  * Shutdown hardware and free up resources. This can be called any
 1250  * time after the mutex has been initialized. It is called in both
 1251  * the error case in attach and the normal detach case so it needs
 1252  * to be careful about only freeing resources that have actually been
 1253  * allocated.
 1254  */
 1255 static int
 1256 sis_detach(device_t dev)
 1257 {
 1258         struct sis_softc        *sc;
 1259         struct ifnet            *ifp;
 1260 
 1261         sc = device_get_softc(dev);
 1262         KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
 1263         ifp = sc->sis_ifp;
 1264 
 1265 #ifdef DEVICE_POLLING
 1266         if (ifp->if_capenable & IFCAP_POLLING)
 1267                 ether_poll_deregister(ifp);
 1268 #endif
 1269 
 1270         /* These should only be active if attach succeeded. */
 1271         if (device_is_attached(dev)) {
 1272                 SIS_LOCK(sc);
 1273                 sis_reset(sc);
 1274                 sis_stop(sc);
 1275                 SIS_UNLOCK(sc);
 1276                 callout_drain(&sc->sis_stat_ch);
 1277                 ether_ifdetach(ifp);
 1278         }
 1279         if (ifp)
 1280                 if_free(ifp);
 1281         if (sc->sis_miibus)
 1282                 device_delete_child(dev, sc->sis_miibus);
 1283         bus_generic_detach(dev);
 1284 
 1285         if (sc->sis_intrhand)
 1286                 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
 1287         if (sc->sis_irq)
 1288                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
 1289         if (sc->sis_res)
 1290                 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
 1291 
 1292         if (sc->sis_rx_tag) {
 1293                 bus_dmamap_unload(sc->sis_rx_tag,
 1294                     sc->sis_rx_dmamap);
 1295                 bus_dmamem_free(sc->sis_rx_tag,
 1296                     sc->sis_rx_list, sc->sis_rx_dmamap);
 1297                 bus_dma_tag_destroy(sc->sis_rx_tag);
 1298         }
 1299         if (sc->sis_tx_tag) {
 1300                 bus_dmamap_unload(sc->sis_tx_tag,
 1301                     sc->sis_tx_dmamap);
 1302                 bus_dmamem_free(sc->sis_tx_tag,
 1303                     sc->sis_tx_list, sc->sis_tx_dmamap);
 1304                 bus_dma_tag_destroy(sc->sis_tx_tag);
 1305         }
 1306         if (sc->sis_parent_tag)
 1307                 bus_dma_tag_destroy(sc->sis_parent_tag);
 1308         if (sc->sis_tag)
 1309                 bus_dma_tag_destroy(sc->sis_tag);
 1310 
 1311         mtx_destroy(&sc->sis_mtx);
 1312 
 1313         return(0);
 1314 }
 1315 
 1316 /*
 1317  * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
 1318  * we arrange the descriptors in a closed ring, so that the last descriptor
 1319  * points back to the first.
 1320  */
 1321 static int
 1322 sis_ring_init(struct sis_softc *sc)
 1323 {
 1324         int i, error;
 1325         struct sis_desc *dp;
 1326 
 1327         dp = &sc->sis_tx_list[0];
 1328         for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) {
 1329                 if (i == (SIS_TX_LIST_CNT - 1))
 1330                         dp->sis_nextdesc = &sc->sis_tx_list[0];
 1331                 else
 1332                         dp->sis_nextdesc = dp + 1;
 1333                 bus_dmamap_load(sc->sis_tx_tag,
 1334                     sc->sis_tx_dmamap,
 1335                     dp->sis_nextdesc, sizeof(struct sis_desc),
 1336                     sis_dma_map_desc_next, dp, 0);
 1337                 dp->sis_mbuf = NULL;
 1338                 dp->sis_ptr = 0;
 1339                 dp->sis_ctl = 0;
 1340         }
 1341 
 1342         sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
 1343 
 1344         bus_dmamap_sync(sc->sis_tx_tag,
 1345             sc->sis_tx_dmamap, BUS_DMASYNC_PREWRITE);
 1346 
 1347         dp = &sc->sis_rx_list[0];
 1348         for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) {
 1349                 error = sis_newbuf(sc, dp, NULL);
 1350                 if (error)
 1351                         return(error);
 1352                 if (i == (SIS_RX_LIST_CNT - 1))
 1353                         dp->sis_nextdesc = &sc->sis_rx_list[0];
 1354                 else
 1355                         dp->sis_nextdesc = dp + 1;
 1356                 bus_dmamap_load(sc->sis_rx_tag,
 1357                     sc->sis_rx_dmamap,
 1358                     dp->sis_nextdesc, sizeof(struct sis_desc),
 1359                     sis_dma_map_desc_next, dp, 0);
 1360                 }
 1361 
 1362         bus_dmamap_sync(sc->sis_rx_tag,
 1363             sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE);
 1364 
 1365         sc->sis_rx_pdsc = &sc->sis_rx_list[0];
 1366 
 1367         return(0);
 1368 }
 1369 
 1370 /*
 1371  * Initialize an RX descriptor and attach an MBUF cluster.
 1372  */
 1373 static int
 1374 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
 1375 {
 1376 
 1377         if (c == NULL)
 1378                 return(EINVAL);
 1379 
 1380         if (m == NULL) {
 1381                 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 1382                 if (m == NULL)
 1383                         return(ENOBUFS);
 1384         } else
 1385                 m->m_data = m->m_ext.ext_buf;
 1386 
 1387         c->sis_mbuf = m;
 1388         c->sis_ctl = SIS_RXLEN;
 1389 
 1390         bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
 1391         bus_dmamap_load(sc->sis_tag, c->sis_map,
 1392             mtod(m, void *), MCLBYTES,
 1393             sis_dma_map_desc_ptr, c, 0);
 1394         bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD);
 1395 
 1396         return(0);
 1397 }
 1398 
 1399 /*
 1400  * A frame has been uploaded: pass the resulting mbuf chain up to
 1401  * the higher level protocols.
 1402  */
 1403 static void
 1404 sis_rxeof(struct sis_softc *sc)
 1405 {
 1406         struct mbuf             *m;
 1407         struct ifnet            *ifp;
 1408         struct sis_desc         *cur_rx;
 1409         int                     total_len = 0;
 1410         u_int32_t               rxstat;
 1411 
 1412         SIS_LOCK_ASSERT(sc);
 1413 
 1414         ifp = sc->sis_ifp;
 1415 
 1416         for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx);
 1417             cur_rx = cur_rx->sis_nextdesc) {
 1418 
 1419 #ifdef DEVICE_POLLING
 1420                 if (ifp->if_capenable & IFCAP_POLLING) {
 1421                         if (sc->rxcycles <= 0)
 1422                                 break;
 1423                         sc->rxcycles--;
 1424                 }
 1425 #endif
 1426                 rxstat = cur_rx->sis_rxstat;
 1427                 bus_dmamap_sync(sc->sis_tag,
 1428                     cur_rx->sis_map, BUS_DMASYNC_POSTWRITE);
 1429                 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
 1430                 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
 1431                 m = cur_rx->sis_mbuf;
 1432                 cur_rx->sis_mbuf = NULL;
 1433                 total_len = SIS_RXBYTES(cur_rx);
 1434 
 1435                 /*
 1436                  * If an error occurs, update stats, clear the
 1437                  * status word and leave the mbuf cluster in place:
 1438                  * it should simply get re-used next time this descriptor
 1439                  * comes up in the ring.
 1440                  */
 1441                 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
 1442                         ifp->if_ierrors++;
 1443                         if (rxstat & SIS_RXSTAT_COLL)
 1444                                 ifp->if_collisions++;
 1445                         sis_newbuf(sc, cur_rx, m);
 1446                         continue;
 1447                 }
 1448 
 1449                 /* No errors; receive the packet. */    
 1450 #if defined(__i386__) || defined(__amd64__)
 1451                 /*
 1452                  * On the x86 we do not have alignment problems, so try to
 1453                  * allocate a new buffer for the receive ring, and pass up
 1454                  * the one where the packet is already, saving the expensive
 1455                  * copy done in m_devget().
 1456                  * If we are on an architecture with alignment problems, or
 1457                  * if the allocation fails, then use m_devget and leave the
 1458                  * existing buffer in the receive ring.
 1459                  */
 1460                 if (sis_newbuf(sc, cur_rx, NULL) == 0)
 1461                         m->m_pkthdr.len = m->m_len = total_len;
 1462                 else
 1463 #endif
 1464                 {
 1465                         struct mbuf             *m0;
 1466                         m0 = m_devget(mtod(m, char *), total_len,
 1467                                 ETHER_ALIGN, ifp, NULL);
 1468                         sis_newbuf(sc, cur_rx, m);
 1469                         if (m0 == NULL) {
 1470                                 ifp->if_ierrors++;
 1471                                 continue;
 1472                         }
 1473                         m = m0;
 1474                 }
 1475 
 1476                 ifp->if_ipackets++;
 1477                 m->m_pkthdr.rcvif = ifp;
 1478 
 1479                 SIS_UNLOCK(sc);
 1480                 (*ifp->if_input)(ifp, m);
 1481                 SIS_LOCK(sc);
 1482         }
 1483 
 1484         sc->sis_rx_pdsc = cur_rx;
 1485 }
 1486 
 1487 static void
 1488 sis_rxeoc(struct sis_softc *sc)
 1489 {
 1490 
 1491         SIS_LOCK_ASSERT(sc);
 1492         sis_rxeof(sc);
 1493         sis_initl(sc);
 1494 }
 1495 
 1496 /*
 1497  * A frame was downloaded to the chip. It's safe for us to clean up
 1498  * the list buffers.
 1499  */
 1500 
 1501 static void
 1502 sis_txeof(struct sis_softc *sc)
 1503 {
 1504         struct ifnet            *ifp;
 1505         u_int32_t               idx;
 1506 
 1507         SIS_LOCK_ASSERT(sc);
 1508         ifp = sc->sis_ifp;
 1509 
 1510         /*
 1511          * Go through our tx list and free mbufs for those
 1512          * frames that have been transmitted.
 1513          */
 1514         for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0;
 1515             sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
 1516                 struct sis_desc *cur_tx = &sc->sis_tx_list[idx];
 1517 
 1518                 if (SIS_OWNDESC(cur_tx))
 1519                         break;
 1520 
 1521                 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
 1522                         continue;
 1523 
 1524                 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
 1525                         ifp->if_oerrors++;
 1526                         if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
 1527                                 ifp->if_collisions++;
 1528                         if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
 1529                                 ifp->if_collisions++;
 1530                 }
 1531 
 1532                 ifp->if_collisions +=
 1533                     (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
 1534 
 1535                 ifp->if_opackets++;
 1536                 if (cur_tx->sis_mbuf != NULL) {
 1537                         m_freem(cur_tx->sis_mbuf);
 1538                         cur_tx->sis_mbuf = NULL;
 1539                         bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
 1540                         bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
 1541                 }
 1542         }
 1543 
 1544         if (idx != sc->sis_tx_cons) {
 1545                 /* we freed up some buffers */
 1546                 sc->sis_tx_cons = idx;
 1547                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1548         }
 1549 
 1550         ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5;
 1551 
 1552         return;
 1553 }
 1554 
 1555 static void
 1556 sis_tick(void *xsc)
 1557 {
 1558         struct sis_softc        *sc;
 1559         struct mii_data         *mii;
 1560         struct ifnet            *ifp;
 1561 
 1562         sc = xsc;
 1563         SIS_LOCK_ASSERT(sc);
 1564         sc->in_tick = 1;
 1565         ifp = sc->sis_ifp;
 1566 
 1567         mii = device_get_softc(sc->sis_miibus);
 1568         mii_tick(mii);
 1569 
 1570         if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE &&
 1571             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 1572                 sc->sis_link++;
 1573                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1574                         sis_startl(ifp);
 1575         }
 1576 
 1577         callout_reset(&sc->sis_stat_ch, hz,  sis_tick, sc);
 1578         sc->in_tick = 0;
 1579 }
 1580 
 1581 #ifdef DEVICE_POLLING
 1582 static poll_handler_t sis_poll;
 1583 
 1584 static void
 1585 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
 1586 {
 1587         struct  sis_softc *sc = ifp->if_softc;
 1588 
 1589         SIS_LOCK(sc);
 1590         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
 1591                 SIS_UNLOCK(sc);
 1592                 return;
 1593         }
 1594 
 1595         /*
 1596          * On the sis, reading the status register also clears it.
 1597          * So before returning to intr mode we must make sure that all
 1598          * possible pending sources of interrupts have been served.
 1599          * In practice this means run to completion the *eof routines,
 1600          * and then call the interrupt routine
 1601          */
 1602         sc->rxcycles = count;
 1603         sis_rxeof(sc);
 1604         sis_txeof(sc);
 1605         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1606                 sis_startl(ifp);
 1607 
 1608         if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
 1609                 u_int32_t       status;
 1610 
 1611                 /* Reading the ISR register clears all interrupts. */
 1612                 status = CSR_READ_4(sc, SIS_ISR);
 1613 
 1614                 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
 1615                         sis_rxeoc(sc);
 1616 
 1617                 if (status & (SIS_ISR_RX_IDLE))
 1618                         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
 1619 
 1620                 if (status & SIS_ISR_SYSERR) {
 1621                         sis_reset(sc);
 1622                         sis_initl(sc);
 1623                 }
 1624         }
 1625 
 1626         SIS_UNLOCK(sc);
 1627 }
 1628 #endif /* DEVICE_POLLING */
 1629 
 1630 static void
 1631 sis_intr(void *arg)
 1632 {
 1633         struct sis_softc        *sc;
 1634         struct ifnet            *ifp;
 1635         u_int32_t               status;
 1636 
 1637         sc = arg;
 1638         ifp = sc->sis_ifp;
 1639 
 1640         if (sc->sis_stopped)    /* Most likely shared interrupt */
 1641                 return;
 1642 
 1643         SIS_LOCK(sc);
 1644 #ifdef DEVICE_POLLING
 1645         if (ifp->if_capenable & IFCAP_POLLING) {
 1646                 SIS_UNLOCK(sc);
 1647                 return;
 1648         }
 1649 #endif
 1650 
 1651         /* Disable interrupts. */
 1652         CSR_WRITE_4(sc, SIS_IER, 0);
 1653 
 1654         for (;;) {
 1655                 SIS_LOCK_ASSERT(sc);
 1656                 /* Reading the ISR register clears all interrupts. */
 1657                 status = CSR_READ_4(sc, SIS_ISR);
 1658 
 1659                 if ((status & SIS_INTRS) == 0)
 1660                         break;
 1661 
 1662                 if (status &
 1663                     (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
 1664                      SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
 1665                         sis_txeof(sc);
 1666 
 1667                 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE))
 1668                         sis_rxeof(sc);
 1669 
 1670                 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
 1671                         sis_rxeoc(sc);
 1672 
 1673                 if (status & (SIS_ISR_RX_IDLE))
 1674                         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
 1675 
 1676                 if (status & SIS_ISR_SYSERR) {
 1677                         sis_reset(sc);
 1678                         sis_initl(sc);
 1679                 }
 1680         }
 1681 
 1682         /* Re-enable interrupts. */
 1683         CSR_WRITE_4(sc, SIS_IER, 1);
 1684 
 1685         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1686                 sis_startl(ifp);
 1687 
 1688         SIS_UNLOCK(sc);
 1689 }
 1690 
 1691 /*
 1692  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1693  * pointers to the fragment pointers.
 1694  */
 1695 static int
 1696 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx)
 1697 {
 1698         struct sis_desc         *f = NULL;
 1699         struct mbuf             *m;
 1700         int                     frag, cur, cnt = 0, chainlen = 0;
 1701 
 1702         /*
 1703          * If there's no way we can send any packets, return now.
 1704          */
 1705         if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2)
 1706                 return (ENOBUFS);
 1707 
 1708         /*
 1709          * Count the number of frags in this chain to see if
 1710          * we need to m_defrag.  Since the descriptor list is shared
 1711          * by all packets, we'll m_defrag long chains so that they
 1712          * do not use up the entire list, even if they would fit.
 1713          */
 1714 
 1715         for (m = *m_head; m != NULL; m = m->m_next)
 1716                 chainlen++;
 1717 
 1718         if ((chainlen > SIS_TX_LIST_CNT / 4) ||
 1719             ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) {
 1720                 m = m_defrag(*m_head, M_DONTWAIT);
 1721                 if (m == NULL)
 1722                         return (ENOBUFS);
 1723                 *m_head = m;
 1724         }
 1725         
 1726         /*
 1727          * Start packing the mbufs in this chain into
 1728          * the fragment pointers. Stop when we run out
 1729          * of fragments or hit the end of the mbuf chain.
 1730          */
 1731         cur = frag = *txidx;
 1732 
 1733         for (m = *m_head; m != NULL; m = m->m_next) {
 1734                 if (m->m_len != 0) {
 1735                         if ((SIS_TX_LIST_CNT -
 1736                             (sc->sis_tx_cnt + cnt)) < 2)
 1737                                 return(ENOBUFS);
 1738                         f = &sc->sis_tx_list[frag];
 1739                         f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
 1740                         bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
 1741                         bus_dmamap_load(sc->sis_tag, f->sis_map,
 1742                             mtod(m, void *), m->m_len,
 1743                             sis_dma_map_desc_ptr, f, 0);
 1744                         bus_dmamap_sync(sc->sis_tag,
 1745                             f->sis_map, BUS_DMASYNC_PREREAD);
 1746                         if (cnt != 0)
 1747                                 f->sis_ctl |= SIS_CMDSTS_OWN;
 1748                         cur = frag;
 1749                         SIS_INC(frag, SIS_TX_LIST_CNT);
 1750                         cnt++;
 1751                 }
 1752         }
 1753 
 1754         if (m != NULL)
 1755                 return(ENOBUFS);
 1756 
 1757         sc->sis_tx_list[cur].sis_mbuf = *m_head;
 1758         sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
 1759         sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
 1760         sc->sis_tx_cnt += cnt;
 1761         *txidx = frag;
 1762 
 1763         return(0);
 1764 }
 1765 
 1766 /*
 1767  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 1768  * to the mbuf data regions directly in the transmit lists. We also save a
 1769  * copy of the pointers since the transmit list fragment pointers are
 1770  * physical addresses.
 1771  */
 1772 
 1773 static void
 1774 sis_start(struct ifnet *ifp)
 1775 {
 1776         struct sis_softc        *sc;
 1777 
 1778         sc = ifp->if_softc;
 1779         SIS_LOCK(sc);
 1780         sis_startl(ifp);
 1781         SIS_UNLOCK(sc);
 1782 }
 1783 
 1784 static void
 1785 sis_startl(struct ifnet *ifp)
 1786 {
 1787         struct sis_softc        *sc;
 1788         struct mbuf             *m_head = NULL;
 1789         u_int32_t               idx, queued = 0;
 1790 
 1791         sc = ifp->if_softc;
 1792 
 1793         SIS_LOCK_ASSERT(sc);
 1794 
 1795         if (!sc->sis_link)
 1796                 return;
 1797 
 1798         idx = sc->sis_tx_prod;
 1799 
 1800         if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
 1801                 return;
 1802 
 1803         while(sc->sis_tx_list[idx].sis_mbuf == NULL) {
 1804                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
 1805                 if (m_head == NULL)
 1806                         break;
 1807 
 1808                 if (sis_encap(sc, &m_head, &idx)) {
 1809                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
 1810                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 1811                         break;
 1812                 }
 1813 
 1814                 queued++;
 1815 
 1816                 /*
 1817                  * If there's a BPF listener, bounce a copy of this frame
 1818                  * to him.
 1819                  */
 1820                 BPF_MTAP(ifp, m_head);
 1821 
 1822         }
 1823 
 1824         if (queued) {
 1825                 /* Transmit */
 1826                 sc->sis_tx_prod = idx;
 1827                 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
 1828 
 1829                 /*
 1830                  * Set a timeout in case the chip goes out to lunch.
 1831                  */
 1832                 ifp->if_timer = 5;
 1833         }
 1834 }
 1835 
 1836 static void
 1837 sis_init(void *xsc)
 1838 {
 1839         struct sis_softc        *sc = xsc;
 1840 
 1841         SIS_LOCK(sc);
 1842         sis_initl(sc);
 1843         SIS_UNLOCK(sc);
 1844 }
 1845 
 1846 static void
 1847 sis_initl(struct sis_softc *sc)
 1848 {
 1849         struct ifnet            *ifp = sc->sis_ifp;
 1850         struct mii_data         *mii;
 1851 
 1852         SIS_LOCK_ASSERT(sc);
 1853 
 1854         /*
 1855          * Cancel pending I/O and free all RX/TX buffers.
 1856          */
 1857         sis_stop(sc);
 1858         sc->sis_stopped = 0;
 1859 
 1860 #ifdef notyet
 1861         if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
 1862                 /*
 1863                  * Configure 400usec of interrupt holdoff.  This is based
 1864                  * on emperical tests on a Soekris 4801.
 1865                  */
 1866                 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
 1867         }
 1868 #endif
 1869 
 1870         mii = device_get_softc(sc->sis_miibus);
 1871 
 1872         /* Set MAC address */
 1873         if (sc->sis_type == SIS_TYPE_83815) {
 1874                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
 1875                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 1876                     ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[0]);
 1877                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
 1878                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 1879                     ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[1]);
 1880                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
 1881                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 1882                     ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[2]);
 1883         } else {
 1884                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
 1885                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 1886                     ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[0]);
 1887                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
 1888                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 1889                     ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[1]);
 1890                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
 1891                 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
 1892                     ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[2]);
 1893         }
 1894 
 1895         /* Init circular TX/RX lists. */
 1896         if (sis_ring_init(sc) != 0) {
 1897                 if_printf(ifp,
 1898                     "initialization failed: no memory for rx buffers\n");
 1899                 sis_stop(sc);
 1900                 return;
 1901         }
 1902 
 1903         /*
 1904          * Short Cable Receive Errors (MP21.E)
 1905          * also: Page 78 of the DP83815 data sheet (september 2002 version)
 1906          * recommends the following register settings "for optimum
 1907          * performance." for rev 15C.  The driver from NS also sets
 1908          * the PHY_CR register for later versions.
 1909          */
 1910         if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
 1911                 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
 1912                 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
 1913                 if (sc->sis_srr == NS_SRR_15C) {
 1914                         /* set val for c2 */
 1915                         CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
 1916                         /* load/kill c2 */
 1917                         CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
 1918                         /* rais SD off, from 4 to c */
 1919                         CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
 1920                 }
 1921                 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
 1922         }
 1923 
 1924 
 1925         /*
 1926          * For the NatSemi chip, we have to explicitly enable the
 1927          * reception of ARP frames, as well as turn on the 'perfect
 1928          * match' filter where we store the station address, otherwise
 1929          * we won't receive unicasts meant for this host.
 1930          */
 1931         if (sc->sis_type == SIS_TYPE_83815) {
 1932                 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
 1933                 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
 1934         }
 1935 
 1936          /* If we want promiscuous mode, set the allframes bit. */
 1937         if (ifp->if_flags & IFF_PROMISC) {
 1938                 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
 1939         } else {
 1940                 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
 1941         }
 1942 
 1943         /*
 1944          * Set the capture broadcast bit to capture broadcast frames.
 1945          */
 1946         if (ifp->if_flags & IFF_BROADCAST) {
 1947                 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
 1948         } else {
 1949                 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
 1950         }
 1951 
 1952         /*
 1953          * Load the multicast filter.
 1954          */
 1955         if (sc->sis_type == SIS_TYPE_83815)
 1956                 sis_setmulti_ns(sc);
 1957         else
 1958                 sis_setmulti_sis(sc);
 1959 
 1960         /* Turn the receive filter on */
 1961         SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
 1962 
 1963         /*
 1964          * Load the address of the RX and TX lists.
 1965          */
 1966         CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr);
 1967         CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr);
 1968 
 1969         /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
 1970          * the PCI bus. When this bit is set, the Max DMA Burst Size
 1971          * for TX/RX DMA should be no larger than 16 double words.
 1972          */
 1973         if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
 1974                 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
 1975         } else {
 1976                 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
 1977         }
 1978 
 1979         /* Accept Long Packets for VLAN support */
 1980         SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
 1981 
 1982         /* Set TX configuration */
 1983         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
 1984                 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
 1985         } else {
 1986                 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
 1987         }
 1988 
 1989         /* Set full/half duplex mode. */
 1990         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 1991                 SIS_SETBIT(sc, SIS_TX_CFG,
 1992                     (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
 1993                 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
 1994         } else {
 1995                 SIS_CLRBIT(sc, SIS_TX_CFG,
 1996                     (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
 1997                 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
 1998         }
 1999 
 2000         if (sc->sis_type == SIS_TYPE_83816) {
 2001                 /*
 2002                  * MPII03.D: Half Duplex Excessive Collisions.
 2003                  * Also page 49 in 83816 manual
 2004                  */
 2005                 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
 2006         }
 2007 
 2008         if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
 2009              IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
 2010                 uint32_t reg;
 2011 
 2012                 /*
 2013                  * Short Cable Receive Errors (MP21.E) 
 2014                  */
 2015                 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
 2016                 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
 2017                 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
 2018                 DELAY(100000);
 2019                 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
 2020                 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
 2021                         device_printf(sc->sis_self,
 2022                             "Applying short cable fix (reg=%x)\n", reg);
 2023                         CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
 2024                         reg = CSR_READ_4(sc, NS_PHY_DSPCFG);
 2025                         SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20);
 2026                 }
 2027                 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
 2028         }
 2029 
 2030         /*
 2031          * Enable interrupts.
 2032          */
 2033         CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
 2034 #ifdef DEVICE_POLLING
 2035         /*
 2036          * ... only enable interrupts if we are not polling, make sure
 2037          * they are off otherwise.
 2038          */
 2039         if (ifp->if_capenable & IFCAP_POLLING)
 2040                 CSR_WRITE_4(sc, SIS_IER, 0);
 2041         else
 2042 #endif
 2043         CSR_WRITE_4(sc, SIS_IER, 1);
 2044 
 2045         /* Enable receiver and transmitter. */
 2046         SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
 2047         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
 2048 
 2049 #ifdef notdef
 2050         mii_mediachg(mii);
 2051 #endif
 2052 
 2053         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 2054         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 2055 
 2056         if (!sc->in_tick)
 2057                 callout_reset(&sc->sis_stat_ch, hz,  sis_tick, sc);
 2058 }
 2059 
 2060 /*
 2061  * Set media options.
 2062  */
 2063 static int
 2064 sis_ifmedia_upd(struct ifnet *ifp)
 2065 {
 2066         struct sis_softc        *sc;
 2067         struct mii_data         *mii;
 2068 
 2069         sc = ifp->if_softc;
 2070 
 2071         SIS_LOCK(sc);
 2072         mii = device_get_softc(sc->sis_miibus);
 2073         sc->sis_link = 0;
 2074         if (mii->mii_instance) {
 2075                 struct mii_softc        *miisc;
 2076                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 2077                         mii_phy_reset(miisc);
 2078         }
 2079         mii_mediachg(mii);
 2080         SIS_UNLOCK(sc);
 2081 
 2082         return(0);
 2083 }
 2084 
 2085 /*
 2086  * Report current media status.
 2087  */
 2088 static void
 2089 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 2090 {
 2091         struct sis_softc        *sc;
 2092         struct mii_data         *mii;
 2093 
 2094         sc = ifp->if_softc;
 2095 
 2096         SIS_LOCK(sc);
 2097         mii = device_get_softc(sc->sis_miibus);
 2098         mii_pollstat(mii);
 2099         SIS_UNLOCK(sc);
 2100         ifmr->ifm_active = mii->mii_media_active;
 2101         ifmr->ifm_status = mii->mii_media_status;
 2102 }
 2103 
 2104 static int
 2105 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 2106 {
 2107         struct sis_softc        *sc = ifp->if_softc;
 2108         struct ifreq            *ifr = (struct ifreq *) data;
 2109         struct mii_data         *mii;
 2110         int                     error = 0;
 2111 
 2112         switch(command) {
 2113         case SIOCSIFFLAGS:
 2114                 SIS_LOCK(sc);
 2115                 if (ifp->if_flags & IFF_UP) {
 2116                         sis_initl(sc);
 2117                 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 2118                         sis_stop(sc);
 2119                 }
 2120                 SIS_UNLOCK(sc);
 2121                 error = 0;
 2122                 break;
 2123         case SIOCADDMULTI:
 2124         case SIOCDELMULTI:
 2125                 SIS_LOCK(sc);
 2126                 if (sc->sis_type == SIS_TYPE_83815)
 2127                         sis_setmulti_ns(sc);
 2128                 else
 2129                         sis_setmulti_sis(sc);
 2130                 SIS_UNLOCK(sc);
 2131                 error = 0;
 2132                 break;
 2133         case SIOCGIFMEDIA:
 2134         case SIOCSIFMEDIA:
 2135                 mii = device_get_softc(sc->sis_miibus);
 2136                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 2137                 break;
 2138         case SIOCSIFCAP:
 2139                 /* ok, disable interrupts */
 2140 #ifdef DEVICE_POLLING
 2141                 if (ifr->ifr_reqcap & IFCAP_POLLING &&
 2142                     !(ifp->if_capenable & IFCAP_POLLING)) {
 2143                         error = ether_poll_register(sis_poll, ifp);
 2144                         if (error)
 2145                                 return(error);
 2146                         SIS_LOCK(sc);
 2147                         /* Disable interrupts */
 2148                         CSR_WRITE_4(sc, SIS_IER, 0);
 2149                         ifp->if_capenable |= IFCAP_POLLING;
 2150                         SIS_UNLOCK(sc);
 2151                         return (error);
 2152                         
 2153                 }
 2154                 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
 2155                     ifp->if_capenable & IFCAP_POLLING) {
 2156                         error = ether_poll_deregister(ifp);
 2157                         /* Enable interrupts. */
 2158                         SIS_LOCK(sc);
 2159                         CSR_WRITE_4(sc, SIS_IER, 1);
 2160                         ifp->if_capenable &= ~IFCAP_POLLING;
 2161                         SIS_UNLOCK(sc);
 2162                         return (error);
 2163                 }
 2164 #endif /* DEVICE_POLLING */
 2165                 break;
 2166         default:
 2167                 error = ether_ioctl(ifp, command, data);
 2168                 break;
 2169         }
 2170 
 2171         return(error);
 2172 }
 2173 
 2174 static void
 2175 sis_watchdog(struct ifnet *ifp)
 2176 {
 2177         struct sis_softc *sc;
 2178 
 2179         sc = ifp->if_softc;
 2180 
 2181         SIS_LOCK(sc);
 2182         if (sc->sis_stopped) {
 2183                 SIS_UNLOCK(sc);
 2184                 return;
 2185         }
 2186 
 2187         ifp->if_oerrors++;
 2188         if_printf(ifp, "watchdog timeout\n");
 2189 
 2190         sis_stop(sc);
 2191         sis_reset(sc);
 2192         sis_initl(sc);
 2193 
 2194         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 2195                 sis_startl(ifp);
 2196 
 2197         SIS_UNLOCK(sc);
 2198 }
 2199 
 2200 /*
 2201  * Stop the adapter and free any mbufs allocated to the
 2202  * RX and TX lists.
 2203  */
 2204 static void
 2205 sis_stop(struct sis_softc *sc)
 2206 {
 2207         int i;
 2208         struct ifnet *ifp;
 2209         struct sis_desc *dp;
 2210 
 2211         if (sc->sis_stopped)
 2212                 return;
 2213         SIS_LOCK_ASSERT(sc);
 2214         ifp = sc->sis_ifp;
 2215         ifp->if_timer = 0;
 2216 
 2217         callout_stop(&sc->sis_stat_ch);
 2218 
 2219         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 2220         CSR_WRITE_4(sc, SIS_IER, 0);
 2221         CSR_WRITE_4(sc, SIS_IMR, 0);
 2222         CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
 2223         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
 2224         DELAY(1000);
 2225         CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
 2226         CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
 2227 
 2228         sc->sis_link = 0;
 2229 
 2230         /*
 2231          * Free data in the RX lists.
 2232          */
 2233         dp = &sc->sis_rx_list[0];
 2234         for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) {
 2235                 if (dp->sis_mbuf == NULL)
 2236                         continue;
 2237                 bus_dmamap_unload(sc->sis_tag, dp->sis_map);
 2238                 bus_dmamap_destroy(sc->sis_tag, dp->sis_map);
 2239                 m_freem(dp->sis_mbuf);
 2240                 dp->sis_mbuf = NULL;
 2241         }
 2242         bzero(sc->sis_rx_list, SIS_RX_LIST_SZ);
 2243 
 2244         /*
 2245          * Free the TX list buffers.
 2246          */
 2247         dp = &sc->sis_tx_list[0];
 2248         for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) {
 2249                 if (dp->sis_mbuf == NULL)
 2250                         continue;
 2251                 bus_dmamap_unload(sc->sis_tag, dp->sis_map);
 2252                 bus_dmamap_destroy(sc->sis_tag, dp->sis_map);
 2253                 m_freem(dp->sis_mbuf);
 2254                 dp->sis_mbuf = NULL;
 2255         }
 2256 
 2257         bzero(sc->sis_tx_list, SIS_TX_LIST_SZ);
 2258 
 2259         sc->sis_stopped = 1;
 2260 }
 2261 
 2262 /*
 2263  * Stop all chip I/O so that the kernel's probe routines don't
 2264  * get confused by errant DMAs when rebooting.
 2265  */
 2266 static void
 2267 sis_shutdown(device_t dev)
 2268 {
 2269         struct sis_softc        *sc;
 2270 
 2271         sc = device_get_softc(dev);
 2272         SIS_LOCK(sc);
 2273         sis_reset(sc);
 2274         sis_stop(sc);
 2275         SIS_UNLOCK(sc);
 2276 }
 2277 
 2278 static device_method_t sis_methods[] = {
 2279         /* Device interface */
 2280         DEVMETHOD(device_probe,         sis_probe),
 2281         DEVMETHOD(device_attach,        sis_attach),
 2282         DEVMETHOD(device_detach,        sis_detach),
 2283         DEVMETHOD(device_shutdown,      sis_shutdown),
 2284 
 2285         /* bus interface */
 2286         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 2287         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 2288 
 2289         /* MII interface */
 2290         DEVMETHOD(miibus_readreg,       sis_miibus_readreg),
 2291         DEVMETHOD(miibus_writereg,      sis_miibus_writereg),
 2292         DEVMETHOD(miibus_statchg,       sis_miibus_statchg),
 2293 
 2294         { 0, 0 }
 2295 };
 2296 
 2297 static driver_t sis_driver = {
 2298         "sis",
 2299         sis_methods,
 2300         sizeof(struct sis_softc)
 2301 };
 2302 
 2303 static devclass_t sis_devclass;
 2304 
 2305 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
 2306 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);

Cache object: 542338ed3609210c9dc48a2fd8b98014


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.