FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sis.c
1 /*-
2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
3 * Copyright (c) 1997, 1998, 1999
4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/6.2/sys/pci/if_sis.c 156820 2006-03-17 21:30:57Z glebius $");
36
37 /*
38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
39 * available from http://www.sis.com.tw.
40 *
41 * This driver also supports the NatSemi DP83815. Datasheets are
42 * available from http://www.national.com.
43 *
44 * Written by Bill Paul <wpaul@ee.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
47 */
48 /*
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
56 *
57 * The only downside to this chipset is that RX descriptors must be
58 * longword aligned.
59 */
60
61 #ifdef HAVE_KERNEL_OPTION_HEADERS
62 #include "opt_device_polling.h"
63 #endif
64
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/sockio.h>
68 #include <sys/mbuf.h>
69 #include <sys/malloc.h>
70 #include <sys/kernel.h>
71 #include <sys/module.h>
72 #include <sys/socket.h>
73 #include <sys/sysctl.h>
74
75 #include <net/if.h>
76 #include <net/if_arp.h>
77 #include <net/ethernet.h>
78 #include <net/if_dl.h>
79 #include <net/if_media.h>
80 #include <net/if_types.h>
81 #include <net/if_vlan_var.h>
82
83 #include <net/bpf.h>
84
85 #include <machine/bus.h>
86 #include <machine/resource.h>
87 #include <sys/bus.h>
88 #include <sys/rman.h>
89
90 #include <dev/mii/mii.h>
91 #include <dev/mii/miivar.h>
92
93 #include <dev/pci/pcireg.h>
94 #include <dev/pci/pcivar.h>
95
96 #define SIS_USEIOSPACE
97
98 #include <pci/if_sisreg.h>
99
100 MODULE_DEPEND(sis, pci, 1, 1, 1);
101 MODULE_DEPEND(sis, ether, 1, 1, 1);
102 MODULE_DEPEND(sis, miibus, 1, 1, 1);
103
104 /* "controller miibus0" required. See GENERIC if you get errors here. */
105 #include "miibus_if.h"
106
107 /*
108 * Various supported device vendors/types and their names.
109 */
110 static struct sis_type sis_devs[] = {
111 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
112 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
113 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
114 { 0, 0, NULL }
115 };
116
117 static int sis_detach(device_t);
118 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
119 static int sis_ifmedia_upd(struct ifnet *);
120 static void sis_init(void *);
121 static void sis_initl(struct sis_softc *);
122 static void sis_intr(void *);
123 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
124 static int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *);
125 static void sis_start(struct ifnet *);
126 static void sis_startl(struct ifnet *);
127 static void sis_stop(struct sis_softc *);
128 static void sis_watchdog(struct ifnet *);
129
130 #ifdef SIS_USEIOSPACE
131 #define SIS_RES SYS_RES_IOPORT
132 #define SIS_RID SIS_PCI_LOIO
133 #else
134 #define SIS_RES SYS_RES_MEMORY
135 #define SIS_RID SIS_PCI_LOMEM
136 #endif
137
138 #define SIS_SETBIT(sc, reg, x) \
139 CSR_WRITE_4(sc, reg, \
140 CSR_READ_4(sc, reg) | (x))
141
142 #define SIS_CLRBIT(sc, reg, x) \
143 CSR_WRITE_4(sc, reg, \
144 CSR_READ_4(sc, reg) & ~(x))
145
146 #define SIO_SET(x) \
147 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
148
149 #define SIO_CLR(x) \
150 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
151
152 static void
153 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
154 {
155 struct sis_desc *r;
156
157 r = arg;
158 r->sis_next = segs->ds_addr;
159 }
160
161 static void
162 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
163 {
164 struct sis_desc *r;
165
166 r = arg;
167 r->sis_ptr = segs->ds_addr;
168 }
169
170 static void
171 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
172 {
173 u_int32_t *p;
174
175 p = arg;
176 *p = segs->ds_addr;
177 }
178
179 /*
180 * Routine to reverse the bits in a word. Stolen almost
181 * verbatim from /usr/games/fortune.
182 */
183 static uint16_t
184 sis_reverse(uint16_t n)
185 {
186 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
187 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
188 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
189 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
190
191 return(n);
192 }
193
194 static void
195 sis_delay(struct sis_softc *sc)
196 {
197 int idx;
198
199 for (idx = (300 / 33) + 1; idx > 0; idx--)
200 CSR_READ_4(sc, SIS_CSR);
201 }
202
203 static void
204 sis_eeprom_idle(struct sis_softc *sc)
205 {
206 int i;
207
208 SIO_SET(SIS_EECTL_CSEL);
209 sis_delay(sc);
210 SIO_SET(SIS_EECTL_CLK);
211 sis_delay(sc);
212
213 for (i = 0; i < 25; i++) {
214 SIO_CLR(SIS_EECTL_CLK);
215 sis_delay(sc);
216 SIO_SET(SIS_EECTL_CLK);
217 sis_delay(sc);
218 }
219
220 SIO_CLR(SIS_EECTL_CLK);
221 sis_delay(sc);
222 SIO_CLR(SIS_EECTL_CSEL);
223 sis_delay(sc);
224 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
225 }
226
227 /*
228 * Send a read command and address to the EEPROM, check for ACK.
229 */
230 static void
231 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
232 {
233 int d, i;
234
235 d = addr | SIS_EECMD_READ;
236
237 /*
238 * Feed in each bit and stobe the clock.
239 */
240 for (i = 0x400; i; i >>= 1) {
241 if (d & i) {
242 SIO_SET(SIS_EECTL_DIN);
243 } else {
244 SIO_CLR(SIS_EECTL_DIN);
245 }
246 sis_delay(sc);
247 SIO_SET(SIS_EECTL_CLK);
248 sis_delay(sc);
249 SIO_CLR(SIS_EECTL_CLK);
250 sis_delay(sc);
251 }
252 }
253
254 /*
255 * Read a word of data stored in the EEPROM at address 'addr.'
256 */
257 static void
258 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
259 {
260 int i;
261 u_int16_t word = 0;
262
263 /* Force EEPROM to idle state. */
264 sis_eeprom_idle(sc);
265
266 /* Enter EEPROM access mode. */
267 sis_delay(sc);
268 SIO_CLR(SIS_EECTL_CLK);
269 sis_delay(sc);
270 SIO_SET(SIS_EECTL_CSEL);
271 sis_delay(sc);
272
273 /*
274 * Send address of word we want to read.
275 */
276 sis_eeprom_putbyte(sc, addr);
277
278 /*
279 * Start reading bits from EEPROM.
280 */
281 for (i = 0x8000; i; i >>= 1) {
282 SIO_SET(SIS_EECTL_CLK);
283 sis_delay(sc);
284 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
285 word |= i;
286 sis_delay(sc);
287 SIO_CLR(SIS_EECTL_CLK);
288 sis_delay(sc);
289 }
290
291 /* Turn off EEPROM access mode. */
292 sis_eeprom_idle(sc);
293
294 *dest = word;
295 }
296
297 /*
298 * Read a sequence of words from the EEPROM.
299 */
300 static void
301 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
302 {
303 int i;
304 u_int16_t word = 0, *ptr;
305
306 for (i = 0; i < cnt; i++) {
307 sis_eeprom_getword(sc, off + i, &word);
308 ptr = (u_int16_t *)(dest + (i * 2));
309 if (swap)
310 *ptr = ntohs(word);
311 else
312 *ptr = word;
313 }
314 }
315
316 #if defined(__i386__) || defined(__amd64__)
317 static device_t
318 sis_find_bridge(device_t dev)
319 {
320 devclass_t pci_devclass;
321 device_t *pci_devices;
322 int pci_count = 0;
323 device_t *pci_children;
324 int pci_childcount = 0;
325 device_t *busp, *childp;
326 device_t child = NULL;
327 int i, j;
328
329 if ((pci_devclass = devclass_find("pci")) == NULL)
330 return(NULL);
331
332 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
333
334 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
335 pci_childcount = 0;
336 device_get_children(*busp, &pci_children, &pci_childcount);
337 for (j = 0, childp = pci_children;
338 j < pci_childcount; j++, childp++) {
339 if (pci_get_vendor(*childp) == SIS_VENDORID &&
340 pci_get_device(*childp) == 0x0008) {
341 child = *childp;
342 goto done;
343 }
344 }
345 }
346
347 done:
348 free(pci_devices, M_TEMP);
349 free(pci_children, M_TEMP);
350 return(child);
351 }
352
353 static void
354 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
355 {
356 device_t bridge;
357 u_int8_t reg;
358 int i;
359 bus_space_tag_t btag;
360
361 bridge = sis_find_bridge(dev);
362 if (bridge == NULL)
363 return;
364 reg = pci_read_config(bridge, 0x48, 1);
365 pci_write_config(bridge, 0x48, reg|0x40, 1);
366
367 /* XXX */
368 #if defined(__i386__)
369 btag = I386_BUS_SPACE_IO;
370 #elif defined(__amd64__)
371 btag = AMD64_BUS_SPACE_IO;
372 #endif
373
374 for (i = 0; i < cnt; i++) {
375 bus_space_write_1(btag, 0x0, 0x70, i + off);
376 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
377 }
378
379 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
380 return;
381 }
382
383 static void
384 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
385 {
386 u_int32_t filtsave, csrsave;
387
388 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
389 csrsave = CSR_READ_4(sc, SIS_CSR);
390
391 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
392 CSR_WRITE_4(sc, SIS_CSR, 0);
393
394 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
395
396 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
397 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
398 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
399 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
400 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
401 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
402
403 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
404 CSR_WRITE_4(sc, SIS_CSR, csrsave);
405 return;
406 }
407 #endif
408
409 /*
410 * Sync the PHYs by setting data bit and strobing the clock 32 times.
411 */
412 static void
413 sis_mii_sync(struct sis_softc *sc)
414 {
415 int i;
416
417 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
418
419 for (i = 0; i < 32; i++) {
420 SIO_SET(SIS_MII_CLK);
421 DELAY(1);
422 SIO_CLR(SIS_MII_CLK);
423 DELAY(1);
424 }
425 }
426
427 /*
428 * Clock a series of bits through the MII.
429 */
430 static void
431 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
432 {
433 int i;
434
435 SIO_CLR(SIS_MII_CLK);
436
437 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
438 if (bits & i) {
439 SIO_SET(SIS_MII_DATA);
440 } else {
441 SIO_CLR(SIS_MII_DATA);
442 }
443 DELAY(1);
444 SIO_CLR(SIS_MII_CLK);
445 DELAY(1);
446 SIO_SET(SIS_MII_CLK);
447 }
448 }
449
450 /*
451 * Read an PHY register through the MII.
452 */
453 static int
454 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
455 {
456 int i, ack;
457
458 /*
459 * Set up frame for RX.
460 */
461 frame->mii_stdelim = SIS_MII_STARTDELIM;
462 frame->mii_opcode = SIS_MII_READOP;
463 frame->mii_turnaround = 0;
464 frame->mii_data = 0;
465
466 /*
467 * Turn on data xmit.
468 */
469 SIO_SET(SIS_MII_DIR);
470
471 sis_mii_sync(sc);
472
473 /*
474 * Send command/address info.
475 */
476 sis_mii_send(sc, frame->mii_stdelim, 2);
477 sis_mii_send(sc, frame->mii_opcode, 2);
478 sis_mii_send(sc, frame->mii_phyaddr, 5);
479 sis_mii_send(sc, frame->mii_regaddr, 5);
480
481 /* Idle bit */
482 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
483 DELAY(1);
484 SIO_SET(SIS_MII_CLK);
485 DELAY(1);
486
487 /* Turn off xmit. */
488 SIO_CLR(SIS_MII_DIR);
489
490 /* Check for ack */
491 SIO_CLR(SIS_MII_CLK);
492 DELAY(1);
493 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
494 SIO_SET(SIS_MII_CLK);
495 DELAY(1);
496
497 /*
498 * Now try reading data bits. If the ack failed, we still
499 * need to clock through 16 cycles to keep the PHY(s) in sync.
500 */
501 if (ack) {
502 for(i = 0; i < 16; i++) {
503 SIO_CLR(SIS_MII_CLK);
504 DELAY(1);
505 SIO_SET(SIS_MII_CLK);
506 DELAY(1);
507 }
508 goto fail;
509 }
510
511 for (i = 0x8000; i; i >>= 1) {
512 SIO_CLR(SIS_MII_CLK);
513 DELAY(1);
514 if (!ack) {
515 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
516 frame->mii_data |= i;
517 DELAY(1);
518 }
519 SIO_SET(SIS_MII_CLK);
520 DELAY(1);
521 }
522
523 fail:
524
525 SIO_CLR(SIS_MII_CLK);
526 DELAY(1);
527 SIO_SET(SIS_MII_CLK);
528 DELAY(1);
529
530 if (ack)
531 return(1);
532 return(0);
533 }
534
535 /*
536 * Write to a PHY register through the MII.
537 */
538 static int
539 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
540 {
541
542 /*
543 * Set up frame for TX.
544 */
545
546 frame->mii_stdelim = SIS_MII_STARTDELIM;
547 frame->mii_opcode = SIS_MII_WRITEOP;
548 frame->mii_turnaround = SIS_MII_TURNAROUND;
549
550 /*
551 * Turn on data output.
552 */
553 SIO_SET(SIS_MII_DIR);
554
555 sis_mii_sync(sc);
556
557 sis_mii_send(sc, frame->mii_stdelim, 2);
558 sis_mii_send(sc, frame->mii_opcode, 2);
559 sis_mii_send(sc, frame->mii_phyaddr, 5);
560 sis_mii_send(sc, frame->mii_regaddr, 5);
561 sis_mii_send(sc, frame->mii_turnaround, 2);
562 sis_mii_send(sc, frame->mii_data, 16);
563
564 /* Idle bit. */
565 SIO_SET(SIS_MII_CLK);
566 DELAY(1);
567 SIO_CLR(SIS_MII_CLK);
568 DELAY(1);
569
570 /*
571 * Turn off xmit.
572 */
573 SIO_CLR(SIS_MII_DIR);
574
575 return(0);
576 }
577
578 static int
579 sis_miibus_readreg(device_t dev, int phy, int reg)
580 {
581 struct sis_softc *sc;
582 struct sis_mii_frame frame;
583
584 sc = device_get_softc(dev);
585
586 if (sc->sis_type == SIS_TYPE_83815) {
587 if (phy != 0)
588 return(0);
589 /*
590 * The NatSemi chip can take a while after
591 * a reset to come ready, during which the BMSR
592 * returns a value of 0. This is *never* supposed
593 * to happen: some of the BMSR bits are meant to
594 * be hardwired in the on position, and this can
595 * confuse the miibus code a bit during the probe
596 * and attach phase. So we make an effort to check
597 * for this condition and wait for it to clear.
598 */
599 if (!CSR_READ_4(sc, NS_BMSR))
600 DELAY(1000);
601 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
602 }
603
604 /*
605 * Chipsets < SIS_635 seem not to be able to read/write
606 * through mdio. Use the enhanced PHY access register
607 * again for them.
608 */
609 if (sc->sis_type == SIS_TYPE_900 &&
610 sc->sis_rev < SIS_REV_635) {
611 int i, val = 0;
612
613 if (phy != 0)
614 return(0);
615
616 CSR_WRITE_4(sc, SIS_PHYCTL,
617 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
618 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
619
620 for (i = 0; i < SIS_TIMEOUT; i++) {
621 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
622 break;
623 }
624
625 if (i == SIS_TIMEOUT) {
626 if_printf(sc->sis_ifp, "PHY failed to come ready\n");
627 return(0);
628 }
629
630 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
631
632 if (val == 0xFFFF)
633 return(0);
634
635 return(val);
636 } else {
637 bzero((char *)&frame, sizeof(frame));
638
639 frame.mii_phyaddr = phy;
640 frame.mii_regaddr = reg;
641 sis_mii_readreg(sc, &frame);
642
643 return(frame.mii_data);
644 }
645 }
646
647 static int
648 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
649 {
650 struct sis_softc *sc;
651 struct sis_mii_frame frame;
652
653 sc = device_get_softc(dev);
654
655 if (sc->sis_type == SIS_TYPE_83815) {
656 if (phy != 0)
657 return(0);
658 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
659 return(0);
660 }
661
662 /*
663 * Chipsets < SIS_635 seem not to be able to read/write
664 * through mdio. Use the enhanced PHY access register
665 * again for them.
666 */
667 if (sc->sis_type == SIS_TYPE_900 &&
668 sc->sis_rev < SIS_REV_635) {
669 int i;
670
671 if (phy != 0)
672 return(0);
673
674 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
675 (reg << 6) | SIS_PHYOP_WRITE);
676 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
677
678 for (i = 0; i < SIS_TIMEOUT; i++) {
679 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
680 break;
681 }
682
683 if (i == SIS_TIMEOUT)
684 if_printf(sc->sis_ifp, "PHY failed to come ready\n");
685 } else {
686 bzero((char *)&frame, sizeof(frame));
687
688 frame.mii_phyaddr = phy;
689 frame.mii_regaddr = reg;
690 frame.mii_data = data;
691 sis_mii_writereg(sc, &frame);
692 }
693 return(0);
694 }
695
696 static void
697 sis_miibus_statchg(device_t dev)
698 {
699 struct sis_softc *sc;
700
701 sc = device_get_softc(dev);
702 SIS_LOCK_ASSERT(sc);
703 sis_initl(sc);
704 }
705
706 static uint32_t
707 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
708 {
709 uint32_t crc;
710
711 /* Compute CRC for the address value. */
712 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
713
714 /*
715 * return the filter bit position
716 *
717 * The NatSemi chip has a 512-bit filter, which is
718 * different than the SiS, so we special-case it.
719 */
720 if (sc->sis_type == SIS_TYPE_83815)
721 return (crc >> 23);
722 else if (sc->sis_rev >= SIS_REV_635 ||
723 sc->sis_rev == SIS_REV_900B)
724 return (crc >> 24);
725 else
726 return (crc >> 25);
727 }
728
729 static void
730 sis_setmulti_ns(struct sis_softc *sc)
731 {
732 struct ifnet *ifp;
733 struct ifmultiaddr *ifma;
734 u_int32_t h = 0, i, filtsave;
735 int bit, index;
736
737 ifp = sc->sis_ifp;
738
739 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
740 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
741 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
742 return;
743 }
744
745 /*
746 * We have to explicitly enable the multicast hash table
747 * on the NatSemi chip if we want to use it, which we do.
748 */
749 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
750 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
751
752 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
753
754 /* first, zot all the existing hash bits */
755 for (i = 0; i < 32; i++) {
756 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
757 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
758 }
759
760 IF_ADDR_LOCK(ifp);
761 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
762 if (ifma->ifma_addr->sa_family != AF_LINK)
763 continue;
764 h = sis_mchash(sc,
765 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
766 index = h >> 3;
767 bit = h & 0x1F;
768 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
769 if (bit > 0xF)
770 bit -= 0x10;
771 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
772 }
773 IF_ADDR_UNLOCK(ifp);
774
775 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
776
777 return;
778 }
779
780 static void
781 sis_setmulti_sis(struct sis_softc *sc)
782 {
783 struct ifnet *ifp;
784 struct ifmultiaddr *ifma;
785 u_int32_t h, i, n, ctl;
786 u_int16_t hashes[16];
787
788 ifp = sc->sis_ifp;
789
790 /* hash table size */
791 if (sc->sis_rev >= SIS_REV_635 ||
792 sc->sis_rev == SIS_REV_900B)
793 n = 16;
794 else
795 n = 8;
796
797 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
798
799 if (ifp->if_flags & IFF_BROADCAST)
800 ctl |= SIS_RXFILTCTL_BROAD;
801
802 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
803 ctl |= SIS_RXFILTCTL_ALLMULTI;
804 if (ifp->if_flags & IFF_PROMISC)
805 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
806 for (i = 0; i < n; i++)
807 hashes[i] = ~0;
808 } else {
809 for (i = 0; i < n; i++)
810 hashes[i] = 0;
811 i = 0;
812 IF_ADDR_LOCK(ifp);
813 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
814 if (ifma->ifma_addr->sa_family != AF_LINK)
815 continue;
816 h = sis_mchash(sc,
817 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
818 hashes[h >> 4] |= 1 << (h & 0xf);
819 i++;
820 }
821 IF_ADDR_UNLOCK(ifp);
822 if (i > n) {
823 ctl |= SIS_RXFILTCTL_ALLMULTI;
824 for (i = 0; i < n; i++)
825 hashes[i] = ~0;
826 }
827 }
828
829 for (i = 0; i < n; i++) {
830 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
831 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
832 }
833
834 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
835 }
836
837 static void
838 sis_reset(struct sis_softc *sc)
839 {
840 int i;
841
842 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
843
844 for (i = 0; i < SIS_TIMEOUT; i++) {
845 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
846 break;
847 }
848
849 if (i == SIS_TIMEOUT)
850 if_printf(sc->sis_ifp, "reset never completed\n");
851
852 /* Wait a little while for the chip to get its brains in order. */
853 DELAY(1000);
854
855 /*
856 * If this is a NetSemi chip, make sure to clear
857 * PME mode.
858 */
859 if (sc->sis_type == SIS_TYPE_83815) {
860 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
861 CSR_WRITE_4(sc, NS_CLKRUN, 0);
862 }
863
864 return;
865 }
866
867 /*
868 * Probe for an SiS chip. Check the PCI vendor and device
869 * IDs against our list and return a device name if we find a match.
870 */
871 static int
872 sis_probe(device_t dev)
873 {
874 struct sis_type *t;
875
876 t = sis_devs;
877
878 while(t->sis_name != NULL) {
879 if ((pci_get_vendor(dev) == t->sis_vid) &&
880 (pci_get_device(dev) == t->sis_did)) {
881 device_set_desc(dev, t->sis_name);
882 return (BUS_PROBE_DEFAULT);
883 }
884 t++;
885 }
886
887 return(ENXIO);
888 }
889
890 /*
891 * Attach the interface. Allocate softc structures, do ifmedia
892 * setup and ethernet/BPF attach.
893 */
894 static int
895 sis_attach(device_t dev)
896 {
897 u_char eaddr[ETHER_ADDR_LEN];
898 struct sis_softc *sc;
899 struct ifnet *ifp;
900 int error = 0, rid, waittime = 0;
901
902 waittime = 0;
903 sc = device_get_softc(dev);
904
905 sc->sis_self = dev;
906
907 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
908 MTX_DEF);
909 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
910
911 if (pci_get_device(dev) == SIS_DEVICEID_900)
912 sc->sis_type = SIS_TYPE_900;
913 if (pci_get_device(dev) == SIS_DEVICEID_7016)
914 sc->sis_type = SIS_TYPE_7016;
915 if (pci_get_vendor(dev) == NS_VENDORID)
916 sc->sis_type = SIS_TYPE_83815;
917
918 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
919 /*
920 * Map control/status registers.
921 */
922 pci_enable_busmaster(dev);
923
924 rid = SIS_RID;
925 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
926
927 if (sc->sis_res == NULL) {
928 device_printf(dev, "couldn't map ports/memory\n");
929 error = ENXIO;
930 goto fail;
931 }
932
933 sc->sis_btag = rman_get_bustag(sc->sis_res);
934 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
935
936 /* Allocate interrupt */
937 rid = 0;
938 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
939 RF_SHAREABLE | RF_ACTIVE);
940
941 if (sc->sis_irq == NULL) {
942 device_printf(dev, "couldn't map interrupt\n");
943 error = ENXIO;
944 goto fail;
945 }
946
947 /* Reset the adapter. */
948 sis_reset(sc);
949
950 if (sc->sis_type == SIS_TYPE_900 &&
951 (sc->sis_rev == SIS_REV_635 ||
952 sc->sis_rev == SIS_REV_900B)) {
953 SIO_SET(SIS_CFG_RND_CNT);
954 SIO_SET(SIS_CFG_PERR_DETECT);
955 }
956
957 /*
958 * Get station address from the EEPROM.
959 */
960 switch (pci_get_vendor(dev)) {
961 case NS_VENDORID:
962 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
963
964 /* We can't update the device description, so spew */
965 if (sc->sis_srr == NS_SRR_15C)
966 device_printf(dev, "Silicon Revision: DP83815C\n");
967 else if (sc->sis_srr == NS_SRR_15D)
968 device_printf(dev, "Silicon Revision: DP83815D\n");
969 else if (sc->sis_srr == NS_SRR_16A)
970 device_printf(dev, "Silicon Revision: DP83816A\n");
971 else
972 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
973
974 /*
975 * Reading the MAC address out of the EEPROM on
976 * the NatSemi chip takes a bit more work than
977 * you'd expect. The address spans 4 16-bit words,
978 * with the first word containing only a single bit.
979 * You have to shift everything over one bit to
980 * get it aligned properly. Also, the bits are
981 * stored backwards (the LSB is really the MSB,
982 * and so on) so you have to reverse them in order
983 * to get the MAC address into the form we want.
984 * Why? Who the hell knows.
985 */
986 {
987 u_int16_t tmp[4];
988
989 sis_read_eeprom(sc, (caddr_t)&tmp,
990 NS_EE_NODEADDR, 4, 0);
991
992 /* Shift everything over one bit. */
993 tmp[3] = tmp[3] >> 1;
994 tmp[3] |= tmp[2] << 15;
995 tmp[2] = tmp[2] >> 1;
996 tmp[2] |= tmp[1] << 15;
997 tmp[1] = tmp[1] >> 1;
998 tmp[1] |= tmp[0] << 15;
999
1000 /* Now reverse all the bits. */
1001 tmp[3] = sis_reverse(tmp[3]);
1002 tmp[2] = sis_reverse(tmp[2]);
1003 tmp[1] = sis_reverse(tmp[1]);
1004
1005 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1006 }
1007 break;
1008 case SIS_VENDORID:
1009 default:
1010 #if defined(__i386__) || defined(__amd64__)
1011 /*
1012 * If this is a SiS 630E chipset with an embedded
1013 * SiS 900 controller, we have to read the MAC address
1014 * from the APC CMOS RAM. Our method for doing this
1015 * is very ugly since we have to reach out and grab
1016 * ahold of hardware for which we cannot properly
1017 * allocate resources. This code is only compiled on
1018 * the i386 architecture since the SiS 630E chipset
1019 * is for x86 motherboards only. Note that there are
1020 * a lot of magic numbers in this hack. These are
1021 * taken from SiS's Linux driver. I'd like to replace
1022 * them with proper symbolic definitions, but that
1023 * requires some datasheets that I don't have access
1024 * to at the moment.
1025 */
1026 if (sc->sis_rev == SIS_REV_630S ||
1027 sc->sis_rev == SIS_REV_630E ||
1028 sc->sis_rev == SIS_REV_630EA1)
1029 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1030
1031 else if (sc->sis_rev == SIS_REV_635 ||
1032 sc->sis_rev == SIS_REV_630ET)
1033 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1034 else if (sc->sis_rev == SIS_REV_96x) {
1035 /* Allow to read EEPROM from LAN. It is shared
1036 * between a 1394 controller and the NIC and each
1037 * time we access it, we need to set SIS_EECMD_REQ.
1038 */
1039 SIO_SET(SIS_EECMD_REQ);
1040 for (waittime = 0; waittime < SIS_TIMEOUT;
1041 waittime++) {
1042 /* Force EEPROM to idle state. */
1043 sis_eeprom_idle(sc);
1044 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1045 sis_read_eeprom(sc, (caddr_t)&eaddr,
1046 SIS_EE_NODEADDR, 3, 0);
1047 break;
1048 }
1049 DELAY(1);
1050 }
1051 /*
1052 * Set SIS_EECTL_CLK to high, so a other master
1053 * can operate on the i2c bus.
1054 */
1055 SIO_SET(SIS_EECTL_CLK);
1056 /* Refuse EEPROM access by LAN */
1057 SIO_SET(SIS_EECMD_DONE);
1058 } else
1059 #endif
1060 sis_read_eeprom(sc, (caddr_t)&eaddr,
1061 SIS_EE_NODEADDR, 3, 0);
1062 break;
1063 }
1064
1065 /*
1066 * Allocate the parent bus DMA tag appropriate for PCI.
1067 */
1068 #define SIS_NSEG_NEW 32
1069 error = bus_dma_tag_create(NULL, /* parent */
1070 1, 0, /* alignment, boundary */
1071 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1072 BUS_SPACE_MAXADDR, /* highaddr */
1073 NULL, NULL, /* filter, filterarg */
1074 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1075 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1076 BUS_DMA_ALLOCNOW, /* flags */
1077 NULL, NULL, /* lockfunc, lockarg */
1078 &sc->sis_parent_tag);
1079 if (error)
1080 goto fail;
1081
1082 /*
1083 * Now allocate a tag for the DMA descriptor lists and a chunk
1084 * of DMA-able memory based on the tag. Also obtain the physical
1085 * addresses of the RX and TX ring, which we'll need later.
1086 * All of our lists are allocated as a contiguous block
1087 * of memory.
1088 */
1089 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1090 1, 0, /* alignment, boundary */
1091 BUS_SPACE_MAXADDR, /* lowaddr */
1092 BUS_SPACE_MAXADDR, /* highaddr */
1093 NULL, NULL, /* filter, filterarg */
1094 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */
1095 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1096 0, /* flags */
1097 busdma_lock_mutex, /* lockfunc */
1098 &Giant, /* lockarg */
1099 &sc->sis_rx_tag);
1100 if (error)
1101 goto fail;
1102
1103 error = bus_dmamem_alloc(sc->sis_rx_tag,
1104 (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1105 &sc->sis_rx_dmamap);
1106
1107 if (error) {
1108 device_printf(dev, "no memory for rx list buffers!\n");
1109 bus_dma_tag_destroy(sc->sis_rx_tag);
1110 sc->sis_rx_tag = NULL;
1111 goto fail;
1112 }
1113
1114 error = bus_dmamap_load(sc->sis_rx_tag,
1115 sc->sis_rx_dmamap, &(sc->sis_rx_list[0]),
1116 sizeof(struct sis_desc), sis_dma_map_ring,
1117 &sc->sis_rx_paddr, 0);
1118
1119 if (error) {
1120 device_printf(dev, "cannot get address of the rx ring!\n");
1121 bus_dmamem_free(sc->sis_rx_tag,
1122 sc->sis_rx_list, sc->sis_rx_dmamap);
1123 bus_dma_tag_destroy(sc->sis_rx_tag);
1124 sc->sis_rx_tag = NULL;
1125 goto fail;
1126 }
1127
1128 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1129 1, 0, /* alignment, boundary */
1130 BUS_SPACE_MAXADDR, /* lowaddr */
1131 BUS_SPACE_MAXADDR, /* highaddr */
1132 NULL, NULL, /* filter, filterarg */
1133 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */
1134 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1135 0, /* flags */
1136 busdma_lock_mutex, /* lockfunc */
1137 &Giant, /* lockarg */
1138 &sc->sis_tx_tag);
1139 if (error)
1140 goto fail;
1141
1142 error = bus_dmamem_alloc(sc->sis_tx_tag,
1143 (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1144 &sc->sis_tx_dmamap);
1145
1146 if (error) {
1147 device_printf(dev, "no memory for tx list buffers!\n");
1148 bus_dma_tag_destroy(sc->sis_tx_tag);
1149 sc->sis_tx_tag = NULL;
1150 goto fail;
1151 }
1152
1153 error = bus_dmamap_load(sc->sis_tx_tag,
1154 sc->sis_tx_dmamap, &(sc->sis_tx_list[0]),
1155 sizeof(struct sis_desc), sis_dma_map_ring,
1156 &sc->sis_tx_paddr, 0);
1157
1158 if (error) {
1159 device_printf(dev, "cannot get address of the tx ring!\n");
1160 bus_dmamem_free(sc->sis_tx_tag,
1161 sc->sis_tx_list, sc->sis_tx_dmamap);
1162 bus_dma_tag_destroy(sc->sis_tx_tag);
1163 sc->sis_tx_tag = NULL;
1164 goto fail;
1165 }
1166
1167 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1168 1, 0, /* alignment, boundary */
1169 BUS_SPACE_MAXADDR, /* lowaddr */
1170 BUS_SPACE_MAXADDR, /* highaddr */
1171 NULL, NULL, /* filter, filterarg */
1172 MCLBYTES, 1, /* maxsize,nsegments */
1173 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1174 0, /* flags */
1175 busdma_lock_mutex, /* lockfunc */
1176 &Giant, /* lockarg */
1177 &sc->sis_tag);
1178 if (error)
1179 goto fail;
1180
1181 /*
1182 * Obtain the physical addresses of the RX and TX
1183 * rings which we'll need later in the init routine.
1184 */
1185
1186 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1187 if (ifp == NULL) {
1188 device_printf(dev, "can not if_alloc()\n");
1189 error = ENOSPC;
1190 goto fail;
1191 }
1192 ifp->if_softc = sc;
1193 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1194 ifp->if_mtu = ETHERMTU;
1195 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1196 ifp->if_ioctl = sis_ioctl;
1197 ifp->if_start = sis_start;
1198 ifp->if_watchdog = sis_watchdog;
1199 ifp->if_init = sis_init;
1200 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1201 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
1202 IFQ_SET_READY(&ifp->if_snd);
1203
1204 /*
1205 * Do MII setup.
1206 */
1207 if (mii_phy_probe(dev, &sc->sis_miibus,
1208 sis_ifmedia_upd, sis_ifmedia_sts)) {
1209 device_printf(dev, "MII without any PHY!\n");
1210 if_free(ifp);
1211 error = ENXIO;
1212 goto fail;
1213 }
1214
1215 /*
1216 * Call MI attach routine.
1217 */
1218 ether_ifattach(ifp, eaddr);
1219
1220 /*
1221 * Tell the upper layer(s) we support long frames.
1222 */
1223 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1224 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1225 ifp->if_capenable = ifp->if_capabilities;
1226 #ifdef DEVICE_POLLING
1227 ifp->if_capabilities |= IFCAP_POLLING;
1228 #endif
1229
1230 /* Hook interrupt last to avoid having to lock softc */
1231 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE,
1232 sis_intr, sc, &sc->sis_intrhand);
1233
1234 if (error) {
1235 device_printf(dev, "couldn't set up irq\n");
1236 ether_ifdetach(ifp);
1237 goto fail;
1238 }
1239
1240 fail:
1241 if (error)
1242 sis_detach(dev);
1243
1244 return(error);
1245 }
1246
1247 /*
1248 * Shutdown hardware and free up resources. This can be called any
1249 * time after the mutex has been initialized. It is called in both
1250 * the error case in attach and the normal detach case so it needs
1251 * to be careful about only freeing resources that have actually been
1252 * allocated.
1253 */
1254 static int
1255 sis_detach(device_t dev)
1256 {
1257 struct sis_softc *sc;
1258 struct ifnet *ifp;
1259
1260 sc = device_get_softc(dev);
1261 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1262 ifp = sc->sis_ifp;
1263
1264 #ifdef DEVICE_POLLING
1265 if (ifp->if_capenable & IFCAP_POLLING)
1266 ether_poll_deregister(ifp);
1267 #endif
1268
1269 /* These should only be active if attach succeeded. */
1270 if (device_is_attached(dev)) {
1271 SIS_LOCK(sc);
1272 sis_reset(sc);
1273 sis_stop(sc);
1274 SIS_UNLOCK(sc);
1275 callout_drain(&sc->sis_stat_ch);
1276 ether_ifdetach(ifp);
1277 }
1278 if (ifp)
1279 if_free(ifp);
1280 if (sc->sis_miibus)
1281 device_delete_child(dev, sc->sis_miibus);
1282 bus_generic_detach(dev);
1283
1284 if (sc->sis_intrhand)
1285 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1286 if (sc->sis_irq)
1287 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1288 if (sc->sis_res)
1289 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1290
1291 if (sc->sis_rx_tag) {
1292 bus_dmamap_unload(sc->sis_rx_tag,
1293 sc->sis_rx_dmamap);
1294 bus_dmamem_free(sc->sis_rx_tag,
1295 sc->sis_rx_list, sc->sis_rx_dmamap);
1296 bus_dma_tag_destroy(sc->sis_rx_tag);
1297 }
1298 if (sc->sis_tx_tag) {
1299 bus_dmamap_unload(sc->sis_tx_tag,
1300 sc->sis_tx_dmamap);
1301 bus_dmamem_free(sc->sis_tx_tag,
1302 sc->sis_tx_list, sc->sis_tx_dmamap);
1303 bus_dma_tag_destroy(sc->sis_tx_tag);
1304 }
1305 if (sc->sis_parent_tag)
1306 bus_dma_tag_destroy(sc->sis_parent_tag);
1307 if (sc->sis_tag)
1308 bus_dma_tag_destroy(sc->sis_tag);
1309
1310 mtx_destroy(&sc->sis_mtx);
1311
1312 return(0);
1313 }
1314
1315 /*
1316 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1317 * we arrange the descriptors in a closed ring, so that the last descriptor
1318 * points back to the first.
1319 */
1320 static int
1321 sis_ring_init(struct sis_softc *sc)
1322 {
1323 int i, error;
1324 struct sis_desc *dp;
1325
1326 dp = &sc->sis_tx_list[0];
1327 for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) {
1328 if (i == (SIS_TX_LIST_CNT - 1))
1329 dp->sis_nextdesc = &sc->sis_tx_list[0];
1330 else
1331 dp->sis_nextdesc = dp + 1;
1332 bus_dmamap_load(sc->sis_tx_tag,
1333 sc->sis_tx_dmamap,
1334 dp->sis_nextdesc, sizeof(struct sis_desc),
1335 sis_dma_map_desc_next, dp, 0);
1336 dp->sis_mbuf = NULL;
1337 dp->sis_ptr = 0;
1338 dp->sis_ctl = 0;
1339 }
1340
1341 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1342
1343 bus_dmamap_sync(sc->sis_tx_tag,
1344 sc->sis_tx_dmamap, BUS_DMASYNC_PREWRITE);
1345
1346 dp = &sc->sis_rx_list[0];
1347 for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) {
1348 error = sis_newbuf(sc, dp, NULL);
1349 if (error)
1350 return(error);
1351 if (i == (SIS_RX_LIST_CNT - 1))
1352 dp->sis_nextdesc = &sc->sis_rx_list[0];
1353 else
1354 dp->sis_nextdesc = dp + 1;
1355 bus_dmamap_load(sc->sis_rx_tag,
1356 sc->sis_rx_dmamap,
1357 dp->sis_nextdesc, sizeof(struct sis_desc),
1358 sis_dma_map_desc_next, dp, 0);
1359 }
1360
1361 bus_dmamap_sync(sc->sis_rx_tag,
1362 sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE);
1363
1364 sc->sis_rx_pdsc = &sc->sis_rx_list[0];
1365
1366 return(0);
1367 }
1368
1369 /*
1370 * Initialize an RX descriptor and attach an MBUF cluster.
1371 */
1372 static int
1373 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
1374 {
1375
1376 if (c == NULL)
1377 return(EINVAL);
1378
1379 if (m == NULL) {
1380 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1381 if (m == NULL)
1382 return(ENOBUFS);
1383 } else
1384 m->m_data = m->m_ext.ext_buf;
1385
1386 c->sis_mbuf = m;
1387 c->sis_ctl = SIS_RXLEN;
1388
1389 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1390 bus_dmamap_load(sc->sis_tag, c->sis_map,
1391 mtod(m, void *), MCLBYTES,
1392 sis_dma_map_desc_ptr, c, 0);
1393 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD);
1394
1395 return(0);
1396 }
1397
1398 /*
1399 * A frame has been uploaded: pass the resulting mbuf chain up to
1400 * the higher level protocols.
1401 */
1402 static void
1403 sis_rxeof(struct sis_softc *sc)
1404 {
1405 struct mbuf *m;
1406 struct ifnet *ifp;
1407 struct sis_desc *cur_rx;
1408 int total_len = 0;
1409 u_int32_t rxstat;
1410
1411 SIS_LOCK_ASSERT(sc);
1412
1413 ifp = sc->sis_ifp;
1414
1415 for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx);
1416 cur_rx = cur_rx->sis_nextdesc) {
1417
1418 #ifdef DEVICE_POLLING
1419 if (ifp->if_capenable & IFCAP_POLLING) {
1420 if (sc->rxcycles <= 0)
1421 break;
1422 sc->rxcycles--;
1423 }
1424 #endif
1425 rxstat = cur_rx->sis_rxstat;
1426 bus_dmamap_sync(sc->sis_tag,
1427 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE);
1428 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1429 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1430 m = cur_rx->sis_mbuf;
1431 cur_rx->sis_mbuf = NULL;
1432 total_len = SIS_RXBYTES(cur_rx);
1433
1434 /*
1435 * If an error occurs, update stats, clear the
1436 * status word and leave the mbuf cluster in place:
1437 * it should simply get re-used next time this descriptor
1438 * comes up in the ring.
1439 */
1440 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1441 ifp->if_ierrors++;
1442 if (rxstat & SIS_RXSTAT_COLL)
1443 ifp->if_collisions++;
1444 sis_newbuf(sc, cur_rx, m);
1445 continue;
1446 }
1447
1448 /* No errors; receive the packet. */
1449 #if defined(__i386__) || defined(__amd64__)
1450 /*
1451 * On the x86 we do not have alignment problems, so try to
1452 * allocate a new buffer for the receive ring, and pass up
1453 * the one where the packet is already, saving the expensive
1454 * copy done in m_devget().
1455 * If we are on an architecture with alignment problems, or
1456 * if the allocation fails, then use m_devget and leave the
1457 * existing buffer in the receive ring.
1458 */
1459 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1460 m->m_pkthdr.len = m->m_len = total_len;
1461 else
1462 #endif
1463 {
1464 struct mbuf *m0;
1465 m0 = m_devget(mtod(m, char *), total_len,
1466 ETHER_ALIGN, ifp, NULL);
1467 sis_newbuf(sc, cur_rx, m);
1468 if (m0 == NULL) {
1469 ifp->if_ierrors++;
1470 continue;
1471 }
1472 m = m0;
1473 }
1474
1475 ifp->if_ipackets++;
1476 m->m_pkthdr.rcvif = ifp;
1477
1478 SIS_UNLOCK(sc);
1479 (*ifp->if_input)(ifp, m);
1480 SIS_LOCK(sc);
1481 }
1482
1483 sc->sis_rx_pdsc = cur_rx;
1484 }
1485
1486 static void
1487 sis_rxeoc(struct sis_softc *sc)
1488 {
1489
1490 SIS_LOCK_ASSERT(sc);
1491 sis_rxeof(sc);
1492 sis_initl(sc);
1493 }
1494
1495 /*
1496 * A frame was downloaded to the chip. It's safe for us to clean up
1497 * the list buffers.
1498 */
1499
1500 static void
1501 sis_txeof(struct sis_softc *sc)
1502 {
1503 struct ifnet *ifp;
1504 u_int32_t idx;
1505
1506 SIS_LOCK_ASSERT(sc);
1507 ifp = sc->sis_ifp;
1508
1509 /*
1510 * Go through our tx list and free mbufs for those
1511 * frames that have been transmitted.
1512 */
1513 for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0;
1514 sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1515 struct sis_desc *cur_tx = &sc->sis_tx_list[idx];
1516
1517 if (SIS_OWNDESC(cur_tx))
1518 break;
1519
1520 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1521 continue;
1522
1523 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1524 ifp->if_oerrors++;
1525 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1526 ifp->if_collisions++;
1527 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1528 ifp->if_collisions++;
1529 }
1530
1531 ifp->if_collisions +=
1532 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1533
1534 ifp->if_opackets++;
1535 if (cur_tx->sis_mbuf != NULL) {
1536 m_freem(cur_tx->sis_mbuf);
1537 cur_tx->sis_mbuf = NULL;
1538 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1539 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1540 }
1541 }
1542
1543 if (idx != sc->sis_tx_cons) {
1544 /* we freed up some buffers */
1545 sc->sis_tx_cons = idx;
1546 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1547 }
1548
1549 ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5;
1550
1551 return;
1552 }
1553
1554 static void
1555 sis_tick(void *xsc)
1556 {
1557 struct sis_softc *sc;
1558 struct mii_data *mii;
1559 struct ifnet *ifp;
1560
1561 sc = xsc;
1562 SIS_LOCK_ASSERT(sc);
1563 sc->in_tick = 1;
1564 ifp = sc->sis_ifp;
1565
1566 mii = device_get_softc(sc->sis_miibus);
1567 mii_tick(mii);
1568
1569 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE &&
1570 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1571 sc->sis_link++;
1572 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1573 sis_startl(ifp);
1574 }
1575
1576 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1577 sc->in_tick = 0;
1578 }
1579
1580 #ifdef DEVICE_POLLING
1581 static poll_handler_t sis_poll;
1582
1583 static void
1584 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1585 {
1586 struct sis_softc *sc = ifp->if_softc;
1587
1588 SIS_LOCK(sc);
1589 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1590 SIS_UNLOCK(sc);
1591 return;
1592 }
1593
1594 /*
1595 * On the sis, reading the status register also clears it.
1596 * So before returning to intr mode we must make sure that all
1597 * possible pending sources of interrupts have been served.
1598 * In practice this means run to completion the *eof routines,
1599 * and then call the interrupt routine
1600 */
1601 sc->rxcycles = count;
1602 sis_rxeof(sc);
1603 sis_txeof(sc);
1604 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1605 sis_startl(ifp);
1606
1607 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1608 u_int32_t status;
1609
1610 /* Reading the ISR register clears all interrupts. */
1611 status = CSR_READ_4(sc, SIS_ISR);
1612
1613 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1614 sis_rxeoc(sc);
1615
1616 if (status & (SIS_ISR_RX_IDLE))
1617 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1618
1619 if (status & SIS_ISR_SYSERR) {
1620 sis_reset(sc);
1621 sis_initl(sc);
1622 }
1623 }
1624
1625 SIS_UNLOCK(sc);
1626 }
1627 #endif /* DEVICE_POLLING */
1628
1629 static void
1630 sis_intr(void *arg)
1631 {
1632 struct sis_softc *sc;
1633 struct ifnet *ifp;
1634 u_int32_t status;
1635
1636 sc = arg;
1637 ifp = sc->sis_ifp;
1638
1639 if (sc->sis_stopped) /* Most likely shared interrupt */
1640 return;
1641
1642 SIS_LOCK(sc);
1643 #ifdef DEVICE_POLLING
1644 if (ifp->if_capenable & IFCAP_POLLING) {
1645 SIS_UNLOCK(sc);
1646 return;
1647 }
1648 #endif
1649
1650 /* Disable interrupts. */
1651 CSR_WRITE_4(sc, SIS_IER, 0);
1652
1653 for (;;) {
1654 SIS_LOCK_ASSERT(sc);
1655 /* Reading the ISR register clears all interrupts. */
1656 status = CSR_READ_4(sc, SIS_ISR);
1657
1658 if ((status & SIS_INTRS) == 0)
1659 break;
1660
1661 if (status &
1662 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1663 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1664 sis_txeof(sc);
1665
1666 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE))
1667 sis_rxeof(sc);
1668
1669 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1670 sis_rxeoc(sc);
1671
1672 if (status & (SIS_ISR_RX_IDLE))
1673 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1674
1675 if (status & SIS_ISR_SYSERR) {
1676 sis_reset(sc);
1677 sis_initl(sc);
1678 }
1679 }
1680
1681 /* Re-enable interrupts. */
1682 CSR_WRITE_4(sc, SIS_IER, 1);
1683
1684 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1685 sis_startl(ifp);
1686
1687 SIS_UNLOCK(sc);
1688 }
1689
1690 /*
1691 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1692 * pointers to the fragment pointers.
1693 */
1694 static int
1695 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1696 {
1697 struct sis_desc *f = NULL;
1698 struct mbuf *m;
1699 int frag, cur, cnt = 0, chainlen = 0;
1700
1701 /*
1702 * If there's no way we can send any packets, return now.
1703 */
1704 if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2)
1705 return (ENOBUFS);
1706
1707 /*
1708 * Count the number of frags in this chain to see if
1709 * we need to m_defrag. Since the descriptor list is shared
1710 * by all packets, we'll m_defrag long chains so that they
1711 * do not use up the entire list, even if they would fit.
1712 */
1713
1714 for (m = *m_head; m != NULL; m = m->m_next)
1715 chainlen++;
1716
1717 if ((chainlen > SIS_TX_LIST_CNT / 4) ||
1718 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) {
1719 m = m_defrag(*m_head, M_DONTWAIT);
1720 if (m == NULL)
1721 return (ENOBUFS);
1722 *m_head = m;
1723 }
1724
1725 /*
1726 * Start packing the mbufs in this chain into
1727 * the fragment pointers. Stop when we run out
1728 * of fragments or hit the end of the mbuf chain.
1729 */
1730 cur = frag = *txidx;
1731
1732 for (m = *m_head; m != NULL; m = m->m_next) {
1733 if (m->m_len != 0) {
1734 if ((SIS_TX_LIST_CNT -
1735 (sc->sis_tx_cnt + cnt)) < 2)
1736 return(ENOBUFS);
1737 f = &sc->sis_tx_list[frag];
1738 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1739 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1740 bus_dmamap_load(sc->sis_tag, f->sis_map,
1741 mtod(m, void *), m->m_len,
1742 sis_dma_map_desc_ptr, f, 0);
1743 bus_dmamap_sync(sc->sis_tag,
1744 f->sis_map, BUS_DMASYNC_PREREAD);
1745 if (cnt != 0)
1746 f->sis_ctl |= SIS_CMDSTS_OWN;
1747 cur = frag;
1748 SIS_INC(frag, SIS_TX_LIST_CNT);
1749 cnt++;
1750 }
1751 }
1752
1753 if (m != NULL)
1754 return(ENOBUFS);
1755
1756 sc->sis_tx_list[cur].sis_mbuf = *m_head;
1757 sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1758 sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1759 sc->sis_tx_cnt += cnt;
1760 *txidx = frag;
1761
1762 return(0);
1763 }
1764
1765 /*
1766 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1767 * to the mbuf data regions directly in the transmit lists. We also save a
1768 * copy of the pointers since the transmit list fragment pointers are
1769 * physical addresses.
1770 */
1771
1772 static void
1773 sis_start(struct ifnet *ifp)
1774 {
1775 struct sis_softc *sc;
1776
1777 sc = ifp->if_softc;
1778 SIS_LOCK(sc);
1779 sis_startl(ifp);
1780 SIS_UNLOCK(sc);
1781 }
1782
1783 static void
1784 sis_startl(struct ifnet *ifp)
1785 {
1786 struct sis_softc *sc;
1787 struct mbuf *m_head = NULL;
1788 u_int32_t idx, queued = 0;
1789
1790 sc = ifp->if_softc;
1791
1792 SIS_LOCK_ASSERT(sc);
1793
1794 if (!sc->sis_link)
1795 return;
1796
1797 idx = sc->sis_tx_prod;
1798
1799 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1800 return;
1801
1802 while(sc->sis_tx_list[idx].sis_mbuf == NULL) {
1803 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1804 if (m_head == NULL)
1805 break;
1806
1807 if (sis_encap(sc, &m_head, &idx)) {
1808 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1809 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1810 break;
1811 }
1812
1813 queued++;
1814
1815 /*
1816 * If there's a BPF listener, bounce a copy of this frame
1817 * to him.
1818 */
1819 BPF_MTAP(ifp, m_head);
1820
1821 }
1822
1823 if (queued) {
1824 /* Transmit */
1825 sc->sis_tx_prod = idx;
1826 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1827
1828 /*
1829 * Set a timeout in case the chip goes out to lunch.
1830 */
1831 ifp->if_timer = 5;
1832 }
1833 }
1834
1835 static void
1836 sis_init(void *xsc)
1837 {
1838 struct sis_softc *sc = xsc;
1839
1840 SIS_LOCK(sc);
1841 sis_initl(sc);
1842 SIS_UNLOCK(sc);
1843 }
1844
1845 static void
1846 sis_initl(struct sis_softc *sc)
1847 {
1848 struct ifnet *ifp = sc->sis_ifp;
1849 struct mii_data *mii;
1850
1851 SIS_LOCK_ASSERT(sc);
1852
1853 /*
1854 * Cancel pending I/O and free all RX/TX buffers.
1855 */
1856 sis_stop(sc);
1857 sc->sis_stopped = 0;
1858
1859 #ifdef notyet
1860 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
1861 /*
1862 * Configure 400usec of interrupt holdoff. This is based
1863 * on emperical tests on a Soekris 4801.
1864 */
1865 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
1866 }
1867 #endif
1868
1869 mii = device_get_softc(sc->sis_miibus);
1870
1871 /* Set MAC address */
1872 if (sc->sis_type == SIS_TYPE_83815) {
1873 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1874 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1875 ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[0]);
1876 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1877 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1878 ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[1]);
1879 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1880 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1881 ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[2]);
1882 } else {
1883 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1884 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1885 ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[0]);
1886 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1887 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1888 ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[1]);
1889 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1890 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1891 ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[2]);
1892 }
1893
1894 /* Init circular TX/RX lists. */
1895 if (sis_ring_init(sc) != 0) {
1896 if_printf(ifp,
1897 "initialization failed: no memory for rx buffers\n");
1898 sis_stop(sc);
1899 return;
1900 }
1901
1902 /*
1903 * Short Cable Receive Errors (MP21.E)
1904 * also: Page 78 of the DP83815 data sheet (september 2002 version)
1905 * recommends the following register settings "for optimum
1906 * performance." for rev 15C. The driver from NS also sets
1907 * the PHY_CR register for later versions.
1908 */
1909 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
1910 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1911 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1912 if (sc->sis_srr == NS_SRR_15C) {
1913 /* set val for c2 */
1914 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1915 /* load/kill c2 */
1916 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1917 /* rais SD off, from 4 to c */
1918 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1919 }
1920 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
1921 }
1922
1923
1924 /*
1925 * For the NatSemi chip, we have to explicitly enable the
1926 * reception of ARP frames, as well as turn on the 'perfect
1927 * match' filter where we store the station address, otherwise
1928 * we won't receive unicasts meant for this host.
1929 */
1930 if (sc->sis_type == SIS_TYPE_83815) {
1931 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1932 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1933 }
1934
1935 /* If we want promiscuous mode, set the allframes bit. */
1936 if (ifp->if_flags & IFF_PROMISC) {
1937 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1938 } else {
1939 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1940 }
1941
1942 /*
1943 * Set the capture broadcast bit to capture broadcast frames.
1944 */
1945 if (ifp->if_flags & IFF_BROADCAST) {
1946 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1947 } else {
1948 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1949 }
1950
1951 /*
1952 * Load the multicast filter.
1953 */
1954 if (sc->sis_type == SIS_TYPE_83815)
1955 sis_setmulti_ns(sc);
1956 else
1957 sis_setmulti_sis(sc);
1958
1959 /* Turn the receive filter on */
1960 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1961
1962 /*
1963 * Load the address of the RX and TX lists.
1964 */
1965 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr);
1966 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr);
1967
1968 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1969 * the PCI bus. When this bit is set, the Max DMA Burst Size
1970 * for TX/RX DMA should be no larger than 16 double words.
1971 */
1972 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
1973 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1974 } else {
1975 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1976 }
1977
1978 /* Accept Long Packets for VLAN support */
1979 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1980
1981 /* Set TX configuration */
1982 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
1983 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1984 } else {
1985 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1986 }
1987
1988 /* Set full/half duplex mode. */
1989 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1990 SIS_SETBIT(sc, SIS_TX_CFG,
1991 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1992 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1993 } else {
1994 SIS_CLRBIT(sc, SIS_TX_CFG,
1995 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1996 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1997 }
1998
1999 if (sc->sis_type == SIS_TYPE_83816) {
2000 /*
2001 * MPII03.D: Half Duplex Excessive Collisions.
2002 * Also page 49 in 83816 manual
2003 */
2004 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
2005 }
2006
2007 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
2008 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2009 uint32_t reg;
2010
2011 /*
2012 * Short Cable Receive Errors (MP21.E)
2013 */
2014 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2015 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
2016 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
2017 DELAY(100000);
2018 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
2019 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
2020 device_printf(sc->sis_self,
2021 "Applying short cable fix (reg=%x)\n", reg);
2022 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
2023 reg = CSR_READ_4(sc, NS_PHY_DSPCFG);
2024 SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20);
2025 }
2026 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2027 }
2028
2029 /*
2030 * Enable interrupts.
2031 */
2032 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2033 #ifdef DEVICE_POLLING
2034 /*
2035 * ... only enable interrupts if we are not polling, make sure
2036 * they are off otherwise.
2037 */
2038 if (ifp->if_capenable & IFCAP_POLLING)
2039 CSR_WRITE_4(sc, SIS_IER, 0);
2040 else
2041 #endif
2042 CSR_WRITE_4(sc, SIS_IER, 1);
2043
2044 /* Enable receiver and transmitter. */
2045 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2046 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2047
2048 #ifdef notdef
2049 mii_mediachg(mii);
2050 #endif
2051
2052 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2053 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2054
2055 if (!sc->in_tick)
2056 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2057 }
2058
2059 /*
2060 * Set media options.
2061 */
2062 static int
2063 sis_ifmedia_upd(struct ifnet *ifp)
2064 {
2065 struct sis_softc *sc;
2066 struct mii_data *mii;
2067
2068 sc = ifp->if_softc;
2069
2070 SIS_LOCK(sc);
2071 mii = device_get_softc(sc->sis_miibus);
2072 sc->sis_link = 0;
2073 if (mii->mii_instance) {
2074 struct mii_softc *miisc;
2075 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2076 mii_phy_reset(miisc);
2077 }
2078 mii_mediachg(mii);
2079 SIS_UNLOCK(sc);
2080
2081 return(0);
2082 }
2083
2084 /*
2085 * Report current media status.
2086 */
2087 static void
2088 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2089 {
2090 struct sis_softc *sc;
2091 struct mii_data *mii;
2092
2093 sc = ifp->if_softc;
2094
2095 SIS_LOCK(sc);
2096 mii = device_get_softc(sc->sis_miibus);
2097 mii_pollstat(mii);
2098 SIS_UNLOCK(sc);
2099 ifmr->ifm_active = mii->mii_media_active;
2100 ifmr->ifm_status = mii->mii_media_status;
2101 }
2102
2103 static int
2104 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2105 {
2106 struct sis_softc *sc = ifp->if_softc;
2107 struct ifreq *ifr = (struct ifreq *) data;
2108 struct mii_data *mii;
2109 int error = 0;
2110
2111 switch(command) {
2112 case SIOCSIFFLAGS:
2113 SIS_LOCK(sc);
2114 if (ifp->if_flags & IFF_UP) {
2115 sis_initl(sc);
2116 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2117 sis_stop(sc);
2118 }
2119 SIS_UNLOCK(sc);
2120 error = 0;
2121 break;
2122 case SIOCADDMULTI:
2123 case SIOCDELMULTI:
2124 SIS_LOCK(sc);
2125 if (sc->sis_type == SIS_TYPE_83815)
2126 sis_setmulti_ns(sc);
2127 else
2128 sis_setmulti_sis(sc);
2129 SIS_UNLOCK(sc);
2130 error = 0;
2131 break;
2132 case SIOCGIFMEDIA:
2133 case SIOCSIFMEDIA:
2134 mii = device_get_softc(sc->sis_miibus);
2135 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2136 break;
2137 case SIOCSIFCAP:
2138 /* ok, disable interrupts */
2139 #ifdef DEVICE_POLLING
2140 if (ifr->ifr_reqcap & IFCAP_POLLING &&
2141 !(ifp->if_capenable & IFCAP_POLLING)) {
2142 error = ether_poll_register(sis_poll, ifp);
2143 if (error)
2144 return(error);
2145 SIS_LOCK(sc);
2146 /* Disable interrupts */
2147 CSR_WRITE_4(sc, SIS_IER, 0);
2148 ifp->if_capenable |= IFCAP_POLLING;
2149 SIS_UNLOCK(sc);
2150 return (error);
2151
2152 }
2153 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
2154 ifp->if_capenable & IFCAP_POLLING) {
2155 error = ether_poll_deregister(ifp);
2156 /* Enable interrupts. */
2157 SIS_LOCK(sc);
2158 CSR_WRITE_4(sc, SIS_IER, 1);
2159 ifp->if_capenable &= ~IFCAP_POLLING;
2160 SIS_UNLOCK(sc);
2161 return (error);
2162 }
2163 #endif /* DEVICE_POLLING */
2164 break;
2165 default:
2166 error = ether_ioctl(ifp, command, data);
2167 break;
2168 }
2169
2170 return(error);
2171 }
2172
2173 static void
2174 sis_watchdog(struct ifnet *ifp)
2175 {
2176 struct sis_softc *sc;
2177
2178 sc = ifp->if_softc;
2179
2180 SIS_LOCK(sc);
2181 if (sc->sis_stopped) {
2182 SIS_UNLOCK(sc);
2183 return;
2184 }
2185
2186 ifp->if_oerrors++;
2187 if_printf(ifp, "watchdog timeout\n");
2188
2189 sis_stop(sc);
2190 sis_reset(sc);
2191 sis_initl(sc);
2192
2193 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2194 sis_startl(ifp);
2195
2196 SIS_UNLOCK(sc);
2197 }
2198
2199 /*
2200 * Stop the adapter and free any mbufs allocated to the
2201 * RX and TX lists.
2202 */
2203 static void
2204 sis_stop(struct sis_softc *sc)
2205 {
2206 int i;
2207 struct ifnet *ifp;
2208 struct sis_desc *dp;
2209
2210 if (sc->sis_stopped)
2211 return;
2212 SIS_LOCK_ASSERT(sc);
2213 ifp = sc->sis_ifp;
2214 ifp->if_timer = 0;
2215
2216 callout_stop(&sc->sis_stat_ch);
2217
2218 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2219 CSR_WRITE_4(sc, SIS_IER, 0);
2220 CSR_WRITE_4(sc, SIS_IMR, 0);
2221 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2222 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2223 DELAY(1000);
2224 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2225 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2226
2227 sc->sis_link = 0;
2228
2229 /*
2230 * Free data in the RX lists.
2231 */
2232 dp = &sc->sis_rx_list[0];
2233 for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) {
2234 if (dp->sis_mbuf == NULL)
2235 continue;
2236 bus_dmamap_unload(sc->sis_tag, dp->sis_map);
2237 bus_dmamap_destroy(sc->sis_tag, dp->sis_map);
2238 m_freem(dp->sis_mbuf);
2239 dp->sis_mbuf = NULL;
2240 }
2241 bzero(sc->sis_rx_list, SIS_RX_LIST_SZ);
2242
2243 /*
2244 * Free the TX list buffers.
2245 */
2246 dp = &sc->sis_tx_list[0];
2247 for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) {
2248 if (dp->sis_mbuf == NULL)
2249 continue;
2250 bus_dmamap_unload(sc->sis_tag, dp->sis_map);
2251 bus_dmamap_destroy(sc->sis_tag, dp->sis_map);
2252 m_freem(dp->sis_mbuf);
2253 dp->sis_mbuf = NULL;
2254 }
2255
2256 bzero(sc->sis_tx_list, SIS_TX_LIST_SZ);
2257
2258 sc->sis_stopped = 1;
2259 }
2260
2261 /*
2262 * Stop all chip I/O so that the kernel's probe routines don't
2263 * get confused by errant DMAs when rebooting.
2264 */
2265 static void
2266 sis_shutdown(device_t dev)
2267 {
2268 struct sis_softc *sc;
2269
2270 sc = device_get_softc(dev);
2271 SIS_LOCK(sc);
2272 sis_reset(sc);
2273 sis_stop(sc);
2274 SIS_UNLOCK(sc);
2275 }
2276
2277 static device_method_t sis_methods[] = {
2278 /* Device interface */
2279 DEVMETHOD(device_probe, sis_probe),
2280 DEVMETHOD(device_attach, sis_attach),
2281 DEVMETHOD(device_detach, sis_detach),
2282 DEVMETHOD(device_shutdown, sis_shutdown),
2283
2284 /* bus interface */
2285 DEVMETHOD(bus_print_child, bus_generic_print_child),
2286 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
2287
2288 /* MII interface */
2289 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2290 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2291 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2292
2293 { 0, 0 }
2294 };
2295
2296 static driver_t sis_driver = {
2297 "sis",
2298 sis_methods,
2299 sizeof(struct sis_softc)
2300 };
2301
2302 static devclass_t sis_devclass;
2303
2304 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
2305 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
Cache object: 1d475e5b05f76e4c704912f571cef7b6
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