FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sisreg.h
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: releng/5.0/sys/pci/if_sisreg.h 99163 2002-06-30 21:59:08Z luigi $
33 */
34
35 /*
36 * Register definitions for the SiS 900 and SiS 7016 chipsets. The
37 * 7016 is actually an older chip and some of its registers differ
38 * from the 900, however the core operational registers are the same:
39 * the differences lie in the OnNow/Wake on LAN stuff which we don't
40 * use anyway. The 7016 needs an external MII compliant PHY while the
41 * SiS 900 has one built in. All registers are 32-bits wide.
42 */
43
44 /* Registers common to SiS 900 and SiS 7016 */
45 #define SIS_CSR 0x00
46 #define SIS_CFG 0x04
47 #define SIS_EECTL 0x08
48 #define SIS_PCICTL 0x0C
49 #define SIS_ISR 0x10
50 #define SIS_IMR 0x14
51 #define SIS_IER 0x18
52 #define SIS_PHYCTL 0x1C
53 #define SIS_TX_LISTPTR 0x20
54 #define SIS_TX_CFG 0x24
55 #define SIS_RX_LISTPTR 0x30
56 #define SIS_RX_CFG 0x34
57 #define SIS_FLOWCTL 0x38
58 #define SIS_RXFILT_CTL 0x48
59 #define SIS_RXFILT_DATA 0x4C
60 #define SIS_PWRMAN_CTL 0xB0
61 #define SIS_PWERMAN_WKUP_EVENT 0xB4
62 #define SIS_WKUP_FRAME_CRC 0xBC
63 #define SIS_WKUP_FRAME_MASK0 0xC0
64 #define SIS_WKUP_FRAME_MASKXX 0xEC
65
66 /* SiS 7016 specific registers */
67 #define SIS_SILICON_REV 0x5C
68 #define SIS_MIB_CTL0 0x60
69 #define SIS_MIB_CTL1 0x64
70 #define SIS_MIB_CTL2 0x68
71 #define SIS_MIB_CTL3 0x6C
72 #define SIS_MIB 0x80
73 #define SIS_LINKSTS 0xA0
74 #define SIS_TIMEUNIT 0xA4
75 #define SIS_GPIO 0xB8
76
77 /* NS DP83815 registers */
78 #define NS_CLKRUN 0x3C
79 #define NS_BMCR 0x80
80 #define NS_BMSR 0x84
81 #define NS_PHYIDR1 0x88
82 #define NS_PHYIDR2 0x8C
83 #define NS_ANAR 0x90
84 #define NS_ANLPAR 0x94
85 #define NS_ANER 0x98
86 #define NS_ANNPTR 0x9C
87
88 #define NS_PHY_CR 0xE4
89 #define NS_PHY_10BTSCR 0xE8
90 #define NS_PHY_PAGE 0xCC
91 #define NS_PHY_EXTCFG 0xF0
92 #define NS_PHY_DSPCFG 0xF4
93 #define NS_PHY_SDCFG 0xF8
94 #define NS_PHY_TDATA 0xFC
95
96 #define NS_CLKRUN_PMESTS 0x00008000
97 #define NS_CLKRUN_PMEENB 0x00000100
98 #define NS_CLNRUN_CLKRUN_ENB 0x00000001
99
100 #define SIS_CSR_TX_ENABLE 0x00000001
101 #define SIS_CSR_TX_DISABLE 0x00000002
102 #define SIS_CSR_RX_ENABLE 0x00000004
103 #define SIS_CSR_RX_DISABLE 0x00000008
104 #define SIS_CSR_TX_RESET 0x00000010
105 #define SIS_CSR_RX_RESET 0x00000020
106 #define SIS_CSR_SOFTINTR 0x00000080
107 #define SIS_CSR_RESET 0x00000100
108 #define SIS_CSR_ACCESS_MODE 0x00000200
109 #define SIS_CSR_RELOAD 0x00000400
110
111 #define SIS_CFG_BIGENDIAN 0x00000001
112 #define SIS_CFG_PERR_DETECT 0x00000008
113 #define SIS_CFG_DEFER_DISABLE 0x00000010
114 #define SIS_CFG_OUTOFWIN_TIMER 0x00000020
115 #define SIS_CFG_SINGLE_BACKOFF 0x00000040
116 #define SIS_CFG_PCIREQ_ALG 0x00000080
117
118 #define SIS_EECTL_DIN 0x00000001
119 #define SIS_EECTL_DOUT 0x00000002
120 #define SIS_EECTL_CLK 0x00000004
121 #define SIS_EECTL_CSEL 0x00000008
122
123 #define SIS_EECMD_WRITE 0x140
124 #define SIS_EECMD_READ 0x180
125 #define SIS_EECMD_ERASE 0x1c0
126
127 #define SIS_EE_NODEADDR 0x8
128 #define NS_EE_NODEADDR 0x6
129
130 #define SIS_PCICTL_SRAMADDR 0x0000001F
131 #define SIS_PCICTL_RAMTSTENB 0x00000020
132 #define SIS_PCICTL_TXTSTENB 0x00000040
133 #define SIS_PCICTL_RXTSTENB 0x00000080
134 #define SIS_PCICTL_BMTSTENB 0x00000200
135 #define SIS_PCICTL_RAMADDR 0x001F0000
136 #define SIS_PCICTL_ROMTIME 0x0F000000
137 #define SIS_PCICTL_DISCTEST 0x40000000
138
139 #define SIS_ISR_RX_OK 0x00000001
140 #define SIS_ISR_RX_DESC_OK 0x00000002
141 #define SIS_ISR_RX_ERR 0x00000004
142 #define SIS_ISR_RX_EARLY 0x00000008
143 #define SIS_ISR_RX_IDLE 0x00000010
144 #define SIS_ISR_RX_OFLOW 0x00000020
145 #define SIS_ISR_TX_OK 0x00000040
146 #define SIS_ISR_TX_DESC_OK 0x00000080
147 #define SIS_ISR_TX_ERR 0x00000100
148 #define SIS_ISR_TX_IDLE 0x00000200
149 #define SIS_ISR_TX_UFLOW 0x00000400
150 #define SIS_ISR_SOFTINTR 0x00000800
151 #define SIS_ISR_HIBITS 0x00008000
152 #define SIS_ISR_RX_FIFO_OFLOW 0x00010000
153 #define SIS_ISR_TGT_ABRT 0x00100000
154 #define SIS_ISR_BM_ABRT 0x00200000
155 #define SIS_ISR_SYSERR 0x00400000
156 #define SIS_ISR_PARITY_ERR 0x00800000
157 #define SIS_ISR_RX_RESET_DONE 0x01000000
158 #define SIS_ISR_TX_RESET_DONE 0x02000000
159 #define SIS_ISR_TX_PAUSE_START 0x04000000
160 #define SIS_ISR_TX_PAUSE_DONE 0x08000000
161 #define SIS_ISR_WAKE_EVENT 0x10000000
162
163 #define SIS_IMR_RX_OK 0x00000001
164 #define SIS_IMR_RX_DESC_OK 0x00000002
165 #define SIS_IMR_RX_ERR 0x00000004
166 #define SIS_IMR_RX_EARLY 0x00000008
167 #define SIS_IMR_RX_IDLE 0x00000010
168 #define SIS_IMR_RX_OFLOW 0x00000020
169 #define SIS_IMR_TX_OK 0x00000040
170 #define SIS_IMR_TX_DESC_OK 0x00000080
171 #define SIS_IMR_TX_ERR 0x00000100
172 #define SIS_IMR_TX_IDLE 0x00000200
173 #define SIS_IMR_TX_UFLOW 0x00000400
174 #define SIS_IMR_SOFTINTR 0x00000800
175 #define SIS_IMR_HIBITS 0x00008000
176 #define SIS_IMR_RX_FIFO_OFLOW 0x00010000
177 #define SIS_IMR_TGT_ABRT 0x00100000
178 #define SIS_IMR_BM_ABRT 0x00200000
179 #define SIS_IMR_SYSERR 0x00400000
180 #define SIS_IMR_PARITY_ERR 0x00800000
181 #define SIS_IMR_RX_RESET_DONE 0x01000000
182 #define SIS_IMR_TX_RESET_DONE 0x02000000
183 #define SIS_IMR_TX_PAUSE_START 0x04000000
184 #define SIS_IMR_TX_PAUSE_DONE 0x08000000
185 #define SIS_IMR_WAKE_EVENT 0x10000000
186
187 #define SIS_INTRS \
188 (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\
189 SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\
190 SIS_IMR_RX_IDLE|\
191 SIS_IMR_SYSERR)
192
193 #define SIS_IER_INTRENB 0x00000001
194
195 #define SIS_PHYCTL_ACCESS 0x00000010
196 #define SIS_PHYCTL_OP 0x00000020
197 #define SIS_PHYCTL_REGADDR 0x000007C0
198 #define SIS_PHYCTL_PHYADDR 0x0000F800
199 #define SIS_PHYCTL_PHYDATA 0xFFFF0000
200
201 #define SIS_PHYOP_READ 0x00000020
202 #define SIS_PHYOP_WRITE 0x00000000
203
204 #define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */
205 #define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */
206 #define SIS_TXCFG_DMABURST 0x00700000
207 #define SIS_TXCFG_AUTOPAD 0x10000000
208 #define SIS_TXCFG_LOOPBK 0x20000000
209 #define SIS_TXCFG_IGN_HBEAT 0x40000000
210 #define SIS_TXCFG_IGN_CARR 0x80000000
211
212 #define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH)
213 #define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH)
214
215 #define SIS_TXDMA_512BYTES 0x00000000
216 #define SIS_TXDMA_4BYTES 0x00100000
217 #define SIS_TXDMA_8BYTES 0x00200000
218 #define SIS_TXDMA_16BYTES 0x00300000
219 #define SIS_TXDMA_32BYTES 0x00400000
220 #define SIS_TXDMA_64BYTES 0x00500000
221 #define SIS_TXDMA_128BYTES 0x00600000
222 #define SIS_TXDMA_256BYTES 0x00700000
223
224 #define SIS_TXCFG_100 \
225 (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\
226 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
227
228 #define SIS_TXCFG_10 \
229 (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\
230 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
231
232 #define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */
233 #define SIS_RXCFG_DMABURST 0x00700000
234 #define SIS_RXCFG_RX_JABBER 0x08000000
235 #define SIS_RXCFG_RX_TXPKTS 0x10000000
236 #define SIS_RXCFG_RX_RUNTS 0x40000000
237 #define SIS_RXCFG_RX_GIANTS 0x80000000
238
239 #define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH)
240
241 #define SIS_RXDMA_512BYTES 0x00000000
242 #define SIS_RXDMA_4BYTES 0x00100000
243 #define SIS_RXDMA_8BYTES 0x00200000
244 #define SIS_RXDMA_16BYTES 0x00300000
245 #define SIS_RXDMA_32BYTES 0x00400000
246 #define SIS_RXDMA_64BYTES 0x00500000
247 #define SIS_RXDMA_128BYTES 0x00600000
248 #define SIS_RXDMA_256BYTES 0x00700000
249
250 #define SIS_RXCFG \
251 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES)
252
253 #define SIS_RXFILTCTL_ADDR 0x000F0000
254 #define NS_RXFILTCTL_MCHASH 0x00200000
255 #define NS_RXFILTCTL_ARP 0x00400000
256 #define NS_RXFILTCTL_PERFECT 0x08000000
257 #define SIS_RXFILTCTL_ALLPHYS 0x10000000
258 #define SIS_RXFILTCTL_ALLMULTI 0x20000000
259 #define SIS_RXFILTCTL_BROAD 0x40000000
260 #define SIS_RXFILTCTL_ENABLE 0x80000000
261
262 #define SIS_FILTADDR_PAR0 0x00000000
263 #define SIS_FILTADDR_PAR1 0x00010000
264 #define SIS_FILTADDR_PAR2 0x00020000
265 #define SIS_FILTADDR_MAR0 0x00040000
266 #define SIS_FILTADDR_MAR1 0x00050000
267 #define SIS_FILTADDR_MAR2 0x00060000
268 #define SIS_FILTADDR_MAR3 0x00070000
269 #define SIS_FILTADDR_MAR4 0x00080000
270 #define SIS_FILTADDR_MAR5 0x00090000
271 #define SIS_FILTADDR_MAR6 0x000A0000
272 #define SIS_FILTADDR_MAR7 0x000B0000
273
274 #define NS_FILTADDR_PAR0 0x00000000
275 #define NS_FILTADDR_PAR1 0x00000002
276 #define NS_FILTADDR_PAR2 0x00000004
277
278 #define NS_FILTADDR_FMEM_LO 0x00000200
279 #define NS_FILTADDR_FMEM_HI 0x000003FE
280
281 /*
282 * DMA descriptor structures. The first part of the descriptor
283 * is the hardware descriptor format, which is just three longwords.
284 * After this, we include some additional structure members for
285 * use by the driver. Note that for this structure will be a different
286 * size on the alpha, but that's okay as long as it's a multiple of 4
287 * bytes in size.
288 */
289 struct sis_desc {
290 /* SiS hardware descriptor section */
291 u_int32_t sis_next;
292 u_int32_t sis_cmdsts;
293 #define sis_rxstat sis_cmdsts
294 #define sis_txstat sis_cmdsts
295 #define sis_ctl sis_cmdsts
296 u_int32_t sis_ptr;
297 /* Driver software section */
298 struct mbuf *sis_mbuf;
299 struct sis_desc *sis_nextdesc;
300 bus_dmamap_t sis_map;
301 };
302
303 #define SIS_CMDSTS_BUFLEN 0x00000FFF
304 #define SIS_CMDSTS_PKT_OK 0x08000000
305 #define SIS_CMDSTS_CRC 0x10000000
306 #define SIS_CMDSTS_INTR 0x20000000
307 #define SIS_CMDSTS_MORE 0x40000000
308 #define SIS_CMDSTS_OWN 0x80000000
309
310 #define SIS_LASTDESC(x) (!((x)->sis_ctl & SIS_CMDSTS_MORE)))
311 #define SIS_OWNDESC(x) ((x)->sis_ctl & SIS_CMDSTS_OWN)
312 #define SIS_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1
313 #define SIS_RXBYTES(x) (((x)->sis_ctl & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN)
314
315 #define SIS_RXSTAT_COLL 0x00010000
316 #define SIS_RXSTAT_LOOPBK 0x00020000
317 #define SIS_RXSTAT_ALIGNERR 0x00040000
318 #define SIS_RXSTAT_CRCERR 0x00080000
319 #define SIS_RXSTAT_SYMBOLERR 0x00100000
320 #define SIS_RXSTAT_RUNT 0x00200000
321 #define SIS_RXSTAT_GIANT 0x00400000
322 #define SIS_RXSTAT_DSTCLASS 0x01800000
323 #define SIS_RXSTAT_OVERRUN 0x02000000
324 #define SIS_RXSTAT_RX_ABORT 0x04000000
325
326 #define SIS_DSTCLASS_REJECT 0x00000000
327 #define SIS_DSTCLASS_UNICAST 0x00800000
328 #define SIS_DSTCLASS_MULTICAST 0x01000000
329 #define SIS_DSTCLASS_BROADCAST 0x02000000
330
331 #define SIS_TXSTAT_COLLCNT 0x000F0000
332 #define SIS_TXSTAT_EXCESSCOLLS 0x00100000
333 #define SIS_TXSTAT_OUTOFWINCOLL 0x00200000
334 #define SIS_TXSTAT_EXCESS_DEFER 0x00400000
335 #define SIS_TXSTAT_DEFERED 0x00800000
336 #define SIS_TXSTAT_CARR_LOST 0x01000000
337 #define SIS_TXSTAT_UNDERRUN 0x02000000
338 #define SIS_TXSTAT_TX_ABORT 0x04000000
339
340 #define SIS_RX_LIST_CNT 64
341 #define SIS_TX_LIST_CNT 128
342
343 #define SIS_RX_LIST_SZ SIS_RX_LIST_CNT * sizeof(struct sis_desc)
344 #define SIS_TX_LIST_SZ SIS_TX_LIST_CNT * sizeof(struct sis_desc)
345
346 struct sis_list_data {
347 #ifdef foo
348 struct sis_desc sis_rx_list[SIS_RX_LIST_CNT];
349 struct sis_desc sis_tx_list[SIS_TX_LIST_CNT];
350 #endif
351 struct sis_desc *sis_rx_list;
352 struct sis_desc *sis_tx_list;
353 bus_dma_tag_t sis_rx_tag;
354 bus_dmamap_t sis_rx_dmamap;
355 bus_dma_tag_t sis_tx_tag;
356 bus_dmamap_t sis_tx_dmamap;
357 };
358
359 struct sis_ring_data {
360 int sis_rx_prod;
361 int sis_tx_prod;
362 int sis_tx_cons;
363 int sis_tx_cnt;
364 u_int32_t sis_rx_paddr;
365 u_int32_t sis_tx_paddr;
366 };
367
368
369 /*
370 * SiS PCI vendor ID.
371 */
372 #define SIS_VENDORID 0x1039
373
374 /*
375 * SiS PCI device IDs
376 */
377 #define SIS_DEVICEID_900 0x0900
378 #define SIS_DEVICEID_7016 0x7016
379
380 /*
381 * SiS 900 PCI revision codes.
382 */
383 #define SIS_REV_630E 0x0081
384 #define SIS_REV_630S 0x0082
385 #define SIS_REV_630EA1 0x0083
386 #define SIS_REV_630ET 0x0084
387 #define SIS_REV_635 0x0090
388
389 /*
390 * NatSemi vendor ID
391 */
392 #define NS_VENDORID 0x100B
393
394 /*
395 * DP83815 device ID
396 */
397 #define NS_DEVICEID_DP83815 0x0020
398
399 struct sis_type {
400 u_int16_t sis_vid;
401 u_int16_t sis_did;
402 char *sis_name;
403 };
404
405 #define SIS_TYPE_900 1
406 #define SIS_TYPE_7016 2
407 #define SIS_TYPE_83815 3
408
409 struct sis_softc {
410 struct arpcom arpcom; /* interface info */
411 bus_space_handle_t sis_bhandle;
412 bus_space_tag_t sis_btag;
413 struct resource *sis_res;
414 struct resource *sis_irq;
415 void *sis_intrhand;
416 device_t sis_miibus;
417 u_int8_t sis_unit;
418 u_int8_t sis_type;
419 u_int8_t sis_rev;
420 u_int8_t sis_link;
421 struct sis_list_data sis_ldata;
422 bus_dma_tag_t sis_parent_tag;
423 bus_dma_tag_t sis_tag;
424 struct sis_ring_data sis_cdata;
425 struct callout_handle sis_stat_ch;
426 #ifdef DEVICE_POLLING
427 int rxcycles;
428 #endif
429 struct mtx sis_mtx;
430 };
431
432 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
433 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
434
435 /*
436 * register space access macros
437 */
438 #define CSR_WRITE_4(sc, reg, val) \
439 bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val)
440
441 #define CSR_READ_4(sc, reg) \
442 bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg)
443
444 #define CSR_READ_2(sc, reg) \
445 bus_space_read_2(sc->sis_btag, sc->sis_bhandle, reg)
446
447 #define SIS_TIMEOUT 1000
448 #define ETHER_ALIGN 2
449 #define SIS_RXLEN 1536
450 #define SIS_MIN_FRAMELEN 60
451
452 /*
453 * PCI low memory base and low I/O base register, and
454 * other PCI registers.
455 */
456
457 #define SIS_PCI_VENDOR_ID 0x00
458 #define SIS_PCI_DEVICE_ID 0x02
459 #define SIS_PCI_COMMAND 0x04
460 #define SIS_PCI_STATUS 0x06
461 #define SIS_PCI_REVID 0x08
462 #define SIS_PCI_CLASSCODE 0x09
463 #define SIS_PCI_CACHELEN 0x0C
464 #define SIS_PCI_LATENCY_TIMER 0x0D
465 #define SIS_PCI_HEADER_TYPE 0x0E
466 #define SIS_PCI_LOIO 0x10
467 #define SIS_PCI_LOMEM 0x14
468 #define SIS_PCI_BIOSROM 0x30
469 #define SIS_PCI_INTLINE 0x3C
470 #define SIS_PCI_INTPIN 0x3D
471 #define SIS_PCI_MINGNT 0x3E
472 #define SIS_PCI_MINLAT 0x0F
473 #define SIS_PCI_RESETOPT 0x48
474 #define SIS_PCI_EEPROM_DATA 0x4C
475
476 /* power management registers */
477 #define SIS_PCI_CAPID 0x50 /* 8 bits */
478 #define SIS_PCI_NEXTPTR 0x51 /* 8 bits */
479 #define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */
480 #define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
481
482 #define SIS_PSTATE_MASK 0x0003
483 #define SIS_PSTATE_D0 0x0000
484 #define SIS_PSTATE_D1 0x0001
485 #define SIS_PSTATE_D2 0x0002
486 #define SIS_PSTATE_D3 0x0003
487 #define SIS_PME_EN 0x0010
488 #define SIS_PME_STATUS 0x8000
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