FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sk.c
1 /*
2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: releng/5.0/sys/pci/if_sk.c 106936 2002-11-14 23:49:09Z sam $
33 */
34
35 /*
36 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
37 * the SK-984x series adapters, both single port and dual port.
38 * References:
39 * The XaQti XMAC II datasheet,
40 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
41 * The SysKonnect GEnesis manual, http://www.syskonnect.com
42 *
43 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
44 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
45 * convenience to others until Vitesse corrects this problem:
46 *
47 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
48 *
49 * Written by Bill Paul <wpaul@ee.columbia.edu>
50 * Department of Electrical Engineering
51 * Columbia University, New York City
52 */
53
54 /*
55 * The SysKonnect gigabit ethernet adapters consist of two main
56 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
57 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
58 * components and a PHY while the GEnesis controller provides a PCI
59 * interface with DMA support. Each card may have between 512K and
60 * 2MB of SRAM on board depending on the configuration.
61 *
62 * The SysKonnect GEnesis controller can have either one or two XMAC
63 * chips connected to it, allowing single or dual port NIC configurations.
64 * SysKonnect has the distinction of being the only vendor on the market
65 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
66 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
67 * XMAC registers. This driver takes advantage of these features to allow
68 * both XMACs to operate as independent interfaces.
69 */
70
71 #include <sys/param.h>
72 #include <sys/systm.h>
73 #include <sys/sockio.h>
74 #include <sys/mbuf.h>
75 #include <sys/malloc.h>
76 #include <sys/kernel.h>
77 #include <sys/socket.h>
78 #include <sys/queue.h>
79
80 #include <net/if.h>
81 #include <net/if_arp.h>
82 #include <net/ethernet.h>
83 #include <net/if_dl.h>
84 #include <net/if_media.h>
85
86 #include <net/bpf.h>
87
88 #include <vm/vm.h> /* for vtophys */
89 #include <vm/pmap.h> /* for vtophys */
90 #include <machine/bus_pio.h>
91 #include <machine/bus_memio.h>
92 #include <machine/bus.h>
93 #include <machine/resource.h>
94 #include <sys/bus.h>
95 #include <sys/rman.h>
96
97 #include <dev/mii/mii.h>
98 #include <dev/mii/miivar.h>
99 #include <dev/mii/brgphyreg.h>
100
101 #include <pci/pcireg.h>
102 #include <pci/pcivar.h>
103
104 #define SK_USEIOSPACE
105
106 #include <pci/if_skreg.h>
107 #include <pci/xmaciireg.h>
108
109 MODULE_DEPEND(sk, miibus, 1, 1, 1);
110
111 /* "controller miibus0" required. See GENERIC if you get errors here. */
112 #include "miibus_if.h"
113
114 #ifndef lint
115 static const char rcsid[] =
116 "$FreeBSD: releng/5.0/sys/pci/if_sk.c 106936 2002-11-14 23:49:09Z sam $";
117 #endif
118
119 static struct sk_type sk_devs[] = {
120 { SK_VENDORID, SK_DEVICEID_GE, "SysKonnect Gigabit Ethernet" },
121 { 0, 0, NULL }
122 };
123
124 static int sk_probe (device_t);
125 static int sk_attach (device_t);
126 static int sk_detach (device_t);
127 static int sk_detach_xmac (device_t);
128 static int sk_probe_xmac (device_t);
129 static int sk_attach_xmac (device_t);
130 static void sk_tick (void *);
131 static void sk_intr (void *);
132 static void sk_intr_xmac (struct sk_if_softc *);
133 static void sk_intr_bcom (struct sk_if_softc *);
134 static void sk_rxeof (struct sk_if_softc *);
135 static void sk_txeof (struct sk_if_softc *);
136 static int sk_encap (struct sk_if_softc *, struct mbuf *,
137 u_int32_t *);
138 static void sk_start (struct ifnet *);
139 static int sk_ioctl (struct ifnet *, u_long, caddr_t);
140 static void sk_init (void *);
141 static void sk_init_xmac (struct sk_if_softc *);
142 static void sk_stop (struct sk_if_softc *);
143 static void sk_watchdog (struct ifnet *);
144 static void sk_shutdown (device_t);
145 static int sk_ifmedia_upd (struct ifnet *);
146 static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *);
147 static void sk_reset (struct sk_softc *);
148 static int sk_newbuf (struct sk_if_softc *,
149 struct sk_chain *, struct mbuf *);
150 static int sk_alloc_jumbo_mem (struct sk_if_softc *);
151 static void *sk_jalloc (struct sk_if_softc *);
152 static void sk_jfree (void *, void *);
153 static int sk_init_rx_ring (struct sk_if_softc *);
154 static void sk_init_tx_ring (struct sk_if_softc *);
155 static u_int32_t sk_win_read_4 (struct sk_softc *, int);
156 static u_int16_t sk_win_read_2 (struct sk_softc *, int);
157 static u_int8_t sk_win_read_1 (struct sk_softc *, int);
158 static void sk_win_write_4 (struct sk_softc *, int, u_int32_t);
159 static void sk_win_write_2 (struct sk_softc *, int, u_int32_t);
160 static void sk_win_write_1 (struct sk_softc *, int, u_int32_t);
161 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int);
162 static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int);
163 static void sk_vpd_read (struct sk_softc *);
164
165 static int sk_miibus_readreg (device_t, int, int);
166 static int sk_miibus_writereg (device_t, int, int, int);
167 static void sk_miibus_statchg (device_t);
168
169 static u_int32_t sk_calchash (caddr_t);
170 static void sk_setfilt (struct sk_if_softc *, caddr_t, int);
171 static void sk_setmulti (struct sk_if_softc *);
172
173 #ifdef SK_USEIOSPACE
174 #define SK_RES SYS_RES_IOPORT
175 #define SK_RID SK_PCI_LOIO
176 #else
177 #define SK_RES SYS_RES_MEMORY
178 #define SK_RID SK_PCI_LOMEM
179 #endif
180
181 /*
182 * Note that we have newbus methods for both the GEnesis controller
183 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
184 * the miibus code is a child of the XMACs. We need to do it this way
185 * so that the miibus drivers can access the PHY registers on the
186 * right PHY. It's not quite what I had in mind, but it's the only
187 * design that achieves the desired effect.
188 */
189 static device_method_t skc_methods[] = {
190 /* Device interface */
191 DEVMETHOD(device_probe, sk_probe),
192 DEVMETHOD(device_attach, sk_attach),
193 DEVMETHOD(device_detach, sk_detach),
194 DEVMETHOD(device_shutdown, sk_shutdown),
195
196 /* bus interface */
197 DEVMETHOD(bus_print_child, bus_generic_print_child),
198 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
199
200 { 0, 0 }
201 };
202
203 static driver_t skc_driver = {
204 "skc",
205 skc_methods,
206 sizeof(struct sk_softc)
207 };
208
209 static devclass_t skc_devclass;
210
211 static device_method_t sk_methods[] = {
212 /* Device interface */
213 DEVMETHOD(device_probe, sk_probe_xmac),
214 DEVMETHOD(device_attach, sk_attach_xmac),
215 DEVMETHOD(device_detach, sk_detach_xmac),
216 DEVMETHOD(device_shutdown, bus_generic_shutdown),
217
218 /* bus interface */
219 DEVMETHOD(bus_print_child, bus_generic_print_child),
220 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
221
222 /* MII interface */
223 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
224 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
225 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
226
227 { 0, 0 }
228 };
229
230 static driver_t sk_driver = {
231 "sk",
232 sk_methods,
233 sizeof(struct sk_if_softc)
234 };
235
236 static devclass_t sk_devclass;
237
238 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
239 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0);
240 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
241
242 #define SK_SETBIT(sc, reg, x) \
243 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
244
245 #define SK_CLRBIT(sc, reg, x) \
246 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
247
248 #define SK_WIN_SETBIT_4(sc, reg, x) \
249 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
250
251 #define SK_WIN_CLRBIT_4(sc, reg, x) \
252 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
253
254 #define SK_WIN_SETBIT_2(sc, reg, x) \
255 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
256
257 #define SK_WIN_CLRBIT_2(sc, reg, x) \
258 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
259
260 static u_int32_t
261 sk_win_read_4(sc, reg)
262 struct sk_softc *sc;
263 int reg;
264 {
265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
266 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
267 }
268
269 static u_int16_t
270 sk_win_read_2(sc, reg)
271 struct sk_softc *sc;
272 int reg;
273 {
274 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
275 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
276 }
277
278 static u_int8_t
279 sk_win_read_1(sc, reg)
280 struct sk_softc *sc;
281 int reg;
282 {
283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
284 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
285 }
286
287 static void
288 sk_win_write_4(sc, reg, val)
289 struct sk_softc *sc;
290 int reg;
291 u_int32_t val;
292 {
293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
294 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
295 return;
296 }
297
298 static void
299 sk_win_write_2(sc, reg, val)
300 struct sk_softc *sc;
301 int reg;
302 u_int32_t val;
303 {
304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
305 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val);
306 return;
307 }
308
309 static void
310 sk_win_write_1(sc, reg, val)
311 struct sk_softc *sc;
312 int reg;
313 u_int32_t val;
314 {
315 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
316 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
317 return;
318 }
319
320 /*
321 * The VPD EEPROM contains Vital Product Data, as suggested in
322 * the PCI 2.1 specification. The VPD data is separared into areas
323 * denoted by resource IDs. The SysKonnect VPD contains an ID string
324 * resource (the name of the adapter), a read-only area resource
325 * containing various key/data fields and a read/write area which
326 * can be used to store asset management information or log messages.
327 * We read the ID string and read-only into buffers attached to
328 * the controller softc structure for later use. At the moment,
329 * we only use the ID string during sk_attach().
330 */
331 static u_int8_t
332 sk_vpd_readbyte(sc, addr)
333 struct sk_softc *sc;
334 int addr;
335 {
336 int i;
337
338 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
339 for (i = 0; i < SK_TIMEOUT; i++) {
340 DELAY(1);
341 if (sk_win_read_2(sc,
342 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
343 break;
344 }
345
346 if (i == SK_TIMEOUT)
347 return(0);
348
349 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
350 }
351
352 static void
353 sk_vpd_read_res(sc, res, addr)
354 struct sk_softc *sc;
355 struct vpd_res *res;
356 int addr;
357 {
358 int i;
359 u_int8_t *ptr;
360
361 ptr = (u_int8_t *)res;
362 for (i = 0; i < sizeof(struct vpd_res); i++)
363 ptr[i] = sk_vpd_readbyte(sc, i + addr);
364
365 return;
366 }
367
368 static void
369 sk_vpd_read(sc)
370 struct sk_softc *sc;
371 {
372 int pos = 0, i;
373 struct vpd_res res;
374
375 if (sc->sk_vpd_prodname != NULL)
376 free(sc->sk_vpd_prodname, M_DEVBUF);
377 if (sc->sk_vpd_readonly != NULL)
378 free(sc->sk_vpd_readonly, M_DEVBUF);
379 sc->sk_vpd_prodname = NULL;
380 sc->sk_vpd_readonly = NULL;
381
382 sk_vpd_read_res(sc, &res, pos);
383
384 if (res.vr_id != VPD_RES_ID) {
385 printf("skc%d: bad VPD resource id: expected %x got %x\n",
386 sc->sk_unit, VPD_RES_ID, res.vr_id);
387 return;
388 }
389
390 pos += sizeof(res);
391 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
392 for (i = 0; i < res.vr_len; i++)
393 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
394 sc->sk_vpd_prodname[i] = '\0';
395 pos += i;
396
397 sk_vpd_read_res(sc, &res, pos);
398
399 if (res.vr_id != VPD_RES_READ) {
400 printf("skc%d: bad VPD resource id: expected %x got %x\n",
401 sc->sk_unit, VPD_RES_READ, res.vr_id);
402 return;
403 }
404
405 pos += sizeof(res);
406 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
407 for (i = 0; i < res.vr_len + 1; i++)
408 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
409
410 return;
411 }
412
413 static int
414 sk_miibus_readreg(dev, phy, reg)
415 device_t dev;
416 int phy, reg;
417 {
418 struct sk_if_softc *sc_if;
419 int i;
420
421 sc_if = device_get_softc(dev);
422
423 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
424 return(0);
425
426 SK_IF_LOCK(sc_if);
427
428 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
429 SK_XM_READ_2(sc_if, XM_PHY_DATA);
430 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
431 for (i = 0; i < SK_TIMEOUT; i++) {
432 DELAY(1);
433 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
434 XM_MMUCMD_PHYDATARDY)
435 break;
436 }
437
438 if (i == SK_TIMEOUT) {
439 printf("sk%d: phy failed to come ready\n",
440 sc_if->sk_unit);
441 return(0);
442 }
443 }
444 DELAY(1);
445 i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
446 SK_IF_UNLOCK(sc_if);
447 return(i);
448 }
449
450 static int
451 sk_miibus_writereg(dev, phy, reg, val)
452 device_t dev;
453 int phy, reg, val;
454 {
455 struct sk_if_softc *sc_if;
456 int i;
457
458 sc_if = device_get_softc(dev);
459 SK_IF_LOCK(sc_if);
460
461 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
462 for (i = 0; i < SK_TIMEOUT; i++) {
463 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
464 break;
465 }
466
467 if (i == SK_TIMEOUT) {
468 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
469 return(ETIMEDOUT);
470 }
471
472 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
473 for (i = 0; i < SK_TIMEOUT; i++) {
474 DELAY(1);
475 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
476 break;
477 }
478
479 SK_IF_UNLOCK(sc_if);
480
481 if (i == SK_TIMEOUT)
482 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
483
484 return(0);
485 }
486
487 static void
488 sk_miibus_statchg(dev)
489 device_t dev;
490 {
491 struct sk_if_softc *sc_if;
492 struct mii_data *mii;
493
494 sc_if = device_get_softc(dev);
495 mii = device_get_softc(sc_if->sk_miibus);
496 SK_IF_LOCK(sc_if);
497 /*
498 * If this is a GMII PHY, manually set the XMAC's
499 * duplex mode accordingly.
500 */
501 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
502 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
503 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
504 } else {
505 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
506 }
507 }
508 SK_IF_UNLOCK(sc_if);
509
510 return;
511 }
512
513 #define SK_POLY 0xEDB88320
514 #define SK_BITS 6
515
516 static u_int32_t
517 sk_calchash(addr)
518 caddr_t addr;
519 {
520 u_int32_t idx, bit, data, crc;
521
522 /* Compute CRC for the address value. */
523 crc = 0xFFFFFFFF; /* initial value */
524
525 for (idx = 0; idx < 6; idx++) {
526 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
527 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0);
528 }
529
530 return (~crc & ((1 << SK_BITS) - 1));
531 }
532
533 static void
534 sk_setfilt(sc_if, addr, slot)
535 struct sk_if_softc *sc_if;
536 caddr_t addr;
537 int slot;
538 {
539 int base;
540
541 base = XM_RXFILT_ENTRY(slot);
542
543 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
544 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
545 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
546
547 return;
548 }
549
550 static void
551 sk_setmulti(sc_if)
552 struct sk_if_softc *sc_if;
553 {
554 struct ifnet *ifp;
555 u_int32_t hashes[2] = { 0, 0 };
556 int h, i;
557 struct ifmultiaddr *ifma;
558 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
559
560 ifp = &sc_if->arpcom.ac_if;
561
562 /* First, zot all the existing filters. */
563 for (i = 1; i < XM_RXFILT_MAX; i++)
564 sk_setfilt(sc_if, (caddr_t)&dummy, i);
565 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
566 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
567
568 /* Now program new ones. */
569 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
570 hashes[0] = 0xFFFFFFFF;
571 hashes[1] = 0xFFFFFFFF;
572 } else {
573 i = 1;
574 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
575 if (ifma->ifma_addr->sa_family != AF_LINK)
576 continue;
577 /*
578 * Program the first XM_RXFILT_MAX multicast groups
579 * into the perfect filter. For all others,
580 * use the hash table.
581 */
582 if (i < XM_RXFILT_MAX) {
583 sk_setfilt(sc_if,
584 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
585 i++;
586 continue;
587 }
588
589 h = sk_calchash(
590 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
591 if (h < 32)
592 hashes[0] |= (1 << h);
593 else
594 hashes[1] |= (1 << (h - 32));
595 }
596 }
597
598 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
599 XM_MODE_RX_USE_PERFECT);
600 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
601 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
602
603 return;
604 }
605
606 static int
607 sk_init_rx_ring(sc_if)
608 struct sk_if_softc *sc_if;
609 {
610 struct sk_chain_data *cd;
611 struct sk_ring_data *rd;
612 int i;
613
614 cd = &sc_if->sk_cdata;
615 rd = sc_if->sk_rdata;
616
617 bzero((char *)rd->sk_rx_ring,
618 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
619
620 for (i = 0; i < SK_RX_RING_CNT; i++) {
621 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
622 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
623 return(ENOBUFS);
624 if (i == (SK_RX_RING_CNT - 1)) {
625 cd->sk_rx_chain[i].sk_next =
626 &cd->sk_rx_chain[0];
627 rd->sk_rx_ring[i].sk_next =
628 vtophys(&rd->sk_rx_ring[0]);
629 } else {
630 cd->sk_rx_chain[i].sk_next =
631 &cd->sk_rx_chain[i + 1];
632 rd->sk_rx_ring[i].sk_next =
633 vtophys(&rd->sk_rx_ring[i + 1]);
634 }
635 }
636
637 sc_if->sk_cdata.sk_rx_prod = 0;
638 sc_if->sk_cdata.sk_rx_cons = 0;
639
640 return(0);
641 }
642
643 static void
644 sk_init_tx_ring(sc_if)
645 struct sk_if_softc *sc_if;
646 {
647 struct sk_chain_data *cd;
648 struct sk_ring_data *rd;
649 int i;
650
651 cd = &sc_if->sk_cdata;
652 rd = sc_if->sk_rdata;
653
654 bzero((char *)sc_if->sk_rdata->sk_tx_ring,
655 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
656
657 for (i = 0; i < SK_TX_RING_CNT; i++) {
658 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
659 if (i == (SK_TX_RING_CNT - 1)) {
660 cd->sk_tx_chain[i].sk_next =
661 &cd->sk_tx_chain[0];
662 rd->sk_tx_ring[i].sk_next =
663 vtophys(&rd->sk_tx_ring[0]);
664 } else {
665 cd->sk_tx_chain[i].sk_next =
666 &cd->sk_tx_chain[i + 1];
667 rd->sk_tx_ring[i].sk_next =
668 vtophys(&rd->sk_tx_ring[i + 1]);
669 }
670 }
671
672 sc_if->sk_cdata.sk_tx_prod = 0;
673 sc_if->sk_cdata.sk_tx_cons = 0;
674 sc_if->sk_cdata.sk_tx_cnt = 0;
675
676 return;
677 }
678
679 static int
680 sk_newbuf(sc_if, c, m)
681 struct sk_if_softc *sc_if;
682 struct sk_chain *c;
683 struct mbuf *m;
684 {
685 struct mbuf *m_new = NULL;
686 struct sk_rx_desc *r;
687
688 if (m == NULL) {
689 caddr_t *buf = NULL;
690
691 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
692 if (m_new == NULL)
693 return(ENOBUFS);
694
695 /* Allocate the jumbo buffer */
696 buf = sk_jalloc(sc_if);
697 if (buf == NULL) {
698 m_freem(m_new);
699 #ifdef SK_VERBOSE
700 printf("sk%d: jumbo allocation failed "
701 "-- packet dropped!\n", sc_if->sk_unit);
702 #endif
703 return(ENOBUFS);
704 }
705
706 /* Attach the buffer to the mbuf */
707 MEXTADD(m_new, buf, SK_JLEN, sk_jfree,
708 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV);
709 m_new->m_data = (void *)buf;
710 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN;
711 } else {
712 /*
713 * We're re-using a previously allocated mbuf;
714 * be sure to re-init pointers and lengths to
715 * default values.
716 */
717 m_new = m;
718 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
719 m_new->m_data = m_new->m_ext.ext_buf;
720 }
721
722 /*
723 * Adjust alignment so packet payload begins on a
724 * longword boundary. Mandatory for Alpha, useful on
725 * x86 too.
726 */
727 m_adj(m_new, ETHER_ALIGN);
728
729 r = c->sk_desc;
730 c->sk_mbuf = m_new;
731 r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
732 r->sk_ctl = m_new->m_len | SK_RXSTAT;
733
734 return(0);
735 }
736
737 /*
738 * Allocate jumbo buffer storage. The SysKonnect adapters support
739 * "jumbograms" (9K frames), although SysKonnect doesn't currently
740 * use them in their drivers. In order for us to use them, we need
741 * large 9K receive buffers, however standard mbuf clusters are only
742 * 2048 bytes in size. Consequently, we need to allocate and manage
743 * our own jumbo buffer pool. Fortunately, this does not require an
744 * excessive amount of additional code.
745 */
746 static int
747 sk_alloc_jumbo_mem(sc_if)
748 struct sk_if_softc *sc_if;
749 {
750 caddr_t ptr;
751 register int i;
752 struct sk_jpool_entry *entry;
753
754 /* Grab a big chunk o' storage. */
755 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
756 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
757
758 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
759 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
760 return(ENOBUFS);
761 }
762
763 SLIST_INIT(&sc_if->sk_jfree_listhead);
764 SLIST_INIT(&sc_if->sk_jinuse_listhead);
765
766 /*
767 * Now divide it up into 9K pieces and save the addresses
768 * in an array.
769 */
770 ptr = sc_if->sk_cdata.sk_jumbo_buf;
771 for (i = 0; i < SK_JSLOTS; i++) {
772 sc_if->sk_cdata.sk_jslots[i] = ptr;
773 ptr += SK_JLEN;
774 entry = malloc(sizeof(struct sk_jpool_entry),
775 M_DEVBUF, M_NOWAIT);
776 if (entry == NULL) {
777 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF);
778 sc_if->sk_cdata.sk_jumbo_buf = NULL;
779 printf("sk%d: no memory for jumbo "
780 "buffer queue!\n", sc_if->sk_unit);
781 return(ENOBUFS);
782 }
783 entry->slot = i;
784 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
785 entry, jpool_entries);
786 }
787
788 return(0);
789 }
790
791 /*
792 * Allocate a jumbo buffer.
793 */
794 static void *
795 sk_jalloc(sc_if)
796 struct sk_if_softc *sc_if;
797 {
798 struct sk_jpool_entry *entry;
799
800 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
801
802 if (entry == NULL) {
803 #ifdef SK_VERBOSE
804 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
805 #endif
806 return(NULL);
807 }
808
809 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
810 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
811 return(sc_if->sk_cdata.sk_jslots[entry->slot]);
812 }
813
814 /*
815 * Release a jumbo buffer.
816 */
817 static void
818 sk_jfree(buf, args)
819 void *buf;
820 void *args;
821 {
822 struct sk_if_softc *sc_if;
823 int i;
824 struct sk_jpool_entry *entry;
825
826 /* Extract the softc struct pointer. */
827 sc_if = (struct sk_if_softc *)args;
828
829 if (sc_if == NULL)
830 panic("sk_jfree: didn't get softc pointer!");
831
832 /* calculate the slot this buffer belongs to */
833 i = ((vm_offset_t)buf
834 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
835
836 if ((i < 0) || (i >= SK_JSLOTS))
837 panic("sk_jfree: asked to free buffer that we don't manage!");
838
839 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
840 if (entry == NULL)
841 panic("sk_jfree: buffer not in use!");
842 entry->slot = i;
843 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries);
844 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries);
845
846 return;
847 }
848
849 /*
850 * Set media options.
851 */
852 static int
853 sk_ifmedia_upd(ifp)
854 struct ifnet *ifp;
855 {
856 struct sk_if_softc *sc_if;
857 struct mii_data *mii;
858
859 sc_if = ifp->if_softc;
860 mii = device_get_softc(sc_if->sk_miibus);
861 sk_init(sc_if);
862 mii_mediachg(mii);
863
864 return(0);
865 }
866
867 /*
868 * Report current media status.
869 */
870 static void
871 sk_ifmedia_sts(ifp, ifmr)
872 struct ifnet *ifp;
873 struct ifmediareq *ifmr;
874 {
875 struct sk_if_softc *sc_if;
876 struct mii_data *mii;
877
878 sc_if = ifp->if_softc;
879 mii = device_get_softc(sc_if->sk_miibus);
880
881 mii_pollstat(mii);
882 ifmr->ifm_active = mii->mii_media_active;
883 ifmr->ifm_status = mii->mii_media_status;
884
885 return;
886 }
887
888 static int
889 sk_ioctl(ifp, command, data)
890 struct ifnet *ifp;
891 u_long command;
892 caddr_t data;
893 {
894 struct sk_if_softc *sc_if = ifp->if_softc;
895 struct ifreq *ifr = (struct ifreq *) data;
896 int error = 0;
897 struct mii_data *mii;
898
899 SK_IF_LOCK(sc_if);
900
901 switch(command) {
902 case SIOCSIFMTU:
903 if (ifr->ifr_mtu > SK_JUMBO_MTU)
904 error = EINVAL;
905 else {
906 ifp->if_mtu = ifr->ifr_mtu;
907 sk_init(sc_if);
908 }
909 break;
910 case SIOCSIFFLAGS:
911 if (ifp->if_flags & IFF_UP) {
912 if (ifp->if_flags & IFF_RUNNING &&
913 ifp->if_flags & IFF_PROMISC &&
914 !(sc_if->sk_if_flags & IFF_PROMISC)) {
915 SK_XM_SETBIT_4(sc_if, XM_MODE,
916 XM_MODE_RX_PROMISC);
917 sk_setmulti(sc_if);
918 } else if (ifp->if_flags & IFF_RUNNING &&
919 !(ifp->if_flags & IFF_PROMISC) &&
920 sc_if->sk_if_flags & IFF_PROMISC) {
921 SK_XM_CLRBIT_4(sc_if, XM_MODE,
922 XM_MODE_RX_PROMISC);
923 sk_setmulti(sc_if);
924 } else
925 sk_init(sc_if);
926 } else {
927 if (ifp->if_flags & IFF_RUNNING)
928 sk_stop(sc_if);
929 }
930 sc_if->sk_if_flags = ifp->if_flags;
931 error = 0;
932 break;
933 case SIOCADDMULTI:
934 case SIOCDELMULTI:
935 sk_setmulti(sc_if);
936 error = 0;
937 break;
938 case SIOCGIFMEDIA:
939 case SIOCSIFMEDIA:
940 mii = device_get_softc(sc_if->sk_miibus);
941 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
942 break;
943 default:
944 error = ether_ioctl(ifp, command, data);
945 break;
946 }
947
948 SK_IF_UNLOCK(sc_if);
949
950 return(error);
951 }
952
953 /*
954 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
955 * IDs against our list and return a device name if we find a match.
956 */
957 static int
958 sk_probe(dev)
959 device_t dev;
960 {
961 struct sk_type *t;
962
963 t = sk_devs;
964
965 while(t->sk_name != NULL) {
966 if ((pci_get_vendor(dev) == t->sk_vid) &&
967 (pci_get_device(dev) == t->sk_did)) {
968 device_set_desc(dev, t->sk_name);
969 return(0);
970 }
971 t++;
972 }
973
974 return(ENXIO);
975 }
976
977 /*
978 * Force the GEnesis into reset, then bring it out of reset.
979 */
980 static void
981 sk_reset(sc)
982 struct sk_softc *sc;
983 {
984 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET);
985 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET);
986 DELAY(1000);
987 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET);
988 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
989
990 /* Configure packet arbiter */
991 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
992 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
993 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
994 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
995 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
996
997 /* Enable RAM interface */
998 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
999
1000 /*
1001 * Configure interrupt moderation. The moderation timer
1002 * defers interrupts specified in the interrupt moderation
1003 * timer mask based on the timeout specified in the interrupt
1004 * moderation timer init register. Each bit in the timer
1005 * register represents 18.825ns, so to specify a timeout in
1006 * microseconds, we have to multiply by 54.
1007 */
1008 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1009 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1010 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1011 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1012
1013 return;
1014 }
1015
1016 static int
1017 sk_probe_xmac(dev)
1018 device_t dev;
1019 {
1020 /*
1021 * Not much to do here. We always know there will be
1022 * at least one XMAC present, and if there are two,
1023 * sk_attach() will create a second device instance
1024 * for us.
1025 */
1026 device_set_desc(dev, "XaQti Corp. XMAC II");
1027
1028 return(0);
1029 }
1030
1031 /*
1032 * Each XMAC chip is attached as a separate logical IP interface.
1033 * Single port cards will have only one logical interface of course.
1034 */
1035 static int
1036 sk_attach_xmac(dev)
1037 device_t dev;
1038 {
1039 struct sk_softc *sc;
1040 struct sk_if_softc *sc_if;
1041 struct ifnet *ifp;
1042 int i, port;
1043
1044 if (dev == NULL)
1045 return(EINVAL);
1046
1047 sc_if = device_get_softc(dev);
1048 sc = device_get_softc(device_get_parent(dev));
1049 SK_LOCK(sc);
1050 port = *(int *)device_get_ivars(dev);
1051 free(device_get_ivars(dev), M_DEVBUF);
1052 device_set_ivars(dev, NULL);
1053 sc_if->sk_dev = dev;
1054
1055 bzero((char *)sc_if, sizeof(struct sk_if_softc));
1056
1057 sc_if->sk_dev = dev;
1058 sc_if->sk_unit = device_get_unit(dev);
1059 sc_if->sk_port = port;
1060 sc_if->sk_softc = sc;
1061 sc->sk_if[port] = sc_if;
1062 if (port == SK_PORT_A)
1063 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1064 if (port == SK_PORT_B)
1065 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1066
1067 /*
1068 * Get station address for this interface. Note that
1069 * dual port cards actually come with three station
1070 * addresses: one for each port, plus an extra. The
1071 * extra one is used by the SysKonnect driver software
1072 * as a 'virtual' station address for when both ports
1073 * are operating in failover mode. Currently we don't
1074 * use this extra address.
1075 */
1076 for (i = 0; i < ETHER_ADDR_LEN; i++)
1077 sc_if->arpcom.ac_enaddr[i] =
1078 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1079
1080 printf("sk%d: Ethernet address: %6D\n",
1081 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":");
1082
1083 /*
1084 * Set up RAM buffer addresses. The NIC will have a certain
1085 * amount of SRAM on it, somewhere between 512K and 2MB. We
1086 * need to divide this up a) between the transmitter and
1087 * receiver and b) between the two XMACs, if this is a
1088 * dual port NIC. Our algotithm is to divide up the memory
1089 * evenly so that everyone gets a fair share.
1090 */
1091 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1092 u_int32_t chunk, val;
1093
1094 chunk = sc->sk_ramsize / 2;
1095 val = sc->sk_rboff / sizeof(u_int64_t);
1096 sc_if->sk_rx_ramstart = val;
1097 val += (chunk / sizeof(u_int64_t));
1098 sc_if->sk_rx_ramend = val - 1;
1099 sc_if->sk_tx_ramstart = val;
1100 val += (chunk / sizeof(u_int64_t));
1101 sc_if->sk_tx_ramend = val - 1;
1102 } else {
1103 u_int32_t chunk, val;
1104
1105 chunk = sc->sk_ramsize / 4;
1106 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1107 sizeof(u_int64_t);
1108 sc_if->sk_rx_ramstart = val;
1109 val += (chunk / sizeof(u_int64_t));
1110 sc_if->sk_rx_ramend = val - 1;
1111 sc_if->sk_tx_ramstart = val;
1112 val += (chunk / sizeof(u_int64_t));
1113 sc_if->sk_tx_ramend = val - 1;
1114 }
1115
1116 /* Read and save PHY type and set PHY address */
1117 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1118 switch(sc_if->sk_phytype) {
1119 case SK_PHYTYPE_XMAC:
1120 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1121 break;
1122 case SK_PHYTYPE_BCOM:
1123 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1124 break;
1125 default:
1126 printf("skc%d: unsupported PHY type: %d\n",
1127 sc->sk_unit, sc_if->sk_phytype);
1128 SK_UNLOCK(sc);
1129 return(ENODEV);
1130 }
1131
1132 /* Allocate the descriptor queues. */
1133 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1134 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1135
1136 if (sc_if->sk_rdata == NULL) {
1137 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1138 sc->sk_if[port] = NULL;
1139 SK_UNLOCK(sc);
1140 return(ENOMEM);
1141 }
1142
1143 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1144
1145 /* Try to allocate memory for jumbo buffers. */
1146 if (sk_alloc_jumbo_mem(sc_if)) {
1147 printf("sk%d: jumbo buffer allocation failed\n",
1148 sc_if->sk_unit);
1149 contigfree(sc_if->sk_rdata,
1150 sizeof(struct sk_ring_data), M_DEVBUF);
1151 sc->sk_if[port] = NULL;
1152 SK_UNLOCK(sc);
1153 return(ENOMEM);
1154 }
1155
1156 ifp = &sc_if->arpcom.ac_if;
1157 ifp->if_softc = sc_if;
1158 ifp->if_unit = sc_if->sk_unit;
1159 ifp->if_name = "sk";
1160 ifp->if_mtu = ETHERMTU;
1161 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1162 ifp->if_ioctl = sk_ioctl;
1163 ifp->if_output = ether_output;
1164 ifp->if_start = sk_start;
1165 ifp->if_watchdog = sk_watchdog;
1166 ifp->if_init = sk_init;
1167 ifp->if_baudrate = 1000000000;
1168 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1;
1169
1170 /*
1171 * Call MI attach routine.
1172 */
1173 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr);
1174 callout_handle_init(&sc_if->sk_tick_ch);
1175
1176 /*
1177 * Do miibus setup.
1178 */
1179 sk_init_xmac(sc_if);
1180 if (mii_phy_probe(dev, &sc_if->sk_miibus,
1181 sk_ifmedia_upd, sk_ifmedia_sts)) {
1182 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1183 contigfree(sc_if->sk_rdata,
1184 sizeof(struct sk_ring_data), M_DEVBUF);
1185 ether_ifdetach(ifp);
1186 SK_UNLOCK(sc);
1187 return(ENXIO);
1188 }
1189
1190 SK_UNLOCK(sc);
1191
1192 return(0);
1193 }
1194
1195 /*
1196 * Attach the interface. Allocate softc structures, do ifmedia
1197 * setup and ethernet/BPF attach.
1198 */
1199 static int
1200 sk_attach(dev)
1201 device_t dev;
1202 {
1203 u_int32_t command;
1204 struct sk_softc *sc;
1205 int unit, error = 0, rid, *port;
1206
1207 sc = device_get_softc(dev);
1208 unit = device_get_unit(dev);
1209 bzero(sc, sizeof(struct sk_softc));
1210
1211 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1212 MTX_DEF | MTX_RECURSE);
1213 SK_LOCK(sc);
1214
1215 /*
1216 * Handle power management nonsense.
1217 */
1218 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1219 u_int32_t iobase, membase, irq;
1220
1221 /* Save important PCI config data. */
1222 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1223 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1224 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1225
1226 /* Reset the power state. */
1227 printf("skc%d: chip is in D%d power mode "
1228 "-- setting to D0\n", unit,
1229 pci_get_powerstate(dev));
1230 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1231
1232 /* Restore PCI config data. */
1233 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1234 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1235 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1236 }
1237
1238 /*
1239 * Map control/status registers.
1240 */
1241 pci_enable_busmaster(dev);
1242 pci_enable_io(dev, SYS_RES_IOPORT);
1243 pci_enable_io(dev, SYS_RES_MEMORY);
1244 command = pci_read_config(dev, PCIR_COMMAND, 4);
1245
1246 #ifdef SK_USEIOSPACE
1247 if (!(command & PCIM_CMD_PORTEN)) {
1248 printf("skc%d: failed to enable I/O ports!\n", unit);
1249 error = ENXIO;
1250 goto fail;
1251 }
1252 #else
1253 if (!(command & PCIM_CMD_MEMEN)) {
1254 printf("skc%d: failed to enable memory mapping!\n", unit);
1255 error = ENXIO;
1256 goto fail;
1257 }
1258 #endif
1259
1260 rid = SK_RID;
1261 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid,
1262 0, ~0, 1, RF_ACTIVE);
1263
1264 if (sc->sk_res == NULL) {
1265 printf("sk%d: couldn't map ports/memory\n", unit);
1266 error = ENXIO;
1267 goto fail;
1268 }
1269
1270 sc->sk_btag = rman_get_bustag(sc->sk_res);
1271 sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1272
1273 /* Allocate interrupt */
1274 rid = 0;
1275 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1276 RF_SHAREABLE | RF_ACTIVE);
1277
1278 if (sc->sk_irq == NULL) {
1279 printf("skc%d: couldn't map interrupt\n", unit);
1280 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1281 error = ENXIO;
1282 goto fail;
1283 }
1284
1285 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1286 sk_intr, sc, &sc->sk_intrhand);
1287
1288 if (error) {
1289 printf("skc%d: couldn't set up irq\n", unit);
1290 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1291 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1292 goto fail;
1293 }
1294
1295 /* Reset the adapter. */
1296 sk_reset(sc);
1297
1298 sc->sk_unit = unit;
1299
1300 /* Read and save vital product data from EEPROM. */
1301 sk_vpd_read(sc);
1302
1303 /* Read and save RAM size and RAMbuffer offset */
1304 switch(sk_win_read_1(sc, SK_EPROM0)) {
1305 case SK_RAMSIZE_512K_64:
1306 sc->sk_ramsize = 0x80000;
1307 sc->sk_rboff = SK_RBOFF_0;
1308 break;
1309 case SK_RAMSIZE_1024K_64:
1310 sc->sk_ramsize = 0x100000;
1311 sc->sk_rboff = SK_RBOFF_80000;
1312 break;
1313 case SK_RAMSIZE_1024K_128:
1314 sc->sk_ramsize = 0x100000;
1315 sc->sk_rboff = SK_RBOFF_0;
1316 break;
1317 case SK_RAMSIZE_2048K_128:
1318 sc->sk_ramsize = 0x200000;
1319 sc->sk_rboff = SK_RBOFF_0;
1320 break;
1321 default:
1322 printf("skc%d: unknown ram size: %d\n",
1323 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1324 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1325 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1326 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1327 error = ENXIO;
1328 goto fail;
1329 break;
1330 }
1331
1332 /* Read and save physical media type */
1333 switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1334 case SK_PMD_1000BASESX:
1335 sc->sk_pmd = IFM_1000_SX;
1336 break;
1337 case SK_PMD_1000BASELX:
1338 sc->sk_pmd = IFM_1000_LX;
1339 break;
1340 case SK_PMD_1000BASECX:
1341 sc->sk_pmd = IFM_1000_CX;
1342 break;
1343 case SK_PMD_1000BASETX:
1344 sc->sk_pmd = IFM_1000_T;
1345 break;
1346 default:
1347 printf("skc%d: unknown media type: 0x%x\n",
1348 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1349 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1350 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1351 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1352 error = ENXIO;
1353 goto fail;
1354 }
1355
1356 /* Announce the product name. */
1357 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1358 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1359 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1360 *port = SK_PORT_A;
1361 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1362
1363 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1364 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1365 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1366 *port = SK_PORT_B;
1367 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1368 }
1369
1370 /* Turn on the 'driver is loaded' LED. */
1371 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1372
1373 bus_generic_attach(dev);
1374 SK_UNLOCK(sc);
1375 return(0);
1376
1377 fail:
1378 SK_UNLOCK(sc);
1379 mtx_destroy(&sc->sk_mtx);
1380 return(error);
1381 }
1382
1383 static int
1384 sk_detach_xmac(dev)
1385 device_t dev;
1386 {
1387 struct sk_softc *sc;
1388 struct sk_if_softc *sc_if;
1389 struct ifnet *ifp;
1390
1391 sc = device_get_softc(device_get_parent(dev));
1392 sc_if = device_get_softc(dev);
1393 SK_IF_LOCK(sc_if);
1394
1395 ifp = &sc_if->arpcom.ac_if;
1396 sk_stop(sc_if);
1397 ether_ifdetach(ifp);
1398 bus_generic_detach(dev);
1399 if (sc_if->sk_miibus != NULL)
1400 device_delete_child(dev, sc_if->sk_miibus);
1401 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1402 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1403 SK_IF_UNLOCK(sc_if);
1404
1405 return(0);
1406 }
1407
1408 static int
1409 sk_detach(dev)
1410 device_t dev;
1411 {
1412 struct sk_softc *sc;
1413
1414 sc = device_get_softc(dev);
1415 SK_LOCK(sc);
1416
1417 bus_generic_detach(dev);
1418 if (sc->sk_devs[SK_PORT_A] != NULL)
1419 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1420 if (sc->sk_devs[SK_PORT_B] != NULL)
1421 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1422
1423 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1424 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1425 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1426
1427 SK_UNLOCK(sc);
1428 mtx_destroy(&sc->sk_mtx);
1429
1430 return(0);
1431 }
1432
1433 static int
1434 sk_encap(sc_if, m_head, txidx)
1435 struct sk_if_softc *sc_if;
1436 struct mbuf *m_head;
1437 u_int32_t *txidx;
1438 {
1439 struct sk_tx_desc *f = NULL;
1440 struct mbuf *m;
1441 u_int32_t frag, cur, cnt = 0;
1442
1443 m = m_head;
1444 cur = frag = *txidx;
1445
1446 /*
1447 * Start packing the mbufs in this chain into
1448 * the fragment pointers. Stop when we run out
1449 * of fragments or hit the end of the mbuf chain.
1450 */
1451 for (m = m_head; m != NULL; m = m->m_next) {
1452 if (m->m_len != 0) {
1453 if ((SK_TX_RING_CNT -
1454 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1455 return(ENOBUFS);
1456 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1457 f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1458 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1459 if (cnt == 0)
1460 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1461 else
1462 f->sk_ctl |= SK_TXCTL_OWN;
1463 cur = frag;
1464 SK_INC(frag, SK_TX_RING_CNT);
1465 cnt++;
1466 }
1467 }
1468
1469 if (m != NULL)
1470 return(ENOBUFS);
1471
1472 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1473 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1474 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1475 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1476 sc_if->sk_cdata.sk_tx_cnt += cnt;
1477
1478 *txidx = frag;
1479
1480 return(0);
1481 }
1482
1483 static void
1484 sk_start(ifp)
1485 struct ifnet *ifp;
1486 {
1487 struct sk_softc *sc;
1488 struct sk_if_softc *sc_if;
1489 struct mbuf *m_head = NULL;
1490 u_int32_t idx;
1491
1492 sc_if = ifp->if_softc;
1493 sc = sc_if->sk_softc;
1494
1495 SK_IF_LOCK(sc_if);
1496
1497 idx = sc_if->sk_cdata.sk_tx_prod;
1498
1499 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1500 IF_DEQUEUE(&ifp->if_snd, m_head);
1501 if (m_head == NULL)
1502 break;
1503
1504 /*
1505 * Pack the data into the transmit ring. If we
1506 * don't have room, set the OACTIVE flag and wait
1507 * for the NIC to drain the ring.
1508 */
1509 if (sk_encap(sc_if, m_head, &idx)) {
1510 IF_PREPEND(&ifp->if_snd, m_head);
1511 ifp->if_flags |= IFF_OACTIVE;
1512 break;
1513 }
1514
1515 /*
1516 * If there's a BPF listener, bounce a copy of this frame
1517 * to him.
1518 */
1519 BPF_MTAP(ifp, m_head);
1520 }
1521
1522 /* Transmit */
1523 sc_if->sk_cdata.sk_tx_prod = idx;
1524 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1525
1526 /* Set a timeout in case the chip goes out to lunch. */
1527 ifp->if_timer = 5;
1528 SK_IF_UNLOCK(sc_if);
1529
1530 return;
1531 }
1532
1533
1534 static void
1535 sk_watchdog(ifp)
1536 struct ifnet *ifp;
1537 {
1538 struct sk_if_softc *sc_if;
1539
1540 sc_if = ifp->if_softc;
1541
1542 printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1543 sk_init(sc_if);
1544
1545 return;
1546 }
1547
1548 static void
1549 sk_shutdown(dev)
1550 device_t dev;
1551 {
1552 struct sk_softc *sc;
1553
1554 sc = device_get_softc(dev);
1555 SK_LOCK(sc);
1556
1557 /* Turn off the 'driver is loaded' LED. */
1558 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1559
1560 /*
1561 * Reset the GEnesis controller. Doing this should also
1562 * assert the resets on the attached XMAC(s).
1563 */
1564 sk_reset(sc);
1565 SK_UNLOCK(sc);
1566
1567 return;
1568 }
1569
1570 static void
1571 sk_rxeof(sc_if)
1572 struct sk_if_softc *sc_if;
1573 {
1574 struct mbuf *m;
1575 struct ifnet *ifp;
1576 struct sk_chain *cur_rx;
1577 int total_len = 0;
1578 int i;
1579 u_int32_t rxstat;
1580
1581 ifp = &sc_if->arpcom.ac_if;
1582 i = sc_if->sk_cdata.sk_rx_prod;
1583 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1584
1585 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1586
1587 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1588 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1589 m = cur_rx->sk_mbuf;
1590 cur_rx->sk_mbuf = NULL;
1591 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1592 SK_INC(i, SK_RX_RING_CNT);
1593
1594 if (rxstat & XM_RXSTAT_ERRFRAME) {
1595 ifp->if_ierrors++;
1596 sk_newbuf(sc_if, cur_rx, m);
1597 continue;
1598 }
1599
1600 /*
1601 * Try to allocate a new jumbo buffer. If that
1602 * fails, copy the packet to mbufs and put the
1603 * jumbo buffer back in the ring so it can be
1604 * re-used. If allocating mbufs fails, then we
1605 * have to drop the packet.
1606 */
1607 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1608 struct mbuf *m0;
1609 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
1610 ifp, NULL);
1611 sk_newbuf(sc_if, cur_rx, m);
1612 if (m0 == NULL) {
1613 printf("sk%d: no receive buffers "
1614 "available -- packet dropped!\n",
1615 sc_if->sk_unit);
1616 ifp->if_ierrors++;
1617 continue;
1618 }
1619 m = m0;
1620 } else {
1621 m->m_pkthdr.rcvif = ifp;
1622 m->m_pkthdr.len = m->m_len = total_len;
1623 }
1624
1625 ifp->if_ipackets++;
1626 (*ifp->if_input)(ifp, m);
1627 }
1628
1629 sc_if->sk_cdata.sk_rx_prod = i;
1630
1631 return;
1632 }
1633
1634 static void
1635 sk_txeof(sc_if)
1636 struct sk_if_softc *sc_if;
1637 {
1638 struct sk_tx_desc *cur_tx = NULL;
1639 struct ifnet *ifp;
1640 u_int32_t idx;
1641
1642 ifp = &sc_if->arpcom.ac_if;
1643
1644 /*
1645 * Go through our tx ring and free mbufs for those
1646 * frames that have been sent.
1647 */
1648 idx = sc_if->sk_cdata.sk_tx_cons;
1649 while(idx != sc_if->sk_cdata.sk_tx_prod) {
1650 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1651 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
1652 break;
1653 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
1654 ifp->if_opackets++;
1655 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
1656 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
1657 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
1658 }
1659 sc_if->sk_cdata.sk_tx_cnt--;
1660 SK_INC(idx, SK_TX_RING_CNT);
1661 ifp->if_timer = 0;
1662 }
1663
1664 sc_if->sk_cdata.sk_tx_cons = idx;
1665
1666 if (cur_tx != NULL)
1667 ifp->if_flags &= ~IFF_OACTIVE;
1668
1669 return;
1670 }
1671
1672 static void
1673 sk_tick(xsc_if)
1674 void *xsc_if;
1675 {
1676 struct sk_if_softc *sc_if;
1677 struct mii_data *mii;
1678 struct ifnet *ifp;
1679 int i;
1680
1681 sc_if = xsc_if;
1682 SK_IF_LOCK(sc_if);
1683 ifp = &sc_if->arpcom.ac_if;
1684 mii = device_get_softc(sc_if->sk_miibus);
1685
1686 if (!(ifp->if_flags & IFF_UP)) {
1687 SK_IF_UNLOCK(sc_if);
1688 return;
1689 }
1690
1691 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1692 sk_intr_bcom(sc_if);
1693 SK_IF_UNLOCK(sc_if);
1694 return;
1695 }
1696
1697 /*
1698 * According to SysKonnect, the correct way to verify that
1699 * the link has come back up is to poll bit 0 of the GPIO
1700 * register three times. This pin has the signal from the
1701 * link_sync pin connected to it; if we read the same link
1702 * state 3 times in a row, we know the link is up.
1703 */
1704 for (i = 0; i < 3; i++) {
1705 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
1706 break;
1707 }
1708
1709 if (i != 3) {
1710 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1711 SK_IF_UNLOCK(sc_if);
1712 return;
1713 }
1714
1715 /* Turn the GP0 interrupt back on. */
1716 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1717 SK_XM_READ_2(sc_if, XM_ISR);
1718 mii_tick(mii);
1719 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
1720
1721 SK_IF_UNLOCK(sc_if);
1722 return;
1723 }
1724
1725 static void
1726 sk_intr_bcom(sc_if)
1727 struct sk_if_softc *sc_if;
1728 {
1729 struct sk_softc *sc;
1730 struct mii_data *mii;
1731 struct ifnet *ifp;
1732 int status;
1733
1734 sc = sc_if->sk_softc;
1735 mii = device_get_softc(sc_if->sk_miibus);
1736 ifp = &sc_if->arpcom.ac_if;
1737
1738 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1739
1740 /*
1741 * Read the PHY interrupt register to make sure
1742 * we clear any pending interrupts.
1743 */
1744 status = sk_miibus_readreg(sc_if->sk_dev,
1745 SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
1746
1747 if (!(ifp->if_flags & IFF_RUNNING)) {
1748 sk_init_xmac(sc_if);
1749 return;
1750 }
1751
1752 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
1753 int lstat;
1754 lstat = sk_miibus_readreg(sc_if->sk_dev,
1755 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS);
1756
1757 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
1758 mii_mediachg(mii);
1759 /* Turn off the link LED. */
1760 SK_IF_WRITE_1(sc_if, 0,
1761 SK_LINKLED1_CTL, SK_LINKLED_OFF);
1762 sc_if->sk_link = 0;
1763 } else if (status & BRGPHY_ISR_LNK_CHG) {
1764 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM,
1765 BRGPHY_MII_IMR, 0xFF00);
1766 mii_tick(mii);
1767 sc_if->sk_link = 1;
1768 /* Turn on the link LED. */
1769 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
1770 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
1771 SK_LINKLED_BLINK_OFF);
1772 } else {
1773 mii_tick(mii);
1774 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1775 }
1776 }
1777
1778 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1779
1780 return;
1781 }
1782
1783 static void
1784 sk_intr_xmac(sc_if)
1785 struct sk_if_softc *sc_if;
1786 {
1787 struct sk_softc *sc;
1788 u_int16_t status;
1789 struct mii_data *mii;
1790
1791 sc = sc_if->sk_softc;
1792 mii = device_get_softc(sc_if->sk_miibus);
1793 status = SK_XM_READ_2(sc_if, XM_ISR);
1794
1795 /*
1796 * Link has gone down. Start MII tick timeout to
1797 * watch for link resync.
1798 */
1799 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
1800 if (status & XM_ISR_GP0_SET) {
1801 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1802 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1803 }
1804
1805 if (status & XM_ISR_AUTONEG_DONE) {
1806 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1807 }
1808 }
1809
1810 if (status & XM_IMR_TX_UNDERRUN)
1811 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
1812
1813 if (status & XM_IMR_RX_OVERRUN)
1814 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
1815
1816 status = SK_XM_READ_2(sc_if, XM_ISR);
1817
1818 return;
1819 }
1820
1821 static void
1822 sk_intr(xsc)
1823 void *xsc;
1824 {
1825 struct sk_softc *sc = xsc;
1826 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL;
1827 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
1828 u_int32_t status;
1829
1830 SK_LOCK(sc);
1831
1832 sc_if0 = sc->sk_if[SK_PORT_A];
1833 sc_if1 = sc->sk_if[SK_PORT_B];
1834
1835 if (sc_if0 != NULL)
1836 ifp0 = &sc_if0->arpcom.ac_if;
1837 if (sc_if1 != NULL)
1838 ifp1 = &sc_if1->arpcom.ac_if;
1839
1840 for (;;) {
1841 status = CSR_READ_4(sc, SK_ISSR);
1842 if (!(status & sc->sk_intrmask))
1843 break;
1844
1845 /* Handle receive interrupts first. */
1846 if (status & SK_ISR_RX1_EOF) {
1847 sk_rxeof(sc_if0);
1848 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
1849 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1850 }
1851 if (status & SK_ISR_RX2_EOF) {
1852 sk_rxeof(sc_if1);
1853 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
1854 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1855 }
1856
1857 /* Then transmit interrupts. */
1858 if (status & SK_ISR_TX1_S_EOF) {
1859 sk_txeof(sc_if0);
1860 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
1861 SK_TXBMU_CLR_IRQ_EOF);
1862 }
1863 if (status & SK_ISR_TX2_S_EOF) {
1864 sk_txeof(sc_if1);
1865 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
1866 SK_TXBMU_CLR_IRQ_EOF);
1867 }
1868
1869 /* Then MAC interrupts. */
1870 if (status & SK_ISR_MAC1 &&
1871 ifp0->if_flags & IFF_RUNNING)
1872 sk_intr_xmac(sc_if0);
1873
1874 if (status & SK_ISR_MAC2 &&
1875 ifp1->if_flags & IFF_RUNNING)
1876 sk_intr_xmac(sc_if1);
1877
1878 if (status & SK_ISR_EXTERNAL_REG) {
1879 if (ifp0 != NULL)
1880 sk_intr_bcom(sc_if0);
1881 if (ifp1 != NULL)
1882 sk_intr_bcom(sc_if1);
1883 }
1884 }
1885
1886 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
1887
1888 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL)
1889 sk_start(ifp0);
1890 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL)
1891 sk_start(ifp1);
1892
1893 SK_UNLOCK(sc);
1894
1895 return;
1896 }
1897
1898 static void
1899 sk_init_xmac(sc_if)
1900 struct sk_if_softc *sc_if;
1901 {
1902 struct sk_softc *sc;
1903 struct ifnet *ifp;
1904 struct sk_bcom_hack bhack[] = {
1905 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
1906 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
1907 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1908 { 0, 0 } };
1909
1910 sc = sc_if->sk_softc;
1911 ifp = &sc_if->arpcom.ac_if;
1912
1913 /* Unreset the XMAC. */
1914 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
1915 DELAY(1000);
1916
1917 /* Reset the XMAC's internal state. */
1918 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
1919
1920 /* Save the XMAC II revision */
1921 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
1922
1923 /*
1924 * Perform additional initialization for external PHYs,
1925 * namely for the 1000baseTX cards that use the XMAC's
1926 * GMII mode.
1927 */
1928 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1929 int i = 0;
1930 u_int32_t val;
1931
1932 /* Take PHY out of reset. */
1933 val = sk_win_read_4(sc, SK_GPIO);
1934 if (sc_if->sk_port == SK_PORT_A)
1935 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
1936 else
1937 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
1938 sk_win_write_4(sc, SK_GPIO, val);
1939
1940 /* Enable GMII mode on the XMAC. */
1941 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
1942
1943 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM,
1944 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
1945 DELAY(10000);
1946 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM,
1947 BRGPHY_MII_IMR, 0xFFF0);
1948
1949 /*
1950 * Early versions of the BCM5400 apparently have
1951 * a bug that requires them to have their reserved
1952 * registers initialized to some magic values. I don't
1953 * know what the numbers do, I'm just the messenger.
1954 */
1955 if (sk_miibus_readreg(sc_if->sk_dev,
1956 SK_PHYADDR_BCOM, 0x03) == 0x6041) {
1957 while(bhack[i].reg) {
1958 sk_miibus_writereg(sc_if->sk_dev,
1959 SK_PHYADDR_BCOM, bhack[i].reg,
1960 bhack[i].val);
1961 i++;
1962 }
1963 }
1964 }
1965
1966 /* Set station address */
1967 SK_XM_WRITE_2(sc_if, XM_PAR0,
1968 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]));
1969 SK_XM_WRITE_2(sc_if, XM_PAR1,
1970 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]));
1971 SK_XM_WRITE_2(sc_if, XM_PAR2,
1972 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]));
1973 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
1974
1975 if (ifp->if_flags & IFF_PROMISC) {
1976 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
1977 } else {
1978 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
1979 }
1980
1981 if (ifp->if_flags & IFF_BROADCAST) {
1982 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
1983 } else {
1984 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
1985 }
1986
1987 /* We don't need the FCS appended to the packet. */
1988 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
1989
1990 /* We want short frames padded to 60 bytes. */
1991 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
1992
1993 /*
1994 * Enable the reception of all error frames. This is is
1995 * a necessary evil due to the design of the XMAC. The
1996 * XMAC's receive FIFO is only 8K in size, however jumbo
1997 * frames can be up to 9000 bytes in length. When bad
1998 * frame filtering is enabled, the XMAC's RX FIFO operates
1999 * in 'store and forward' mode. For this to work, the
2000 * entire frame has to fit into the FIFO, but that means
2001 * that jumbo frames larger than 8192 bytes will be
2002 * truncated. Disabling all bad frame filtering causes
2003 * the RX FIFO to operate in streaming mode, in which
2004 * case the XMAC will start transfering frames out of the
2005 * RX FIFO as soon as the FIFO threshold is reached.
2006 */
2007 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2008 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2009 XM_MODE_RX_INRANGELEN);
2010
2011 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2012 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2013 else
2014 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2015
2016 /*
2017 * Bump up the transmit threshold. This helps hold off transmit
2018 * underruns when we're blasting traffic from both ports at once.
2019 */
2020 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2021
2022 /* Set multicast filter */
2023 sk_setmulti(sc_if);
2024
2025 /* Clear and enable interrupts */
2026 SK_XM_READ_2(sc_if, XM_ISR);
2027 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2028 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2029 else
2030 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2031
2032 /* Configure MAC arbiter */
2033 switch(sc_if->sk_xmac_rev) {
2034 case XM_XMAC_REV_B2:
2035 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2036 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2037 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2038 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2039 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2040 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2041 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2042 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2043 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2044 break;
2045 case XM_XMAC_REV_C1:
2046 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2047 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2048 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2049 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2050 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2051 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2052 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2053 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2054 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2055 break;
2056 default:
2057 break;
2058 }
2059 sk_win_write_2(sc, SK_MACARB_CTL,
2060 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2061
2062 sc_if->sk_link = 1;
2063
2064 return;
2065 }
2066
2067 /*
2068 * Note that to properly initialize any part of the GEnesis chip,
2069 * you first have to take it out of reset mode.
2070 */
2071 static void
2072 sk_init(xsc)
2073 void *xsc;
2074 {
2075 struct sk_if_softc *sc_if = xsc;
2076 struct sk_softc *sc;
2077 struct ifnet *ifp;
2078 struct mii_data *mii;
2079
2080 SK_IF_LOCK(sc_if);
2081
2082 ifp = &sc_if->arpcom.ac_if;
2083 sc = sc_if->sk_softc;
2084 mii = device_get_softc(sc_if->sk_miibus);
2085
2086 /* Cancel pending I/O and free all RX/TX buffers. */
2087 sk_stop(sc_if);
2088
2089 /* Configure LINK_SYNC LED */
2090 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2091 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON);
2092
2093 /* Configure RX LED */
2094 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START);
2095
2096 /* Configure TX LED */
2097 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START);
2098
2099 /* Configure I2C registers */
2100
2101 /* Configure XMAC(s) */
2102 sk_init_xmac(sc_if);
2103 mii_mediachg(mii);
2104
2105 /* Configure MAC FIFOs */
2106 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2107 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2108 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2109
2110 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2111 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2112 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2113
2114 /* Configure transmit arbiter(s) */
2115 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2116 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2117
2118 /* Configure RAMbuffers */
2119 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2120 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2121 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2122 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2123 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2124 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2125
2126 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2127 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2128 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2129 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2130 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2131 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2132 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2133
2134 /* Configure BMUs */
2135 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2136 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2137 vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2138 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2139
2140 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2141 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2142 vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2143 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2144
2145 /* Init descriptors */
2146 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2147 printf("sk%d: initialization failed: no "
2148 "memory for rx buffers\n", sc_if->sk_unit);
2149 sk_stop(sc_if);
2150 SK_IF_UNLOCK(sc_if);
2151 return;
2152 }
2153 sk_init_tx_ring(sc_if);
2154
2155 /* Configure interrupt handling */
2156 CSR_READ_4(sc, SK_ISSR);
2157 if (sc_if->sk_port == SK_PORT_A)
2158 sc->sk_intrmask |= SK_INTRS1;
2159 else
2160 sc->sk_intrmask |= SK_INTRS2;
2161
2162 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2163
2164 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2165
2166 /* Start BMUs. */
2167 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2168
2169 /* Enable XMACs TX and RX state machines */
2170 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2171 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2172
2173 ifp->if_flags |= IFF_RUNNING;
2174 ifp->if_flags &= ~IFF_OACTIVE;
2175
2176 SK_IF_UNLOCK(sc_if);
2177
2178 return;
2179 }
2180
2181 static void
2182 sk_stop(sc_if)
2183 struct sk_if_softc *sc_if;
2184 {
2185 int i;
2186 struct sk_softc *sc;
2187 struct ifnet *ifp;
2188
2189 SK_IF_LOCK(sc_if);
2190 sc = sc_if->sk_softc;
2191 ifp = &sc_if->arpcom.ac_if;
2192
2193 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2194
2195 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2196 u_int32_t val;
2197
2198 /* Put PHY back into reset. */
2199 val = sk_win_read_4(sc, SK_GPIO);
2200 if (sc_if->sk_port == SK_PORT_A) {
2201 val |= SK_GPIO_DIR0;
2202 val &= ~SK_GPIO_DAT0;
2203 } else {
2204 val |= SK_GPIO_DIR2;
2205 val &= ~SK_GPIO_DAT2;
2206 }
2207 sk_win_write_4(sc, SK_GPIO, val);
2208 }
2209
2210 /* Turn off various components of this interface. */
2211 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2212 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2213 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2214 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2215 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2216 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2217 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2218 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2219 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2220 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2221 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2222 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2223
2224 /* Disable interrupts */
2225 if (sc_if->sk_port == SK_PORT_A)
2226 sc->sk_intrmask &= ~SK_INTRS1;
2227 else
2228 sc->sk_intrmask &= ~SK_INTRS2;
2229 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2230
2231 SK_XM_READ_2(sc_if, XM_ISR);
2232 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2233
2234 /* Free RX and TX mbufs still in the queues. */
2235 for (i = 0; i < SK_RX_RING_CNT; i++) {
2236 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2237 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2238 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2239 }
2240 }
2241
2242 for (i = 0; i < SK_TX_RING_CNT; i++) {
2243 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2244 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2245 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2246 }
2247 }
2248
2249 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2250 SK_IF_UNLOCK(sc_if);
2251 return;
2252 }
Cache object: 7139f9e99ed93f981bde2e26d00a41a5
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