The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_sk.c

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    1 /*      $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
    2 
    3 /*-
    4  * Copyright (c) 1997, 1998, 1999, 2000
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  */
   34 /*-
   35  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
   36  *
   37  * Permission to use, copy, modify, and distribute this software for any
   38  * purpose with or without fee is hereby granted, provided that the above
   39  * copyright notice and this permission notice appear in all copies.
   40  *
   41  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   42  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   43  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   44  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   45  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   46  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   47  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   48  */
   49 
   50 #include <sys/cdefs.h>
   51 __FBSDID("$FreeBSD: releng/6.0/sys/pci/if_sk.c 151140 2005-10-09 04:11:20Z delphij $");
   52 
   53 /*
   54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
   55  * the SK-984x series adapters, both single port and dual port.
   56  * References:
   57  *      The XaQti XMAC II datasheet,
   58  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
   59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
   60  *
   61  * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
   62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
   63  * convenience to others until Vitesse corrects this problem:
   64  *
   65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
   66  *
   67  * Written by Bill Paul <wpaul@ee.columbia.edu>
   68  * Department of Electrical Engineering
   69  * Columbia University, New York City
   70  */
   71 /*
   72  * The SysKonnect gigabit ethernet adapters consist of two main
   73  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
   74  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
   75  * components and a PHY while the GEnesis controller provides a PCI
   76  * interface with DMA support. Each card may have between 512K and
   77  * 2MB of SRAM on board depending on the configuration.
   78  *
   79  * The SysKonnect GEnesis controller can have either one or two XMAC
   80  * chips connected to it, allowing single or dual port NIC configurations.
   81  * SysKonnect has the distinction of being the only vendor on the market
   82  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
   83  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
   84  * XMAC registers. This driver takes advantage of these features to allow
   85  * both XMACs to operate as independent interfaces.
   86  */
   87  
   88 #include <sys/param.h>
   89 #include <sys/systm.h>
   90 #include <sys/sockio.h>
   91 #include <sys/mbuf.h>
   92 #include <sys/malloc.h>
   93 #include <sys/kernel.h>
   94 #include <sys/module.h>
   95 #include <sys/socket.h>
   96 #include <sys/queue.h>
   97 #include <sys/sysctl.h>
   98 
   99 #include <net/if.h>
  100 #include <net/if_arp.h>
  101 #include <net/ethernet.h>
  102 #include <net/if_dl.h>
  103 #include <net/if_media.h>
  104 #include <net/if_types.h>
  105 
  106 #include <net/bpf.h>
  107 
  108 #include <vm/vm.h>              /* for vtophys */
  109 #include <vm/pmap.h>            /* for vtophys */
  110 #include <machine/bus.h>
  111 #include <machine/resource.h>
  112 #include <sys/bus.h>
  113 #include <sys/rman.h>
  114 
  115 #include <dev/mii/mii.h>
  116 #include <dev/mii/miivar.h>
  117 #include <dev/mii/brgphyreg.h>
  118 
  119 #include <dev/pci/pcireg.h>
  120 #include <dev/pci/pcivar.h>
  121 
  122 #if 0
  123 #define SK_USEIOSPACE
  124 #endif
  125 
  126 #include <pci/if_skreg.h>
  127 #include <pci/xmaciireg.h>
  128 #include <pci/yukonreg.h>
  129 
  130 MODULE_DEPEND(sk, pci, 1, 1, 1);
  131 MODULE_DEPEND(sk, ether, 1, 1, 1);
  132 MODULE_DEPEND(sk, miibus, 1, 1, 1);
  133 
  134 /* "controller miibus0" required.  See GENERIC if you get errors here. */
  135 #include "miibus_if.h"
  136 
  137 #ifndef lint
  138 static const char rcsid[] =
  139   "$FreeBSD: releng/6.0/sys/pci/if_sk.c 151140 2005-10-09 04:11:20Z delphij $";
  140 #endif
  141 
  142 static struct sk_type sk_devs[] = {
  143         {
  144                 VENDORID_SK,
  145                 DEVICEID_SK_V1,
  146                 "SysKonnect Gigabit Ethernet (V1.0)"
  147         },
  148         {
  149                 VENDORID_SK,
  150                 DEVICEID_SK_V2,
  151                 "SysKonnect Gigabit Ethernet (V2.0)"
  152         },
  153         {
  154                 VENDORID_MARVELL,
  155                 DEVICEID_SK_V2,
  156                 "Marvell Gigabit Ethernet"
  157         },
  158         {
  159                 VENDORID_MARVELL,
  160                 DEVICEID_BELKIN_5005,
  161                 "Belkin F5D5005 Gigabit Ethernet"
  162         },
  163         {
  164                 VENDORID_3COM,
  165                 DEVICEID_3COM_3C940,
  166                 "3Com 3C940 Gigabit Ethernet"
  167         },
  168         {
  169                 VENDORID_LINKSYS,
  170                 DEVICEID_LINKSYS_EG1032,
  171                 "Linksys EG1032 Gigabit Ethernet"
  172         },
  173         {
  174                 VENDORID_DLINK,
  175                 DEVICEID_DLINK_DGE530T,
  176                 "D-Link DGE-530T Gigabit Ethernet"
  177         },
  178         { 0, 0, NULL }
  179 };
  180 
  181 static int skc_probe(device_t);
  182 static int skc_attach(device_t);
  183 static int skc_detach(device_t);
  184 static void skc_shutdown(device_t);
  185 static int sk_detach(device_t);
  186 static int sk_probe(device_t);
  187 static int sk_attach(device_t);
  188 static void sk_tick(void *);
  189 static void sk_intr(void *);
  190 static void sk_intr_xmac(struct sk_if_softc *);
  191 static void sk_intr_bcom(struct sk_if_softc *);
  192 static void sk_intr_yukon(struct sk_if_softc *);
  193 static void sk_rxeof(struct sk_if_softc *);
  194 static void sk_txeof(struct sk_if_softc *);
  195 static int sk_encap(struct sk_if_softc *, struct mbuf *,
  196                                         u_int32_t *);
  197 static void sk_start(struct ifnet *);
  198 static void sk_start_locked(struct ifnet *);
  199 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
  200 static void sk_init(void *);
  201 static void sk_init_locked(struct sk_if_softc *);
  202 static void sk_init_xmac(struct sk_if_softc *);
  203 static void sk_init_yukon(struct sk_if_softc *);
  204 static void sk_stop(struct sk_if_softc *);
  205 static void sk_watchdog(struct ifnet *);
  206 static int sk_ifmedia_upd(struct ifnet *);
  207 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  208 static void sk_reset(struct sk_softc *);
  209 static int sk_newbuf(struct sk_if_softc *,
  210                                         struct sk_chain *, struct mbuf *);
  211 static int sk_alloc_jumbo_mem(struct sk_if_softc *);
  212 static void sk_free_jumbo_mem(struct sk_if_softc *);
  213 static void *sk_jalloc(struct sk_if_softc *);
  214 static void sk_jfree(void *, void *);
  215 static int sk_init_rx_ring(struct sk_if_softc *);
  216 static void sk_init_tx_ring(struct sk_if_softc *);
  217 static u_int32_t sk_win_read_4(struct sk_softc *, int);
  218 static u_int16_t sk_win_read_2(struct sk_softc *, int);
  219 static u_int8_t sk_win_read_1(struct sk_softc *, int);
  220 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
  221 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
  222 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
  223 static u_int8_t sk_vpd_readbyte(struct sk_softc *, int);
  224 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int);
  225 static void sk_vpd_read(struct sk_softc *);
  226 
  227 static int sk_miibus_readreg(device_t, int, int);
  228 static int sk_miibus_writereg(device_t, int, int, int);
  229 static void sk_miibus_statchg(device_t);
  230 
  231 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
  232 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
  233                                                 int);
  234 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
  235 
  236 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
  237 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
  238                                                 int);
  239 static void sk_marv_miibus_statchg(struct sk_if_softc *);
  240 
  241 static uint32_t sk_xmchash(const uint8_t *);
  242 static uint32_t sk_gmchash(const uint8_t *);
  243 static void sk_setfilt(struct sk_if_softc *, caddr_t, int);
  244 static void sk_setmulti(struct sk_if_softc *);
  245 static void sk_setpromisc(struct sk_if_softc *);
  246 
  247 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
  248 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
  249 
  250 #ifdef SK_USEIOSPACE
  251 #define SK_RES          SYS_RES_IOPORT
  252 #define SK_RID          SK_PCI_LOIO
  253 #else
  254 #define SK_RES          SYS_RES_MEMORY
  255 #define SK_RID          SK_PCI_LOMEM
  256 #endif
  257 
  258 /*
  259  * Note that we have newbus methods for both the GEnesis controller
  260  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
  261  * the miibus code is a child of the XMACs. We need to do it this way
  262  * so that the miibus drivers can access the PHY registers on the
  263  * right PHY. It's not quite what I had in mind, but it's the only
  264  * design that achieves the desired effect.
  265  */
  266 static device_method_t skc_methods[] = {
  267         /* Device interface */
  268         DEVMETHOD(device_probe,         skc_probe),
  269         DEVMETHOD(device_attach,        skc_attach),
  270         DEVMETHOD(device_detach,        skc_detach),
  271         DEVMETHOD(device_shutdown,      skc_shutdown),
  272 
  273         /* bus interface */
  274         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  275         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  276 
  277         { 0, 0 }
  278 };
  279 
  280 static driver_t skc_driver = {
  281         "skc",
  282         skc_methods,
  283         sizeof(struct sk_softc)
  284 };
  285 
  286 static devclass_t skc_devclass;
  287 
  288 static device_method_t sk_methods[] = {
  289         /* Device interface */
  290         DEVMETHOD(device_probe,         sk_probe),
  291         DEVMETHOD(device_attach,        sk_attach),
  292         DEVMETHOD(device_detach,        sk_detach),
  293         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  294 
  295         /* bus interface */
  296         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  297         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  298 
  299         /* MII interface */
  300         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
  301         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
  302         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
  303 
  304         { 0, 0 }
  305 };
  306 
  307 static driver_t sk_driver = {
  308         "sk",
  309         sk_methods,
  310         sizeof(struct sk_if_softc)
  311 };
  312 
  313 static devclass_t sk_devclass;
  314 
  315 DRIVER_MODULE(sk, pci, skc_driver, skc_devclass, 0, 0);
  316 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0);
  317 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
  318 
  319 #define SK_SETBIT(sc, reg, x)           \
  320         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
  321 
  322 #define SK_CLRBIT(sc, reg, x)           \
  323         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
  324 
  325 #define SK_WIN_SETBIT_4(sc, reg, x)     \
  326         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
  327 
  328 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
  329         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
  330 
  331 #define SK_WIN_SETBIT_2(sc, reg, x)     \
  332         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
  333 
  334 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
  335         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
  336 
  337 static u_int32_t
  338 sk_win_read_4(sc, reg)
  339         struct sk_softc         *sc;
  340         int                     reg;
  341 {
  342 #ifdef SK_USEIOSPACE
  343         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
  344         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
  345 #else
  346         return(CSR_READ_4(sc, reg));
  347 #endif
  348 }
  349 
  350 static u_int16_t
  351 sk_win_read_2(sc, reg)
  352         struct sk_softc         *sc;
  353         int                     reg;
  354 {
  355 #ifdef SK_USEIOSPACE
  356         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
  357         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
  358 #else
  359         return(CSR_READ_2(sc, reg));
  360 #endif
  361 }
  362 
  363 static u_int8_t
  364 sk_win_read_1(sc, reg)
  365         struct sk_softc         *sc;
  366         int                     reg;
  367 {
  368 #ifdef SK_USEIOSPACE
  369         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
  370         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
  371 #else
  372         return(CSR_READ_1(sc, reg));
  373 #endif
  374 }
  375 
  376 static void
  377 sk_win_write_4(sc, reg, val)
  378         struct sk_softc         *sc;
  379         int                     reg;
  380         u_int32_t               val;
  381 {
  382 #ifdef SK_USEIOSPACE
  383         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
  384         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
  385 #else
  386         CSR_WRITE_4(sc, reg, val);
  387 #endif
  388         return;
  389 }
  390 
  391 static void
  392 sk_win_write_2(sc, reg, val)
  393         struct sk_softc         *sc;
  394         int                     reg;
  395         u_int32_t               val;
  396 {
  397 #ifdef SK_USEIOSPACE
  398         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
  399         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
  400 #else
  401         CSR_WRITE_2(sc, reg, val);
  402 #endif
  403         return;
  404 }
  405 
  406 static void
  407 sk_win_write_1(sc, reg, val)
  408         struct sk_softc         *sc;
  409         int                     reg;
  410         u_int32_t               val;
  411 {
  412 #ifdef SK_USEIOSPACE
  413         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
  414         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
  415 #else
  416         CSR_WRITE_1(sc, reg, val);
  417 #endif
  418         return;
  419 }
  420 
  421 /*
  422  * The VPD EEPROM contains Vital Product Data, as suggested in
  423  * the PCI 2.1 specification. The VPD data is separared into areas
  424  * denoted by resource IDs. The SysKonnect VPD contains an ID string
  425  * resource (the name of the adapter), a read-only area resource
  426  * containing various key/data fields and a read/write area which
  427  * can be used to store asset management information or log messages.
  428  * We read the ID string and read-only into buffers attached to
  429  * the controller softc structure for later use. At the moment,
  430  * we only use the ID string during skc_attach().
  431  */
  432 static u_int8_t
  433 sk_vpd_readbyte(sc, addr)
  434         struct sk_softc         *sc;
  435         int                     addr;
  436 {
  437         int                     i;
  438 
  439         sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
  440         for (i = 0; i < SK_TIMEOUT; i++) {
  441                 DELAY(1);
  442                 if (sk_win_read_2(sc,
  443                     SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
  444                         break;
  445         }
  446 
  447         if (i == SK_TIMEOUT)
  448                 return(0);
  449 
  450         return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
  451 }
  452 
  453 static void
  454 sk_vpd_read_res(sc, res, addr)
  455         struct sk_softc         *sc;
  456         struct vpd_res          *res;
  457         int                     addr;
  458 {
  459         int                     i;
  460         u_int8_t                *ptr;
  461 
  462         ptr = (u_int8_t *)res;
  463         for (i = 0; i < sizeof(struct vpd_res); i++)
  464                 ptr[i] = sk_vpd_readbyte(sc, i + addr);
  465 
  466         return;
  467 }
  468 
  469 static void
  470 sk_vpd_read(sc)
  471         struct sk_softc         *sc;
  472 {
  473         int                     pos = 0, i;
  474         struct vpd_res          res;
  475 
  476         if (sc->sk_vpd_prodname != NULL)
  477                 free(sc->sk_vpd_prodname, M_DEVBUF);
  478         if (sc->sk_vpd_readonly != NULL)
  479                 free(sc->sk_vpd_readonly, M_DEVBUF);
  480         sc->sk_vpd_prodname = NULL;
  481         sc->sk_vpd_readonly = NULL;
  482         sc->sk_vpd_readonly_len = 0;
  483 
  484         sk_vpd_read_res(sc, &res, pos);
  485 
  486         /*
  487          * Bail out quietly if the eeprom appears to be missing or empty.
  488          */
  489         if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff)
  490                 return;
  491 
  492         if (res.vr_id != VPD_RES_ID) {
  493                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
  494                     sc->sk_unit, VPD_RES_ID, res.vr_id);
  495                 return;
  496         }
  497 
  498         pos += sizeof(res);
  499         sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
  500         if (sc->sk_vpd_prodname != NULL) {
  501                 for (i = 0; i < res.vr_len; i++)
  502                         sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
  503                 sc->sk_vpd_prodname[i] = '\0';
  504         }
  505         pos += res.vr_len;
  506 
  507         sk_vpd_read_res(sc, &res, pos);
  508 
  509         if (res.vr_id != VPD_RES_READ) {
  510                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
  511                     sc->sk_unit, VPD_RES_READ, res.vr_id);
  512                 return;
  513         }
  514 
  515         pos += sizeof(res);
  516         sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
  517         for (i = 0; i < res.vr_len; i++)
  518                 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
  519         sc->sk_vpd_readonly_len = res.vr_len;
  520 
  521         return;
  522 }
  523 
  524 static int
  525 sk_miibus_readreg(dev, phy, reg)
  526         device_t                dev;
  527         int                     phy, reg;
  528 {
  529         struct sk_if_softc      *sc_if;
  530 
  531         sc_if = device_get_softc(dev);
  532 
  533         switch(sc_if->sk_softc->sk_type) {
  534         case SK_GENESIS:
  535                 return(sk_xmac_miibus_readreg(sc_if, phy, reg));
  536         case SK_YUKON:
  537         case SK_YUKON_LITE:
  538         case SK_YUKON_LP:
  539                 return(sk_marv_miibus_readreg(sc_if, phy, reg));
  540         }
  541 
  542         return(0);
  543 }
  544 
  545 static int
  546 sk_miibus_writereg(dev, phy, reg, val)
  547         device_t                dev;
  548         int                     phy, reg, val;
  549 {
  550         struct sk_if_softc      *sc_if;
  551 
  552         sc_if = device_get_softc(dev);
  553 
  554         switch(sc_if->sk_softc->sk_type) {
  555         case SK_GENESIS:
  556                 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val));
  557         case SK_YUKON:
  558         case SK_YUKON_LITE:
  559         case SK_YUKON_LP:
  560                 return(sk_marv_miibus_writereg(sc_if, phy, reg, val));
  561         }
  562 
  563         return(0);
  564 }
  565 
  566 static void
  567 sk_miibus_statchg(dev)
  568         device_t                dev;
  569 {
  570         struct sk_if_softc      *sc_if;
  571 
  572         sc_if = device_get_softc(dev);
  573 
  574         switch(sc_if->sk_softc->sk_type) {
  575         case SK_GENESIS:
  576                 sk_xmac_miibus_statchg(sc_if);
  577                 break;
  578         case SK_YUKON:
  579         case SK_YUKON_LITE:
  580         case SK_YUKON_LP:
  581                 sk_marv_miibus_statchg(sc_if);
  582                 break;
  583         }
  584 
  585         return;
  586 }
  587 
  588 static int
  589 sk_xmac_miibus_readreg(sc_if, phy, reg)
  590         struct sk_if_softc      *sc_if;
  591         int                     phy, reg;
  592 {
  593         int                     i;
  594 
  595         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
  596                 return(0);
  597 
  598         SK_IF_LOCK(sc_if);
  599         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
  600         SK_XM_READ_2(sc_if, XM_PHY_DATA);
  601         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
  602                 for (i = 0; i < SK_TIMEOUT; i++) {
  603                         DELAY(1);
  604                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
  605                             XM_MMUCMD_PHYDATARDY)
  606                                 break;
  607                 }
  608 
  609                 if (i == SK_TIMEOUT) {
  610                         printf("sk%d: phy failed to come ready\n",
  611                             sc_if->sk_unit);
  612                         SK_IF_UNLOCK(sc_if);
  613                         return(0);
  614                 }
  615         }
  616         DELAY(1);
  617         i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
  618         SK_IF_UNLOCK(sc_if);
  619         return(i);
  620 }
  621 
  622 static int
  623 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
  624         struct sk_if_softc      *sc_if;
  625         int                     phy, reg, val;
  626 {
  627         int                     i;
  628 
  629         SK_IF_LOCK(sc_if);
  630         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
  631         for (i = 0; i < SK_TIMEOUT; i++) {
  632                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
  633                         break;
  634         }
  635 
  636         if (i == SK_TIMEOUT) {
  637                 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
  638                 SK_IF_UNLOCK(sc_if);
  639                 return(ETIMEDOUT);
  640         }
  641 
  642         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
  643         for (i = 0; i < SK_TIMEOUT; i++) {
  644                 DELAY(1);
  645                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
  646                         break;
  647         }
  648         SK_IF_UNLOCK(sc_if);
  649         if (i == SK_TIMEOUT)
  650                 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
  651 
  652         return(0);
  653 }
  654 
  655 static void
  656 sk_xmac_miibus_statchg(sc_if)
  657         struct sk_if_softc      *sc_if;
  658 {
  659         struct mii_data         *mii;
  660 
  661         mii = device_get_softc(sc_if->sk_miibus);
  662 
  663         SK_IF_LOCK(sc_if);
  664         /*
  665          * If this is a GMII PHY, manually set the XMAC's
  666          * duplex mode accordingly.
  667          */
  668         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
  669                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
  670                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
  671                 } else {
  672                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
  673                 }
  674         }
  675         SK_IF_UNLOCK(sc_if);
  676 
  677         return;
  678 }
  679 
  680 static int
  681 sk_marv_miibus_readreg(sc_if, phy, reg)
  682         struct sk_if_softc      *sc_if;
  683         int                     phy, reg;
  684 {
  685         u_int16_t               val;
  686         int                     i;
  687 
  688         if (phy != 0 ||
  689             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
  690              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
  691                 return(0);
  692         }
  693 
  694         SK_IF_LOCK(sc_if);
  695         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
  696                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
  697         
  698         for (i = 0; i < SK_TIMEOUT; i++) {
  699                 DELAY(1);
  700                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
  701                 if (val & YU_SMICR_READ_VALID)
  702                         break;
  703         }
  704 
  705         if (i == SK_TIMEOUT) {
  706                 printf("sk%d: phy failed to come ready\n",
  707                     sc_if->sk_unit);
  708                 SK_IF_UNLOCK(sc_if);
  709                 return(0);
  710         }
  711         
  712         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
  713         SK_IF_UNLOCK(sc_if);
  714 
  715         return(val);
  716 }
  717 
  718 static int
  719 sk_marv_miibus_writereg(sc_if, phy, reg, val)
  720         struct sk_if_softc      *sc_if;
  721         int                     phy, reg, val;
  722 {
  723         int                     i;
  724 
  725         SK_IF_LOCK(sc_if);
  726         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
  727         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
  728                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
  729 
  730         for (i = 0; i < SK_TIMEOUT; i++) {
  731                 DELAY(1);
  732                 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
  733                         break;
  734         }
  735         SK_IF_UNLOCK(sc_if);
  736 
  737         return(0);
  738 }
  739 
  740 static void
  741 sk_marv_miibus_statchg(sc_if)
  742         struct sk_if_softc      *sc_if;
  743 {
  744         return;
  745 }
  746 
  747 #define HASH_BITS               6
  748 
  749 static u_int32_t
  750 sk_xmchash(addr)
  751         const uint8_t *addr;
  752 {
  753         uint32_t crc;
  754 
  755         /* Compute CRC for the address value. */
  756         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
  757 
  758         return (~crc & ((1 << HASH_BITS) - 1));
  759 }
  760 
  761 /* gmchash is just a big endian crc */
  762 static u_int32_t
  763 sk_gmchash(addr)
  764         const uint8_t *addr;
  765 {
  766         uint32_t crc;
  767 
  768         /* Compute CRC for the address value. */
  769         crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
  770 
  771         return (crc & ((1 << HASH_BITS) - 1));
  772 }
  773 
  774 static void
  775 sk_setfilt(sc_if, addr, slot)
  776         struct sk_if_softc      *sc_if;
  777         caddr_t                 addr;
  778         int                     slot;
  779 {
  780         int                     base;
  781 
  782         base = XM_RXFILT_ENTRY(slot);
  783 
  784         SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
  785         SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
  786         SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
  787 
  788         return;
  789 }
  790 
  791 static void
  792 sk_setmulti(sc_if)
  793         struct sk_if_softc      *sc_if;
  794 {
  795         struct sk_softc         *sc = sc_if->sk_softc;
  796         struct ifnet            *ifp = sc_if->sk_ifp;
  797         u_int32_t               hashes[2] = { 0, 0 };
  798         int                     h = 0, i;
  799         struct ifmultiaddr      *ifma;
  800         u_int8_t                dummy[] = { 0, 0, 0, 0, 0 ,0 };
  801 
  802         SK_IF_LOCK_ASSERT(sc_if);
  803 
  804         /* First, zot all the existing filters. */
  805         switch(sc->sk_type) {
  806         case SK_GENESIS:
  807                 for (i = 1; i < XM_RXFILT_MAX; i++)
  808                         sk_setfilt(sc_if, (caddr_t)&dummy, i);
  809 
  810                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
  811                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
  812                 break;
  813         case SK_YUKON:
  814         case SK_YUKON_LITE:
  815         case SK_YUKON_LP:
  816                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
  817                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
  818                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
  819                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
  820                 break;
  821         }
  822 
  823         /* Now program new ones. */
  824         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  825                 hashes[0] = 0xFFFFFFFF;
  826                 hashes[1] = 0xFFFFFFFF;
  827         } else {
  828                 i = 1;
  829                 IF_ADDR_LOCK(ifp);
  830                 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
  831                         if (ifma->ifma_addr->sa_family != AF_LINK)
  832                                 continue;
  833                         /*
  834                          * Program the first XM_RXFILT_MAX multicast groups
  835                          * into the perfect filter. For all others,
  836                          * use the hash table.
  837                          */
  838                         if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
  839                                 sk_setfilt(sc_if,
  840                         LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
  841                                 i++;
  842                                 continue;
  843                         }
  844 
  845                         switch(sc->sk_type) {
  846                         case SK_GENESIS:
  847                                 h = sk_xmchash(
  848                                         LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  849                                 break;
  850                         case SK_YUKON:
  851                         case SK_YUKON_LITE:
  852                         case SK_YUKON_LP:
  853                                 h = sk_gmchash(
  854                                         LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  855                                 break;
  856                         }
  857                         if (h < 32)
  858                                 hashes[0] |= (1 << h);
  859                         else
  860                                 hashes[1] |= (1 << (h - 32));
  861                 }
  862                 IF_ADDR_UNLOCK(ifp);
  863         }
  864 
  865         switch(sc->sk_type) {
  866         case SK_GENESIS:
  867                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
  868                                XM_MODE_RX_USE_PERFECT);
  869                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
  870                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
  871                 break;
  872         case SK_YUKON:
  873         case SK_YUKON_LITE:
  874         case SK_YUKON_LP:
  875                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
  876                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
  877                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
  878                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
  879                 break;
  880         }
  881 
  882         return;
  883 }
  884 
  885 static void
  886 sk_setpromisc(sc_if)
  887         struct sk_if_softc      *sc_if;
  888 {
  889         struct sk_softc         *sc = sc_if->sk_softc;
  890         struct ifnet            *ifp = sc_if->sk_ifp;
  891 
  892         SK_IF_LOCK_ASSERT(sc_if);
  893 
  894         switch(sc->sk_type) {
  895         case SK_GENESIS:
  896                 if (ifp->if_flags & IFF_PROMISC) {
  897                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
  898                 } else {
  899                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
  900                 }
  901                 break;
  902         case SK_YUKON:
  903         case SK_YUKON_LITE:
  904         case SK_YUKON_LP:
  905                 if (ifp->if_flags & IFF_PROMISC) {
  906                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
  907                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
  908                 } else {
  909                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
  910                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
  911                 }
  912                 break;
  913         }
  914 
  915         return;
  916 }
  917 
  918 static int
  919 sk_init_rx_ring(sc_if)
  920         struct sk_if_softc      *sc_if;
  921 {
  922         struct sk_chain_data    *cd = &sc_if->sk_cdata;
  923         struct sk_ring_data     *rd = sc_if->sk_rdata;
  924         int                     i;
  925 
  926         bzero((char *)rd->sk_rx_ring,
  927             sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
  928 
  929         for (i = 0; i < SK_RX_RING_CNT; i++) {
  930                 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
  931                 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
  932                         return(ENOBUFS);
  933                 if (i == (SK_RX_RING_CNT - 1)) {
  934                         cd->sk_rx_chain[i].sk_next =
  935                             &cd->sk_rx_chain[0];
  936                         rd->sk_rx_ring[i].sk_next = 
  937                             vtophys(&rd->sk_rx_ring[0]);
  938                 } else {
  939                         cd->sk_rx_chain[i].sk_next =
  940                             &cd->sk_rx_chain[i + 1];
  941                         rd->sk_rx_ring[i].sk_next = 
  942                             vtophys(&rd->sk_rx_ring[i + 1]);
  943                 }
  944         }
  945 
  946         sc_if->sk_cdata.sk_rx_prod = 0;
  947         sc_if->sk_cdata.sk_rx_cons = 0;
  948 
  949         return(0);
  950 }
  951 
  952 static void
  953 sk_init_tx_ring(sc_if)
  954         struct sk_if_softc      *sc_if;
  955 {
  956         struct sk_chain_data    *cd = &sc_if->sk_cdata;
  957         struct sk_ring_data     *rd = sc_if->sk_rdata;
  958         int                     i;
  959 
  960         bzero((char *)sc_if->sk_rdata->sk_tx_ring,
  961             sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
  962 
  963         for (i = 0; i < SK_TX_RING_CNT; i++) {
  964                 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
  965                 if (i == (SK_TX_RING_CNT - 1)) {
  966                         cd->sk_tx_chain[i].sk_next =
  967                             &cd->sk_tx_chain[0];
  968                         rd->sk_tx_ring[i].sk_next = 
  969                             vtophys(&rd->sk_tx_ring[0]);
  970                 } else {
  971                         cd->sk_tx_chain[i].sk_next =
  972                             &cd->sk_tx_chain[i + 1];
  973                         rd->sk_tx_ring[i].sk_next = 
  974                             vtophys(&rd->sk_tx_ring[i + 1]);
  975                 }
  976         }
  977 
  978         sc_if->sk_cdata.sk_tx_prod = 0;
  979         sc_if->sk_cdata.sk_tx_cons = 0;
  980         sc_if->sk_cdata.sk_tx_cnt = 0;
  981 
  982         return;
  983 }
  984 
  985 static int
  986 sk_newbuf(sc_if, c, m)
  987         struct sk_if_softc      *sc_if;
  988         struct sk_chain         *c;
  989         struct mbuf             *m;
  990 {
  991         struct mbuf             *m_new = NULL;
  992         struct sk_rx_desc       *r;
  993 
  994         if (m == NULL) {
  995                 caddr_t                 *buf = NULL;
  996 
  997                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  998                 if (m_new == NULL)
  999                         return(ENOBUFS);
 1000 
 1001                 /* Allocate the jumbo buffer */
 1002                 buf = sk_jalloc(sc_if);
 1003                 if (buf == NULL) {
 1004                         m_freem(m_new);
 1005 #ifdef SK_VERBOSE
 1006                         printf("sk%d: jumbo allocation failed "
 1007                             "-- packet dropped!\n", sc_if->sk_unit);
 1008 #endif
 1009                         return(ENOBUFS);
 1010                 }
 1011 
 1012                 /* Attach the buffer to the mbuf */
 1013                 MEXTADD(m_new, buf, SK_JLEN, sk_jfree,
 1014                     (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 
 1015                 m_new->m_data = (void *)buf;
 1016                 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN;
 1017         } else {
 1018                 /*
 1019                  * We're re-using a previously allocated mbuf;
 1020                  * be sure to re-init pointers and lengths to
 1021                  * default values.
 1022                  */
 1023                 m_new = m;
 1024                 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
 1025                 m_new->m_data = m_new->m_ext.ext_buf;
 1026         }
 1027 
 1028         /*
 1029          * Adjust alignment so packet payload begins on a
 1030          * longword boundary. Mandatory for Alpha, useful on
 1031          * x86 too.
 1032          */
 1033         m_adj(m_new, ETHER_ALIGN);
 1034 
 1035         r = c->sk_desc;
 1036         c->sk_mbuf = m_new;
 1037         r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
 1038         r->sk_ctl = m_new->m_len | SK_RXSTAT;
 1039 
 1040         return(0);
 1041 }
 1042 
 1043 /*
 1044  * Allocate jumbo buffer storage. The SysKonnect adapters support
 1045  * "jumbograms" (9K frames), although SysKonnect doesn't currently
 1046  * use them in their drivers. In order for us to use them, we need
 1047  * large 9K receive buffers, however standard mbuf clusters are only
 1048  * 2048 bytes in size. Consequently, we need to allocate and manage
 1049  * our own jumbo buffer pool. Fortunately, this does not require an
 1050  * excessive amount of additional code.
 1051  */
 1052 static int
 1053 sk_alloc_jumbo_mem(sc_if)
 1054         struct sk_if_softc      *sc_if;
 1055 {
 1056         caddr_t                 ptr;
 1057         register int            i;
 1058         struct sk_jpool_entry   *entry;
 1059 
 1060         /* Grab a big chunk o' storage. */
 1061         sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
 1062             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 1063 
 1064         if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
 1065                 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
 1066                 return(ENOBUFS);
 1067         }
 1068 
 1069         mtx_init(&sc_if->sk_jlist_mtx, "sk_jlist_mtx", NULL, MTX_DEF);
 1070 
 1071         SLIST_INIT(&sc_if->sk_jfree_listhead);
 1072         SLIST_INIT(&sc_if->sk_jinuse_listhead);
 1073 
 1074         /*
 1075          * Now divide it up into 9K pieces and save the addresses
 1076          * in an array.
 1077          */
 1078         ptr = sc_if->sk_cdata.sk_jumbo_buf;
 1079         for (i = 0; i < SK_JSLOTS; i++) {
 1080                 sc_if->sk_cdata.sk_jslots[i] = ptr;
 1081                 ptr += SK_JLEN;
 1082                 entry = malloc(sizeof(struct sk_jpool_entry), 
 1083                     M_DEVBUF, M_NOWAIT);
 1084                 if (entry == NULL) {
 1085                         sk_free_jumbo_mem(sc_if);
 1086                         sc_if->sk_cdata.sk_jumbo_buf = NULL;
 1087                         printf("sk%d: no memory for jumbo "
 1088                             "buffer queue!\n", sc_if->sk_unit);
 1089                         return(ENOBUFS);
 1090                 }
 1091                 entry->slot = i;
 1092                 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
 1093                     entry, jpool_entries);
 1094         }
 1095 
 1096         return(0);
 1097 }
 1098 
 1099 static void
 1100 sk_free_jumbo_mem(sc_if)
 1101         struct sk_if_softc      *sc_if;
 1102 {
 1103         struct sk_jpool_entry   *entry;
 1104 
 1105         SK_JLIST_LOCK(sc_if);
 1106 
 1107         /* We cannot release external mbuf storage while in use. */
 1108         if (!SLIST_EMPTY(&sc_if->sk_jinuse_listhead)) {
 1109                 printf("sk%d: will leak jumbo buffer memory!\n", sc_if->sk_unit);
 1110                 SK_JLIST_UNLOCK(sc_if);
 1111                 return;
 1112         }
 1113 
 1114         while (!SLIST_EMPTY(&sc_if->sk_jfree_listhead)) {
 1115                 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
 1116                 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
 1117                 free(entry, M_DEVBUF);
 1118         }
 1119 
 1120         SK_JLIST_UNLOCK(sc_if);
 1121 
 1122         mtx_destroy(&sc_if->sk_jlist_mtx);
 1123 
 1124         contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
 1125 
 1126         return;
 1127 }
 1128 
 1129 /*
 1130  * Allocate a jumbo buffer.
 1131  */
 1132 static void *
 1133 sk_jalloc(sc_if)
 1134         struct sk_if_softc      *sc_if;
 1135 {
 1136         struct sk_jpool_entry   *entry;
 1137 
 1138         SK_JLIST_LOCK(sc_if);
 1139 
 1140         entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
 1141 
 1142         if (entry == NULL) {
 1143 #ifdef SK_VERBOSE
 1144                 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
 1145 #endif
 1146                 SK_JLIST_UNLOCK(sc_if);
 1147                 return(NULL);
 1148         }
 1149 
 1150         SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
 1151         SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
 1152 
 1153         SK_JLIST_UNLOCK(sc_if);
 1154 
 1155         return(sc_if->sk_cdata.sk_jslots[entry->slot]);
 1156 }
 1157 
 1158 /*
 1159  * Release a jumbo buffer.
 1160  */
 1161 static void
 1162 sk_jfree(buf, args)
 1163         void                    *buf;
 1164         void                    *args;
 1165 {
 1166         struct sk_if_softc      *sc_if;
 1167         int                     i;
 1168         struct sk_jpool_entry   *entry;
 1169 
 1170         /* Extract the softc struct pointer. */
 1171         sc_if = (struct sk_if_softc *)args;
 1172         if (sc_if == NULL)
 1173                 panic("sk_jfree: didn't get softc pointer!");
 1174 
 1175         SK_JLIST_LOCK(sc_if);
 1176 
 1177         /* calculate the slot this buffer belongs to */
 1178         i = ((vm_offset_t)buf
 1179              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
 1180 
 1181         if ((i < 0) || (i >= SK_JSLOTS))
 1182                 panic("sk_jfree: asked to free buffer that we don't manage!");
 1183 
 1184         entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
 1185         if (entry == NULL)
 1186                 panic("sk_jfree: buffer not in use!");
 1187         entry->slot = i;
 1188         SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries);
 1189         SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries);
 1190         if (SLIST_EMPTY(&sc_if->sk_jinuse_listhead))
 1191                 wakeup(sc_if);
 1192 
 1193         SK_JLIST_UNLOCK(sc_if);
 1194         return;
 1195 }
 1196 
 1197 /*
 1198  * Set media options.
 1199  */
 1200 static int
 1201 sk_ifmedia_upd(ifp)
 1202         struct ifnet            *ifp;
 1203 {
 1204         struct sk_if_softc      *sc_if = ifp->if_softc;
 1205         struct mii_data         *mii;
 1206 
 1207         mii = device_get_softc(sc_if->sk_miibus);
 1208         sk_init(sc_if);
 1209         mii_mediachg(mii);
 1210 
 1211         return(0);
 1212 }
 1213 
 1214 /*
 1215  * Report current media status.
 1216  */
 1217 static void
 1218 sk_ifmedia_sts(ifp, ifmr)
 1219         struct ifnet            *ifp;
 1220         struct ifmediareq       *ifmr;
 1221 {
 1222         struct sk_if_softc      *sc_if;
 1223         struct mii_data         *mii;
 1224 
 1225         sc_if = ifp->if_softc;
 1226         mii = device_get_softc(sc_if->sk_miibus);
 1227 
 1228         mii_pollstat(mii);
 1229         ifmr->ifm_active = mii->mii_media_active;
 1230         ifmr->ifm_status = mii->mii_media_status;
 1231 
 1232         return;
 1233 }
 1234 
 1235 static int
 1236 sk_ioctl(ifp, command, data)
 1237         struct ifnet            *ifp;
 1238         u_long                  command;
 1239         caddr_t                 data;
 1240 {
 1241         struct sk_if_softc      *sc_if = ifp->if_softc;
 1242         struct ifreq            *ifr = (struct ifreq *) data;
 1243         int                     error = 0;
 1244         struct mii_data         *mii;
 1245 
 1246         switch(command) {
 1247         case SIOCSIFMTU:
 1248                 SK_IF_LOCK(sc_if);
 1249                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
 1250                         error = EINVAL;
 1251                 else {
 1252                         ifp->if_mtu = ifr->ifr_mtu;
 1253                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 1254                         sk_init_locked(sc_if);
 1255                 }
 1256                 SK_IF_UNLOCK(sc_if);
 1257                 break;
 1258         case SIOCSIFFLAGS:
 1259                 SK_IF_LOCK(sc_if);
 1260                 if (ifp->if_flags & IFF_UP) {
 1261                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 1262                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
 1263                                     & IFF_PROMISC) {
 1264                                         sk_setpromisc(sc_if);
 1265                                         sk_setmulti(sc_if);
 1266                                 }
 1267                         } else
 1268                                 sk_init_locked(sc_if);
 1269                 } else {
 1270                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1271                                 sk_stop(sc_if);
 1272                 }
 1273                 sc_if->sk_if_flags = ifp->if_flags;
 1274                 SK_IF_UNLOCK(sc_if);
 1275                 error = 0;
 1276                 break;
 1277         case SIOCADDMULTI:
 1278         case SIOCDELMULTI:
 1279                 SK_IF_LOCK(sc_if);
 1280                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 1281                         sk_setmulti(sc_if);
 1282                         error = 0;
 1283                 }
 1284                 SK_IF_UNLOCK(sc_if);
 1285                 break;
 1286         case SIOCGIFMEDIA:
 1287         case SIOCSIFMEDIA:
 1288                 mii = device_get_softc(sc_if->sk_miibus);
 1289                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1290                 break;
 1291         default:
 1292                 error = ether_ioctl(ifp, command, data);
 1293                 break;
 1294         }
 1295 
 1296         return(error);
 1297 }
 1298 
 1299 /*
 1300  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
 1301  * IDs against our list and return a device name if we find a match.
 1302  */
 1303 static int
 1304 skc_probe(dev)
 1305         device_t                dev;
 1306 {
 1307         struct sk_softc         *sc;
 1308         struct sk_type          *t = sk_devs;
 1309 
 1310         sc = device_get_softc(dev);
 1311 
 1312         while(t->sk_name != NULL) {
 1313                 if ((pci_get_vendor(dev) == t->sk_vid) &&
 1314                     (pci_get_device(dev) == t->sk_did)) {
 1315                         device_set_desc(dev, t->sk_name);
 1316                         return (BUS_PROBE_DEFAULT);
 1317                 }
 1318                 t++;
 1319         }
 1320 
 1321         return(ENXIO);
 1322 }
 1323 
 1324 /*
 1325  * Force the GEnesis into reset, then bring it out of reset.
 1326  */
 1327 static void
 1328 sk_reset(sc)
 1329         struct sk_softc         *sc;
 1330 {
 1331         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
 1332         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
 1333         if (SK_YUKON_FAMILY(sc->sk_type))
 1334                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
 1335 
 1336         DELAY(1000);
 1337         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
 1338         DELAY(2);
 1339         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
 1340         if (SK_YUKON_FAMILY(sc->sk_type))
 1341                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
 1342 
 1343         if (sc->sk_type == SK_GENESIS) {
 1344                 /* Configure packet arbiter */
 1345                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
 1346                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
 1347                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
 1348                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
 1349                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
 1350         }
 1351 
 1352         /* Enable RAM interface */
 1353         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
 1354 
 1355         /*
 1356          * Configure interrupt moderation. The moderation timer
 1357          * defers interrupts specified in the interrupt moderation
 1358          * timer mask based on the timeout specified in the interrupt
 1359          * moderation timer init register. Each bit in the timer
 1360          * register represents 18.825ns, so to specify a timeout in
 1361          * microseconds, we have to multiply by 54.
 1362          */
 1363         if (bootverbose)
 1364                 printf("skc%d: interrupt moderation is %d us\n",
 1365                     sc->sk_unit, sc->sk_int_mod);
 1366         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod));
 1367         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
 1368             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
 1369         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
 1370 
 1371         return;
 1372 }
 1373 
 1374 static int
 1375 sk_probe(dev)
 1376         device_t                dev;
 1377 {
 1378         struct sk_softc         *sc;
 1379 
 1380         sc = device_get_softc(device_get_parent(dev));
 1381 
 1382         /*
 1383          * Not much to do here. We always know there will be
 1384          * at least one XMAC present, and if there are two,
 1385          * skc_attach() will create a second device instance
 1386          * for us.
 1387          */
 1388         switch (sc->sk_type) {
 1389         case SK_GENESIS:
 1390                 device_set_desc(dev, "XaQti Corp. XMAC II");
 1391                 break;
 1392         case SK_YUKON:
 1393         case SK_YUKON_LITE:
 1394         case SK_YUKON_LP:
 1395                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
 1396                 break;
 1397         }
 1398 
 1399         return (BUS_PROBE_DEFAULT);
 1400 }
 1401 
 1402 /*
 1403  * Each XMAC chip is attached as a separate logical IP interface.
 1404  * Single port cards will have only one logical interface of course.
 1405  */
 1406 static int
 1407 sk_attach(dev)
 1408         device_t                dev;
 1409 {
 1410         struct sk_softc         *sc;
 1411         struct sk_if_softc      *sc_if;
 1412         struct ifnet            *ifp;
 1413         int                     i, port, error;
 1414         u_char                  eaddr[6];
 1415 
 1416         if (dev == NULL)
 1417                 return(EINVAL);
 1418 
 1419         error = 0;
 1420         sc_if = device_get_softc(dev);
 1421         sc = device_get_softc(device_get_parent(dev));
 1422         port = *(int *)device_get_ivars(dev);
 1423 
 1424         sc_if->sk_dev = dev;
 1425         sc_if->sk_unit = device_get_unit(dev);
 1426         sc_if->sk_port = port;
 1427         sc_if->sk_softc = sc;
 1428         sc->sk_if[port] = sc_if;
 1429         if (port == SK_PORT_A)
 1430                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
 1431         if (port == SK_PORT_B)
 1432                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
 1433 
 1434         /* Allocate the descriptor queues. */
 1435         sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
 1436             M_NOWAIT, M_ZERO, 0xffffffff, PAGE_SIZE, 0);
 1437 
 1438         if (sc_if->sk_rdata == NULL) {
 1439                 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
 1440                 error = ENOMEM;
 1441                 goto fail;
 1442         }
 1443 
 1444         /* Try to allocate memory for jumbo buffers. */
 1445         if (sk_alloc_jumbo_mem(sc_if)) {
 1446                 printf("sk%d: jumbo buffer allocation failed\n",
 1447                     sc_if->sk_unit);
 1448                 error = ENOMEM;
 1449                 goto fail;
 1450         }
 1451 
 1452         ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
 1453         if (ifp == NULL) {
 1454                 printf("sk%d: can not if_alloc()\n", sc_if->sk_unit);
 1455                 error = ENOSPC;
 1456                 goto fail;
 1457         }
 1458         ifp->if_softc = sc_if;
 1459         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 1460         ifp->if_mtu = ETHERMTU;
 1461         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1462         ifp->if_ioctl = sk_ioctl;
 1463         ifp->if_start = sk_start;
 1464         ifp->if_watchdog = sk_watchdog;
 1465         ifp->if_init = sk_init;
 1466         ifp->if_baudrate = 1000000000;
 1467         IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
 1468         ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
 1469         IFQ_SET_READY(&ifp->if_snd);
 1470 
 1471         callout_handle_init(&sc_if->sk_tick_ch);
 1472 
 1473         /*
 1474          * Get station address for this interface. Note that
 1475          * dual port cards actually come with three station
 1476          * addresses: one for each port, plus an extra. The
 1477          * extra one is used by the SysKonnect driver software
 1478          * as a 'virtual' station address for when both ports
 1479          * are operating in failover mode. Currently we don't
 1480          * use this extra address.
 1481          */
 1482         SK_LOCK(sc);
 1483         for (i = 0; i < ETHER_ADDR_LEN; i++)
 1484                 eaddr[i] =
 1485                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
 1486 
 1487         /*
 1488          * Set up RAM buffer addresses. The NIC will have a certain
 1489          * amount of SRAM on it, somewhere between 512K and 2MB. We
 1490          * need to divide this up a) between the transmitter and
 1491          * receiver and b) between the two XMACs, if this is a
 1492          * dual port NIC. Our algotithm is to divide up the memory
 1493          * evenly so that everyone gets a fair share.
 1494          */
 1495         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
 1496                 u_int32_t               chunk, val;
 1497 
 1498                 chunk = sc->sk_ramsize / 2;
 1499                 val = sc->sk_rboff / sizeof(u_int64_t);
 1500                 sc_if->sk_rx_ramstart = val;
 1501                 val += (chunk / sizeof(u_int64_t));
 1502                 sc_if->sk_rx_ramend = val - 1;
 1503                 sc_if->sk_tx_ramstart = val;
 1504                 val += (chunk / sizeof(u_int64_t));
 1505                 sc_if->sk_tx_ramend = val - 1;
 1506         } else {
 1507                 u_int32_t               chunk, val;
 1508 
 1509                 chunk = sc->sk_ramsize / 4;
 1510                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
 1511                     sizeof(u_int64_t);
 1512                 sc_if->sk_rx_ramstart = val;
 1513                 val += (chunk / sizeof(u_int64_t));
 1514                 sc_if->sk_rx_ramend = val - 1;
 1515                 sc_if->sk_tx_ramstart = val;
 1516                 val += (chunk / sizeof(u_int64_t));
 1517                 sc_if->sk_tx_ramend = val - 1;
 1518         }
 1519 
 1520         /* Read and save PHY type and set PHY address */
 1521         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
 1522         switch(sc_if->sk_phytype) {
 1523         case SK_PHYTYPE_XMAC:
 1524                 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
 1525                 break;
 1526         case SK_PHYTYPE_BCOM:
 1527                 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
 1528                 break;
 1529         case SK_PHYTYPE_MARV_COPPER:
 1530                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
 1531                 break;
 1532         default:
 1533                 printf("skc%d: unsupported PHY type: %d\n",
 1534                     sc->sk_unit, sc_if->sk_phytype);
 1535                 error = ENODEV;
 1536                 SK_UNLOCK(sc);
 1537                 goto fail;
 1538         }
 1539 
 1540 
 1541         /*
 1542          * Call MI attach routine.  Can't hold locks when calling into ether_*.
 1543          */
 1544         SK_UNLOCK(sc);
 1545         ether_ifattach(ifp, eaddr);
 1546         SK_LOCK(sc);
 1547 
 1548         /*
 1549          * Do miibus setup.
 1550          */
 1551         switch (sc->sk_type) {
 1552         case SK_GENESIS:
 1553                 sk_init_xmac(sc_if);
 1554                 break;
 1555         case SK_YUKON:
 1556         case SK_YUKON_LITE:
 1557         case SK_YUKON_LP:
 1558                 sk_init_yukon(sc_if);
 1559                 break;
 1560         }
 1561 
 1562         SK_UNLOCK(sc);
 1563         if (mii_phy_probe(dev, &sc_if->sk_miibus,
 1564             sk_ifmedia_upd, sk_ifmedia_sts)) {
 1565                 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
 1566                 ether_ifdetach(ifp);
 1567                 error = ENXIO;
 1568                 goto fail;
 1569         }
 1570 
 1571 fail:
 1572         if (error) {
 1573                 /* Access should be ok even though lock has been dropped */
 1574                 sc->sk_if[port] = NULL;
 1575                 sk_detach(dev);
 1576         }
 1577 
 1578         return(error);
 1579 }
 1580 
 1581 /*
 1582  * Attach the interface. Allocate softc structures, do ifmedia
 1583  * setup and ethernet/BPF attach.
 1584  */
 1585 static int
 1586 skc_attach(dev)
 1587         device_t                dev;
 1588 {
 1589         struct sk_softc         *sc;
 1590         int                     unit, error = 0, rid, *port;
 1591         uint8_t                 skrs;
 1592         char                    *pname, *revstr;
 1593 
 1594         sc = device_get_softc(dev);
 1595         unit = device_get_unit(dev);
 1596 
 1597         mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 1598             MTX_DEF | MTX_RECURSE);
 1599         /*
 1600          * Map control/status registers.
 1601          */
 1602         pci_enable_busmaster(dev);
 1603 
 1604         rid = SK_RID;
 1605         sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE);
 1606 
 1607         if (sc->sk_res == NULL) {
 1608                 printf("sk%d: couldn't map ports/memory\n", unit);
 1609                 error = ENXIO;
 1610                 goto fail;
 1611         }
 1612 
 1613         sc->sk_btag = rman_get_bustag(sc->sk_res);
 1614         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
 1615 
 1616         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
 1617         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
 1618 
 1619         /* Bail out if chip is not recognized. */
 1620         if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
 1621                 printf("skc%d: unknown device: chipver=%02x, rev=%x\n",
 1622                         unit, sc->sk_type, sc->sk_rev);
 1623                 error = ENXIO;
 1624                 goto fail;
 1625         }
 1626 
 1627         /* Allocate interrupt */
 1628         rid = 0;
 1629         sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 1630             RF_SHAREABLE | RF_ACTIVE);
 1631 
 1632         if (sc->sk_irq == NULL) {
 1633                 printf("skc%d: couldn't map interrupt\n", unit);
 1634                 error = ENXIO;
 1635                 goto fail;
 1636         }
 1637 
 1638         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 1639                 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 1640                 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
 1641                 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
 1642                 "SK interrupt moderation");
 1643 
 1644         /* Pull in device tunables. */
 1645         sc->sk_int_mod = SK_IM_DEFAULT;
 1646         error = resource_int_value(device_get_name(dev), unit,
 1647                 "int_mod", &sc->sk_int_mod);
 1648         if (error == 0) {
 1649                 if (sc->sk_int_mod < SK_IM_MIN ||
 1650                     sc->sk_int_mod > SK_IM_MAX) {
 1651                         printf("skc%d: int_mod value out of range; "
 1652                             "using default: %d\n", unit, SK_IM_DEFAULT);
 1653                         sc->sk_int_mod = SK_IM_DEFAULT;
 1654                 }
 1655         }
 1656 
 1657         /* Reset the adapter. */
 1658         sk_reset(sc);
 1659 
 1660         sc->sk_unit = unit;
 1661 
 1662         /* Read and save vital product data from EEPROM. */
 1663         sk_vpd_read(sc);
 1664 
 1665         skrs = sk_win_read_1(sc, SK_EPROM0);
 1666         if (sc->sk_type == SK_GENESIS) {
 1667                 /* Read and save RAM size and RAMbuffer offset */
 1668                 switch(skrs) {
 1669                 case SK_RAMSIZE_512K_64:
 1670                         sc->sk_ramsize = 0x80000;
 1671                         sc->sk_rboff = SK_RBOFF_0;
 1672                         break;
 1673                 case SK_RAMSIZE_1024K_64:
 1674                         sc->sk_ramsize = 0x100000;
 1675                         sc->sk_rboff = SK_RBOFF_80000;
 1676                         break;
 1677                 case SK_RAMSIZE_1024K_128:
 1678                         sc->sk_ramsize = 0x100000;
 1679                         sc->sk_rboff = SK_RBOFF_0;
 1680                         break;
 1681                 case SK_RAMSIZE_2048K_128:
 1682                         sc->sk_ramsize = 0x200000;
 1683                         sc->sk_rboff = SK_RBOFF_0;
 1684                         break;
 1685                 default:
 1686                         printf("skc%d: unknown ram size: %d\n",
 1687                             sc->sk_unit, skrs);
 1688                         error = ENXIO;
 1689                         goto fail;
 1690                 }
 1691         } else { /* SK_YUKON_FAMILY */
 1692                 if (skrs == 0x00)
 1693                         sc->sk_ramsize = 0x20000;
 1694                 else
 1695                         sc->sk_ramsize = skrs * (1<<12);
 1696                 sc->sk_rboff = SK_RBOFF_0;
 1697         }
 1698 
 1699         /* Read and save physical media type */
 1700         switch(sk_win_read_1(sc, SK_PMDTYPE)) {
 1701         case SK_PMD_1000BASESX:
 1702                 sc->sk_pmd = IFM_1000_SX;
 1703                 break;
 1704         case SK_PMD_1000BASELX:
 1705                 sc->sk_pmd = IFM_1000_LX;
 1706                 break;
 1707         case SK_PMD_1000BASECX:
 1708                 sc->sk_pmd = IFM_1000_CX;
 1709                 break;
 1710         case SK_PMD_1000BASETX:
 1711                 sc->sk_pmd = IFM_1000_T;
 1712                 break;
 1713         default:
 1714                 printf("skc%d: unknown media type: 0x%x\n",
 1715                     sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
 1716                 error = ENXIO;
 1717                 goto fail;
 1718         }
 1719 
 1720         /* Determine whether to name it with VPD PN or just make it up.
 1721          * Marvell Yukon VPD PN seems to freqently be bogus. */
 1722         switch (pci_get_device(dev)) {
 1723         case DEVICEID_SK_V1:
 1724         case DEVICEID_BELKIN_5005:
 1725         case DEVICEID_3COM_3C940:
 1726         case DEVICEID_LINKSYS_EG1032:
 1727         case DEVICEID_DLINK_DGE530T:
 1728                 /* Stay with VPD PN. */
 1729                 pname = sc->sk_vpd_prodname;
 1730                 break;
 1731         case DEVICEID_SK_V2:
 1732                 /* YUKON VPD PN might bear no resemblance to reality. */
 1733                 switch (sc->sk_type) {
 1734                 case SK_GENESIS:
 1735                         /* Stay with VPD PN. */
 1736                         pname = sc->sk_vpd_prodname;
 1737                         break;
 1738                 case SK_YUKON:
 1739                         pname = "Marvell Yukon Gigabit Ethernet";
 1740                         break;
 1741                 case SK_YUKON_LITE:
 1742                         pname = "Marvell Yukon Lite Gigabit Ethernet";
 1743                         break;
 1744                 case SK_YUKON_LP:
 1745                         pname = "Marvell Yukon LP Gigabit Ethernet";
 1746                         break;
 1747                 default:
 1748                         pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
 1749                         break;
 1750                 }
 1751 
 1752                 /* Yukon Lite Rev. A0 needs special test. */
 1753                 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
 1754                         u_int32_t far;
 1755                         u_int8_t testbyte;
 1756 
 1757                         /* Save flash address register before testing. */
 1758                         far = sk_win_read_4(sc, SK_EP_ADDR);
 1759 
 1760                         sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
 1761                         testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
 1762 
 1763                         if (testbyte != 0x00) {
 1764                                 /* Yukon Lite Rev. A0 detected. */
 1765                                 sc->sk_type = SK_YUKON_LITE;
 1766                                 sc->sk_rev = SK_YUKON_LITE_REV_A0;
 1767                                 /* Restore flash address register. */
 1768                                 sk_win_write_4(sc, SK_EP_ADDR, far);
 1769                         }
 1770                 }
 1771                 break;
 1772         default:
 1773                 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
 1774                         "chipver=%02x, rev=%x\n",
 1775                         pci_get_vendor(dev), pci_get_device(dev),
 1776                         sc->sk_type, sc->sk_rev);
 1777                 error = ENXIO;
 1778                 goto fail;
 1779         }
 1780 
 1781         if (sc->sk_type == SK_YUKON_LITE) {
 1782                 switch (sc->sk_rev) {
 1783                 case SK_YUKON_LITE_REV_A0:
 1784                         revstr = "A0";
 1785                         break;
 1786                 case SK_YUKON_LITE_REV_A1:
 1787                         revstr = "A1";
 1788                         break;
 1789                 case SK_YUKON_LITE_REV_A3:
 1790                         revstr = "A3";
 1791                         break;
 1792                 default:
 1793                         revstr = "";
 1794                         break;
 1795                 }
 1796         } else {
 1797                 revstr = "";
 1798         }
 1799 
 1800         /* Announce the product name and more VPD data if there. */
 1801         device_printf(dev, "%s rev. %s(0x%x)\n",
 1802                 pname != NULL ? pname : "<unknown>", revstr, sc->sk_rev);
 1803 
 1804         if (bootverbose) {
 1805                 if (sc->sk_vpd_readonly != NULL &&
 1806                     sc->sk_vpd_readonly_len != 0) {
 1807                         char buf[256];
 1808                         char *dp = sc->sk_vpd_readonly;
 1809                         uint16_t l, len = sc->sk_vpd_readonly_len;
 1810 
 1811                         while (len >= 3) {
 1812                                 if ((*dp == 'P' && *(dp+1) == 'N') ||
 1813                                     (*dp == 'E' && *(dp+1) == 'C') ||
 1814                                     (*dp == 'M' && *(dp+1) == 'N') ||
 1815                                     (*dp == 'S' && *(dp+1) == 'N')) {
 1816                                         l = 0;
 1817                                         while (l < *(dp+2)) {
 1818                                                 buf[l] = *(dp+3+l);
 1819                                                 ++l;
 1820                                         }
 1821                                         buf[l] = '\0';
 1822                                         device_printf(dev, "%c%c: %s\n",
 1823                                             *dp, *(dp+1), buf);
 1824                                         len -= (3 + l);
 1825                                         dp += (3 + l);
 1826                                 } else {
 1827                                         len -= (3 + *(dp+2));
 1828                                         dp += (3 + *(dp+2));
 1829                                 }
 1830                         }
 1831                 }
 1832                 device_printf(dev, "chip ver  = 0x%02x\n", sc->sk_type);
 1833                 device_printf(dev, "chip rev  = 0x%02x\n", sc->sk_rev);
 1834                 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
 1835                 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
 1836         }
 1837 
 1838         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
 1839         if (sc->sk_devs[SK_PORT_A] == NULL) {
 1840                 device_printf(dev, "failed to add child for PORT_A\n");
 1841                 error = ENXIO;
 1842                 goto fail;
 1843         }
 1844         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
 1845         if (port == NULL) {
 1846                 device_printf(dev, "failed to allocate memory for "
 1847                     "ivars of PORT_A\n");
 1848                 error = ENXIO;
 1849                 goto fail;
 1850         }
 1851         *port = SK_PORT_A;
 1852         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
 1853 
 1854         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
 1855                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
 1856                 if (sc->sk_devs[SK_PORT_B] == NULL) {
 1857                         device_printf(dev, "failed to add child for PORT_B\n");
 1858                         error = ENXIO;
 1859                         goto fail;
 1860                 }
 1861                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
 1862                 if (port == NULL) {
 1863                         device_printf(dev, "failed to allocate memory for "
 1864                             "ivars of PORT_B\n");
 1865                         error = ENXIO;
 1866                         goto fail;
 1867                 }
 1868                 *port = SK_PORT_B;
 1869                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
 1870         }
 1871 
 1872         /* Turn on the 'driver is loaded' LED. */
 1873         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
 1874 
 1875         error = bus_generic_attach(dev);
 1876         if (error) {
 1877                 device_printf(dev, "failed to attach port(s)\n");
 1878                 goto fail;
 1879         }
 1880 
 1881         /* Hook interrupt last to avoid having to lock softc */
 1882         error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET|INTR_MPSAFE,
 1883             sk_intr, sc, &sc->sk_intrhand);
 1884 
 1885         if (error) {
 1886                 printf("skc%d: couldn't set up irq\n", unit);
 1887                 goto fail;
 1888         }
 1889 
 1890 fail:
 1891         if (error)
 1892                 skc_detach(dev);
 1893 
 1894         return(error);
 1895 }
 1896 
 1897 /*
 1898  * Shutdown hardware and free up resources. This can be called any
 1899  * time after the mutex has been initialized. It is called in both
 1900  * the error case in attach and the normal detach case so it needs
 1901  * to be careful about only freeing resources that have actually been
 1902  * allocated.
 1903  */
 1904 static int
 1905 sk_detach(dev)
 1906         device_t                dev;
 1907 {
 1908         struct sk_if_softc      *sc_if;
 1909         struct ifnet            *ifp;
 1910 
 1911         sc_if = device_get_softc(dev);
 1912         KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
 1913             ("sk mutex not initialized in sk_detach"));
 1914         SK_IF_LOCK(sc_if);
 1915 
 1916         ifp = sc_if->sk_ifp;
 1917         /* These should only be active if attach_xmac succeeded */
 1918         if (device_is_attached(dev)) {
 1919                 sk_stop(sc_if);
 1920                 /* Can't hold locks while calling detach */
 1921                 SK_IF_UNLOCK(sc_if);
 1922                 ether_ifdetach(ifp);
 1923                 SK_IF_LOCK(sc_if);
 1924         }
 1925         if (ifp)
 1926                 if_free(ifp);
 1927         /*
 1928          * We're generally called from skc_detach() which is using
 1929          * device_delete_child() to get to here. It's already trashed
 1930          * miibus for us, so don't do it here or we'll panic.
 1931          */
 1932         /*
 1933         if (sc_if->sk_miibus != NULL)
 1934                 device_delete_child(dev, sc_if->sk_miibus);
 1935         */
 1936         bus_generic_detach(dev);
 1937         if (sc_if->sk_cdata.sk_jumbo_buf != NULL)
 1938                 sk_free_jumbo_mem(sc_if);
 1939         if (sc_if->sk_rdata != NULL) {
 1940                 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data),
 1941                     M_DEVBUF);
 1942         }
 1943         SK_IF_UNLOCK(sc_if);
 1944 
 1945         return(0);
 1946 }
 1947 
 1948 static int
 1949 skc_detach(dev)
 1950         device_t                dev;
 1951 {
 1952         struct sk_softc         *sc;
 1953 
 1954         sc = device_get_softc(dev);
 1955         KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
 1956 
 1957         if (device_is_alive(dev)) {
 1958                 if (sc->sk_devs[SK_PORT_A] != NULL) {
 1959                         free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
 1960                         device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
 1961                 }
 1962                 if (sc->sk_devs[SK_PORT_B] != NULL) {
 1963                         free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
 1964                         device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
 1965                 }
 1966                 bus_generic_detach(dev);
 1967         }
 1968 
 1969         if (sc->sk_vpd_prodname != NULL)
 1970                 free(sc->sk_vpd_prodname, M_DEVBUF);
 1971         if (sc->sk_vpd_readonly != NULL)
 1972                 free(sc->sk_vpd_readonly, M_DEVBUF);
 1973 
 1974         if (sc->sk_intrhand)
 1975                 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
 1976         if (sc->sk_irq)
 1977                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
 1978         if (sc->sk_res)
 1979                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
 1980 
 1981         mtx_destroy(&sc->sk_mtx);
 1982 
 1983         return(0);
 1984 }
 1985 
 1986 static int
 1987 sk_encap(sc_if, m_head, txidx)
 1988         struct sk_if_softc      *sc_if;
 1989         struct mbuf             *m_head;
 1990         u_int32_t               *txidx;
 1991 {
 1992         struct sk_tx_desc       *f = NULL;
 1993         struct mbuf             *m;
 1994         u_int32_t               frag, cur, cnt = 0;
 1995 
 1996         SK_IF_LOCK_ASSERT(sc_if);
 1997 
 1998         m = m_head;
 1999         cur = frag = *txidx;
 2000 
 2001         /*
 2002          * Start packing the mbufs in this chain into
 2003          * the fragment pointers. Stop when we run out
 2004          * of fragments or hit the end of the mbuf chain.
 2005          */
 2006         for (m = m_head; m != NULL; m = m->m_next) {
 2007                 if (m->m_len != 0) {
 2008                         if ((SK_TX_RING_CNT -
 2009                             (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
 2010                                 return(ENOBUFS);
 2011                         f = &sc_if->sk_rdata->sk_tx_ring[frag];
 2012                         f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
 2013                         f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
 2014                         if (cnt == 0)
 2015                                 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
 2016                         else
 2017                                 f->sk_ctl |= SK_TXCTL_OWN;
 2018                         cur = frag;
 2019                         SK_INC(frag, SK_TX_RING_CNT);
 2020                         cnt++;
 2021                 }
 2022         }
 2023 
 2024         if (m != NULL)
 2025                 return(ENOBUFS);
 2026 
 2027         sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
 2028                 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
 2029         sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
 2030         sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
 2031         sc_if->sk_cdata.sk_tx_cnt += cnt;
 2032 
 2033         *txidx = frag;
 2034 
 2035         return(0);
 2036 }
 2037 
 2038 static void
 2039 sk_start(ifp)
 2040         struct ifnet            *ifp;
 2041 {
 2042         struct sk_if_softc *sc_if;
 2043 
 2044         sc_if = ifp->if_softc;
 2045 
 2046         SK_IF_LOCK(sc_if);
 2047         sk_start_locked(ifp);
 2048         SK_IF_UNLOCK(sc_if);
 2049 
 2050         return;
 2051 }
 2052 
 2053 static void
 2054 sk_start_locked(ifp)
 2055         struct ifnet            *ifp;
 2056 {
 2057         struct sk_softc         *sc;
 2058         struct sk_if_softc      *sc_if;
 2059         struct mbuf             *m_head = NULL;
 2060         u_int32_t               idx;
 2061 
 2062         sc_if = ifp->if_softc;
 2063         sc = sc_if->sk_softc;
 2064 
 2065         SK_IF_LOCK_ASSERT(sc_if);
 2066 
 2067         idx = sc_if->sk_cdata.sk_tx_prod;
 2068 
 2069         while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
 2070                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
 2071                 if (m_head == NULL)
 2072                         break;
 2073 
 2074                 /*
 2075                  * Pack the data into the transmit ring. If we
 2076                  * don't have room, set the OACTIVE flag and wait
 2077                  * for the NIC to drain the ring.
 2078                  */
 2079                 if (sk_encap(sc_if, m_head, &idx)) {
 2080                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
 2081                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 2082                         break;
 2083                 }
 2084 
 2085                 /*
 2086                  * If there's a BPF listener, bounce a copy of this frame
 2087                  * to him.
 2088                  */
 2089                 BPF_MTAP(ifp, m_head);
 2090         }
 2091 
 2092         /* Transmit */
 2093         if (idx != sc_if->sk_cdata.sk_tx_prod) {
 2094                 sc_if->sk_cdata.sk_tx_prod = idx;
 2095                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
 2096 
 2097                 /* Set a timeout in case the chip goes out to lunch. */
 2098                 ifp->if_timer = 5;
 2099         }
 2100 
 2101         return;
 2102 }
 2103 
 2104 
 2105 static void
 2106 sk_watchdog(ifp)
 2107         struct ifnet            *ifp;
 2108 {
 2109         struct sk_if_softc      *sc_if;
 2110 
 2111         sc_if = ifp->if_softc;
 2112 
 2113         printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
 2114         SK_IF_LOCK(sc_if);
 2115         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 2116         sk_init_locked(sc_if);
 2117         SK_IF_UNLOCK(sc_if);
 2118 
 2119         return;
 2120 }
 2121 
 2122 static void
 2123 skc_shutdown(dev)
 2124         device_t                dev;
 2125 {
 2126         struct sk_softc         *sc;
 2127 
 2128         sc = device_get_softc(dev);
 2129         SK_LOCK(sc);
 2130 
 2131         /* Turn off the 'driver is loaded' LED. */
 2132         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
 2133 
 2134         /*
 2135          * Reset the GEnesis controller. Doing this should also
 2136          * assert the resets on the attached XMAC(s).
 2137          */
 2138         sk_reset(sc);
 2139         SK_UNLOCK(sc);
 2140 
 2141         return;
 2142 }
 2143 
 2144 static void
 2145 sk_rxeof(sc_if)
 2146         struct sk_if_softc      *sc_if;
 2147 {
 2148         struct sk_softc         *sc;
 2149         struct mbuf             *m;
 2150         struct ifnet            *ifp;
 2151         struct sk_chain         *cur_rx;
 2152         int                     total_len = 0;
 2153         int                     i;
 2154         u_int32_t               rxstat;
 2155 
 2156         sc = sc_if->sk_softc;
 2157         ifp = sc_if->sk_ifp;
 2158         i = sc_if->sk_cdata.sk_rx_prod;
 2159         cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
 2160 
 2161         SK_LOCK_ASSERT(sc);
 2162 
 2163         while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
 2164 
 2165                 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
 2166                 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
 2167                 m = cur_rx->sk_mbuf;
 2168                 cur_rx->sk_mbuf = NULL;
 2169                 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
 2170                 SK_INC(i, SK_RX_RING_CNT);
 2171 
 2172                 if (rxstat & XM_RXSTAT_ERRFRAME) {
 2173                         ifp->if_ierrors++;
 2174                         sk_newbuf(sc_if, cur_rx, m);
 2175                         continue;
 2176                 }
 2177 
 2178                 /*
 2179                  * Try to allocate a new jumbo buffer. If that
 2180                  * fails, copy the packet to mbufs and put the
 2181                  * jumbo buffer back in the ring so it can be
 2182                  * re-used. If allocating mbufs fails, then we
 2183                  * have to drop the packet.
 2184                  */
 2185                 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
 2186                         struct mbuf             *m0;
 2187                         m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
 2188                             ifp, NULL);
 2189                         sk_newbuf(sc_if, cur_rx, m);
 2190                         if (m0 == NULL) {
 2191                                 printf("sk%d: no receive buffers "
 2192                                     "available -- packet dropped!\n",
 2193                                     sc_if->sk_unit);
 2194                                 ifp->if_ierrors++;
 2195                                 continue;
 2196                         }
 2197                         m = m0;
 2198                 } else {
 2199                         m->m_pkthdr.rcvif = ifp;
 2200                         m->m_pkthdr.len = m->m_len = total_len;
 2201                 }
 2202 
 2203                 ifp->if_ipackets++;
 2204                 SK_UNLOCK(sc);
 2205                 (*ifp->if_input)(ifp, m);
 2206                 SK_LOCK(sc);
 2207         }
 2208 
 2209         sc_if->sk_cdata.sk_rx_prod = i;
 2210 
 2211         return;
 2212 }
 2213 
 2214 static void
 2215 sk_txeof(sc_if)
 2216         struct sk_if_softc      *sc_if;
 2217 {
 2218         struct sk_softc         *sc;
 2219         struct sk_tx_desc       *cur_tx;
 2220         struct ifnet            *ifp;
 2221         u_int32_t               idx;
 2222 
 2223         sc = sc_if->sk_softc;
 2224         ifp = sc_if->sk_ifp;
 2225 
 2226         /*
 2227          * Go through our tx ring and free mbufs for those
 2228          * frames that have been sent.
 2229          */
 2230         idx = sc_if->sk_cdata.sk_tx_cons;
 2231         while(idx != sc_if->sk_cdata.sk_tx_prod) {
 2232                 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
 2233                 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
 2234                         break;
 2235                 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
 2236                         ifp->if_opackets++;
 2237                 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
 2238                         m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
 2239                         sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
 2240                 }
 2241                 sc_if->sk_cdata.sk_tx_cnt--;
 2242                 SK_INC(idx, SK_TX_RING_CNT);
 2243         }
 2244 
 2245         if (sc_if->sk_cdata.sk_tx_cnt == 0) {
 2246                 ifp->if_timer = 0;
 2247         } else /* nudge chip to keep tx ring moving */
 2248                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
 2249 
 2250         if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2)
 2251                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 2252 
 2253         sc_if->sk_cdata.sk_tx_cons = idx;
 2254 }
 2255 
 2256 static void
 2257 sk_tick(xsc_if)
 2258         void                    *xsc_if;
 2259 {
 2260         struct sk_if_softc      *sc_if;
 2261         struct mii_data         *mii;
 2262         struct ifnet            *ifp;
 2263         int                     i;
 2264 
 2265         sc_if = xsc_if;
 2266         SK_IF_LOCK(sc_if);
 2267         ifp = sc_if->sk_ifp;
 2268         mii = device_get_softc(sc_if->sk_miibus);
 2269 
 2270         if (!(ifp->if_flags & IFF_UP)) {
 2271                 SK_IF_UNLOCK(sc_if);
 2272                 return;
 2273         }
 2274 
 2275         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
 2276                 sk_intr_bcom(sc_if);
 2277                 SK_IF_UNLOCK(sc_if);
 2278                 return;
 2279         }
 2280 
 2281         /*
 2282          * According to SysKonnect, the correct way to verify that
 2283          * the link has come back up is to poll bit 0 of the GPIO
 2284          * register three times. This pin has the signal from the
 2285          * link_sync pin connected to it; if we read the same link
 2286          * state 3 times in a row, we know the link is up.
 2287          */
 2288         for (i = 0; i < 3; i++) {
 2289                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
 2290                         break;
 2291         }
 2292 
 2293         if (i != 3) {
 2294                 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
 2295                 SK_IF_UNLOCK(sc_if);
 2296                 return;
 2297         }
 2298 
 2299         /* Turn the GP0 interrupt back on. */
 2300         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
 2301         SK_XM_READ_2(sc_if, XM_ISR);
 2302         mii_tick(mii);
 2303         untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
 2304 
 2305         SK_IF_UNLOCK(sc_if);
 2306         return;
 2307 }
 2308 
 2309 static void
 2310 sk_intr_bcom(sc_if)
 2311         struct sk_if_softc      *sc_if;
 2312 {
 2313         struct mii_data         *mii;
 2314         struct ifnet            *ifp;
 2315         int                     status;
 2316         mii = device_get_softc(sc_if->sk_miibus);
 2317         ifp = sc_if->sk_ifp;
 2318 
 2319         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
 2320 
 2321         /*
 2322          * Read the PHY interrupt register to make sure
 2323          * we clear any pending interrupts.
 2324          */
 2325         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
 2326 
 2327         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
 2328                 sk_init_xmac(sc_if);
 2329                 return;
 2330         }
 2331 
 2332         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
 2333                 int                     lstat;
 2334                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
 2335                     BRGPHY_MII_AUXSTS);
 2336 
 2337                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
 2338                         mii_mediachg(mii);
 2339                         /* Turn off the link LED. */
 2340                         SK_IF_WRITE_1(sc_if, 0,
 2341                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
 2342                         sc_if->sk_link = 0;
 2343                 } else if (status & BRGPHY_ISR_LNK_CHG) {
 2344                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
 2345                             BRGPHY_MII_IMR, 0xFF00);
 2346                         mii_tick(mii);
 2347                         sc_if->sk_link = 1;
 2348                         /* Turn on the link LED. */
 2349                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
 2350                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
 2351                             SK_LINKLED_BLINK_OFF);
 2352                 } else {
 2353                         mii_tick(mii);
 2354                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
 2355                 }
 2356         }
 2357 
 2358         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
 2359 
 2360         return;
 2361 }
 2362 
 2363 static void
 2364 sk_intr_xmac(sc_if)
 2365         struct sk_if_softc      *sc_if;
 2366 {
 2367         struct sk_softc         *sc;
 2368         u_int16_t               status;
 2369 
 2370         sc = sc_if->sk_softc;
 2371         status = SK_XM_READ_2(sc_if, XM_ISR);
 2372 
 2373         /*
 2374          * Link has gone down. Start MII tick timeout to
 2375          * watch for link resync.
 2376          */
 2377         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
 2378                 if (status & XM_ISR_GP0_SET) {
 2379                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
 2380                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
 2381                 }
 2382 
 2383                 if (status & XM_ISR_AUTONEG_DONE) {
 2384                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
 2385                 }
 2386         }
 2387 
 2388         if (status & XM_IMR_TX_UNDERRUN)
 2389                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
 2390 
 2391         if (status & XM_IMR_RX_OVERRUN)
 2392                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
 2393 
 2394         status = SK_XM_READ_2(sc_if, XM_ISR);
 2395 
 2396         return;
 2397 }
 2398 
 2399 static void
 2400 sk_intr_yukon(sc_if)
 2401         struct sk_if_softc      *sc_if;
 2402 {
 2403         int status;
 2404 
 2405         status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
 2406 
 2407         return;
 2408 }
 2409 
 2410 static void
 2411 sk_intr(xsc)
 2412         void                    *xsc;
 2413 {
 2414         struct sk_softc         *sc = xsc;
 2415         struct sk_if_softc      *sc_if0 = NULL, *sc_if1 = NULL;
 2416         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
 2417         u_int32_t               status;
 2418 
 2419         SK_LOCK(sc);
 2420 
 2421         sc_if0 = sc->sk_if[SK_PORT_A];
 2422         sc_if1 = sc->sk_if[SK_PORT_B];
 2423 
 2424         if (sc_if0 != NULL)
 2425                 ifp0 = sc_if0->sk_ifp;
 2426         if (sc_if1 != NULL)
 2427                 ifp1 = sc_if1->sk_ifp;
 2428 
 2429         for (;;) {
 2430                 status = CSR_READ_4(sc, SK_ISSR);
 2431                 if (!(status & sc->sk_intrmask))
 2432                         break;
 2433 
 2434                 /* Handle receive interrupts first. */
 2435                 if (status & SK_ISR_RX1_EOF) {
 2436                         sk_rxeof(sc_if0);
 2437                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
 2438                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
 2439                 }
 2440                 if (status & SK_ISR_RX2_EOF) {
 2441                         sk_rxeof(sc_if1);
 2442                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
 2443                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
 2444                 }
 2445 
 2446                 /* Then transmit interrupts. */
 2447                 if (status & SK_ISR_TX1_S_EOF) {
 2448                         sk_txeof(sc_if0);
 2449                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
 2450                             SK_TXBMU_CLR_IRQ_EOF);
 2451                 }
 2452                 if (status & SK_ISR_TX2_S_EOF) {
 2453                         sk_txeof(sc_if1);
 2454                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
 2455                             SK_TXBMU_CLR_IRQ_EOF);
 2456                 }
 2457 
 2458                 /* Then MAC interrupts. */
 2459                 if (status & SK_ISR_MAC1 &&
 2460                     ifp0->if_drv_flags & IFF_DRV_RUNNING) {
 2461                         if (sc->sk_type == SK_GENESIS)
 2462                                 sk_intr_xmac(sc_if0);
 2463                         else
 2464                                 sk_intr_yukon(sc_if0);
 2465                 }
 2466 
 2467                 if (status & SK_ISR_MAC2 &&
 2468                     ifp1->if_drv_flags & IFF_DRV_RUNNING) {
 2469                         if (sc->sk_type == SK_GENESIS)
 2470                                 sk_intr_xmac(sc_if1);
 2471                         else
 2472                                 sk_intr_yukon(sc_if1);
 2473                 }
 2474 
 2475                 if (status & SK_ISR_EXTERNAL_REG) {
 2476                         if (ifp0 != NULL &&
 2477                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
 2478                                 sk_intr_bcom(sc_if0);
 2479                         if (ifp1 != NULL &&
 2480                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
 2481                                 sk_intr_bcom(sc_if1);
 2482                 }
 2483         }
 2484 
 2485         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
 2486 
 2487         if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
 2488                 sk_start_locked(ifp0);
 2489         if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
 2490                 sk_start_locked(ifp1);
 2491 
 2492         SK_UNLOCK(sc);
 2493 
 2494         return;
 2495 }
 2496 
 2497 static void
 2498 sk_init_xmac(sc_if)
 2499         struct sk_if_softc      *sc_if;
 2500 {
 2501         struct sk_softc         *sc;
 2502         struct ifnet            *ifp;
 2503         struct sk_bcom_hack     bhack[] = {
 2504         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
 2505         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
 2506         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
 2507         { 0, 0 } };
 2508 
 2509         sc = sc_if->sk_softc;
 2510         ifp = sc_if->sk_ifp;
 2511 
 2512         /* Unreset the XMAC. */
 2513         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
 2514         DELAY(1000);
 2515 
 2516         /* Reset the XMAC's internal state. */
 2517         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
 2518 
 2519         /* Save the XMAC II revision */
 2520         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
 2521 
 2522         /*
 2523          * Perform additional initialization for external PHYs,
 2524          * namely for the 1000baseTX cards that use the XMAC's
 2525          * GMII mode.
 2526          */
 2527         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
 2528                 int                     i = 0;
 2529                 u_int32_t               val;
 2530 
 2531                 /* Take PHY out of reset. */
 2532                 val = sk_win_read_4(sc, SK_GPIO);
 2533                 if (sc_if->sk_port == SK_PORT_A)
 2534                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
 2535                 else
 2536                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
 2537                 sk_win_write_4(sc, SK_GPIO, val);
 2538 
 2539                 /* Enable GMII mode on the XMAC. */
 2540                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
 2541 
 2542                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
 2543                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
 2544                 DELAY(10000);
 2545                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
 2546                     BRGPHY_MII_IMR, 0xFFF0);
 2547 
 2548                 /*
 2549                  * Early versions of the BCM5400 apparently have
 2550                  * a bug that requires them to have their reserved
 2551                  * registers initialized to some magic values. I don't
 2552                  * know what the numbers do, I'm just the messenger.
 2553                  */
 2554                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
 2555                     == 0x6041) {
 2556                         while(bhack[i].reg) {
 2557                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
 2558                                     bhack[i].reg, bhack[i].val);
 2559                                 i++;
 2560                         }
 2561                 }
 2562         }
 2563 
 2564         /* Set station address */
 2565         SK_XM_WRITE_2(sc_if, XM_PAR0,
 2566             *(u_int16_t *)(&IFP2ENADDR(sc_if->sk_ifp)[0]));
 2567         SK_XM_WRITE_2(sc_if, XM_PAR1,
 2568             *(u_int16_t *)(&IFP2ENADDR(sc_if->sk_ifp)[2]));
 2569         SK_XM_WRITE_2(sc_if, XM_PAR2,
 2570             *(u_int16_t *)(&IFP2ENADDR(sc_if->sk_ifp)[4]));
 2571         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
 2572 
 2573         if (ifp->if_flags & IFF_BROADCAST) {
 2574                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
 2575         } else {
 2576                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
 2577         }
 2578 
 2579         /* We don't need the FCS appended to the packet. */
 2580         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
 2581 
 2582         /* We want short frames padded to 60 bytes. */
 2583         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
 2584 
 2585         /*
 2586          * Enable the reception of all error frames. This is is
 2587          * a necessary evil due to the design of the XMAC. The
 2588          * XMAC's receive FIFO is only 8K in size, however jumbo
 2589          * frames can be up to 9000 bytes in length. When bad
 2590          * frame filtering is enabled, the XMAC's RX FIFO operates
 2591          * in 'store and forward' mode. For this to work, the
 2592          * entire frame has to fit into the FIFO, but that means
 2593          * that jumbo frames larger than 8192 bytes will be
 2594          * truncated. Disabling all bad frame filtering causes
 2595          * the RX FIFO to operate in streaming mode, in which
 2596          * case the XMAC will start transfering frames out of the
 2597          * RX FIFO as soon as the FIFO threshold is reached.
 2598          */
 2599         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
 2600             XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
 2601             XM_MODE_RX_INRANGELEN);
 2602 
 2603         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
 2604                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
 2605         else
 2606                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
 2607 
 2608         /*
 2609          * Bump up the transmit threshold. This helps hold off transmit
 2610          * underruns when we're blasting traffic from both ports at once.
 2611          */
 2612         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
 2613 
 2614         /* Set promiscuous mode */
 2615         sk_setpromisc(sc_if);
 2616 
 2617         /* Set multicast filter */
 2618         sk_setmulti(sc_if);
 2619 
 2620         /* Clear and enable interrupts */
 2621         SK_XM_READ_2(sc_if, XM_ISR);
 2622         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
 2623                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
 2624         else
 2625                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
 2626 
 2627         /* Configure MAC arbiter */
 2628         switch(sc_if->sk_xmac_rev) {
 2629         case XM_XMAC_REV_B2:
 2630                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
 2631                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
 2632                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
 2633                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
 2634                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
 2635                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
 2636                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
 2637                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
 2638                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
 2639                 break;
 2640         case XM_XMAC_REV_C1:
 2641                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
 2642                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
 2643                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
 2644                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
 2645                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
 2646                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
 2647                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
 2648                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
 2649                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
 2650                 break;
 2651         default:
 2652                 break;
 2653         }
 2654         sk_win_write_2(sc, SK_MACARB_CTL,
 2655             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
 2656 
 2657         sc_if->sk_link = 1;
 2658 
 2659         return;
 2660 }
 2661 
 2662 static void
 2663 sk_init_yukon(sc_if)
 2664         struct sk_if_softc      *sc_if;
 2665 {
 2666         u_int32_t               phy;
 2667         u_int16_t               reg;
 2668         struct sk_softc         *sc;
 2669         struct ifnet            *ifp;
 2670         int                     i;
 2671 
 2672         sc = sc_if->sk_softc;
 2673         ifp = sc_if->sk_ifp;
 2674 
 2675         if (sc->sk_type == SK_YUKON_LITE &&
 2676             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
 2677                 /* Take PHY out of reset. */
 2678                 sk_win_write_4(sc, SK_GPIO,
 2679                         (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9);
 2680         }
 2681 
 2682         /* GMAC and GPHY Reset */
 2683         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
 2684         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
 2685         DELAY(1000);
 2686         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
 2687         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
 2688         DELAY(1000);
 2689 
 2690         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
 2691                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
 2692 
 2693         switch(sc_if->sk_softc->sk_pmd) {
 2694         case IFM_1000_SX:
 2695         case IFM_1000_LX:
 2696                 phy |= SK_GPHY_FIBER;
 2697                 break;
 2698 
 2699         case IFM_1000_CX:
 2700         case IFM_1000_T:
 2701                 phy |= SK_GPHY_COPPER;
 2702                 break;
 2703         }
 2704 
 2705         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
 2706         DELAY(1000);
 2707         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
 2708         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
 2709                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
 2710 
 2711         /* unused read of the interrupt source register */
 2712         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
 2713 
 2714         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
 2715 
 2716         /* MIB Counter Clear Mode set */
 2717         reg |= YU_PAR_MIB_CLR;
 2718         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
 2719 
 2720         /* MIB Counter Clear Mode clear */
 2721         reg &= ~YU_PAR_MIB_CLR;
 2722         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
 2723 
 2724         /* receive control reg */
 2725         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
 2726 
 2727         /* transmit parameter register */
 2728         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
 2729                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
 2730 
 2731         /* serial mode register */
 2732         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
 2733         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
 2734                 reg |= YU_SMR_MFL_JUMBO;
 2735         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
 2736 
 2737         /* Setup Yukon's address */
 2738         for (i = 0; i < 3; i++) {
 2739                 /* Write Source Address 1 (unicast filter) */
 2740                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 
 2741                               IFP2ENADDR(sc_if->sk_ifp)[i * 2] |
 2742                               IFP2ENADDR(sc_if->sk_ifp)[i * 2 + 1] << 8);
 2743         }
 2744 
 2745         for (i = 0; i < 3; i++) {
 2746                 reg = sk_win_read_2(sc_if->sk_softc,
 2747                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
 2748                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
 2749         }
 2750 
 2751         /* Set promiscuous mode */
 2752         sk_setpromisc(sc_if);
 2753 
 2754         /* Set multicast filter */
 2755         sk_setmulti(sc_if);
 2756 
 2757         /* enable interrupt mask for counter overflows */
 2758         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
 2759         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
 2760         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
 2761 
 2762         /* Configure RX MAC FIFO */
 2763         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
 2764         SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
 2765 
 2766         /* Configure TX MAC FIFO */
 2767         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
 2768         SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
 2769 }
 2770 
 2771 /*
 2772  * Note that to properly initialize any part of the GEnesis chip,
 2773  * you first have to take it out of reset mode.
 2774  */
 2775 static void
 2776 sk_init(xsc)
 2777         void                    *xsc;
 2778 {
 2779         struct sk_if_softc      *sc_if = xsc;
 2780 
 2781         SK_IF_LOCK(sc_if);
 2782         sk_init_locked(sc_if);
 2783         SK_IF_UNLOCK(sc_if);
 2784 
 2785         return;
 2786 }
 2787 
 2788 static void
 2789 sk_init_locked(sc_if)
 2790         struct sk_if_softc      *sc_if;
 2791 {
 2792         struct sk_softc         *sc;
 2793         struct ifnet            *ifp;
 2794         struct mii_data         *mii;
 2795         u_int16_t               reg;
 2796         u_int32_t               imr;
 2797 
 2798         SK_IF_LOCK_ASSERT(sc_if);
 2799 
 2800         ifp = sc_if->sk_ifp;
 2801         sc = sc_if->sk_softc;
 2802         mii = device_get_softc(sc_if->sk_miibus);
 2803 
 2804         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 2805                 return;
 2806 
 2807         /* Cancel pending I/O and free all RX/TX buffers. */
 2808         sk_stop(sc_if);
 2809 
 2810         if (sc->sk_type == SK_GENESIS) {
 2811                 /* Configure LINK_SYNC LED */
 2812                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
 2813                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
 2814                         SK_LINKLED_LINKSYNC_ON);
 2815 
 2816                 /* Configure RX LED */
 2817                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,  
 2818                         SK_RXLEDCTL_COUNTER_START);
 2819 
 2820                 /* Configure TX LED */
 2821                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
 2822                         SK_TXLEDCTL_COUNTER_START);
 2823         }
 2824 
 2825         /* Configure I2C registers */
 2826 
 2827         /* Configure XMAC(s) */
 2828         switch (sc->sk_type) {
 2829         case SK_GENESIS:
 2830                 sk_init_xmac(sc_if);
 2831                 break;
 2832         case SK_YUKON:
 2833         case SK_YUKON_LITE:
 2834         case SK_YUKON_LP:
 2835                 sk_init_yukon(sc_if);
 2836                 break;
 2837         }
 2838         mii_mediachg(mii);
 2839 
 2840         if (sc->sk_type == SK_GENESIS) {
 2841                 /* Configure MAC FIFOs */
 2842                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
 2843                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
 2844                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
 2845 
 2846                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
 2847                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
 2848                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
 2849         }
 2850 
 2851         /* Configure transmit arbiter(s) */
 2852         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
 2853             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
 2854 
 2855         /* Configure RAMbuffers */
 2856         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
 2857         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
 2858         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
 2859         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
 2860         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
 2861         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
 2862 
 2863         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
 2864         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
 2865         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
 2866         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
 2867         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
 2868         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
 2869         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
 2870 
 2871         /* Configure BMUs */
 2872         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
 2873         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
 2874             vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
 2875         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
 2876 
 2877         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
 2878         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
 2879             vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
 2880         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
 2881 
 2882         /* Init descriptors */
 2883         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
 2884                 printf("sk%d: initialization failed: no "
 2885                     "memory for rx buffers\n", sc_if->sk_unit);
 2886                 sk_stop(sc_if);
 2887                 return;
 2888         }
 2889         sk_init_tx_ring(sc_if);
 2890 
 2891         /* Set interrupt moderation if changed via sysctl. */
 2892         /* SK_LOCK(sc); */
 2893         imr = sk_win_read_4(sc, SK_IMTIMERINIT);
 2894         if (imr != SK_IM_USECS(sc->sk_int_mod)) {
 2895                 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod));
 2896                 if (bootverbose)
 2897                         printf("skc%d: interrupt moderation is %d us\n",
 2898                             sc->sk_unit, sc->sk_int_mod);
 2899         }
 2900         /* SK_UNLOCK(sc); */
 2901 
 2902         /* Configure interrupt handling */
 2903         CSR_READ_4(sc, SK_ISSR);
 2904         if (sc_if->sk_port == SK_PORT_A)
 2905                 sc->sk_intrmask |= SK_INTRS1;
 2906         else
 2907                 sc->sk_intrmask |= SK_INTRS2;
 2908 
 2909         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
 2910 
 2911         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
 2912 
 2913         /* Start BMUs. */
 2914         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
 2915 
 2916         switch(sc->sk_type) {
 2917         case SK_GENESIS:
 2918                 /* Enable XMACs TX and RX state machines */
 2919                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
 2920                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
 2921                 break;
 2922         case SK_YUKON:
 2923         case SK_YUKON_LITE:
 2924         case SK_YUKON_LP:
 2925                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
 2926                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
 2927                 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);
 2928                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
 2929         }
 2930 
 2931         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 2932         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 2933 
 2934         return;
 2935 }
 2936 
 2937 static void
 2938 sk_stop(sc_if)
 2939         struct sk_if_softc      *sc_if;
 2940 {
 2941         int                     i;
 2942         struct sk_softc         *sc;
 2943         struct ifnet            *ifp;
 2944 
 2945         SK_IF_LOCK_ASSERT(sc_if);
 2946         sc = sc_if->sk_softc;
 2947         ifp = sc_if->sk_ifp;
 2948 
 2949         untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
 2950 
 2951         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
 2952                 u_int32_t               val;
 2953 
 2954                 /* Put PHY back into reset. */
 2955                 val = sk_win_read_4(sc, SK_GPIO);
 2956                 if (sc_if->sk_port == SK_PORT_A) {
 2957                         val |= SK_GPIO_DIR0;
 2958                         val &= ~SK_GPIO_DAT0;
 2959                 } else {
 2960                         val |= SK_GPIO_DIR2;
 2961                         val &= ~SK_GPIO_DAT2;
 2962                 }
 2963                 sk_win_write_4(sc, SK_GPIO, val);
 2964         }
 2965 
 2966         /* Turn off various components of this interface. */
 2967         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
 2968         switch (sc->sk_type) {
 2969         case SK_GENESIS:
 2970                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
 2971                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
 2972                 break;
 2973         case SK_YUKON:
 2974         case SK_YUKON_LITE:
 2975         case SK_YUKON_LP:
 2976                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
 2977                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
 2978                 break;
 2979         }
 2980         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
 2981         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
 2982         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
 2983         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
 2984         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
 2985         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
 2986         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
 2987         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
 2988         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
 2989 
 2990         /* Disable interrupts */
 2991         if (sc_if->sk_port == SK_PORT_A)
 2992                 sc->sk_intrmask &= ~SK_INTRS1;
 2993         else
 2994                 sc->sk_intrmask &= ~SK_INTRS2;
 2995         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
 2996 
 2997         SK_XM_READ_2(sc_if, XM_ISR);
 2998         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
 2999 
 3000         /* Free RX and TX mbufs still in the queues. */
 3001         for (i = 0; i < SK_RX_RING_CNT; i++) {
 3002                 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
 3003                         m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
 3004                         sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
 3005                 }
 3006         }
 3007 
 3008         for (i = 0; i < SK_TX_RING_CNT; i++) {
 3009                 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
 3010                         m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
 3011                         sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
 3012                 }
 3013         }
 3014 
 3015         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
 3016 
 3017         return;
 3018 }
 3019 
 3020 static int
 3021 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
 3022 {
 3023         int error, value;
 3024 
 3025         if (!arg1)
 3026                 return (EINVAL);
 3027         value = *(int *)arg1;
 3028         error = sysctl_handle_int(oidp, &value, 0, req);
 3029         if (error || !req->newptr)
 3030                 return (error);
 3031         if (value < low || value > high)
 3032                 return (EINVAL);
 3033         *(int *)arg1 = value;
 3034         return (0);
 3035 }
 3036 
 3037 static int
 3038 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
 3039 {
 3040         return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
 3041 }

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