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sys/pci/if_skreg.h
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1 /* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* Values to keep the different chip revisions apart */ 54 #define SK_GENESIS 0 55 #define SK_YUKON 1 56 57 /* 58 * SysKonnect PCI vendor ID 59 */ 60 #define VENDORID_SK 0x1148 61 62 /* 63 * Marvell PCI vendor ID 64 */ 65 #define VENDORID_MARVELL 0x11AB 66 67 /* 68 * SK-NET gigabit ethernet device IDs 69 */ 70 #define DEVICEID_SK_V1 0x4300 71 #define DEVICEID_SK_V2 0x4320 72 73 /* 74 * 3Com PCI vendor ID 75 */ 76 #define VENDORID_3COM 0x10b7 77 78 /* 79 * 3Com gigabit ethernet device ID 80 */ 81 #define DEVICEID_3COM_3C940 0x1700 82 83 /* 84 * Linksys PCI vendor ID 85 */ 86 #define VENDORID_LINKSYS 0x1737 87 88 /* 89 * Linksys gigabit ethernet device ID 90 */ 91 #define DEVICEID_LINKSYS_EG1032 0x1032 92 93 /* 94 * D-Link PCI vendor ID 95 */ 96 #define VENDORID_DLINK 0x1186 97 98 /* 99 * D-Link gigabit ethernet device ID 100 */ 101 #define DEVICEID_DLINK_DGE530T 0x4c00 102 103 /* 104 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 105 * but internally it has a 16K register space. This 16K space is 106 * divided into 128-byte blocks. The first 128 bytes of the I/O 107 * window represent the first block, which is permanently mapped 108 * at the start of the window. The other 127 blocks can be mapped 109 * to the second 128 bytes of the I/O window by setting the desired 110 * block value in the RAP register in block 0. Not all of the 127 111 * blocks are actually used. Most registers are 32 bits wide, but 112 * there are a few 16-bit and 8-bit ones as well. 113 */ 114 115 116 /* Start of remappable register window. */ 117 #define SK_WIN_BASE 0x0080 118 119 /* Size of a window */ 120 #define SK_WIN_LEN 0x80 121 122 #define SK_WIN_MASK 0x3F80 123 #define SK_REG_MASK 0x7F 124 125 /* Compute the window of a given register (for the RAP register) */ 126 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 127 128 /* Compute the relative offset of a register within the window */ 129 #define SK_REG(reg) ((reg) & SK_REG_MASK) 130 131 #define SK_PORT_A 0 132 #define SK_PORT_B 1 133 134 /* 135 * Compute offset of port-specific register. Since there are two 136 * ports, there are two of some GEnesis modules (e.g. two sets of 137 * DMA queues, two sets of FIFO control registers, etc...). Normally, 138 * the block for port 0 is at offset 0x0 and the block for port 1 is 139 * at offset 0x80 (i.e. the next page over). However for the transmit 140 * BMUs and RAMbuffers, there are two blocks for each port: one for 141 * the sync transmit queue and one for the async queue (which we don't 142 * use). However instead of ordering them like this: 143 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 144 * SysKonnect has instead ordered them like this: 145 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 146 * This means that when referencing the TX BMU and RAMbuffer registers, 147 * we have to double the block offset (0x80 * 2) in order to reach the 148 * second queue. This prevents us from using the same formula 149 * (sk_port * 0x80) to compute the offsets for all of the port-specific 150 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 151 * The simplest thing is to provide an extra argument to these macros: 152 * the 'skip' parameter. The 'skip' value is the number of extra pages 153 * for skip when computing the port0/port1 offsets. For most registers, 154 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 155 */ 156 #define SK_IF_READ_4(sc_if, skip, reg) \ 157 sk_win_read_4(sc_if->sk_softc, reg + \ 158 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 159 #define SK_IF_READ_2(sc_if, skip, reg) \ 160 sk_win_read_2(sc_if->sk_softc, reg + \ 161 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 162 #define SK_IF_READ_1(sc_if, skip, reg) \ 163 sk_win_read_1(sc_if->sk_softc, reg + \ 164 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 165 166 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 167 sk_win_write_4(sc_if->sk_softc, \ 168 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 169 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 170 sk_win_write_2(sc_if->sk_softc, \ 171 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 172 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 173 sk_win_write_1(sc_if->sk_softc, \ 174 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 175 176 /* Block 0 registers, permanently mapped at iobase. */ 177 #define SK_RAP 0x0000 178 #define SK_CSR 0x0004 179 #define SK_LED 0x0006 180 #define SK_ISR 0x0008 /* interrupt source */ 181 #define SK_IMR 0x000C /* interrupt mask */ 182 #define SK_IESR 0x0010 /* interrupt hardware error source */ 183 #define SK_IEMR 0x0014 /* interrupt hardware error mask */ 184 #define SK_ISSR 0x0018 /* special interrupt source */ 185 #define SK_XM_IMR0 0x0020 186 #define SK_XM_ISR0 0x0028 187 #define SK_XM_PHYADDR0 0x0030 188 #define SK_XM_PHYDATA0 0x0034 189 #define SK_XM_IMR1 0x0040 190 #define SK_XM_ISR1 0x0048 191 #define SK_XM_PHYADDR1 0x0050 192 #define SK_XM_PHYDATA1 0x0054 193 #define SK_BMU_RX_CSR0 0x0060 194 #define SK_BMU_RX_CSR1 0x0064 195 #define SK_BMU_TXS_CSR0 0x0068 196 #define SK_BMU_TXA_CSR0 0x006C 197 #define SK_BMU_TXS_CSR1 0x0070 198 #define SK_BMU_TXA_CSR1 0x0074 199 200 /* SK_CSR register */ 201 #define SK_CSR_SW_RESET 0x0001 202 #define SK_CSR_SW_UNRESET 0x0002 203 #define SK_CSR_MASTER_RESET 0x0004 204 #define SK_CSR_MASTER_UNRESET 0x0008 205 #define SK_CSR_MASTER_STOP 0x0010 206 #define SK_CSR_MASTER_DONE 0x0020 207 #define SK_CSR_SW_IRQ_CLEAR 0x0040 208 #define SK_CSR_SW_IRQ_SET 0x0080 209 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 210 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 211 212 /* SK_LED register */ 213 #define SK_LED_GREEN_OFF 0x01 214 #define SK_LED_GREEN_ON 0x02 215 216 /* SK_ISR register */ 217 #define SK_ISR_TX2_AS_CHECK 0x00000001 218 #define SK_ISR_TX2_AS_EOF 0x00000002 219 #define SK_ISR_TX2_AS_EOB 0x00000004 220 #define SK_ISR_TX2_S_CHECK 0x00000008 221 #define SK_ISR_TX2_S_EOF 0x00000010 222 #define SK_ISR_TX2_S_EOB 0x00000020 223 #define SK_ISR_TX1_AS_CHECK 0x00000040 224 #define SK_ISR_TX1_AS_EOF 0x00000080 225 #define SK_ISR_TX1_AS_EOB 0x00000100 226 #define SK_ISR_TX1_S_CHECK 0x00000200 227 #define SK_ISR_TX1_S_EOF 0x00000400 228 #define SK_ISR_TX1_S_EOB 0x00000800 229 #define SK_ISR_RX2_CHECK 0x00001000 230 #define SK_ISR_RX2_EOF 0x00002000 231 #define SK_ISR_RX2_EOB 0x00004000 232 #define SK_ISR_RX1_CHECK 0x00008000 233 #define SK_ISR_RX1_EOF 0x00010000 234 #define SK_ISR_RX1_EOB 0x00020000 235 #define SK_ISR_LINK2_OFLOW 0x00040000 236 #define SK_ISR_MAC2 0x00080000 237 #define SK_ISR_LINK1_OFLOW 0x00100000 238 #define SK_ISR_MAC1 0x00200000 239 #define SK_ISR_TIMER 0x00400000 240 #define SK_ISR_EXTERNAL_REG 0x00800000 241 #define SK_ISR_SW 0x01000000 242 #define SK_ISR_I2C_RDY 0x02000000 243 #define SK_ISR_TX2_TIMEO 0x04000000 244 #define SK_ISR_TX1_TIMEO 0x08000000 245 #define SK_ISR_RX2_TIMEO 0x10000000 246 #define SK_ISR_RX1_TIMEO 0x20000000 247 #define SK_ISR_RSVD 0x40000000 248 #define SK_ISR_HWERR 0x80000000 249 250 /* SK_IMR register */ 251 #define SK_IMR_TX2_AS_CHECK 0x00000001 252 #define SK_IMR_TX2_AS_EOF 0x00000002 253 #define SK_IMR_TX2_AS_EOB 0x00000004 254 #define SK_IMR_TX2_S_CHECK 0x00000008 255 #define SK_IMR_TX2_S_EOF 0x00000010 256 #define SK_IMR_TX2_S_EOB 0x00000020 257 #define SK_IMR_TX1_AS_CHECK 0x00000040 258 #define SK_IMR_TX1_AS_EOF 0x00000080 259 #define SK_IMR_TX1_AS_EOB 0x00000100 260 #define SK_IMR_TX1_S_CHECK 0x00000200 261 #define SK_IMR_TX1_S_EOF 0x00000400 262 #define SK_IMR_TX1_S_EOB 0x00000800 263 #define SK_IMR_RX2_CHECK 0x00001000 264 #define SK_IMR_RX2_EOF 0x00002000 265 #define SK_IMR_RX2_EOB 0x00004000 266 #define SK_IMR_RX1_CHECK 0x00008000 267 #define SK_IMR_RX1_EOF 0x00010000 268 #define SK_IMR_RX1_EOB 0x00020000 269 #define SK_IMR_LINK2_OFLOW 0x00040000 270 #define SK_IMR_MAC2 0x00080000 271 #define SK_IMR_LINK1_OFLOW 0x00100000 272 #define SK_IMR_MAC1 0x00200000 273 #define SK_IMR_TIMER 0x00400000 274 #define SK_IMR_EXTERNAL_REG 0x00800000 275 #define SK_IMR_SW 0x01000000 276 #define SK_IMR_I2C_RDY 0x02000000 277 #define SK_IMR_TX2_TIMEO 0x04000000 278 #define SK_IMR_TX1_TIMEO 0x08000000 279 #define SK_IMR_RX2_TIMEO 0x10000000 280 #define SK_IMR_RX1_TIMEO 0x20000000 281 #define SK_IMR_RSVD 0x40000000 282 #define SK_IMR_HWERR 0x80000000 283 284 #define SK_INTRS1 \ 285 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 286 287 #define SK_INTRS2 \ 288 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 289 290 /* SK_IESR register */ 291 #define SK_IESR_PAR_RX2 0x00000001 292 #define SK_IESR_PAR_RX1 0x00000002 293 #define SK_IESR_PAR_MAC2 0x00000004 294 #define SK_IESR_PAR_MAC1 0x00000008 295 #define SK_IESR_PAR_WR_RAM 0x00000010 296 #define SK_IESR_PAR_RD_RAM 0x00000020 297 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040 298 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080 299 #define SK_IESR_NO_STS_MAC2 0x00000100 300 #define SK_IESR_NO_STS_MAC1 0x00000200 301 #define SK_IESR_IRQ_STS 0x00000400 302 #define SK_IESR_MASTERERR 0x00000800 303 304 /* SK_IEMR register */ 305 #define SK_IEMR_PAR_RX2 0x00000001 306 #define SK_IEMR_PAR_RX1 0x00000002 307 #define SK_IEMR_PAR_MAC2 0x00000004 308 #define SK_IEMR_PAR_MAC1 0x00000008 309 #define SK_IEMR_PAR_WR_RAM 0x00000010 310 #define SK_IEMR_PAR_RD_RAM 0x00000020 311 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 312 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 313 #define SK_IEMR_NO_STS_MAC2 0x00000100 314 #define SK_IEMR_NO_STS_MAC1 0x00000200 315 #define SK_IEMR_IRQ_STS 0x00000400 316 #define SK_IEMR_MASTERERR 0x00000800 317 318 /* Block 2 */ 319 #define SK_MAC0_0 0x0100 320 #define SK_MAC0_1 0x0104 321 #define SK_MAC1_0 0x0108 322 #define SK_MAC1_1 0x010C 323 #define SK_MAC2_0 0x0110 324 #define SK_MAC2_1 0x0114 325 #define SK_CONNTYPE 0x0118 326 #define SK_PMDTYPE 0x0119 327 #define SK_CONFIG 0x011A 328 #define SK_CHIPVER 0x011B 329 #define SK_EPROM0 0x011C 330 #define SK_EPROM1 0x011D 331 #define SK_EPROM2 0x011E 332 #define SK_EPROM3 0x011F 333 #define SK_EP_ADDR 0x0120 334 #define SK_EP_DATA 0x0124 335 #define SK_EP_LOADCTL 0x0128 336 #define SK_EP_LOADTST 0x0129 337 #define SK_TIMERINIT 0x0130 338 #define SK_TIMER 0x0134 339 #define SK_TIMERCTL 0x0138 340 #define SK_TIMERTST 0x0139 341 #define SK_IMTIMERINIT 0x0140 342 #define SK_IMTIMER 0x0144 343 #define SK_IMTIMERCTL 0x0148 344 #define SK_IMTIMERTST 0x0149 345 #define SK_IMMR 0x014C 346 #define SK_IHWEMR 0x0150 347 #define SK_TESTCTL1 0x0158 348 #define SK_TESTCTL2 0x0159 349 #define SK_GPIO 0x015C 350 #define SK_I2CHWCTL 0x0160 351 #define SK_I2CHWDATA 0x0164 352 #define SK_I2CHWIRQ 0x0168 353 #define SK_I2CSW 0x016C 354 #define SK_BLNKINIT 0x0170 355 #define SK_BLNKCOUNT 0x0174 356 #define SK_BLNKCTL 0x0178 357 #define SK_BLNKSTS 0x0179 358 #define SK_BLNKTST 0x017A 359 360 #define SK_IMCTL_STOP 0x02 361 #define SK_IMCTL_START 0x04 362 363 #define SK_IMTIMER_TICKS 54 364 #define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 365 366 /* 367 * The SK_EPROM0 register contains a byte that describes the 368 * amount of SRAM mounted on the NIC. The value also tells if 369 * the chips are 64K or 128K. This affects the RAMbuffer address 370 * offset that we need to use. 371 */ 372 #define SK_RAMSIZE_512K_64 0x1 373 #define SK_RAMSIZE_1024K_128 0x2 374 #define SK_RAMSIZE_1024K_64 0x3 375 #define SK_RAMSIZE_2048K_128 0x4 376 377 #define SK_RBOFF_0 0x0 378 #define SK_RBOFF_80000 0x80000 379 380 /* 381 * SK_EEPROM1 contains the PHY type, which may be XMAC for 382 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 383 * PHY. 384 */ 385 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 386 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 387 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 388 #define SK_PHYTYPE_NAT 3 /* National DP83891 */ 389 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 390 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 391 392 /* 393 * PHY addresses. 394 */ 395 #define SK_PHYADDR_XMAC 0x0 396 #define SK_PHYADDR_BCOM 0x1 397 #define SK_PHYADDR_LONE 0x3 398 #define SK_PHYADDR_NAT 0x0 399 #define SK_PHYADDR_MARV 0x0 400 401 #define SK_CONFIG_SINGLEMAC 0x01 402 #define SK_CONFIG_DIS_DSL_CLK 0x02 403 404 #define SK_PMD_1000BASELX 0x4C 405 #define SK_PMD_1000BASESX 0x53 406 #define SK_PMD_1000BASECX 0x43 407 #define SK_PMD_1000BASETX 0x54 408 409 /* GPIO bits */ 410 #define SK_GPIO_DAT0 0x00000001 411 #define SK_GPIO_DAT1 0x00000002 412 #define SK_GPIO_DAT2 0x00000004 413 #define SK_GPIO_DAT3 0x00000008 414 #define SK_GPIO_DAT4 0x00000010 415 #define SK_GPIO_DAT5 0x00000020 416 #define SK_GPIO_DAT6 0x00000040 417 #define SK_GPIO_DAT7 0x00000080 418 #define SK_GPIO_DAT8 0x00000100 419 #define SK_GPIO_DAT9 0x00000200 420 #define SK_GPIO_DIR0 0x00010000 421 #define SK_GPIO_DIR1 0x00020000 422 #define SK_GPIO_DIR2 0x00040000 423 #define SK_GPIO_DIR3 0x00080000 424 #define SK_GPIO_DIR4 0x00100000 425 #define SK_GPIO_DIR5 0x00200000 426 #define SK_GPIO_DIR6 0x00400000 427 #define SK_GPIO_DIR7 0x00800000 428 #define SK_GPIO_DIR8 0x01000000 429 #define SK_GPIO_DIR9 0x02000000 430 431 /* Block 3 Ram interface and MAC arbiter registers */ 432 #define SK_RAMADDR 0x0180 433 #define SK_RAMDATA0 0x0184 434 #define SK_RAMDATA1 0x0188 435 #define SK_TO0 0x0190 436 #define SK_TO1 0x0191 437 #define SK_TO2 0x0192 438 #define SK_TO3 0x0193 439 #define SK_TO4 0x0194 440 #define SK_TO5 0x0195 441 #define SK_TO6 0x0196 442 #define SK_TO7 0x0197 443 #define SK_TO8 0x0198 444 #define SK_TO9 0x0199 445 #define SK_TO10 0x019A 446 #define SK_TO11 0x019B 447 #define SK_RITIMEO_TMR 0x019C 448 #define SK_RAMCTL 0x01A0 449 #define SK_RITIMER_TST 0x01A2 450 451 #define SK_RAMCTL_RESET 0x0001 452 #define SK_RAMCTL_UNRESET 0x0002 453 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 454 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 455 456 /* Mac arbiter registers */ 457 #define SK_MINIT_RX1 0x01B0 458 #define SK_MINIT_RX2 0x01B1 459 #define SK_MINIT_TX1 0x01B2 460 #define SK_MINIT_TX2 0x01B3 461 #define SK_MTIMEO_RX1 0x01B4 462 #define SK_MTIMEO_RX2 0x01B5 463 #define SK_MTIMEO_TX1 0x01B6 464 #define SK_MTIEMO_TX2 0x01B7 465 #define SK_MACARB_CTL 0x01B8 466 #define SK_MTIMER_TST 0x01BA 467 #define SK_RCINIT_RX1 0x01C0 468 #define SK_RCINIT_RX2 0x01C1 469 #define SK_RCINIT_TX1 0x01C2 470 #define SK_RCINIT_TX2 0x01C3 471 #define SK_RCTIMEO_RX1 0x01C4 472 #define SK_RCTIMEO_RX2 0x01C5 473 #define SK_RCTIMEO_TX1 0x01C6 474 #define SK_RCTIMEO_TX2 0x01C7 475 #define SK_RECOVERY_CTL 0x01C8 476 #define SK_RCTIMER_TST 0x01CA 477 478 /* Packet arbiter registers */ 479 #define SK_RXPA1_TINIT 0x01D0 480 #define SK_RXPA2_TINIT 0x01D4 481 #define SK_TXPA1_TINIT 0x01D8 482 #define SK_TXPA2_TINIT 0x01DC 483 #define SK_RXPA1_TIMEO 0x01E0 484 #define SK_RXPA2_TIMEO 0x01E4 485 #define SK_TXPA1_TIMEO 0x01E8 486 #define SK_TXPA2_TIMEO 0x01EC 487 #define SK_PKTARB_CTL 0x01F0 488 #define SK_PKTATB_TST 0x01F2 489 490 #define SK_PKTARB_TIMEOUT 0x2000 491 492 #define SK_PKTARBCTL_RESET 0x0001 493 #define SK_PKTARBCTL_UNRESET 0x0002 494 #define SK_PKTARBCTL_RXTO1_OFF 0x0004 495 #define SK_PKTARBCTL_RXTO1_ON 0x0008 496 #define SK_PKTARBCTL_RXTO2_OFF 0x0010 497 #define SK_PKTARBCTL_RXTO2_ON 0x0020 498 #define SK_PKTARBCTL_TXTO1_OFF 0x0040 499 #define SK_PKTARBCTL_TXTO1_ON 0x0080 500 #define SK_PKTARBCTL_TXTO2_OFF 0x0100 501 #define SK_PKTARBCTL_TXTO2_ON 0x0200 502 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 503 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 504 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 505 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 506 507 #define SK_MINIT_XMAC_B2 54 508 #define SK_MINIT_XMAC_C1 63 509 510 #define SK_MACARBCTL_RESET 0x0001 511 #define SK_MACARBCTL_UNRESET 0x0002 512 #define SK_MACARBCTL_FASTOE_OFF 0x0004 513 #define SK_MACARBCRL_FASTOE_ON 0x0008 514 515 #define SK_RCINIT_XMAC_B2 54 516 #define SK_RCINIT_XMAC_C1 0 517 518 #define SK_RECOVERYCTL_RX1_OFF 0x0001 519 #define SK_RECOVERYCTL_RX1_ON 0x0002 520 #define SK_RECOVERYCTL_RX2_OFF 0x0004 521 #define SK_RECOVERYCTL_RX2_ON 0x0008 522 #define SK_RECOVERYCTL_TX1_OFF 0x0010 523 #define SK_RECOVERYCTL_TX1_ON 0x0020 524 #define SK_RECOVERYCTL_TX2_OFF 0x0040 525 #define SK_RECOVERYCTL_TX2_ON 0x0080 526 527 #define SK_RECOVERY_XMAC_B2 \ 528 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 529 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 530 531 #define SK_RECOVERY_XMAC_C1 \ 532 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 533 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 534 535 /* Block 4 -- TX Arbiter MAC 1 */ 536 #define SK_TXAR1_TIMERINIT 0x0200 537 #define SK_TXAR1_TIMERVAL 0x0204 538 #define SK_TXAR1_LIMITINIT 0x0208 539 #define SK_TXAR1_LIMITCNT 0x020C 540 #define SK_TXAR1_COUNTERCTL 0x0210 541 #define SK_TXAR1_COUNTERTST 0x0212 542 #define SK_TXAR1_COUNTERSTS 0x0212 543 544 /* Block 5 -- TX Arbiter MAC 2 */ 545 #define SK_TXAR2_TIMERINIT 0x0280 546 #define SK_TXAR2_TIMERVAL 0x0284 547 #define SK_TXAR2_LIMITINIT 0x0288 548 #define SK_TXAR2_LIMITCNT 0x028C 549 #define SK_TXAR2_COUNTERCTL 0x0290 550 #define SK_TXAR2_COUNTERTST 0x0291 551 #define SK_TXAR2_COUNTERSTS 0x0292 552 553 #define SK_TXARCTL_OFF 0x01 554 #define SK_TXARCTL_ON 0x02 555 #define SK_TXARCTL_RATECTL_OFF 0x04 556 #define SK_TXARCTL_RATECTL_ON 0x08 557 #define SK_TXARCTL_ALLOC_OFF 0x10 558 #define SK_TXARCTL_ALLOC_ON 0x20 559 #define SK_TXARCTL_FSYNC_OFF 0x40 560 #define SK_TXARCTL_FSYNC_ON 0x80 561 562 /* Block 6 -- External registers */ 563 #define SK_EXTREG_BASE 0x300 564 #define SK_EXTREG_END 0x37C 565 566 /* Block 7 -- PCI config registers */ 567 #define SK_PCI_BASE 0x0380 568 #define SK_PCI_END 0x03FC 569 570 /* Compute offset of mirrored PCI register */ 571 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 572 573 /* Block 8 -- RX queue 1 */ 574 #define SK_RXQ1_BUFCNT 0x0400 575 #define SK_RXQ1_BUFCTL 0x0402 576 #define SK_RXQ1_NEXTDESC 0x0404 577 #define SK_RXQ1_RXBUF_LO 0x0408 578 #define SK_RXQ1_RXBUF_HI 0x040C 579 #define SK_RXQ1_RXSTAT 0x0410 580 #define SK_RXQ1_TIMESTAMP 0x0414 581 #define SK_RXQ1_CSUM1 0x0418 582 #define SK_RXQ1_CSUM2 0x041A 583 #define SK_RXQ1_CSUM1_START 0x041C 584 #define SK_RXQ1_CSUM2_START 0x041E 585 #define SK_RXQ1_CURADDR_LO 0x0420 586 #define SK_RXQ1_CURADDR_HI 0x0424 587 #define SK_RXQ1_CURCNT_LO 0x0428 588 #define SK_RXQ1_CURCNT_HI 0x042C 589 #define SK_RXQ1_CURBYTES 0x0430 590 #define SK_RXQ1_BMU_CSR 0x0434 591 #define SK_RXQ1_WATERMARK 0x0438 592 #define SK_RXQ1_FLAG 0x043A 593 #define SK_RXQ1_TEST1 0x043C 594 #define SK_RXQ1_TEST2 0x0440 595 #define SK_RXQ1_TEST3 0x0444 596 597 /* Block 9 -- RX queue 2 */ 598 #define SK_RXQ2_BUFCNT 0x0480 599 #define SK_RXQ2_BUFCTL 0x0482 600 #define SK_RXQ2_NEXTDESC 0x0484 601 #define SK_RXQ2_RXBUF_LO 0x0488 602 #define SK_RXQ2_RXBUF_HI 0x048C 603 #define SK_RXQ2_RXSTAT 0x0490 604 #define SK_RXQ2_TIMESTAMP 0x0494 605 #define SK_RXQ2_CSUM1 0x0498 606 #define SK_RXQ2_CSUM2 0x049A 607 #define SK_RXQ2_CSUM1_START 0x049C 608 #define SK_RXQ2_CSUM2_START 0x049E 609 #define SK_RXQ2_CURADDR_LO 0x04A0 610 #define SK_RXQ2_CURADDR_HI 0x04A4 611 #define SK_RXQ2_CURCNT_LO 0x04A8 612 #define SK_RXQ2_CURCNT_HI 0x04AC 613 #define SK_RXQ2_CURBYTES 0x04B0 614 #define SK_RXQ2_BMU_CSR 0x04B4 615 #define SK_RXQ2_WATERMARK 0x04B8 616 #define SK_RXQ2_FLAG 0x04BA 617 #define SK_RXQ2_TEST1 0x04BC 618 #define SK_RXQ2_TEST2 0x04C0 619 #define SK_RXQ2_TEST3 0x04C4 620 621 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001 622 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002 623 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004 624 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008 625 #define SK_RXBMU_RX_START 0x00000010 626 #define SK_RXBMU_RX_STOP 0x00000020 627 #define SK_RXBMU_POLL_OFF 0x00000040 628 #define SK_RXBMU_POLL_ON 0x00000080 629 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 630 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 631 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400 632 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 633 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000 634 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 635 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 636 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 637 #define SK_RXBMU_PFI_SM_RESET 0x00010000 638 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000 639 #define SK_RXBMU_FIFO_RESET 0x00040000 640 #define SK_RXBMU_FIFO_UNRESET 0x00080000 641 #define SK_RXBMU_DESC_RESET 0x00100000 642 #define SK_RXBMU_DESC_UNRESET 0x00200000 643 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 644 645 #define SK_RXBMU_ONLINE \ 646 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 647 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 648 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 649 SK_RXBMU_DESC_UNRESET) 650 651 #define SK_RXBMU_OFFLINE \ 652 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 653 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 654 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 655 SK_RXBMU_DESC_RESET) 656 657 /* Block 12 -- TX sync queue 1 */ 658 #define SK_TXQS1_BUFCNT 0x0600 659 #define SK_TXQS1_BUFCTL 0x0602 660 #define SK_TXQS1_NEXTDESC 0x0604 661 #define SK_TXQS1_RXBUF_LO 0x0608 662 #define SK_TXQS1_RXBUF_HI 0x060C 663 #define SK_TXQS1_RXSTAT 0x0610 664 #define SK_TXQS1_CSUM_STARTVAL 0x0614 665 #define SK_TXQS1_CSUM_STARTPOS 0x0618 666 #define SK_TXQS1_CSUM_WRITEPOS 0x061A 667 #define SK_TXQS1_CURADDR_LO 0x0620 668 #define SK_TXQS1_CURADDR_HI 0x0624 669 #define SK_TXQS1_CURCNT_LO 0x0628 670 #define SK_TXQS1_CURCNT_HI 0x062C 671 #define SK_TXQS1_CURBYTES 0x0630 672 #define SK_TXQS1_BMU_CSR 0x0634 673 #define SK_TXQS1_WATERMARK 0x0638 674 #define SK_TXQS1_FLAG 0x063A 675 #define SK_TXQS1_TEST1 0x063C 676 #define SK_TXQS1_TEST2 0x0640 677 #define SK_TXQS1_TEST3 0x0644 678 679 /* Block 13 -- TX async queue 1 */ 680 #define SK_TXQA1_BUFCNT 0x0680 681 #define SK_TXQA1_BUFCTL 0x0682 682 #define SK_TXQA1_NEXTDESC 0x0684 683 #define SK_TXQA1_RXBUF_LO 0x0688 684 #define SK_TXQA1_RXBUF_HI 0x068C 685 #define SK_TXQA1_RXSTAT 0x0690 686 #define SK_TXQA1_CSUM_STARTVAL 0x0694 687 #define SK_TXQA1_CSUM_STARTPOS 0x0698 688 #define SK_TXQA1_CSUM_WRITEPOS 0x069A 689 #define SK_TXQA1_CURADDR_LO 0x06A0 690 #define SK_TXQA1_CURADDR_HI 0x06A4 691 #define SK_TXQA1_CURCNT_LO 0x06A8 692 #define SK_TXQA1_CURCNT_HI 0x06AC 693 #define SK_TXQA1_CURBYTES 0x06B0 694 #define SK_TXQA1_BMU_CSR 0x06B4 695 #define SK_TXQA1_WATERMARK 0x06B8 696 #define SK_TXQA1_FLAG 0x06BA 697 #define SK_TXQA1_TEST1 0x06BC 698 #define SK_TXQA1_TEST2 0x06C0 699 #define SK_TXQA1_TEST3 0x06C4 700 701 /* Block 14 -- TX sync queue 2 */ 702 #define SK_TXQS2_BUFCNT 0x0700 703 #define SK_TXQS2_BUFCTL 0x0702 704 #define SK_TXQS2_NEXTDESC 0x0704 705 #define SK_TXQS2_RXBUF_LO 0x0708 706 #define SK_TXQS2_RXBUF_HI 0x070C 707 #define SK_TXQS2_RXSTAT 0x0710 708 #define SK_TXQS2_CSUM_STARTVAL 0x0714 709 #define SK_TXQS2_CSUM_STARTPOS 0x0718 710 #define SK_TXQS2_CSUM_WRITEPOS 0x071A 711 #define SK_TXQS2_CURADDR_LO 0x0720 712 #define SK_TXQS2_CURADDR_HI 0x0724 713 #define SK_TXQS2_CURCNT_LO 0x0728 714 #define SK_TXQS2_CURCNT_HI 0x072C 715 #define SK_TXQS2_CURBYTES 0x0730 716 #define SK_TXQS2_BMU_CSR 0x0734 717 #define SK_TXQS2_WATERMARK 0x0738 718 #define SK_TXQS2_FLAG 0x073A 719 #define SK_TXQS2_TEST1 0x073C 720 #define SK_TXQS2_TEST2 0x0740 721 #define SK_TXQS2_TEST3 0x0744 722 723 /* Block 15 -- TX async queue 2 */ 724 #define SK_TXQA2_BUFCNT 0x0780 725 #define SK_TXQA2_BUFCTL 0x0782 726 #define SK_TXQA2_NEXTDESC 0x0784 727 #define SK_TXQA2_RXBUF_LO 0x0788 728 #define SK_TXQA2_RXBUF_HI 0x078C 729 #define SK_TXQA2_RXSTAT 0x0790 730 #define SK_TXQA2_CSUM_STARTVAL 0x0794 731 #define SK_TXQA2_CSUM_STARTPOS 0x0798 732 #define SK_TXQA2_CSUM_WRITEPOS 0x079A 733 #define SK_TXQA2_CURADDR_LO 0x07A0 734 #define SK_TXQA2_CURADDR_HI 0x07A4 735 #define SK_TXQA2_CURCNT_LO 0x07A8 736 #define SK_TXQA2_CURCNT_HI 0x07AC 737 #define SK_TXQA2_CURBYTES 0x07B0 738 #define SK_TXQA2_BMU_CSR 0x07B4 739 #define SK_TXQA2_WATERMARK 0x07B8 740 #define SK_TXQA2_FLAG 0x07BA 741 #define SK_TXQA2_TEST1 0x07BC 742 #define SK_TXQA2_TEST2 0x07C0 743 #define SK_TXQA2_TEST3 0x07C4 744 745 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001 746 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002 747 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004 748 #define SK_TXBMU_TX_START 0x00000010 749 #define SK_TXBMU_TX_STOP 0x00000020 750 #define SK_TXBMU_POLL_OFF 0x00000040 751 #define SK_TXBMU_POLL_ON 0x00000080 752 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 753 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 754 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400 755 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 756 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000 757 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 758 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 759 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 760 #define SK_TXBMU_PFI_SM_RESET 0x00010000 761 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000 762 #define SK_TXBMU_FIFO_RESET 0x00040000 763 #define SK_TXBMU_FIFO_UNRESET 0x00080000 764 #define SK_TXBMU_DESC_RESET 0x00100000 765 #define SK_TXBMU_DESC_UNRESET 0x00200000 766 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 767 768 #define SK_TXBMU_ONLINE \ 769 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 770 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 771 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 772 SK_TXBMU_DESC_UNRESET) 773 774 #define SK_TXBMU_OFFLINE \ 775 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 776 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 777 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 778 SK_TXBMU_DESC_RESET) 779 780 /* Block 16 -- Receive RAMbuffer 1 */ 781 #define SK_RXRB1_START 0x0800 782 #define SK_RXRB1_END 0x0804 783 #define SK_RXRB1_WR_PTR 0x0808 784 #define SK_RXRB1_RD_PTR 0x080C 785 #define SK_RXRB1_UTHR_PAUSE 0x0810 786 #define SK_RXRB1_LTHR_PAUSE 0x0814 787 #define SK_RXRB1_UTHR_HIPRIO 0x0818 788 #define SK_RXRB1_UTHR_LOPRIO 0x081C 789 #define SK_RXRB1_PKTCNT 0x0820 790 #define SK_RXRB1_LVL 0x0824 791 #define SK_RXRB1_CTLTST 0x0828 792 793 /* Block 17 -- Receive RAMbuffer 2 */ 794 #define SK_RXRB2_START 0x0880 795 #define SK_RXRB2_END 0x0884 796 #define SK_RXRB2_WR_PTR 0x0888 797 #define SK_RXRB2_RD_PTR 0x088C 798 #define SK_RXRB2_UTHR_PAUSE 0x0890 799 #define SK_RXRB2_LTHR_PAUSE 0x0894 800 #define SK_RXRB2_UTHR_HIPRIO 0x0898 801 #define SK_RXRB2_UTHR_LOPRIO 0x089C 802 #define SK_RXRB2_PKTCNT 0x08A0 803 #define SK_RXRB2_LVL 0x08A4 804 #define SK_RXRB2_CTLTST 0x08A8 805 806 /* Block 20 -- Sync. Transmit RAMbuffer 1 */ 807 #define SK_TXRBS1_START 0x0A00 808 #define SK_TXRBS1_END 0x0A04 809 #define SK_TXRBS1_WR_PTR 0x0A08 810 #define SK_TXRBS1_RD_PTR 0x0A0C 811 #define SK_TXRBS1_PKTCNT 0x0A20 812 #define SK_TXRBS1_LVL 0x0A24 813 #define SK_TXRBS1_CTLTST 0x0A28 814 815 /* Block 21 -- Async. Transmit RAMbuffer 1 */ 816 #define SK_TXRBA1_START 0x0A80 817 #define SK_TXRBA1_END 0x0A84 818 #define SK_TXRBA1_WR_PTR 0x0A88 819 #define SK_TXRBA1_RD_PTR 0x0A8C 820 #define SK_TXRBA1_PKTCNT 0x0AA0 821 #define SK_TXRBA1_LVL 0x0AA4 822 #define SK_TXRBA1_CTLTST 0x0AA8 823 824 /* Block 22 -- Sync. Transmit RAMbuffer 2 */ 825 #define SK_TXRBS2_START 0x0B00 826 #define SK_TXRBS2_END 0x0B04 827 #define SK_TXRBS2_WR_PTR 0x0B08 828 #define SK_TXRBS2_RD_PTR 0x0B0C 829 #define SK_TXRBS2_PKTCNT 0x0B20 830 #define SK_TXRBS2_LVL 0x0B24 831 #define SK_TXRBS2_CTLTST 0x0B28 832 833 /* Block 23 -- Async. Transmit RAMbuffer 2 */ 834 #define SK_TXRBA2_START 0x0B80 835 #define SK_TXRBA2_END 0x0B84 836 #define SK_TXRBA2_WR_PTR 0x0B88 837 #define SK_TXRBA2_RD_PTR 0x0B8C 838 #define SK_TXRBA2_PKTCNT 0x0BA0 839 #define SK_TXRBA2_LVL 0x0BA4 840 #define SK_TXRBA2_CTLTST 0x0BA8 841 842 #define SK_RBCTL_RESET 0x00000001 843 #define SK_RBCTL_UNRESET 0x00000002 844 #define SK_RBCTL_OFF 0x00000004 845 #define SK_RBCTL_ON 0x00000008 846 #define SK_RBCTL_STORENFWD_OFF 0x00000010 847 #define SK_RBCTL_STORENFWD_ON 0x00000020 848 849 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 850 #define SK_RXF1_END 0x0C00 851 #define SK_RXF1_WPTR 0x0C04 852 #define SK_RXF1_RPTR 0x0C0C 853 #define SK_RXF1_PKTCNT 0x0C10 854 #define SK_RXF1_LVL 0x0C14 855 #define SK_RXF1_MACCTL 0x0C18 856 #define SK_RXF1_CTL 0x0C1C 857 #define SK_RXLED1_CNTINIT 0x0C20 858 #define SK_RXLED1_COUNTER 0x0C24 859 #define SK_RXLED1_CTL 0x0C28 860 #define SK_RXLED1_TST 0x0C29 861 #define SK_LINK_SYNC1_CINIT 0x0C30 862 #define SK_LINK_SYNC1_COUNTER 0x0C34 863 #define SK_LINK_SYNC1_CTL 0x0C38 864 #define SK_LINK_SYNC1_TST 0x0C39 865 #define SK_LINKLED1_CTL 0x0C3C 866 867 #define SK_FIFO_END 0x3F 868 869 /* Receive MAC FIFO 1 (Yukon Only) */ 870 #define SK_RXMF1_END 0x0C40 871 #define SK_RXMF1_THRESHOLD 0x0C44 872 #define SK_RXMF1_CTRL_TEST 0x0C48 873 #define SK_RXMF1_WRITE_PTR 0x0C60 874 #define SK_RXMF1_WRITE_LEVEL 0x0C68 875 #define SK_RXMF1_READ_PTR 0x0C70 876 #define SK_RXMF1_READ_LEVEL 0x0C78 877 878 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 879 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 880 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 881 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 882 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 883 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 884 #define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */ 885 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 886 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 887 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 888 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 889 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 890 891 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 892 #define SK_RXF2_END 0x0C80 893 #define SK_RXF2_WPTR 0x0C84 894 #define SK_RXF2_RPTR 0x0C8C 895 #define SK_RXF2_PKTCNT 0x0C90 896 #define SK_RXF2_LVL 0x0C94 897 #define SK_RXF2_MACCTL 0x0C98 898 #define SK_RXF2_CTL 0x0C9C 899 #define SK_RXLED2_CNTINIT 0x0CA0 900 #define SK_RXLED2_COUNTER 0x0CA4 901 #define SK_RXLED2_CTL 0x0CA8 902 #define SK_RXLED2_TST 0x0CA9 903 #define SK_LINK_SYNC2_CINIT 0x0CB0 904 #define SK_LINK_SYNC2_COUNTER 0x0CB4 905 #define SK_LINK_SYNC2_CTL 0x0CB8 906 #define SK_LINK_SYNC2_TST 0x0CB9 907 #define SK_LINKLED2_CTL 0x0CBC 908 909 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 910 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 911 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004 912 #define SK_RXMACCTL_RSTAMP_ON 0x00000008 913 #define SK_RXMACCTL_FLUSH_OFF 0x00000010 914 #define SK_RXMACCTL_FLUSH_ON 0x00000020 915 #define SK_RXMACCTL_PAUSE_OFF 0x00000040 916 #define SK_RXMACCTL_PAUSE_ON 0x00000080 917 #define SK_RXMACCTL_AFULL_OFF 0x00000100 918 #define SK_RXMACCTL_AFULL_ON 0x00000200 919 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 920 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 921 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 922 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 923 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000 924 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 925 926 #define SK_RXLEDCTL_ENABLE 0x0001 927 #define SK_RXLEDCTL_COUNTER_STOP 0x0002 928 #define SK_RXLEDCTL_COUNTER_START 0x0004 929 930 #define SK_LINKLED_OFF 0x0001 931 #define SK_LINKLED_ON 0x0002 932 #define SK_LINKLED_LINKSYNC_OFF 0x0004 933 #define SK_LINKLED_LINKSYNC_ON 0x0008 934 #define SK_LINKLED_BLINK_OFF 0x0010 935 #define SK_LINKLED_BLINK_ON 0x0020 936 937 /* Block 26 -- TX MAC FIFO 1 regisrers */ 938 #define SK_TXF1_END 0x0D00 939 #define SK_TXF1_WPTR 0x0D04 940 #define SK_TXF1_RPTR 0x0D0C 941 #define SK_TXF1_PKTCNT 0x0D10 942 #define SK_TXF1_LVL 0x0D14 943 #define SK_TXF1_MACCTL 0x0D18 944 #define SK_TXF1_CTL 0x0D1C 945 #define SK_TXLED1_CNTINIT 0x0D20 946 #define SK_TXLED1_COUNTER 0x0D24 947 #define SK_TXLED1_CTL 0x0D28 948 #define SK_TXLED1_TST 0x0D29 949 950 /* Receive MAC FIFO 1 (Yukon Only) */ 951 #define SK_TXMF1_END 0x0D40 952 #define SK_TXMF1_THRESHOLD 0x0D44 953 #define SK_TXMF1_CTRL_TEST 0x0D48 954 #define SK_TXMF1_WRITE_PTR 0x0D60 955 #define SK_TXMF1_WRITE_SHADOW 0x0D64 956 #define SK_TXMF1_WRITE_LEVEL 0x0D68 957 #define SK_TXMF1_READ_PTR 0x0D70 958 #define SK_TXMF1_RESTART_PTR 0x0D74 959 #define SK_TXMF1_READ_LEVEL 0x0D78 960 961 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 962 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 963 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 964 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 965 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 966 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 967 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 968 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 969 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 970 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 971 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 972 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 973 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 974 975 /* Block 27 -- TX MAC FIFO 2 regisrers */ 976 #define SK_TXF2_END 0x0D80 977 #define SK_TXF2_WPTR 0x0D84 978 #define SK_TXF2_RPTR 0x0D8C 979 #define SK_TXF2_PKTCNT 0x0D90 980 #define SK_TXF2_LVL 0x0D94 981 #define SK_TXF2_MACCTL 0x0D98 982 #define SK_TXF2_CTL 0x0D9C 983 #define SK_TXLED2_CNTINIT 0x0DA0 984 #define SK_TXLED2_COUNTER 0x0DA4 985 #define SK_TXLED2_CTL 0x0DA8 986 #define SK_TXLED2_TST 0x0DA9 987 988 #define SK_TXMACCTL_XMAC_RESET 0x00000001 989 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002 990 #define SK_TXMACCTL_LOOP_OFF 0x00000004 991 #define SK_TXMACCTL_LOOP_ON 0x00000008 992 #define SK_TXMACCTL_FLUSH_OFF 0x00000010 993 #define SK_TXMACCTL_FLUSH_ON 0x00000020 994 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 995 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 996 #define SK_TXMACCTL_AFULL_OFF 0x00000100 997 #define SK_TXMACCTL_AFULL_ON 0x00000200 998 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 999 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 1000 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 1001 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1002 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1003 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1004 1005 #define SK_TXLEDCTL_ENABLE 0x0001 1006 #define SK_TXLEDCTL_COUNTER_STOP 0x0002 1007 #define SK_TXLEDCTL_COUNTER_START 0x0004 1008 1009 #define SK_FIFO_RESET 0x00000001 1010 #define SK_FIFO_UNRESET 0x00000002 1011 #define SK_FIFO_OFF 0x00000004 1012 #define SK_FIFO_ON 0x00000008 1013 1014 /* Block 28 -- Descriptor Poll Timer */ 1015 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1016 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1017 1018 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1019 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1020 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1021 1022 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1023 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1024 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1025 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1026 1027 /* Block 29 -- reserved */ 1028 1029 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1030 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1031 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1032 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1033 #define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */ 1034 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1035 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1036 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1037 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1038 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1039 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1040 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1041 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1042 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1043 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1044 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1045 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1046 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1047 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1048 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1049 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1050 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1051 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1052 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1053 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1054 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1055 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1056 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1057 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1058 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1059 1060 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1061 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1062 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1063 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1064 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1065 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1066 1067 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1068 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1069 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1070 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1071 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1072 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1073 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1074 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1075 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1076 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1077 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1078 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1079 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1080 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1081 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1082 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1083 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1084 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1085 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1086 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1087 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1088 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1089 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1090 1091 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1092 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1093 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1094 SK_GPHY_HWCFG_M_2 ) 1095 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1096 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1097 1098 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1099 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1100 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1101 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1102 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1103 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1104 1105 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1106 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1107 1108 /* Block 31 -- reserved */ 1109 1110 /* Block 32-33 -- Pattern Ram */ 1111 #define SK_WOL_PRAM 0x1000 1112 1113 /* Block 0x22 - 0x3f -- reserved */ 1114 1115 /* Block 0x40 to 0x4F -- XMAC 1 registers */ 1116 #define SK_XMAC1_BASE 0x2000 1117 1118 /* Block 0x50 to 0x5F -- MARV 1 registers */ 1119 #define SK_MARV1_BASE 0x2800 1120 1121 /* Block 0x60 to 0x6F -- XMAC 2 registers */ 1122 #define SK_XMAC2_BASE 0x3000 1123 1124 /* Block 0x70 to 0x7F -- MARV 2 registers */ 1125 #define SK_MARV2_BASE 0x3800 1126 1127 /* Compute relative offset of an XMAC register in the XMAC window(s). */ 1128 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1129 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1130 1131 #if 0 1132 #define SK_XM_READ_4(sc, reg) \ 1133 ((sk_win_read_2(sc->sk_softc, \ 1134 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1135 ((sk_win_read_2(sc->sk_softc, \ 1136 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1137 1138 #define SK_XM_WRITE_4(sc, reg, val) \ 1139 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1140 ((val) & 0xFFFF)); \ 1141 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1142 ((val) >> 16) & 0xFFFF) 1143 #else 1144 #define SK_XM_READ_4(sc, reg) \ 1145 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1146 1147 #define SK_XM_WRITE_4(sc, reg, val) \ 1148 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1149 #endif 1150 1151 #define SK_XM_READ_2(sc, reg) \ 1152 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1153 1154 #define SK_XM_WRITE_2(sc, reg, val) \ 1155 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1156 1157 #define SK_XM_SETBIT_4(sc, reg, x) \ 1158 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1159 1160 #define SK_XM_CLRBIT_4(sc, reg, x) \ 1161 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1162 1163 #define SK_XM_SETBIT_2(sc, reg, x) \ 1164 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1165 1166 #define SK_XM_CLRBIT_2(sc, reg, x) \ 1167 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1168 1169 /* Compute relative offset of an MARV register in the MARV window(s). */ 1170 #define SK_YU_REG(sc, reg) \ 1171 ((reg) + SK_MARV1_BASE + \ 1172 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1173 1174 #define SK_YU_READ_4(sc, reg) \ 1175 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1176 1177 #define SK_YU_READ_2(sc, reg) \ 1178 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1179 1180 #define SK_YU_WRITE_4(sc, reg, val) \ 1181 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1182 1183 #define SK_YU_WRITE_2(sc, reg, val) \ 1184 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1185 1186 #define SK_YU_SETBIT_4(sc, reg, x) \ 1187 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1188 1189 #define SK_YU_CLRBIT_4(sc, reg, x) \ 1190 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1191 1192 #define SK_YU_SETBIT_2(sc, reg, x) \ 1193 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1194 1195 #define SK_YU_CLRBIT_2(sc, reg, x) \ 1196 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1197 1198 /* 1199 * The default FIFO threshold on the XMAC II is 4 bytes. On 1200 * dual port NICs, this often leads to transmit underruns, so we 1201 * bump the threshold a little. 1202 */ 1203 #define SK_XM_TX_FIFOTHRESH 512 1204 1205 #define SK_PCI_VENDOR_ID 0x0000 1206 #define SK_PCI_DEVICE_ID 0x0002 1207 #define SK_PCI_COMMAND 0x0004 1208 #define SK_PCI_STATUS 0x0006 1209 #define SK_PCI_REVID 0x0008 1210 #define SK_PCI_CLASSCODE 0x0009 1211 #define SK_PCI_CACHELEN 0x000C 1212 #define SK_PCI_LATENCY_TIMER 0x000D 1213 #define SK_PCI_HEADER_TYPE 0x000E 1214 #define SK_PCI_LOMEM 0x0010 1215 #define SK_PCI_LOIO 0x0014 1216 #define SK_PCI_SUBVEN_ID 0x002C 1217 #define SK_PCI_SYBSYS_ID 0x002E 1218 #define SK_PCI_BIOSROM 0x0030 1219 #define SK_PCI_INTLINE 0x003C 1220 #define SK_PCI_INTPIN 0x003D 1221 #define SK_PCI_MINGNT 0x003E 1222 #define SK_PCI_MINLAT 0x003F 1223 1224 /* device specific PCI registers */ 1225 #define SK_PCI_OURREG1 0x0040 1226 #define SK_PCI_OURREG2 0x0044 1227 #define SK_PCI_CAPID 0x0048 /* 8 bits */ 1228 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1229 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1230 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1231 #define SK_PCI_PME_EVENT 0x004F 1232 #define SK_PCI_VPD_CAPID 0x0050 1233 #define SK_PCI_VPD_NEXTPTR 0x0051 1234 #define SK_PCI_VPD_ADDR 0x0052 1235 #define SK_PCI_VPD_DATA 0x0054 1236 1237 #define SK_PSTATE_MASK 0x0003 1238 #define SK_PSTATE_D0 0x0000 1239 #define SK_PSTATE_D1 0x0001 1240 #define SK_PSTATE_D2 0x0002 1241 #define SK_PSTATE_D3 0x0003 1242 #define SK_PME_EN 0x0010 1243 #define SK_PME_STATUS 0x8000 1244 1245 /* 1246 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1247 * read is complete. Set to 1 to initiate a write, will become 0 1248 * when write is finished. 1249 */ 1250 #define SK_VPD_FLAG 0x8000 1251 1252 /* VPD structures */ 1253 struct vpd_res { 1254 u_int8_t vr_id; 1255 u_int8_t vr_len; 1256 u_int8_t vr_pad; 1257 }; 1258 1259 struct vpd_key { 1260 char vk_key[2]; 1261 u_int8_t vk_len; 1262 }; 1263 1264 #define VPD_RES_ID 0x82 /* ID string */ 1265 #define VPD_RES_READ 0x90 /* start of read only area */ 1266 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 1267 #define VPD_RES_END 0x78 /* end tag */ 1268 1269 #define CSR_WRITE_4(sc, reg, val) \ 1270 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1271 #define CSR_WRITE_2(sc, reg, val) \ 1272 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1273 #define CSR_WRITE_1(sc, reg, val) \ 1274 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1275 1276 #define CSR_READ_4(sc, reg) \ 1277 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1278 #define CSR_READ_2(sc, reg) \ 1279 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1280 #define CSR_READ_1(sc, reg) \ 1281 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1282 1283 struct sk_type { 1284 u_int16_t sk_vid; 1285 u_int16_t sk_did; 1286 char *sk_name; 1287 }; 1288 1289 /* RX queue descriptor data structure */ 1290 struct sk_rx_desc { 1291 u_int32_t sk_ctl; 1292 u_int32_t sk_next; 1293 u_int32_t sk_data_lo; 1294 u_int32_t sk_data_hi; 1295 u_int32_t sk_xmac_rxstat; 1296 u_int32_t sk_timestamp; 1297 u_int16_t sk_csum2; 1298 u_int16_t sk_csum1; 1299 u_int16_t sk_csum2_start; 1300 u_int16_t sk_csum1_start; 1301 }; 1302 1303 #define SK_OPCODE_DEFAULT 0x00550000 1304 #define SK_OPCODE_CSUM 0x00560000 1305 1306 #define SK_RXCTL_LEN 0x0000FFFF 1307 #define SK_RXCTL_OPCODE 0x00FF0000 1308 #define SK_RXCTL_TSTAMP_VALID 0x01000000 1309 #define SK_RXCTL_STATUS_VALID 0x02000000 1310 #define SK_RXCTL_DEV0 0x04000000 1311 #define SK_RXCTL_EOF_INTR 0x08000000 1312 #define SK_RXCTL_EOB_INTR 0x10000000 1313 #define SK_RXCTL_LASTFRAG 0x20000000 1314 #define SK_RXCTL_FIRSTFRAG 0x40000000 1315 #define SK_RXCTL_OWN 0x80000000 1316 1317 #define SK_RXSTAT \ 1318 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1319 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1320 1321 struct sk_tx_desc { 1322 u_int32_t sk_ctl; 1323 u_int32_t sk_next; 1324 u_int32_t sk_data_lo; 1325 u_int32_t sk_data_hi; 1326 u_int32_t sk_xmac_txstat; 1327 u_int16_t sk_rsvd0; 1328 u_int16_t sk_csum_startval; 1329 u_int16_t sk_csum_startpos; 1330 u_int16_t sk_csum_writepos; 1331 u_int32_t sk_rsvd1; 1332 }; 1333 1334 #define SK_TXCTL_LEN 0x0000FFFF 1335 #define SK_TXCTL_OPCODE 0x00FF0000 1336 #define SK_TXCTL_SW 0x01000000 1337 #define SK_TXCTL_NOCRC 0x02000000 1338 #define SK_TXCTL_STORENFWD 0x04000000 1339 #define SK_TXCTL_EOF_INTR 0x08000000 1340 #define SK_TXCTL_EOB_INTR 0x10000000 1341 #define SK_TXCTL_LASTFRAG 0x20000000 1342 #define SK_TXCTL_FIRSTFRAG 0x40000000 1343 #define SK_TXCTL_OWN 0x80000000 1344 1345 #define SK_TXSTAT \ 1346 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1347 1348 #define SK_RXBYTES(x) (x) & 0x0000FFFF; 1349 #define SK_TXBYTES SK_RXBYTES 1350 1351 #define SK_TX_RING_CNT 512 1352 #define SK_RX_RING_CNT 256 1353 1354 /* 1355 * Jumbo buffer stuff. Note that we must allocate more jumbo 1356 * buffers than there are descriptors in the receive ring. This 1357 * is because we don't know how long it will take for a packet 1358 * to be released after we hand it off to the upper protocol 1359 * layers. To be safe, we allocate 1.5 times the number of 1360 * receive descriptors. 1361 */ 1362 #define SK_JUMBO_FRAMELEN 9018 1363 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1364 #define SK_JSLOTS 384 1365 1366 #define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t)) 1367 #define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \ 1368 (SK_JRAWLEN % sizeof(u_int64_t)))) 1369 #define SK_MCLBYTES (SK_JLEN - sizeof(u_int64_t)) 1370 #define SK_JPAGESZ PAGE_SIZE 1371 #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1372 #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1373 1374 struct sk_jslot { 1375 caddr_t sk_buf; 1376 int sk_inuse; 1377 }; 1378 1379 struct sk_jpool_entry { 1380 int slot; 1381 SLIST_ENTRY(sk_jpool_entry) jpool_entries; 1382 }; 1383 1384 struct sk_chain { 1385 void *sk_desc; 1386 struct mbuf *sk_mbuf; 1387 struct sk_chain *sk_next; 1388 }; 1389 1390 struct sk_chain_data { 1391 struct sk_chain sk_tx_chain[SK_TX_RING_CNT]; 1392 struct sk_chain sk_rx_chain[SK_RX_RING_CNT]; 1393 int sk_tx_prod; 1394 int sk_tx_cons; 1395 int sk_tx_cnt; 1396 int sk_rx_prod; 1397 int sk_rx_cons; 1398 int sk_rx_cnt; 1399 /* Stick the jumbo mem management stuff here too. */ 1400 struct sk_jslot sk_jslots[SK_JSLOTS]; 1401 void *sk_jumbo_buf; 1402 1403 }; 1404 1405 struct sk_ring_data { 1406 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT]; 1407 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT]; 1408 }; 1409 1410 struct sk_bcom_hack { 1411 int reg; 1412 int val; 1413 }; 1414 1415 #define SK_INC(x, y) (x) = (x + 1) % y 1416 1417 /* Forward decl. */ 1418 struct sk_if_softc; 1419 1420 /* Softc for the GEnesis controller. */ 1421 struct sk_softc { 1422 bus_space_handle_t sk_bhandle; /* bus space handle */ 1423 bus_space_tag_t sk_btag; /* bus space tag */ 1424 void *sk_intrhand; /* irq handler handle */ 1425 struct resource *sk_irq; /* IRQ resource handle */ 1426 struct resource *sk_res; /* I/O or shared mem handle */ 1427 u_int8_t sk_unit; /* controller number */ 1428 u_int8_t sk_type; 1429 char *sk_vpd_prodname; 1430 char *sk_vpd_readonly; 1431 u_int32_t sk_rboff; /* RAMbuffer offset */ 1432 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1433 u_int32_t sk_pmd; /* physical media type */ 1434 u_int32_t sk_intrmask; 1435 struct sk_if_softc *sk_if[2]; 1436 device_t sk_devs[2]; 1437 }; 1438 1439 /* Softc for each logical interface */ 1440 struct sk_if_softc { 1441 struct arpcom arpcom; /* interface info */ 1442 device_t sk_miibus; 1443 u_int8_t sk_unit; /* interface number */ 1444 u_int8_t sk_port; /* port # on controller */ 1445 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1446 u_int32_t sk_rx_ramstart; 1447 u_int32_t sk_rx_ramend; 1448 u_int32_t sk_tx_ramstart; 1449 u_int32_t sk_tx_ramend; 1450 int sk_phytype; 1451 int sk_phyaddr; 1452 device_t sk_dev; 1453 int sk_cnt; 1454 int sk_link; 1455 struct callout_handle sk_tick_ch; 1456 struct sk_chain_data sk_cdata; 1457 struct sk_ring_data *sk_rdata; 1458 struct sk_softc *sk_softc; /* parent controller */ 1459 int sk_tx_bmu; /* TX BMU register */ 1460 int sk_if_flags; 1461 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1462 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1463 }; 1464 1465 #define SK_MAXUNIT 256 1466 #define SK_TIMEOUT 1000 1467 #define ETHER_ALIGN 2 1468 1469 #ifdef __alpha__ 1470 #undef vtophys 1471 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1472 #endif
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