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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_skreg.h

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    1 /*      $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $      */
    2 
    3 /*-
    4  * Copyright (c) 1997, 1998, 1999, 2000
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  *
   34  * $FreeBSD: src/sys/pci/if_skreg.h,v 1.20.2.5 2005/03/28 16:21:16 bz Exp $
   35  */
   36 
   37 /*-
   38  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
   39  *
   40  * Permission to use, copy, modify, and distribute this software for any
   41  * purpose with or without fee is hereby granted, provided that the above
   42  * copyright notice and this permission notice appear in all copies.
   43  *
   44  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   45  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   46  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   47  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   48  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   49  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   50  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   51  */
   52 
   53 /* Values to keep the different chip revisions apart (SK_CHIPVER). */
   54 #define SK_GENESIS              0x0A
   55 #define SK_YUKON                0xB0
   56 #define SK_YUKON_LITE           0xB1
   57 #define SK_YUKON_LP             0xB2
   58 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
   59 
   60 /* Known revisions in SK_CONFIG. */
   61 #define SK_YUKON_LITE_REV_A0    0x0 /* invented, see test in skc_attach. */
   62 #define SK_YUKON_LITE_REV_A1    0x3
   63 #define SK_YUKON_LITE_REV_A3    0x7
   64 
   65 /*
   66  * SysKonnect PCI vendor ID
   67  */
   68 #define VENDORID_SK             0x1148
   69 
   70 /*
   71  * Marvell PCI vendor ID
   72  */
   73 #define VENDORID_MARVELL        0x11AB
   74 
   75 /*
   76  * SK-NET gigabit ethernet device IDs
   77  */
   78 #define DEVICEID_SK_V1          0x4300
   79 #define DEVICEID_SK_V2          0x4320
   80 
   81 /*
   82  * Belkin F5D5005
   83  */
   84 #define DEVICEID_BELKIN_5005    0x5005
   85 
   86 /*
   87  * 3Com PCI vendor ID
   88  */
   89 #define VENDORID_3COM           0x10b7
   90 
   91 /*
   92  * 3Com gigabit ethernet device ID
   93  */
   94 #define DEVICEID_3COM_3C940     0x1700
   95 
   96 /*
   97  * Linksys PCI vendor ID
   98  */
   99 #define VENDORID_LINKSYS        0x1737
  100 
  101 /*
  102  * Linksys gigabit ethernet device ID
  103  */
  104 #define DEVICEID_LINKSYS_EG1032 0x1032
  105 
  106 /*
  107  * D-Link PCI vendor ID
  108  */
  109 #define VENDORID_DLINK          0x1186
  110 
  111 /*
  112  * D-Link gigabit ethernet device ID
  113  */
  114 #define DEVICEID_DLINK_DGE530T  0x4c00
  115 
  116 /*
  117  * GEnesis registers. The GEnesis chip has a 256-byte I/O window
  118  * but internally it has a 16K register space. This 16K space is
  119  * divided into 128-byte blocks. The first 128 bytes of the I/O
  120  * window represent the first block, which is permanently mapped
  121  * at the start of the window. The other 127 blocks can be mapped
  122  * to the second 128 bytes of the I/O window by setting the desired
  123  * block value in the RAP register in block 0. Not all of the 127
  124  * blocks are actually used. Most registers are 32 bits wide, but
  125  * there are a few 16-bit and 8-bit ones as well.
  126  */
  127 
  128 
  129 /* Start of remappable register window. */
  130 #define SK_WIN_BASE             0x0080
  131 
  132 /* Size of a window */
  133 #define SK_WIN_LEN              0x80
  134 
  135 #define SK_WIN_MASK             0x3F80
  136 #define SK_REG_MASK             0x7F
  137 
  138 /* Compute the window of a given register (for the RAP register) */
  139 #define SK_WIN(reg)             (((reg) & SK_WIN_MASK) / SK_WIN_LEN)
  140 
  141 /* Compute the relative offset of a register within the window */
  142 #define SK_REG(reg)             ((reg) & SK_REG_MASK)
  143 
  144 #define SK_PORT_A       0
  145 #define SK_PORT_B       1
  146 
  147 /*
  148  * Compute offset of port-specific register. Since there are two
  149  * ports, there are two of some GEnesis modules (e.g. two sets of
  150  * DMA queues, two sets of FIFO control registers, etc...). Normally,
  151  * the block for port 0 is at offset 0x0 and the block for port 1 is
  152  * at offset 0x80 (i.e. the next page over). However for the transmit
  153  * BMUs and RAMbuffers, there are two blocks for each port: one for
  154  * the sync transmit queue and one for the async queue (which we don't
  155  * use). However instead of ordering them like this:
  156  * TX sync 1 / TX sync 2 / TX async 1 / TX async 2
  157  * SysKonnect has instead ordered them like this:
  158  * TX sync 1 / TX async 1 / TX sync 2 / TX async 2
  159  * This means that when referencing the TX BMU and RAMbuffer registers,
  160  * we have to double the block offset (0x80 * 2) in order to reach the
  161  * second queue. This prevents us from using the same formula
  162  * (sk_port * 0x80) to compute the offsets for all of the port-specific
  163  * blocks: we need an extra offset for the BMU and RAMbuffer registers.
  164  * The simplest thing is to provide an extra argument to these macros:
  165  * the 'skip' parameter. The 'skip' value is the number of extra pages
  166  * for skip when computing the port0/port1 offsets. For most registers,
  167  * the skip value is 0; for the BMU and RAMbuffer registers, it's 1.
  168  */
  169 #define SK_IF_READ_4(sc_if, skip, reg)          \
  170         sk_win_read_4(sc_if->sk_softc, reg +    \
  171         ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
  172 #define SK_IF_READ_2(sc_if, skip, reg)          \
  173         sk_win_read_2(sc_if->sk_softc, reg +    \
  174         ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
  175 #define SK_IF_READ_1(sc_if, skip, reg)          \
  176         sk_win_read_1(sc_if->sk_softc, reg +    \
  177         ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
  178 
  179 #define SK_IF_WRITE_4(sc_if, skip, reg, val)    \
  180         sk_win_write_4(sc_if->sk_softc,         \
  181         reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
  182 #define SK_IF_WRITE_2(sc_if, skip, reg, val)    \
  183         sk_win_write_2(sc_if->sk_softc,         \
  184         reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
  185 #define SK_IF_WRITE_1(sc_if, skip, reg, val)    \
  186         sk_win_write_1(sc_if->sk_softc,         \
  187         reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
  188 
  189 /* Block 0 registers, permanently mapped at iobase. */
  190 #define SK_RAP          0x0000
  191 #define SK_CSR          0x0004
  192 #define SK_LED          0x0006
  193 #define SK_ISR          0x0008  /* interrupt source */
  194 #define SK_IMR          0x000C  /* interrupt mask */
  195 #define SK_IESR         0x0010  /* interrupt hardware error source */
  196 #define SK_IEMR         0x0014  /* interrupt hardware error mask */
  197 #define SK_ISSR         0x0018  /* special interrupt source */
  198 #define SK_XM_IMR0      0x0020
  199 #define SK_XM_ISR0      0x0028
  200 #define SK_XM_PHYADDR0  0x0030
  201 #define SK_XM_PHYDATA0  0x0034
  202 #define SK_XM_IMR1      0x0040
  203 #define SK_XM_ISR1      0x0048
  204 #define SK_XM_PHYADDR1  0x0050
  205 #define SK_XM_PHYDATA1  0x0054
  206 #define SK_BMU_RX_CSR0  0x0060
  207 #define SK_BMU_RX_CSR1  0x0064
  208 #define SK_BMU_TXS_CSR0 0x0068
  209 #define SK_BMU_TXA_CSR0 0x006C
  210 #define SK_BMU_TXS_CSR1 0x0070
  211 #define SK_BMU_TXA_CSR1 0x0074
  212 
  213 /* SK_CSR register */
  214 #define SK_CSR_SW_RESET                 0x0001
  215 #define SK_CSR_SW_UNRESET               0x0002
  216 #define SK_CSR_MASTER_RESET             0x0004
  217 #define SK_CSR_MASTER_UNRESET           0x0008
  218 #define SK_CSR_MASTER_STOP              0x0010
  219 #define SK_CSR_MASTER_DONE              0x0020
  220 #define SK_CSR_SW_IRQ_CLEAR             0x0040
  221 #define SK_CSR_SW_IRQ_SET               0x0080
  222 #define SK_CSR_SLOTSIZE                 0x0100 /* 1 == 64 bits, 0 == 32 */
  223 #define SK_CSR_BUSCLOCK                 0x0200 /* 1 == 33/66 Mhz, = 33 */
  224 
  225 /* SK_LED register */
  226 #define SK_LED_GREEN_OFF                0x01
  227 #define SK_LED_GREEN_ON                 0x02
  228 
  229 /* SK_ISR register */
  230 #define SK_ISR_TX2_AS_CHECK             0x00000001
  231 #define SK_ISR_TX2_AS_EOF               0x00000002
  232 #define SK_ISR_TX2_AS_EOB               0x00000004
  233 #define SK_ISR_TX2_S_CHECK              0x00000008
  234 #define SK_ISR_TX2_S_EOF                0x00000010
  235 #define SK_ISR_TX2_S_EOB                0x00000020
  236 #define SK_ISR_TX1_AS_CHECK             0x00000040
  237 #define SK_ISR_TX1_AS_EOF               0x00000080
  238 #define SK_ISR_TX1_AS_EOB               0x00000100
  239 #define SK_ISR_TX1_S_CHECK              0x00000200
  240 #define SK_ISR_TX1_S_EOF                0x00000400
  241 #define SK_ISR_TX1_S_EOB                0x00000800
  242 #define SK_ISR_RX2_CHECK                0x00001000
  243 #define SK_ISR_RX2_EOF                  0x00002000
  244 #define SK_ISR_RX2_EOB                  0x00004000
  245 #define SK_ISR_RX1_CHECK                0x00008000
  246 #define SK_ISR_RX1_EOF                  0x00010000
  247 #define SK_ISR_RX1_EOB                  0x00020000
  248 #define SK_ISR_LINK2_OFLOW              0x00040000
  249 #define SK_ISR_MAC2                     0x00080000
  250 #define SK_ISR_LINK1_OFLOW              0x00100000
  251 #define SK_ISR_MAC1                     0x00200000
  252 #define SK_ISR_TIMER                    0x00400000
  253 #define SK_ISR_EXTERNAL_REG             0x00800000
  254 #define SK_ISR_SW                       0x01000000
  255 #define SK_ISR_I2C_RDY                  0x02000000
  256 #define SK_ISR_TX2_TIMEO                0x04000000
  257 #define SK_ISR_TX1_TIMEO                0x08000000
  258 #define SK_ISR_RX2_TIMEO                0x10000000
  259 #define SK_ISR_RX1_TIMEO                0x20000000
  260 #define SK_ISR_RSVD                     0x40000000
  261 #define SK_ISR_HWERR                    0x80000000
  262 
  263 /* SK_IMR register */
  264 #define SK_IMR_TX2_AS_CHECK             0x00000001
  265 #define SK_IMR_TX2_AS_EOF               0x00000002
  266 #define SK_IMR_TX2_AS_EOB               0x00000004
  267 #define SK_IMR_TX2_S_CHECK              0x00000008
  268 #define SK_IMR_TX2_S_EOF                0x00000010
  269 #define SK_IMR_TX2_S_EOB                0x00000020
  270 #define SK_IMR_TX1_AS_CHECK             0x00000040
  271 #define SK_IMR_TX1_AS_EOF               0x00000080
  272 #define SK_IMR_TX1_AS_EOB               0x00000100
  273 #define SK_IMR_TX1_S_CHECK              0x00000200
  274 #define SK_IMR_TX1_S_EOF                0x00000400
  275 #define SK_IMR_TX1_S_EOB                0x00000800
  276 #define SK_IMR_RX2_CHECK                0x00001000
  277 #define SK_IMR_RX2_EOF                  0x00002000
  278 #define SK_IMR_RX2_EOB                  0x00004000
  279 #define SK_IMR_RX1_CHECK                0x00008000
  280 #define SK_IMR_RX1_EOF                  0x00010000
  281 #define SK_IMR_RX1_EOB                  0x00020000
  282 #define SK_IMR_LINK2_OFLOW              0x00040000
  283 #define SK_IMR_MAC2                     0x00080000
  284 #define SK_IMR_LINK1_OFLOW              0x00100000
  285 #define SK_IMR_MAC1                     0x00200000
  286 #define SK_IMR_TIMER                    0x00400000
  287 #define SK_IMR_EXTERNAL_REG             0x00800000
  288 #define SK_IMR_SW                       0x01000000
  289 #define SK_IMR_I2C_RDY                  0x02000000
  290 #define SK_IMR_TX2_TIMEO                0x04000000
  291 #define SK_IMR_TX1_TIMEO                0x08000000
  292 #define SK_IMR_RX2_TIMEO                0x10000000
  293 #define SK_IMR_RX1_TIMEO                0x20000000
  294 #define SK_IMR_RSVD                     0x40000000
  295 #define SK_IMR_HWERR                    0x80000000
  296 
  297 #define SK_INTRS1       \
  298         (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1)
  299 
  300 #define SK_INTRS2       \
  301         (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2)
  302 
  303 /* SK_IESR register */
  304 #define SK_IESR_PAR_RX2                 0x00000001
  305 #define SK_IESR_PAR_RX1                 0x00000002
  306 #define SK_IESR_PAR_MAC2                0x00000004
  307 #define SK_IESR_PAR_MAC1                0x00000008
  308 #define SK_IESR_PAR_WR_RAM              0x00000010
  309 #define SK_IESR_PAR_RD_RAM              0x00000020
  310 #define SK_IESR_NO_TSTAMP_MAC2          0x00000040
  311 #define SK_IESR_NO_TSTAMO_MAC1          0x00000080
  312 #define SK_IESR_NO_STS_MAC2             0x00000100
  313 #define SK_IESR_NO_STS_MAC1             0x00000200
  314 #define SK_IESR_IRQ_STS                 0x00000400
  315 #define SK_IESR_MASTERERR               0x00000800
  316 
  317 /* SK_IEMR register */
  318 #define SK_IEMR_PAR_RX2                 0x00000001
  319 #define SK_IEMR_PAR_RX1                 0x00000002
  320 #define SK_IEMR_PAR_MAC2                0x00000004
  321 #define SK_IEMR_PAR_MAC1                0x00000008
  322 #define SK_IEMR_PAR_WR_RAM              0x00000010
  323 #define SK_IEMR_PAR_RD_RAM              0x00000020
  324 #define SK_IEMR_NO_TSTAMP_MAC2          0x00000040
  325 #define SK_IEMR_NO_TSTAMO_MAC1          0x00000080
  326 #define SK_IEMR_NO_STS_MAC2             0x00000100
  327 #define SK_IEMR_NO_STS_MAC1             0x00000200
  328 #define SK_IEMR_IRQ_STS                 0x00000400
  329 #define SK_IEMR_MASTERERR               0x00000800
  330 
  331 /* Block 2 */
  332 #define SK_MAC0_0       0x0100
  333 #define SK_MAC0_1       0x0104
  334 #define SK_MAC1_0       0x0108
  335 #define SK_MAC1_1       0x010C
  336 #define SK_MAC2_0       0x0110
  337 #define SK_MAC2_1       0x0114
  338 #define SK_CONNTYPE     0x0118
  339 #define SK_PMDTYPE      0x0119
  340 #define SK_CONFIG       0x011A
  341 #define SK_CHIPVER      0x011B
  342 #define SK_EPROM0       0x011C
  343 #define SK_EPROM1       0x011D
  344 #define SK_EPROM2       0x011E
  345 #define SK_EPROM3       0x011F
  346 #define SK_EP_ADDR      0x0120
  347 #define SK_EP_DATA      0x0124
  348 #define SK_EP_LOADCTL   0x0128
  349 #define SK_EP_LOADTST   0x0129
  350 #define SK_TIMERINIT    0x0130
  351 #define SK_TIMER        0x0134
  352 #define SK_TIMERCTL     0x0138
  353 #define SK_TIMERTST     0x0139
  354 #define SK_IMTIMERINIT  0x0140
  355 #define SK_IMTIMER      0x0144
  356 #define SK_IMTIMERCTL   0x0148
  357 #define SK_IMTIMERTST   0x0149
  358 #define SK_IMMR         0x014C
  359 #define SK_IHWEMR       0x0150
  360 #define SK_TESTCTL1     0x0158
  361 #define SK_TESTCTL2     0x0159
  362 #define SK_GPIO         0x015C
  363 #define SK_I2CHWCTL     0x0160
  364 #define SK_I2CHWDATA    0x0164
  365 #define SK_I2CHWIRQ     0x0168
  366 #define SK_I2CSW        0x016C
  367 #define SK_BLNKINIT     0x0170
  368 #define SK_BLNKCOUNT    0x0174
  369 #define SK_BLNKCTL      0x0178
  370 #define SK_BLNKSTS      0x0179
  371 #define SK_BLNKTST      0x017A
  372 
  373 #define SK_IMCTL_STOP   0x02
  374 #define SK_IMCTL_START  0x04
  375 
  376 #define SK_IMTIMER_TICKS        54
  377 #define SK_IM_USECS(x)          ((x) * SK_IMTIMER_TICKS)
  378 
  379 /*
  380  * The SK_EPROM0 register contains a byte that describes the
  381  * amount of SRAM mounted on the NIC. The value also tells if
  382  * the chips are 64K or 128K. This affects the RAMbuffer address
  383  * offset that we need to use.
  384  */
  385 #define SK_RAMSIZE_512K_64      0x1
  386 #define SK_RAMSIZE_1024K_128    0x2
  387 #define SK_RAMSIZE_1024K_64     0x3
  388 #define SK_RAMSIZE_2048K_128    0x4
  389 
  390 #define SK_RBOFF_0              0x0
  391 #define SK_RBOFF_80000          0x80000
  392 
  393 /*
  394  * SK_EEPROM1 contains the PHY type, which may be XMAC for
  395  * fiber-based cards or BCOM for 1000baseT cards with a Broadcom
  396  * PHY.
  397  */
  398 #define SK_PHYTYPE_XMAC         0       /* integeated XMAC II PHY */
  399 #define SK_PHYTYPE_BCOM         1       /* Broadcom BCM5400 */
  400 #define SK_PHYTYPE_LONE         2       /* Level One LXT1000 */
  401 #define SK_PHYTYPE_NAT          3       /* National DP83891 */
  402 #define SK_PHYTYPE_MARV_COPPER  4       /* Marvell 88E1011S */
  403 #define SK_PHYTYPE_MARV_FIBER   5       /* Marvell 88E1011S (fiber) */
  404 
  405 /*
  406  * PHY addresses.
  407  */
  408 #define SK_PHYADDR_XMAC         0x0
  409 #define SK_PHYADDR_BCOM         0x1
  410 #define SK_PHYADDR_LONE         0x3
  411 #define SK_PHYADDR_NAT          0x0
  412 #define SK_PHYADDR_MARV         0x0
  413 
  414 #define SK_CONFIG_SINGLEMAC     0x01
  415 #define SK_CONFIG_DIS_DSL_CLK   0x02
  416 
  417 #define SK_PMD_1000BASELX       0x4C
  418 #define SK_PMD_1000BASESX       0x53
  419 #define SK_PMD_1000BASECX       0x43
  420 #define SK_PMD_1000BASETX       0x54
  421 
  422 /* GPIO bits */
  423 #define SK_GPIO_DAT0            0x00000001
  424 #define SK_GPIO_DAT1            0x00000002
  425 #define SK_GPIO_DAT2            0x00000004
  426 #define SK_GPIO_DAT3            0x00000008
  427 #define SK_GPIO_DAT4            0x00000010
  428 #define SK_GPIO_DAT5            0x00000020
  429 #define SK_GPIO_DAT6            0x00000040
  430 #define SK_GPIO_DAT7            0x00000080
  431 #define SK_GPIO_DAT8            0x00000100
  432 #define SK_GPIO_DAT9            0x00000200
  433 #define SK_GPIO_DIR0            0x00010000
  434 #define SK_GPIO_DIR1            0x00020000
  435 #define SK_GPIO_DIR2            0x00040000
  436 #define SK_GPIO_DIR3            0x00080000
  437 #define SK_GPIO_DIR4            0x00100000
  438 #define SK_GPIO_DIR5            0x00200000
  439 #define SK_GPIO_DIR6            0x00400000
  440 #define SK_GPIO_DIR7            0x00800000
  441 #define SK_GPIO_DIR8            0x01000000
  442 #define SK_GPIO_DIR9            0x02000000
  443 
  444 /* Block 3 Ram interface and MAC arbiter registers */
  445 #define SK_RAMADDR      0x0180
  446 #define SK_RAMDATA0     0x0184
  447 #define SK_RAMDATA1     0x0188
  448 #define SK_TO0          0x0190
  449 #define SK_TO1          0x0191
  450 #define SK_TO2          0x0192
  451 #define SK_TO3          0x0193
  452 #define SK_TO4          0x0194
  453 #define SK_TO5          0x0195
  454 #define SK_TO6          0x0196
  455 #define SK_TO7          0x0197
  456 #define SK_TO8          0x0198
  457 #define SK_TO9          0x0199
  458 #define SK_TO10         0x019A
  459 #define SK_TO11         0x019B
  460 #define SK_RITIMEO_TMR  0x019C
  461 #define SK_RAMCTL       0x01A0
  462 #define SK_RITIMER_TST  0x01A2
  463 
  464 #define SK_RAMCTL_RESET         0x0001
  465 #define SK_RAMCTL_UNRESET       0x0002
  466 #define SK_RAMCTL_CLR_IRQ_WPAR  0x0100
  467 #define SK_RAMCTL_CLR_IRQ_RPAR  0x0200
  468 
  469 /* Mac arbiter registers */
  470 #define SK_MINIT_RX1    0x01B0
  471 #define SK_MINIT_RX2    0x01B1
  472 #define SK_MINIT_TX1    0x01B2
  473 #define SK_MINIT_TX2    0x01B3
  474 #define SK_MTIMEO_RX1   0x01B4
  475 #define SK_MTIMEO_RX2   0x01B5
  476 #define SK_MTIMEO_TX1   0x01B6
  477 #define SK_MTIEMO_TX2   0x01B7
  478 #define SK_MACARB_CTL   0x01B8
  479 #define SK_MTIMER_TST   0x01BA
  480 #define SK_RCINIT_RX1   0x01C0
  481 #define SK_RCINIT_RX2   0x01C1
  482 #define SK_RCINIT_TX1   0x01C2
  483 #define SK_RCINIT_TX2   0x01C3
  484 #define SK_RCTIMEO_RX1  0x01C4
  485 #define SK_RCTIMEO_RX2  0x01C5
  486 #define SK_RCTIMEO_TX1  0x01C6
  487 #define SK_RCTIMEO_TX2  0x01C7
  488 #define SK_RECOVERY_CTL 0x01C8
  489 #define SK_RCTIMER_TST  0x01CA
  490 
  491 /* Packet arbiter registers */
  492 #define SK_RXPA1_TINIT  0x01D0
  493 #define SK_RXPA2_TINIT  0x01D4
  494 #define SK_TXPA1_TINIT  0x01D8
  495 #define SK_TXPA2_TINIT  0x01DC
  496 #define SK_RXPA1_TIMEO  0x01E0
  497 #define SK_RXPA2_TIMEO  0x01E4
  498 #define SK_TXPA1_TIMEO  0x01E8
  499 #define SK_TXPA2_TIMEO  0x01EC
  500 #define SK_PKTARB_CTL   0x01F0
  501 #define SK_PKTATB_TST   0x01F2
  502 
  503 #define SK_PKTARB_TIMEOUT       0x2000
  504 
  505 #define SK_PKTARBCTL_RESET              0x0001
  506 #define SK_PKTARBCTL_UNRESET            0x0002
  507 #define SK_PKTARBCTL_RXTO1_OFF          0x0004
  508 #define SK_PKTARBCTL_RXTO1_ON           0x0008
  509 #define SK_PKTARBCTL_RXTO2_OFF          0x0010
  510 #define SK_PKTARBCTL_RXTO2_ON           0x0020
  511 #define SK_PKTARBCTL_TXTO1_OFF          0x0040
  512 #define SK_PKTARBCTL_TXTO1_ON           0x0080
  513 #define SK_PKTARBCTL_TXTO2_OFF          0x0100
  514 #define SK_PKTARBCTL_TXTO2_ON           0x0200
  515 #define SK_PKTARBCTL_CLR_IRQ_RXTO1      0x0400
  516 #define SK_PKTARBCTL_CLR_IRQ_RXTO2      0x0800
  517 #define SK_PKTARBCTL_CLR_IRQ_TXTO1      0x1000
  518 #define SK_PKTARBCTL_CLR_IRQ_TXTO2      0x2000
  519 
  520 #define SK_MINIT_XMAC_B2        54
  521 #define SK_MINIT_XMAC_C1        63
  522 
  523 #define SK_MACARBCTL_RESET      0x0001
  524 #define SK_MACARBCTL_UNRESET    0x0002
  525 #define SK_MACARBCTL_FASTOE_OFF 0x0004
  526 #define SK_MACARBCRL_FASTOE_ON  0x0008
  527 
  528 #define SK_RCINIT_XMAC_B2       54
  529 #define SK_RCINIT_XMAC_C1       0
  530 
  531 #define SK_RECOVERYCTL_RX1_OFF  0x0001
  532 #define SK_RECOVERYCTL_RX1_ON   0x0002
  533 #define SK_RECOVERYCTL_RX2_OFF  0x0004
  534 #define SK_RECOVERYCTL_RX2_ON   0x0008
  535 #define SK_RECOVERYCTL_TX1_OFF  0x0010
  536 #define SK_RECOVERYCTL_TX1_ON   0x0020
  537 #define SK_RECOVERYCTL_TX2_OFF  0x0040
  538 #define SK_RECOVERYCTL_TX2_ON   0x0080
  539 
  540 #define SK_RECOVERY_XMAC_B2                             \
  541         (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON|   \
  542         SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON)
  543 
  544 #define SK_RECOVERY_XMAC_C1                             \
  545         (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \
  546         SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF)
  547 
  548 /* Block 4 -- TX Arbiter MAC 1 */
  549 #define SK_TXAR1_TIMERINIT      0x0200
  550 #define SK_TXAR1_TIMERVAL       0x0204
  551 #define SK_TXAR1_LIMITINIT      0x0208
  552 #define SK_TXAR1_LIMITCNT       0x020C
  553 #define SK_TXAR1_COUNTERCTL     0x0210
  554 #define SK_TXAR1_COUNTERTST     0x0212
  555 #define SK_TXAR1_COUNTERSTS     0x0212
  556 
  557 /* Block 5 -- TX Arbiter MAC 2 */
  558 #define SK_TXAR2_TIMERINIT      0x0280
  559 #define SK_TXAR2_TIMERVAL       0x0284
  560 #define SK_TXAR2_LIMITINIT      0x0288
  561 #define SK_TXAR2_LIMITCNT       0x028C
  562 #define SK_TXAR2_COUNTERCTL     0x0290
  563 #define SK_TXAR2_COUNTERTST     0x0291
  564 #define SK_TXAR2_COUNTERSTS     0x0292
  565 
  566 #define SK_TXARCTL_OFF          0x01
  567 #define SK_TXARCTL_ON           0x02
  568 #define SK_TXARCTL_RATECTL_OFF  0x04
  569 #define SK_TXARCTL_RATECTL_ON   0x08
  570 #define SK_TXARCTL_ALLOC_OFF    0x10
  571 #define SK_TXARCTL_ALLOC_ON     0x20
  572 #define SK_TXARCTL_FSYNC_OFF    0x40
  573 #define SK_TXARCTL_FSYNC_ON     0x80
  574 
  575 /* Block 6 -- External registers */
  576 #define SK_EXTREG_BASE  0x300
  577 #define SK_EXTREG_END   0x37C
  578 
  579 /* Block 7 -- PCI config registers */
  580 #define SK_PCI_BASE     0x0380
  581 #define SK_PCI_END      0x03FC
  582 
  583 /* Compute offset of mirrored PCI register */
  584 #define SK_PCI_REG(reg)         ((reg) + SK_PCI_BASE)
  585 
  586 /* Block 8 -- RX queue 1 */
  587 #define SK_RXQ1_BUFCNT          0x0400
  588 #define SK_RXQ1_BUFCTL          0x0402
  589 #define SK_RXQ1_NEXTDESC        0x0404
  590 #define SK_RXQ1_RXBUF_LO        0x0408
  591 #define SK_RXQ1_RXBUF_HI        0x040C
  592 #define SK_RXQ1_RXSTAT          0x0410
  593 #define SK_RXQ1_TIMESTAMP       0x0414
  594 #define SK_RXQ1_CSUM1           0x0418
  595 #define SK_RXQ1_CSUM2           0x041A
  596 #define SK_RXQ1_CSUM1_START     0x041C
  597 #define SK_RXQ1_CSUM2_START     0x041E
  598 #define SK_RXQ1_CURADDR_LO      0x0420
  599 #define SK_RXQ1_CURADDR_HI      0x0424
  600 #define SK_RXQ1_CURCNT_LO       0x0428
  601 #define SK_RXQ1_CURCNT_HI       0x042C
  602 #define SK_RXQ1_CURBYTES        0x0430
  603 #define SK_RXQ1_BMU_CSR         0x0434
  604 #define SK_RXQ1_WATERMARK       0x0438
  605 #define SK_RXQ1_FLAG            0x043A
  606 #define SK_RXQ1_TEST1           0x043C
  607 #define SK_RXQ1_TEST2           0x0440
  608 #define SK_RXQ1_TEST3           0x0444
  609 
  610 /* Block 9 -- RX queue 2 */
  611 #define SK_RXQ2_BUFCNT          0x0480
  612 #define SK_RXQ2_BUFCTL          0x0482
  613 #define SK_RXQ2_NEXTDESC        0x0484
  614 #define SK_RXQ2_RXBUF_LO        0x0488
  615 #define SK_RXQ2_RXBUF_HI        0x048C
  616 #define SK_RXQ2_RXSTAT          0x0490
  617 #define SK_RXQ2_TIMESTAMP       0x0494
  618 #define SK_RXQ2_CSUM1           0x0498
  619 #define SK_RXQ2_CSUM2           0x049A
  620 #define SK_RXQ2_CSUM1_START     0x049C
  621 #define SK_RXQ2_CSUM2_START     0x049E
  622 #define SK_RXQ2_CURADDR_LO      0x04A0
  623 #define SK_RXQ2_CURADDR_HI      0x04A4
  624 #define SK_RXQ2_CURCNT_LO       0x04A8
  625 #define SK_RXQ2_CURCNT_HI       0x04AC
  626 #define SK_RXQ2_CURBYTES        0x04B0
  627 #define SK_RXQ2_BMU_CSR         0x04B4
  628 #define SK_RXQ2_WATERMARK       0x04B8
  629 #define SK_RXQ2_FLAG            0x04BA
  630 #define SK_RXQ2_TEST1           0x04BC
  631 #define SK_RXQ2_TEST2           0x04C0
  632 #define SK_RXQ2_TEST3           0x04C4
  633 
  634 #define SK_RXBMU_CLR_IRQ_ERR            0x00000001
  635 #define SK_RXBMU_CLR_IRQ_EOF            0x00000002
  636 #define SK_RXBMU_CLR_IRQ_EOB            0x00000004
  637 #define SK_RXBMU_CLR_IRQ_PAR            0x00000008
  638 #define SK_RXBMU_RX_START               0x00000010
  639 #define SK_RXBMU_RX_STOP                0x00000020
  640 #define SK_RXBMU_POLL_OFF               0x00000040
  641 #define SK_RXBMU_POLL_ON                0x00000080
  642 #define SK_RXBMU_TRANSFER_SM_RESET      0x00000100
  643 #define SK_RXBMU_TRANSFER_SM_UNRESET    0x00000200
  644 #define SK_RXBMU_DESCWR_SM_RESET        0x00000400
  645 #define SK_RXBMU_DESCWR_SM_UNRESET      0x00000800
  646 #define SK_RXBMU_DESCRD_SM_RESET        0x00001000
  647 #define SK_RXBMU_DESCRD_SM_UNRESET      0x00002000
  648 #define SK_RXBMU_SUPERVISOR_SM_RESET    0x00004000
  649 #define SK_RXBMU_SUPERVISOR_SM_UNRESET  0x00008000
  650 #define SK_RXBMU_PFI_SM_RESET           0x00010000
  651 #define SK_RXBMU_PFI_SM_UNRESET         0x00020000
  652 #define SK_RXBMU_FIFO_RESET             0x00040000
  653 #define SK_RXBMU_FIFO_UNRESET           0x00080000
  654 #define SK_RXBMU_DESC_RESET             0x00100000
  655 #define SK_RXBMU_DESC_UNRESET           0x00200000
  656 #define SK_RXBMU_SUPERVISOR_IDLE        0x01000000
  657 
  658 #define SK_RXBMU_ONLINE         \
  659         (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET|       \
  660         SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET|      \
  661         SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET|                  \
  662         SK_RXBMU_DESC_UNRESET)
  663 
  664 #define SK_RXBMU_OFFLINE                \
  665         (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET|   \
  666         SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET|  \
  667         SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET|              \
  668         SK_RXBMU_DESC_RESET)
  669 
  670 /* Block 12 -- TX sync queue 1 */
  671 #define SK_TXQS1_BUFCNT         0x0600
  672 #define SK_TXQS1_BUFCTL         0x0602
  673 #define SK_TXQS1_NEXTDESC       0x0604
  674 #define SK_TXQS1_RXBUF_LO       0x0608
  675 #define SK_TXQS1_RXBUF_HI       0x060C
  676 #define SK_TXQS1_RXSTAT         0x0610
  677 #define SK_TXQS1_CSUM_STARTVAL  0x0614
  678 #define SK_TXQS1_CSUM_STARTPOS  0x0618
  679 #define SK_TXQS1_CSUM_WRITEPOS  0x061A
  680 #define SK_TXQS1_CURADDR_LO     0x0620
  681 #define SK_TXQS1_CURADDR_HI     0x0624
  682 #define SK_TXQS1_CURCNT_LO      0x0628
  683 #define SK_TXQS1_CURCNT_HI      0x062C
  684 #define SK_TXQS1_CURBYTES       0x0630
  685 #define SK_TXQS1_BMU_CSR        0x0634
  686 #define SK_TXQS1_WATERMARK      0x0638
  687 #define SK_TXQS1_FLAG           0x063A
  688 #define SK_TXQS1_TEST1          0x063C
  689 #define SK_TXQS1_TEST2          0x0640
  690 #define SK_TXQS1_TEST3          0x0644
  691 
  692 /* Block 13 -- TX async queue 1 */
  693 #define SK_TXQA1_BUFCNT         0x0680
  694 #define SK_TXQA1_BUFCTL         0x0682
  695 #define SK_TXQA1_NEXTDESC       0x0684
  696 #define SK_TXQA1_RXBUF_LO       0x0688
  697 #define SK_TXQA1_RXBUF_HI       0x068C
  698 #define SK_TXQA1_RXSTAT         0x0690
  699 #define SK_TXQA1_CSUM_STARTVAL  0x0694
  700 #define SK_TXQA1_CSUM_STARTPOS  0x0698
  701 #define SK_TXQA1_CSUM_WRITEPOS  0x069A
  702 #define SK_TXQA1_CURADDR_LO     0x06A0
  703 #define SK_TXQA1_CURADDR_HI     0x06A4
  704 #define SK_TXQA1_CURCNT_LO      0x06A8
  705 #define SK_TXQA1_CURCNT_HI      0x06AC
  706 #define SK_TXQA1_CURBYTES       0x06B0
  707 #define SK_TXQA1_BMU_CSR        0x06B4
  708 #define SK_TXQA1_WATERMARK      0x06B8
  709 #define SK_TXQA1_FLAG           0x06BA
  710 #define SK_TXQA1_TEST1          0x06BC
  711 #define SK_TXQA1_TEST2          0x06C0
  712 #define SK_TXQA1_TEST3          0x06C4
  713 
  714 /* Block 14 -- TX sync queue 2 */
  715 #define SK_TXQS2_BUFCNT         0x0700
  716 #define SK_TXQS2_BUFCTL         0x0702
  717 #define SK_TXQS2_NEXTDESC       0x0704
  718 #define SK_TXQS2_RXBUF_LO       0x0708
  719 #define SK_TXQS2_RXBUF_HI       0x070C
  720 #define SK_TXQS2_RXSTAT         0x0710
  721 #define SK_TXQS2_CSUM_STARTVAL  0x0714
  722 #define SK_TXQS2_CSUM_STARTPOS  0x0718
  723 #define SK_TXQS2_CSUM_WRITEPOS  0x071A
  724 #define SK_TXQS2_CURADDR_LO     0x0720
  725 #define SK_TXQS2_CURADDR_HI     0x0724
  726 #define SK_TXQS2_CURCNT_LO      0x0728
  727 #define SK_TXQS2_CURCNT_HI      0x072C
  728 #define SK_TXQS2_CURBYTES       0x0730
  729 #define SK_TXQS2_BMU_CSR        0x0734
  730 #define SK_TXQS2_WATERMARK      0x0738
  731 #define SK_TXQS2_FLAG           0x073A
  732 #define SK_TXQS2_TEST1          0x073C
  733 #define SK_TXQS2_TEST2          0x0740
  734 #define SK_TXQS2_TEST3          0x0744
  735 
  736 /* Block 15 -- TX async queue 2 */
  737 #define SK_TXQA2_BUFCNT         0x0780
  738 #define SK_TXQA2_BUFCTL         0x0782
  739 #define SK_TXQA2_NEXTDESC       0x0784
  740 #define SK_TXQA2_RXBUF_LO       0x0788
  741 #define SK_TXQA2_RXBUF_HI       0x078C
  742 #define SK_TXQA2_RXSTAT         0x0790
  743 #define SK_TXQA2_CSUM_STARTVAL  0x0794
  744 #define SK_TXQA2_CSUM_STARTPOS  0x0798
  745 #define SK_TXQA2_CSUM_WRITEPOS  0x079A
  746 #define SK_TXQA2_CURADDR_LO     0x07A0
  747 #define SK_TXQA2_CURADDR_HI     0x07A4
  748 #define SK_TXQA2_CURCNT_LO      0x07A8
  749 #define SK_TXQA2_CURCNT_HI      0x07AC
  750 #define SK_TXQA2_CURBYTES       0x07B0
  751 #define SK_TXQA2_BMU_CSR        0x07B4
  752 #define SK_TXQA2_WATERMARK      0x07B8
  753 #define SK_TXQA2_FLAG           0x07BA
  754 #define SK_TXQA2_TEST1          0x07BC
  755 #define SK_TXQA2_TEST2          0x07C0
  756 #define SK_TXQA2_TEST3          0x07C4
  757 
  758 #define SK_TXBMU_CLR_IRQ_ERR            0x00000001
  759 #define SK_TXBMU_CLR_IRQ_EOF            0x00000002
  760 #define SK_TXBMU_CLR_IRQ_EOB            0x00000004
  761 #define SK_TXBMU_TX_START               0x00000010
  762 #define SK_TXBMU_TX_STOP                0x00000020
  763 #define SK_TXBMU_POLL_OFF               0x00000040
  764 #define SK_TXBMU_POLL_ON                0x00000080
  765 #define SK_TXBMU_TRANSFER_SM_RESET      0x00000100
  766 #define SK_TXBMU_TRANSFER_SM_UNRESET    0x00000200
  767 #define SK_TXBMU_DESCWR_SM_RESET        0x00000400
  768 #define SK_TXBMU_DESCWR_SM_UNRESET      0x00000800
  769 #define SK_TXBMU_DESCRD_SM_RESET        0x00001000
  770 #define SK_TXBMU_DESCRD_SM_UNRESET      0x00002000
  771 #define SK_TXBMU_SUPERVISOR_SM_RESET    0x00004000
  772 #define SK_TXBMU_SUPERVISOR_SM_UNRESET  0x00008000
  773 #define SK_TXBMU_PFI_SM_RESET           0x00010000
  774 #define SK_TXBMU_PFI_SM_UNRESET         0x00020000
  775 #define SK_TXBMU_FIFO_RESET             0x00040000
  776 #define SK_TXBMU_FIFO_UNRESET           0x00080000
  777 #define SK_TXBMU_DESC_RESET             0x00100000
  778 #define SK_TXBMU_DESC_UNRESET           0x00200000
  779 #define SK_TXBMU_SUPERVISOR_IDLE        0x01000000
  780 
  781 #define SK_TXBMU_ONLINE         \
  782         (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET|       \
  783         SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET|      \
  784         SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET|                  \
  785         SK_TXBMU_DESC_UNRESET)
  786 
  787 #define SK_TXBMU_OFFLINE                \
  788         (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET|   \
  789         SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET|  \
  790         SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET|              \
  791         SK_TXBMU_DESC_RESET)
  792 
  793 /* Block 16 -- Receive RAMbuffer 1 */
  794 #define SK_RXRB1_START          0x0800
  795 #define SK_RXRB1_END            0x0804
  796 #define SK_RXRB1_WR_PTR         0x0808
  797 #define SK_RXRB1_RD_PTR         0x080C
  798 #define SK_RXRB1_UTHR_PAUSE     0x0810
  799 #define SK_RXRB1_LTHR_PAUSE     0x0814
  800 #define SK_RXRB1_UTHR_HIPRIO    0x0818
  801 #define SK_RXRB1_UTHR_LOPRIO    0x081C
  802 #define SK_RXRB1_PKTCNT         0x0820
  803 #define SK_RXRB1_LVL            0x0824
  804 #define SK_RXRB1_CTLTST         0x0828
  805 
  806 /* Block 17 -- Receive RAMbuffer 2 */
  807 #define SK_RXRB2_START          0x0880
  808 #define SK_RXRB2_END            0x0884
  809 #define SK_RXRB2_WR_PTR         0x0888
  810 #define SK_RXRB2_RD_PTR         0x088C
  811 #define SK_RXRB2_UTHR_PAUSE     0x0890
  812 #define SK_RXRB2_LTHR_PAUSE     0x0894
  813 #define SK_RXRB2_UTHR_HIPRIO    0x0898
  814 #define SK_RXRB2_UTHR_LOPRIO    0x089C
  815 #define SK_RXRB2_PKTCNT         0x08A0
  816 #define SK_RXRB2_LVL            0x08A4
  817 #define SK_RXRB2_CTLTST         0x08A8
  818 
  819 /* Block 20 -- Sync. Transmit RAMbuffer 1 */
  820 #define SK_TXRBS1_START         0x0A00
  821 #define SK_TXRBS1_END           0x0A04
  822 #define SK_TXRBS1_WR_PTR        0x0A08
  823 #define SK_TXRBS1_RD_PTR        0x0A0C
  824 #define SK_TXRBS1_PKTCNT        0x0A20
  825 #define SK_TXRBS1_LVL           0x0A24
  826 #define SK_TXRBS1_CTLTST        0x0A28
  827 
  828 /* Block 21 -- Async. Transmit RAMbuffer 1 */
  829 #define SK_TXRBA1_START         0x0A80
  830 #define SK_TXRBA1_END           0x0A84
  831 #define SK_TXRBA1_WR_PTR        0x0A88
  832 #define SK_TXRBA1_RD_PTR        0x0A8C
  833 #define SK_TXRBA1_PKTCNT        0x0AA0
  834 #define SK_TXRBA1_LVL           0x0AA4
  835 #define SK_TXRBA1_CTLTST        0x0AA8
  836 
  837 /* Block 22 -- Sync. Transmit RAMbuffer 2 */
  838 #define SK_TXRBS2_START         0x0B00
  839 #define SK_TXRBS2_END           0x0B04
  840 #define SK_TXRBS2_WR_PTR        0x0B08
  841 #define SK_TXRBS2_RD_PTR        0x0B0C
  842 #define SK_TXRBS2_PKTCNT        0x0B20
  843 #define SK_TXRBS2_LVL           0x0B24
  844 #define SK_TXRBS2_CTLTST        0x0B28
  845 
  846 /* Block 23 -- Async. Transmit RAMbuffer 2 */
  847 #define SK_TXRBA2_START         0x0B80
  848 #define SK_TXRBA2_END           0x0B84
  849 #define SK_TXRBA2_WR_PTR        0x0B88
  850 #define SK_TXRBA2_RD_PTR        0x0B8C
  851 #define SK_TXRBA2_PKTCNT        0x0BA0
  852 #define SK_TXRBA2_LVL           0x0BA4
  853 #define SK_TXRBA2_CTLTST        0x0BA8
  854 
  855 #define SK_RBCTL_RESET          0x00000001
  856 #define SK_RBCTL_UNRESET        0x00000002
  857 #define SK_RBCTL_OFF            0x00000004
  858 #define SK_RBCTL_ON             0x00000008
  859 #define SK_RBCTL_STORENFWD_OFF  0x00000010
  860 #define SK_RBCTL_STORENFWD_ON   0x00000020
  861 
  862 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
  863 #define SK_RXF1_END             0x0C00
  864 #define SK_RXF1_WPTR            0x0C04
  865 #define SK_RXF1_RPTR            0x0C0C
  866 #define SK_RXF1_PKTCNT          0x0C10
  867 #define SK_RXF1_LVL             0x0C14
  868 #define SK_RXF1_MACCTL          0x0C18
  869 #define SK_RXF1_CTL             0x0C1C
  870 #define SK_RXLED1_CNTINIT       0x0C20
  871 #define SK_RXLED1_COUNTER       0x0C24
  872 #define SK_RXLED1_CTL           0x0C28
  873 #define SK_RXLED1_TST           0x0C29
  874 #define SK_LINK_SYNC1_CINIT     0x0C30
  875 #define SK_LINK_SYNC1_COUNTER   0x0C34
  876 #define SK_LINK_SYNC1_CTL       0x0C38
  877 #define SK_LINK_SYNC1_TST       0x0C39
  878 #define SK_LINKLED1_CTL         0x0C3C
  879 
  880 #define SK_FIFO_END             0x3F
  881 
  882 /* Receive MAC FIFO 1 (Yukon Only) */
  883 #define SK_RXMF1_END            0x0C40
  884 #define SK_RXMF1_THRESHOLD      0x0C44
  885 #define SK_RXMF1_CTRL_TEST      0x0C48
  886 #define SK_RXMF1_WRITE_PTR      0x0C60
  887 #define SK_RXMF1_WRITE_LEVEL    0x0C68
  888 #define SK_RXMF1_READ_PTR       0x0C70
  889 #define SK_RXMF1_READ_LEVEL     0x0C78
  890 
  891 #define SK_RFCTL_WR_PTR_TST_ON  0x00004000      /* Write pointer test on*/
  892 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000      /* Write pointer test off */
  893 #define SK_RFCTL_WR_PTR_STEP    0x00001000      /* Write pointer increment */
  894 #define SK_RFCTL_RD_PTR_TST_ON  0x00000400      /* Read pointer test on */
  895 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200      /* Read pointer test off */
  896 #define SK_RFCTL_RD_PTR_STEP    0x00000100      /* Read pointer increment */
  897 #define SK_RFCTL_RX_FIFO_OVER   0x00000040      /* Clear IRQ RX FIFO Overrun */
  898 #define SK_RFCTL_FRAME_RX_DONE  0x00000010      /* Clear IRQ Frame RX Done */
  899 #define SK_RFCTL_OPERATION_ON   0x00000008      /* Operational mode on */
  900 #define SK_RFCTL_OPERATION_OFF  0x00000004      /* Operational mode off */
  901 #define SK_RFCTL_RESET_CLEAR    0x00000002      /* MAC FIFO Reset Clear */
  902 #define SK_RFCTL_RESET_SET      0x00000001      /* MAC FIFO Reset Set */
  903 
  904 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
  905 #define SK_RXF2_END             0x0C80
  906 #define SK_RXF2_WPTR            0x0C84
  907 #define SK_RXF2_RPTR            0x0C8C
  908 #define SK_RXF2_PKTCNT          0x0C90
  909 #define SK_RXF2_LVL             0x0C94
  910 #define SK_RXF2_MACCTL          0x0C98
  911 #define SK_RXF2_CTL             0x0C9C
  912 #define SK_RXLED2_CNTINIT       0x0CA0
  913 #define SK_RXLED2_COUNTER       0x0CA4
  914 #define SK_RXLED2_CTL           0x0CA8
  915 #define SK_RXLED2_TST           0x0CA9
  916 #define SK_LINK_SYNC2_CINIT     0x0CB0
  917 #define SK_LINK_SYNC2_COUNTER   0x0CB4
  918 #define SK_LINK_SYNC2_CTL       0x0CB8
  919 #define SK_LINK_SYNC2_TST       0x0CB9
  920 #define SK_LINKLED2_CTL         0x0CBC
  921 
  922 #define SK_RXMACCTL_CLR_IRQ_NOSTS       0x00000001
  923 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP    0x00000002
  924 #define SK_RXMACCTL_TSTAMP_OFF          0x00000004
  925 #define SK_RXMACCTL_RSTAMP_ON           0x00000008
  926 #define SK_RXMACCTL_FLUSH_OFF           0x00000010
  927 #define SK_RXMACCTL_FLUSH_ON            0x00000020
  928 #define SK_RXMACCTL_PAUSE_OFF           0x00000040
  929 #define SK_RXMACCTL_PAUSE_ON            0x00000080
  930 #define SK_RXMACCTL_AFULL_OFF           0x00000100
  931 #define SK_RXMACCTL_AFULL_ON            0x00000200
  932 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400
  933 #define SK_RXMACCTL_VALIDTIME_PATCH_ON  0x00000800
  934 #define SK_RXMACCTL_RXRDY_PATCH_OFF     0x00001000
  935 #define SK_RXMACCTL_RXRDY_PATCH_ON      0x00002000
  936 #define SK_RXMACCTL_STS_TIMEO           0x00FF0000
  937 #define SK_RXMACCTL_TSTAMP_TIMEO        0xFF000000
  938 
  939 #define SK_RXLEDCTL_ENABLE              0x0001
  940 #define SK_RXLEDCTL_COUNTER_STOP        0x0002
  941 #define SK_RXLEDCTL_COUNTER_START       0x0004
  942 
  943 #define SK_LINKLED_OFF                  0x0001
  944 #define SK_LINKLED_ON                   0x0002
  945 #define SK_LINKLED_LINKSYNC_OFF         0x0004
  946 #define SK_LINKLED_LINKSYNC_ON          0x0008
  947 #define SK_LINKLED_BLINK_OFF            0x0010
  948 #define SK_LINKLED_BLINK_ON             0x0020
  949 
  950 /* Block 26 -- TX MAC FIFO 1 regisrers  */
  951 #define SK_TXF1_END             0x0D00
  952 #define SK_TXF1_WPTR            0x0D04
  953 #define SK_TXF1_RPTR            0x0D0C
  954 #define SK_TXF1_PKTCNT          0x0D10
  955 #define SK_TXF1_LVL             0x0D14
  956 #define SK_TXF1_MACCTL          0x0D18
  957 #define SK_TXF1_CTL             0x0D1C
  958 #define SK_TXLED1_CNTINIT       0x0D20
  959 #define SK_TXLED1_COUNTER       0x0D24
  960 #define SK_TXLED1_CTL           0x0D28
  961 #define SK_TXLED1_TST           0x0D29
  962 
  963 /* Receive MAC FIFO 1 (Yukon Only) */
  964 #define SK_TXMF1_END            0x0D40
  965 #define SK_TXMF1_THRESHOLD      0x0D44
  966 #define SK_TXMF1_CTRL_TEST      0x0D48
  967 #define SK_TXMF1_WRITE_PTR      0x0D60
  968 #define SK_TXMF1_WRITE_SHADOW   0x0D64
  969 #define SK_TXMF1_WRITE_LEVEL    0x0D68
  970 #define SK_TXMF1_READ_PTR       0x0D70
  971 #define SK_TXMF1_RESTART_PTR    0x0D74
  972 #define SK_TXMF1_READ_LEVEL     0x0D78
  973 
  974 #define SK_TFCTL_WR_PTR_TST_ON  0x00004000      /* Write pointer test on*/
  975 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000      /* Write pointer test off */
  976 #define SK_TFCTL_WR_PTR_STEP    0x00001000      /* Write pointer increment */
  977 #define SK_TFCTL_RD_PTR_TST_ON  0x00000400      /* Read pointer test on */
  978 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200      /* Read pointer test off */
  979 #define SK_TFCTL_RD_PTR_STEP    0x00000100      /* Read pointer increment */
  980 #define SK_TFCTL_TX_FIFO_UNDER  0x00000040      /* Clear IRQ TX FIFO Under */
  981 #define SK_TFCTL_FRAME_TX_DONE  0x00000020      /* Clear IRQ Frame TX Done */
  982 #define SK_TFCTL_IRQ_PARITY_ER  0x00000010      /* Clear IRQ Parity Error */
  983 #define SK_TFCTL_OPERATION_ON   0x00000008      /* Operational mode on */
  984 #define SK_TFCTL_OPERATION_OFF  0x00000004      /* Operational mode off */
  985 #define SK_TFCTL_RESET_CLEAR    0x00000002      /* MAC FIFO Reset Clear */
  986 #define SK_TFCTL_RESET_SET      0x00000001      /* MAC FIFO Reset Set */
  987 
  988 /* Block 27 -- TX MAC FIFO 2 regisrers  */
  989 #define SK_TXF2_END             0x0D80
  990 #define SK_TXF2_WPTR            0x0D84
  991 #define SK_TXF2_RPTR            0x0D8C
  992 #define SK_TXF2_PKTCNT          0x0D90
  993 #define SK_TXF2_LVL             0x0D94
  994 #define SK_TXF2_MACCTL          0x0D98
  995 #define SK_TXF2_CTL             0x0D9C
  996 #define SK_TXLED2_CNTINIT       0x0DA0
  997 #define SK_TXLED2_COUNTER       0x0DA4
  998 #define SK_TXLED2_CTL           0x0DA8
  999 #define SK_TXLED2_TST           0x0DA9
 1000 
 1001 #define SK_TXMACCTL_XMAC_RESET          0x00000001
 1002 #define SK_TXMACCTL_XMAC_UNRESET        0x00000002
 1003 #define SK_TXMACCTL_LOOP_OFF            0x00000004
 1004 #define SK_TXMACCTL_LOOP_ON             0x00000008
 1005 #define SK_TXMACCTL_FLUSH_OFF           0x00000010
 1006 #define SK_TXMACCTL_FLUSH_ON            0x00000020
 1007 #define SK_TXMACCTL_WAITEMPTY_OFF       0x00000040
 1008 #define SK_TXMACCTL_WAITEMPTY_ON        0x00000080
 1009 #define SK_TXMACCTL_AFULL_OFF           0x00000100
 1010 #define SK_TXMACCTL_AFULL_ON            0x00000200
 1011 #define SK_TXMACCTL_TXRDY_PATCH_OFF     0x00000400
 1012 #define SK_TXMACCTL_RXRDY_PATCH_ON      0x00000800
 1013 #define SK_TXMACCTL_PKT_RECOVERY_OFF    0x00001000
 1014 #define SK_TXMACCTL_PKT_RECOVERY_ON     0x00002000
 1015 #define SK_TXMACCTL_CLR_IRQ_PERR        0x00008000
 1016 #define SK_TXMACCTL_WAITAFTERFLUSH      0x00010000
 1017 
 1018 #define SK_TXLEDCTL_ENABLE              0x0001
 1019 #define SK_TXLEDCTL_COUNTER_STOP        0x0002
 1020 #define SK_TXLEDCTL_COUNTER_START       0x0004
 1021 
 1022 #define SK_FIFO_RESET           0x00000001
 1023 #define SK_FIFO_UNRESET         0x00000002
 1024 #define SK_FIFO_OFF             0x00000004
 1025 #define SK_FIFO_ON              0x00000008
 1026 
 1027 /* Block 28 -- Descriptor Poll Timer */
 1028 #define SK_DPT_INIT             0x0e00  /* Initial value 24 bits */
 1029 #define SK_DPT_TIMER            0x0e04  /* Mul of 78.12MHz clk (24b) */
 1030 
 1031 #define SK_DPT_TIMER_CTRL       0x0e08  /* Timer Control 16 bits */
 1032 #define SK_DPT_TCTL_STOP        0x0001  /* Stop Timer */
 1033 #define SK_DPT_TCTL_START       0x0002  /* Start Timer */
 1034 
 1035 #define SK_DPT_TIMER_TEST       0x0e0a  /* Timer Test 16 bits */
 1036 #define SK_DPT_TTEST_STEP       0x0001  /* Timer Decrement */
 1037 #define SK_DPT_TTEST_OFF        0x0002  /* Test Mode Off */
 1038 #define SK_DPT_TTEST_ON         0x0004  /* Test Mode On */
 1039 
 1040 /* Block 29 -- reserved */
 1041 
 1042 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/
 1043 #define SK_GMAC_CTRL            0x0f00  /* GMAC Control Register */
 1044 #define SK_GPHY_CTRL            0x0f04  /* GPHY Control Register */
 1045 #define SK_GMAC_ISR             0x0f08  /* GMAC Interrupt Source Register */
 1046 #define SK_GMAC_IMR             0x0f08  /* GMAC Interrupt Mask Register */
 1047 #define SK_LINK_CTRL            0x0f10  /* Link Control Register (LCR) */
 1048 #define SK_WOL_CTRL             0x0f20  /* Wake on LAN Control Register */
 1049 #define SK_MAC_ADDR_LOW         0x0f24  /* Mack Address Registers LOW */
 1050 #define SK_MAC_ADDR_HIGH        0x0f28  /* Mack Address Registers HIGH */
 1051 #define SK_PAT_READ_PTR         0x0f2c  /* Pattern Read Pointer Register */
 1052 #define SK_PAT_LEN_REG0         0x0f30  /* Pattern Length Register 0 */
 1053 #define SK_PAT_LEN0             0x0f30  /* Pattern Length 0 */
 1054 #define SK_PAT_LEN1             0x0f31  /* Pattern Length 1 */
 1055 #define SK_PAT_LEN2             0x0f32  /* Pattern Length 2 */
 1056 #define SK_PAT_LEN3             0x0f33  /* Pattern Length 3 */
 1057 #define SK_PAT_LEN_REG1         0x0f34  /* Pattern Length Register 1 */
 1058 #define SK_PAT_LEN4             0x0f34  /* Pattern Length 4 */
 1059 #define SK_PAT_LEN5             0x0f35  /* Pattern Length 5 */
 1060 #define SK_PAT_LEN6             0x0f36  /* Pattern Length 6 */
 1061 #define SK_PAT_LEN7             0x0f37  /* Pattern Length 7 */
 1062 #define SK_PAT_CTR_REG0         0x0f38  /* Pattern Counter Register 0 */
 1063 #define SK_PAT_CTR0             0x0f38  /* Pattern Counter 0 */
 1064 #define SK_PAT_CTR1             0x0f39  /* Pattern Counter 1 */
 1065 #define SK_PAT_CTR2             0x0f3a  /* Pattern Counter 2 */
 1066 #define SK_PAT_CTR3             0x0f3b  /* Pattern Counter 3 */
 1067 #define SK_PAT_CTR_REG1         0x0f3c  /* Pattern Counter Register 1 */
 1068 #define SK_PAT_CTR4             0x0f3c  /* Pattern Counter 4 */
 1069 #define SK_PAT_CTR5             0x0f3d  /* Pattern Counter 5 */
 1070 #define SK_PAT_CTR6             0x0f3e  /* Pattern Counter 6 */
 1071 #define SK_PAT_CTR7             0x0f3f  /* Pattern Counter 7 */
 1072 
 1073 #define SK_GMAC_LOOP_ON         0x00000020      /* Loopback mode for testing */
 1074 #define SK_GMAC_LOOP_OFF        0x00000010      /* purposes */
 1075 #define SK_GMAC_PAUSE_ON        0x00000008      /* enable forward of pause */
 1076 #define SK_GMAC_PAUSE_OFF       0x00000004      /* signal to GMAC */
 1077 #define SK_GMAC_RESET_CLEAR     0x00000002      /* Clear GMAC Reset */
 1078 #define SK_GMAC_RESET_SET       0x00000001      /* Set GMAC Reset */
 1079 
 1080 #define SK_GPHY_SEL_BDT         0x10000000      /* Select Bidirectional xfer */
 1081 #define SK_GPHY_INT_POL_HI      0x08000000      /* IRQ Polarity Active */
 1082 #define SK_GPHY_75_OHM          0x04000000      /* Use 75 Ohm Termination */
 1083 #define SK_GPHY_DIS_FC          0x02000000      /* Disable Auto Fiber/Copper */
 1084 #define SK_GPHY_DIS_SLEEP       0x01000000      /* Disable Energy Detect */
 1085 #define SK_GPHY_HWCFG_M_3       0x00800000      /* HWCFG_MODE[3] */
 1086 #define SK_GPHY_HWCFG_M_2       0x00400000      /* HWCFG_MODE[2] */
 1087 #define SK_GPHY_HWCFG_M_1       0x00200000      /* HWCFG_MODE[1] */
 1088 #define SK_GPHY_HWCFG_M_0       0x00100000      /* HWCFG_MODE[0] */
 1089 #define SK_GPHY_ANEG_0          0x00080000      /* ANEG[0] */
 1090 #define SK_GPHY_ENA_XC          0x00040000      /* Enable MDI Crossover */
 1091 #define SK_GPHY_DIS_125         0x00020000      /* Disable 125MHz Clock */
 1092 #define SK_GPHY_ANEG_3          0x00010000      /* ANEG[3] */
 1093 #define SK_GPHY_ANEG_2          0x00008000      /* ANEG[2] */
 1094 #define SK_GPHY_ANEG_1          0x00004000      /* ANEG[1] */
 1095 #define SK_GPHY_ENA_PAUSE       0x00002000      /* Enable Pause */
 1096 #define SK_GPHY_PHYADDR_4       0x00001000      /* Bit 4 of Phy Addr */
 1097 #define SK_GPHY_PHYADDR_3       0x00000800      /* Bit 3 of Phy Addr */
 1098 #define SK_GPHY_PHYADDR_2       0x00000400      /* Bit 2 of Phy Addr */
 1099 #define SK_GPHY_PHYADDR_1       0x00000200      /* Bit 1 of Phy Addr */
 1100 #define SK_GPHY_PHYADDR_0       0x00000100      /* Bit 0 of Phy Addr */
 1101 #define SK_GPHY_RESET_CLEAR     0x00000002      /* Clear GPHY Reset */
 1102 #define SK_GPHY_RESET_SET       0x00000001      /* Set GPHY Reset */
 1103 
 1104 #define SK_GPHY_COPPER          (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
 1105                                  SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 )
 1106 #define SK_GPHY_FIBER           (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
 1107                                  SK_GPHY_HWCFG_M_2 )
 1108 #define SK_GPHY_ANEG_ALL        (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \
 1109                                  SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 )
 1110 
 1111 #define SK_GMAC_INT_TX_OFLOW    0x20    /* Transmit Counter Overflow */
 1112 #define SK_GMAC_INT_RX_OFLOW    0x10    /* Receiver Overflow */
 1113 #define SK_GMAC_INT_TX_UNDER    0x08    /* Transmit FIFO Underrun */
 1114 #define SK_GMAC_INT_TX_DONE     0x04    /* Transmit Complete */
 1115 #define SK_GMAC_INT_RX_OVER     0x02    /* Receive FIFO Overrun */
 1116 #define SK_GMAC_INT_RX_DONE     0x01    /* Receive Complete */
 1117 
 1118 #define SK_LINK_RESET_CLEAR     0x0002  /* Link Reset Clear */
 1119 #define SK_LINK_RESET_SET       0x0001  /* Link Reset Set */
 1120 
 1121 /* Block 31 -- reserved */
 1122 
 1123 /* Block 32-33 -- Pattern Ram */
 1124 #define SK_WOL_PRAM             0x1000
 1125 
 1126 /* Block 0x22 - 0x3f -- reserved */
 1127 
 1128 /* Block 0x40 to 0x4F -- XMAC 1 registers */
 1129 #define SK_XMAC1_BASE   0x2000
 1130 
 1131 /* Block 0x50 to 0x5F -- MARV 1 registers */
 1132 #define SK_MARV1_BASE   0x2800
 1133 
 1134 /* Block 0x60 to 0x6F -- XMAC 2 registers */
 1135 #define SK_XMAC2_BASE   0x3000
 1136 
 1137 /* Block 0x70 to 0x7F -- MARV 2 registers */
 1138 #define SK_MARV2_BASE   0x3800
 1139 
 1140 /* Compute relative offset of an XMAC register in the XMAC window(s). */
 1141 #define SK_XMAC_REG(sc, reg)    (((reg) * 2) + SK_XMAC1_BASE +          \
 1142         (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE)))
 1143 
 1144 #if 0
 1145 #define SK_XM_READ_4(sc, reg)                                           \
 1146         ((sk_win_read_2(sc->sk_softc,                                   \
 1147         SK_XMAC_REG(sc, reg)) & 0xFFFF) |                               \
 1148         ((sk_win_read_2(sc->sk_softc,                                   \
 1149         SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))
 1150 
 1151 #define SK_XM_WRITE_4(sc, reg, val)                                     \
 1152         sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg),              \
 1153         ((val) & 0xFFFF));                                              \
 1154         sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2),          \
 1155         ((val) >> 16) & 0xFFFF)
 1156 #else
 1157 #define SK_XM_READ_4(sc, reg)           \
 1158         sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))
 1159 
 1160 #define SK_XM_WRITE_4(sc, reg, val)     \
 1161         sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))
 1162 #endif
 1163 
 1164 #define SK_XM_READ_2(sc, reg)           \
 1165         sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))
 1166 
 1167 #define SK_XM_WRITE_2(sc, reg, val)     \
 1168         sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)
 1169 
 1170 #define SK_XM_SETBIT_4(sc, reg, x)      \
 1171         SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))
 1172 
 1173 #define SK_XM_CLRBIT_4(sc, reg, x)      \
 1174         SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))
 1175 
 1176 #define SK_XM_SETBIT_2(sc, reg, x)      \
 1177         SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))
 1178 
 1179 #define SK_XM_CLRBIT_2(sc, reg, x)      \
 1180         SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))
 1181 
 1182 /* Compute relative offset of an MARV register in the MARV window(s). */
 1183 #define SK_YU_REG(sc, reg) \
 1184         ((reg) + SK_MARV1_BASE + \
 1185         (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE)))
 1186 
 1187 #define SK_YU_READ_4(sc, reg)           \
 1188         sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))
 1189 
 1190 #define SK_YU_READ_2(sc, reg)           \
 1191         sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))
 1192 
 1193 #define SK_YU_WRITE_4(sc, reg, val)     \
 1194         sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
 1195 
 1196 #define SK_YU_WRITE_2(sc, reg, val)     \
 1197         sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
 1198 
 1199 #define SK_YU_SETBIT_4(sc, reg, x)      \
 1200         SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))
 1201 
 1202 #define SK_YU_CLRBIT_4(sc, reg, x)      \
 1203         SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))
 1204 
 1205 #define SK_YU_SETBIT_2(sc, reg, x)      \
 1206         SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))
 1207 
 1208 #define SK_YU_CLRBIT_2(sc, reg, x)      \
 1209         SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))
 1210 
 1211 /*
 1212  * The default FIFO threshold on the XMAC II is 4 bytes. On
 1213  * dual port NICs, this often leads to transmit underruns, so we
 1214  * bump the threshold a little.
 1215  */
 1216 #define SK_XM_TX_FIFOTHRESH     512
 1217 
 1218 #define SK_PCI_VENDOR_ID        0x0000
 1219 #define SK_PCI_DEVICE_ID        0x0002
 1220 #define SK_PCI_COMMAND          0x0004
 1221 #define SK_PCI_STATUS           0x0006
 1222 #define SK_PCI_REVID            0x0008
 1223 #define SK_PCI_CLASSCODE        0x0009
 1224 #define SK_PCI_CACHELEN         0x000C
 1225 #define SK_PCI_LATENCY_TIMER    0x000D
 1226 #define SK_PCI_HEADER_TYPE      0x000E
 1227 #define SK_PCI_LOMEM            0x0010
 1228 #define SK_PCI_LOIO             0x0014
 1229 #define SK_PCI_SUBVEN_ID        0x002C
 1230 #define SK_PCI_SYBSYS_ID        0x002E
 1231 #define SK_PCI_BIOSROM          0x0030
 1232 #define SK_PCI_INTLINE          0x003C
 1233 #define SK_PCI_INTPIN           0x003D
 1234 #define SK_PCI_MINGNT           0x003E
 1235 #define SK_PCI_MINLAT           0x003F
 1236 
 1237 /* device specific PCI registers */
 1238 #define SK_PCI_OURREG1          0x0040
 1239 #define SK_PCI_OURREG2          0x0044
 1240 #define SK_PCI_CAPID            0x0048 /* 8 bits */
 1241 #define SK_PCI_NEXTPTR          0x0049 /* 8 bits */
 1242 #define SK_PCI_PWRMGMTCAP       0x004A /* 16 bits */
 1243 #define SK_PCI_PWRMGMTCTRL      0x004C /* 16 bits */
 1244 #define SK_PCI_PME_EVENT        0x004F
 1245 #define SK_PCI_VPD_CAPID        0x0050
 1246 #define SK_PCI_VPD_NEXTPTR      0x0051
 1247 #define SK_PCI_VPD_ADDR         0x0052
 1248 #define SK_PCI_VPD_DATA         0x0054
 1249 
 1250 #define SK_PSTATE_MASK          0x0003
 1251 #define SK_PSTATE_D0            0x0000
 1252 #define SK_PSTATE_D1            0x0001
 1253 #define SK_PSTATE_D2            0x0002
 1254 #define SK_PSTATE_D3            0x0003
 1255 #define SK_PME_EN               0x0010
 1256 #define SK_PME_STATUS           0x8000
 1257 
 1258 /*
 1259  * VPD flag bit. Set to 0 to initiate a read, will become 1 when
 1260  * read is complete. Set to 1 to initiate a write, will become 0
 1261  * when write is finished.
 1262  */
 1263 #define SK_VPD_FLAG             0x8000
 1264 
 1265 /* VPD structures */
 1266 struct vpd_res {
 1267         u_int8_t                vr_id;
 1268         u_int8_t                vr_len;
 1269         u_int8_t                vr_pad;
 1270 };
 1271 
 1272 struct vpd_key {
 1273         char                    vk_key[2];
 1274         u_int8_t                vk_len;
 1275 };
 1276 
 1277 #define VPD_RES_ID      0x82    /* ID string */
 1278 #define VPD_RES_READ    0x90    /* start of read only area */
 1279 #define VPD_RES_WRITE   0x81    /* start of read/write area */
 1280 #define VPD_RES_END     0x78    /* end tag */
 1281 
 1282 #define CSR_WRITE_4(sc, reg, val)       \
 1283         bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
 1284 #define CSR_WRITE_2(sc, reg, val)       \
 1285         bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
 1286 #define CSR_WRITE_1(sc, reg, val)       \
 1287         bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
 1288 
 1289 #define CSR_READ_4(sc, reg)             \
 1290         bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg))
 1291 #define CSR_READ_2(sc, reg)             \
 1292         bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg))
 1293 #define CSR_READ_1(sc, reg)             \
 1294         bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg))
 1295 
 1296 struct sk_type {
 1297         u_int16_t               sk_vid;
 1298         u_int16_t               sk_did;
 1299         char                    *sk_name;
 1300 };
 1301 
 1302 /* RX queue descriptor data structure */
 1303 struct sk_rx_desc {
 1304         u_int32_t               sk_ctl;
 1305         u_int32_t               sk_next;
 1306         u_int32_t               sk_data_lo;
 1307         u_int32_t               sk_data_hi;
 1308         u_int32_t               sk_xmac_rxstat;
 1309         u_int32_t               sk_timestamp;
 1310         u_int16_t               sk_csum2;
 1311         u_int16_t               sk_csum1;
 1312         u_int16_t               sk_csum2_start;
 1313         u_int16_t               sk_csum1_start;
 1314 };
 1315 
 1316 #define SK_OPCODE_DEFAULT       0x00550000
 1317 #define SK_OPCODE_CSUM          0x00560000
 1318 
 1319 #define SK_RXCTL_LEN            0x0000FFFF
 1320 #define SK_RXCTL_OPCODE         0x00FF0000
 1321 #define SK_RXCTL_TSTAMP_VALID   0x01000000
 1322 #define SK_RXCTL_STATUS_VALID   0x02000000
 1323 #define SK_RXCTL_DEV0           0x04000000
 1324 #define SK_RXCTL_EOF_INTR       0x08000000
 1325 #define SK_RXCTL_EOB_INTR       0x10000000
 1326 #define SK_RXCTL_LASTFRAG       0x20000000
 1327 #define SK_RXCTL_FIRSTFRAG      0x40000000
 1328 #define SK_RXCTL_OWN            0x80000000
 1329 
 1330 #define SK_RXSTAT       \
 1331         (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \
 1332          SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
 1333 
 1334 struct sk_tx_desc {
 1335         u_int32_t               sk_ctl;
 1336         u_int32_t               sk_next;
 1337         u_int32_t               sk_data_lo;
 1338         u_int32_t               sk_data_hi;
 1339         u_int32_t               sk_xmac_txstat;
 1340         u_int16_t               sk_rsvd0;
 1341         u_int16_t               sk_csum_startval;
 1342         u_int16_t               sk_csum_startpos;
 1343         u_int16_t               sk_csum_writepos;
 1344         u_int32_t               sk_rsvd1;
 1345 };
 1346 
 1347 #define SK_TXCTL_LEN            0x0000FFFF
 1348 #define SK_TXCTL_OPCODE         0x00FF0000
 1349 #define SK_TXCTL_SW             0x01000000
 1350 #define SK_TXCTL_NOCRC          0x02000000
 1351 #define SK_TXCTL_STORENFWD      0x04000000
 1352 #define SK_TXCTL_EOF_INTR       0x08000000
 1353 #define SK_TXCTL_EOB_INTR       0x10000000
 1354 #define SK_TXCTL_LASTFRAG       0x20000000
 1355 #define SK_TXCTL_FIRSTFRAG      0x40000000
 1356 #define SK_TXCTL_OWN            0x80000000
 1357 
 1358 #define SK_TXSTAT       \
 1359         (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
 1360 
 1361 #define SK_RXBYTES(x)           (x) & 0x0000FFFF;
 1362 #define SK_TXBYTES              SK_RXBYTES
 1363 
 1364 #define SK_TX_RING_CNT          512
 1365 #define SK_RX_RING_CNT          256
 1366 
 1367 /*
 1368  * Jumbo buffer stuff. Note that we must allocate more jumbo
 1369  * buffers than there are descriptors in the receive ring. This
 1370  * is because we don't know how long it will take for a packet
 1371  * to be released after we hand it off to the upper protocol
 1372  * layers. To be safe, we allocate 1.5 times the number of
 1373  * receive descriptors.
 1374  */
 1375 #define SK_JUMBO_FRAMELEN       9018
 1376 #define SK_JUMBO_MTU            (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
 1377 #define SK_JSLOTS               ((SK_RX_RING_CNT * 3) / 2)
 1378 
 1379 #define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN)
 1380 #define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \
 1381         (SK_JRAWLEN % sizeof(u_int64_t))))
 1382 #define SK_JPAGESZ PAGE_SIZE
 1383 #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ)
 1384 #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID)
 1385 
 1386 struct sk_jpool_entry {
 1387         int                             slot;
 1388         SLIST_ENTRY(sk_jpool_entry)     jpool_entries;
 1389 };
 1390 
 1391 struct sk_chain {
 1392         void                    *sk_desc;
 1393         struct mbuf             *sk_mbuf;
 1394         struct sk_chain         *sk_next;
 1395 };
 1396 
 1397 struct sk_chain_data {
 1398         struct sk_chain         sk_tx_chain[SK_TX_RING_CNT];
 1399         struct sk_chain         sk_rx_chain[SK_RX_RING_CNT];
 1400         int                     sk_tx_prod;
 1401         int                     sk_tx_cons;
 1402         int                     sk_tx_cnt;
 1403         int                     sk_rx_prod;
 1404         int                     sk_rx_cons;
 1405         int                     sk_rx_cnt;
 1406         /* Stick the jumbo mem management stuff here too. */
 1407         caddr_t                 sk_jslots[SK_JSLOTS];
 1408         void                    *sk_jumbo_buf;
 1409 
 1410 };
 1411 
 1412 struct sk_ring_data {
 1413         struct sk_tx_desc       sk_tx_ring[SK_TX_RING_CNT];
 1414         struct sk_rx_desc       sk_rx_ring[SK_RX_RING_CNT];
 1415 };
 1416 
 1417 struct sk_bcom_hack {
 1418         int                     reg;
 1419         int                     val;
 1420 };
 1421 
 1422 #define SK_INC(x, y)    (x) = (x + 1) % y
 1423 
 1424 /* Forward decl. */
 1425 struct sk_if_softc;
 1426 
 1427 /* Softc for the GEnesis controller. */
 1428 struct sk_softc {
 1429         bus_space_handle_t      sk_bhandle;     /* bus space handle */
 1430         bus_space_tag_t         sk_btag;        /* bus space tag */
 1431         void                    *sk_intrhand;   /* irq handler handle */
 1432         struct resource         *sk_irq;        /* IRQ resource handle */
 1433         struct resource         *sk_res;        /* I/O or shared mem handle */
 1434         u_int8_t                sk_unit;        /* controller number */
 1435         u_int8_t                sk_type;
 1436         u_int8_t                sk_rev;
 1437         u_int8_t                spare;
 1438         char                    *sk_vpd_prodname;
 1439         char                    *sk_vpd_readonly;
 1440         u_int32_t               sk_rboff;       /* RAMbuffer offset */
 1441         u_int32_t               sk_ramsize;     /* amount of RAM on NIC */
 1442         u_int32_t               sk_pmd;         /* physical media type */
 1443         u_int32_t               sk_intrmask;
 1444         struct sk_if_softc      *sk_if[2];
 1445         device_t                sk_devs[2];
 1446         struct mtx              sk_mtx;
 1447 };
 1448 
 1449 #define SK_LOCK(_sc)            mtx_lock(&(_sc)->sk_mtx)
 1450 #define SK_UNLOCK(_sc)          mtx_unlock(&(_sc)->sk_mtx)
 1451 #define SK_LOCK_ASSERT(_sc)     mtx_assert(&(_sc)->sk_mtx, MA_OWNED)
 1452 #define SK_IF_LOCK(_sc)         SK_LOCK((_sc)->sk_softc)
 1453 #define SK_IF_UNLOCK(_sc)       SK_UNLOCK((_sc)->sk_softc)
 1454 #define SK_IF_LOCK_ASSERT(_sc)  SK_LOCK_ASSERT((_sc)->sk_softc)
 1455 
 1456 /* Softc for each logical interface */
 1457 struct sk_if_softc {
 1458         struct arpcom           arpcom;         /* interface info */
 1459         device_t                sk_miibus;
 1460         u_int8_t                sk_unit;        /* interface number */
 1461         u_int8_t                sk_port;        /* port # on controller */
 1462         u_int8_t                sk_xmac_rev;    /* XMAC chip rev (B2 or C1) */
 1463         u_int32_t               sk_rx_ramstart;
 1464         u_int32_t               sk_rx_ramend;
 1465         u_int32_t               sk_tx_ramstart;
 1466         u_int32_t               sk_tx_ramend;
 1467         int                     sk_phytype;
 1468         int                     sk_phyaddr;
 1469         device_t                sk_dev;
 1470         int                     sk_cnt;
 1471         int                     sk_link;
 1472         struct callout_handle   sk_tick_ch;
 1473         struct sk_chain_data    sk_cdata;
 1474         struct sk_ring_data     *sk_rdata;
 1475         struct sk_softc         *sk_softc;      /* parent controller */
 1476         int                     sk_tx_bmu;      /* TX BMU register */
 1477         int                     sk_if_flags;
 1478         SLIST_HEAD(__sk_jfreehead, sk_jpool_entry)      sk_jfree_listhead;
 1479         SLIST_HEAD(__sk_jinusehead, sk_jpool_entry)     sk_jinuse_listhead;
 1480         struct mtx              sk_jlist_mtx;
 1481 };
 1482 
 1483 #define SK_JLIST_LOCK(_sc)      mtx_lock(&(_sc)->sk_jlist_mtx)
 1484 #define SK_JLIST_UNLOCK(_sc)    mtx_unlock(&(_sc)->sk_jlist_mtx)
 1485 
 1486 #define SK_MAXUNIT      256
 1487 #define SK_TIMEOUT      1000
 1488 #define ETHER_ALIGN     2
 1489 
 1490 #ifdef __alpha__
 1491 #undef vtophys
 1492 #define vtophys(va)             alpha_XXX_dmamap((vm_offset_t)va)
 1493 #endif

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