Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_ste.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 36 #include "bpfilter.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #if NBPFILTER > 0 53 #include <net/bpf.h> 54 #endif 55 56 #include "opt_bdg.h" 57 #ifdef BRIDGE 58 #include <net/bridge.h> 59 #endif 60 61 #include <vm/vm.h> /* for vtophys */ 62 #include <vm/pmap.h> /* for vtophys */ 63 #include <machine/clock.h> /* for DELAY */ 64 #include <machine/bus_memio.h> 65 #include <machine/bus_pio.h> 66 #include <machine/bus.h> 67 68 #include <pci/pcireg.h> 69 #include <pci/pcivar.h> 70 71 #define STE_USEIOSPACE 72 73 /*#define STE_BACKGROUND_AUTONEG*/ 74 75 #include <pci/if_stereg.h> 76 77 #if !defined(lint) 78 static const char rcsid[] = 79 "$FreeBSD$"; 80 #endif 81 82 /* 83 * Various supported device vendors/types and their names. 84 */ 85 static struct ste_type ste_devs[] = { 86 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 87 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 88 { 0, 0, NULL } 89 }; 90 91 static struct ste_type ste_phys[] = { 92 { 0, 0, "<MII-compliant physical interface>" } 93 }; 94 95 static unsigned long ste_count = 0; 96 static const char *ste_probe __P((pcici_t, pcidi_t)); 97 static void ste_attach __P((pcici_t, int)); 98 static void ste_init __P((void *)); 99 static void ste_intr __P((void *)); 100 static void ste_rxeof __P((struct ste_softc *)); 101 static void ste_txeoc __P((struct ste_softc *)); 102 static void ste_txeof __P((struct ste_softc *)); 103 static void ste_stats_update __P((void *)); 104 static void ste_stop __P((struct ste_softc *)); 105 static void ste_reset __P((struct ste_softc *)); 106 static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 107 static int ste_encap __P((struct ste_softc *, struct ste_chain *, 108 struct mbuf *)); 109 static void ste_start __P((struct ifnet *)); 110 static void ste_watchdog __P((struct ifnet *)); 111 static void ste_shutdown __P((int, void *)); 112 static int ste_newbuf __P((struct ste_softc *, 113 struct ste_chain_onefrag *, 114 struct mbuf *)); 115 static int ste_ifmedia_upd __P((struct ifnet *)); 116 static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 117 118 static void ste_mii_sync __P((struct ste_softc *)); 119 static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 120 static int ste_mii_readreg __P((struct ste_softc *, struct ste_mii_frame *)); 121 static int ste_mii_writereg __P((struct ste_softc *, struct ste_mii_frame *)); 122 static u_int16_t ste_phy_readreg __P((struct ste_softc *, int)); 123 static void ste_phy_writereg __P((struct ste_softc *, int, int)); 124 125 static void ste_autoneg_xmit __P((struct ste_softc *)); 126 static void ste_autoneg_mii __P((struct ste_softc *, int, int)); 127 static void ste_setmode_mii __P((struct ste_softc *, int)); 128 static void ste_getmode_mii __P((struct ste_softc *)); 129 130 static int ste_eeprom_wait __P((struct ste_softc *)); 131 static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 132 int, int)); 133 static void ste_wait __P((struct ste_softc *)); 134 static u_int8_t ste_calchash __P((caddr_t)); 135 static void ste_setmulti __P((struct ste_softc *)); 136 static int ste_init_rx_list __P((struct ste_softc *)); 137 static void ste_init_tx_list __P((struct ste_softc *)); 138 139 #define STE_SETBIT4(sc, reg, x) \ 140 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 141 142 #define STE_CLRBIT4(sc, reg, x) \ 143 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 144 145 #define STE_SETBIT2(sc, reg, x) \ 146 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 147 148 #define STE_CLRBIT2(sc, reg, x) \ 149 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 150 151 #define STE_SETBIT1(sc, reg, x) \ 152 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 153 154 #define STE_CLRBIT1(sc, reg, x) \ 155 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 156 157 158 #ifdef __i386__ 159 #define STE_BUS_SPACE_IO I386_BUS_SPACE_IO 160 #define STE_BUS_SPACE_MEM I386_BUS_SPACE_MEM 161 #endif 162 #ifdef __alpha__ 163 #define STE_BUS_SPACE_IO ALPHA_BUS_SPACE_IO 164 #define STE_BUS_SPACE_MEM ALPHA_BUS_SPACE_MEM 165 #endif 166 167 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 168 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 169 170 /* 171 * Sync the PHYs by setting data bit and strobing the clock 32 times. 172 */ 173 static void ste_mii_sync(sc) 174 struct ste_softc *sc; 175 { 176 register int i; 177 178 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 179 180 for (i = 0; i < 32; i++) { 181 MII_SET(STE_PHYCTL_MCLK); 182 DELAY(1); 183 MII_CLR(STE_PHYCTL_MCLK); 184 DELAY(1); 185 } 186 187 return; 188 } 189 190 /* 191 * Clock a series of bits through the MII. 192 */ 193 static void ste_mii_send(sc, bits, cnt) 194 struct ste_softc *sc; 195 u_int32_t bits; 196 int cnt; 197 { 198 int i; 199 200 MII_CLR(STE_PHYCTL_MCLK); 201 202 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 203 if (bits & i) { 204 MII_SET(STE_PHYCTL_MDATA); 205 } else { 206 MII_CLR(STE_PHYCTL_MDATA); 207 } 208 DELAY(1); 209 MII_CLR(STE_PHYCTL_MCLK); 210 DELAY(1); 211 MII_SET(STE_PHYCTL_MCLK); 212 } 213 } 214 215 /* 216 * Read an PHY register through the MII. 217 */ 218 static int ste_mii_readreg(sc, frame) 219 struct ste_softc *sc; 220 struct ste_mii_frame *frame; 221 222 { 223 int i, ack, s; 224 225 s = splimp(); 226 227 /* 228 * Set up frame for RX. 229 */ 230 frame->mii_stdelim = STE_MII_STARTDELIM; 231 frame->mii_opcode = STE_MII_READOP; 232 frame->mii_turnaround = 0; 233 frame->mii_data = 0; 234 235 CSR_WRITE_2(sc, STE_PHYCTL, 0); 236 /* 237 * Turn on data xmit. 238 */ 239 MII_SET(STE_PHYCTL_MDIR); 240 241 ste_mii_sync(sc); 242 243 /* 244 * Send command/address info. 245 */ 246 ste_mii_send(sc, frame->mii_stdelim, 2); 247 ste_mii_send(sc, frame->mii_opcode, 2); 248 ste_mii_send(sc, frame->mii_phyaddr, 5); 249 ste_mii_send(sc, frame->mii_regaddr, 5); 250 251 /* Turn off xmit. */ 252 MII_CLR(STE_PHYCTL_MDIR); 253 254 /* Idle bit */ 255 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 256 DELAY(1); 257 MII_SET(STE_PHYCTL_MCLK); 258 DELAY(1); 259 260 /* Check for ack */ 261 MII_CLR(STE_PHYCTL_MCLK); 262 DELAY(1); 263 MII_SET(STE_PHYCTL_MCLK); 264 DELAY(1); 265 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 266 267 /* 268 * Now try reading data bits. If the ack failed, we still 269 * need to clock through 16 cycles to keep the PHY(s) in sync. 270 */ 271 if (ack) { 272 for(i = 0; i < 16; i++) { 273 MII_CLR(STE_PHYCTL_MCLK); 274 DELAY(1); 275 MII_SET(STE_PHYCTL_MCLK); 276 DELAY(1); 277 } 278 goto fail; 279 } 280 281 for (i = 0x8000; i; i >>= 1) { 282 MII_CLR(STE_PHYCTL_MCLK); 283 DELAY(1); 284 if (!ack) { 285 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 286 frame->mii_data |= i; 287 DELAY(1); 288 } 289 MII_SET(STE_PHYCTL_MCLK); 290 DELAY(1); 291 } 292 293 fail: 294 295 MII_CLR(STE_PHYCTL_MCLK); 296 DELAY(1); 297 MII_SET(STE_PHYCTL_MCLK); 298 DELAY(1); 299 300 splx(s); 301 302 if (ack) 303 return(1); 304 return(0); 305 } 306 307 /* 308 * Write to a PHY register through the MII. 309 */ 310 static int ste_mii_writereg(sc, frame) 311 struct ste_softc *sc; 312 struct ste_mii_frame *frame; 313 314 { 315 int s; 316 317 s = splimp(); 318 /* 319 * Set up frame for TX. 320 */ 321 322 frame->mii_stdelim = STE_MII_STARTDELIM; 323 frame->mii_opcode = STE_MII_WRITEOP; 324 frame->mii_turnaround = STE_MII_TURNAROUND; 325 326 /* 327 * Turn on data output. 328 */ 329 MII_SET(STE_PHYCTL_MDIR); 330 331 ste_mii_sync(sc); 332 333 ste_mii_send(sc, frame->mii_stdelim, 2); 334 ste_mii_send(sc, frame->mii_opcode, 2); 335 ste_mii_send(sc, frame->mii_phyaddr, 5); 336 ste_mii_send(sc, frame->mii_regaddr, 5); 337 ste_mii_send(sc, frame->mii_turnaround, 2); 338 ste_mii_send(sc, frame->mii_data, 16); 339 340 /* Idle bit. */ 341 MII_SET(STE_PHYCTL_MCLK); 342 DELAY(1); 343 MII_CLR(STE_PHYCTL_MCLK); 344 DELAY(1); 345 346 /* 347 * Turn off xmit. 348 */ 349 MII_CLR(STE_PHYCTL_MDIR); 350 351 splx(s); 352 353 return(0); 354 } 355 356 static u_int16_t ste_phy_readreg(sc, reg) 357 struct ste_softc *sc; 358 int reg; 359 { 360 struct ste_mii_frame frame; 361 362 bzero((char *)&frame, sizeof(frame)); 363 364 frame.mii_phyaddr = sc->ste_phy_addr; 365 frame.mii_regaddr = reg; 366 ste_mii_readreg(sc, &frame); 367 368 return(frame.mii_data); 369 } 370 371 static void ste_phy_writereg(sc, reg, data) 372 struct ste_softc *sc; 373 int reg; 374 int data; 375 { 376 struct ste_mii_frame frame; 377 378 bzero((char *)&frame, sizeof(frame)); 379 380 frame.mii_phyaddr = sc->ste_phy_addr; 381 frame.mii_regaddr = reg; 382 frame.mii_data = data; 383 384 ste_mii_writereg(sc, &frame); 385 386 return; 387 } 388 389 390 /* 391 * Initiate an autonegotiation session. 392 */ 393 static void ste_autoneg_xmit(sc) 394 struct ste_softc *sc; 395 { 396 u_int16_t phy_sts; 397 398 ste_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 399 DELAY(500); 400 while(ste_phy_readreg(sc, STE_PHY_GENCTL) 401 & PHY_BMCR_RESET); 402 403 phy_sts = ste_phy_readreg(sc, PHY_BMCR); 404 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 405 ste_phy_writereg(sc, PHY_BMCR, phy_sts); 406 407 return; 408 } 409 410 /* 411 * Invoke autonegotiation on a PHY. Also used with the 3Com internal 412 * autoneg logic which is mapped onto the MII. 413 */ 414 static void ste_autoneg_mii(sc, flag, verbose) 415 struct ste_softc *sc; 416 int flag; 417 int verbose; 418 { 419 u_int16_t phy_sts = 0, media, advert, ability; 420 struct ifnet *ifp; 421 struct ifmedia *ifm; 422 423 ifm = &sc->ifmedia; 424 ifp = &sc->arpcom.ac_if; 425 426 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 427 428 /* 429 * The 100baseT4 PHY on the 3c905-T4 has the 'autoneg supported' 430 * bit cleared in the status register, but has the 'autoneg enabled' 431 * bit set in the control register. This is a contradiction, and 432 * I'm not sure how to handle it. If you want to force an attempt 433 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR 434 * and see what happens. 435 */ 436 #ifndef FORCE_AUTONEG_TFOUR 437 /* 438 * First, see if autoneg is supported. If not, there's 439 * no point in continuing. 440 */ 441 phy_sts = ste_phy_readreg(sc, PHY_BMSR); 442 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 443 if (verbose) 444 printf("ste%d: autonegotiation not supported\n", 445 sc->ste_unit); 446 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 447 media = ste_phy_readreg(sc, PHY_BMCR); 448 media &= ~PHY_BMCR_SPEEDSEL; 449 media &= ~PHY_BMCR_DUPLEX; 450 ste_phy_writereg(sc, PHY_BMCR, media); 451 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 452 return; 453 } 454 #endif 455 456 switch (flag) { 457 case STE_FLAG_FORCEDELAY: 458 /* 459 * XXX Never use this option anywhere but in the probe 460 * routine: making the kernel stop dead in its tracks 461 * for three whole seconds after we've gone multi-user 462 * is really bad manners. 463 */ 464 ste_autoneg_xmit(sc); 465 DELAY(5000000); 466 break; 467 case STE_FLAG_SCHEDDELAY: 468 /* 469 * Wait for the transmitter to go idle before starting 470 * an autoneg session, otherwise ste_start() may clobber 471 * our timeout, and we don't want to allow transmission 472 * during an autoneg session since that can screw it up. 473 */ 474 if (sc->ste_cdata.ste_tx_head != NULL) { 475 sc->ste_want_auto = 1; 476 return; 477 } 478 ste_autoneg_xmit(sc); 479 ifp->if_timer = 5; 480 sc->ste_autoneg = 1; 481 sc->ste_want_auto = 0; 482 return; 483 break; 484 case STE_FLAG_DELAYTIMEO: 485 ifp->if_timer = 0; 486 sc->ste_autoneg = 0; 487 break; 488 default: 489 printf("ste%d: invalid autoneg flag: %d\n", sc->ste_unit, flag); 490 return; 491 } 492 493 if (ste_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 494 if (verbose) 495 printf("ste%d: autoneg complete, ", sc->ste_unit); 496 phy_sts = ste_phy_readreg(sc, PHY_BMSR); 497 } else { 498 if (verbose) 499 printf("ste%d: autoneg not complete, ", sc->ste_unit); 500 } 501 502 media = ste_phy_readreg(sc, PHY_BMCR); 503 504 /* Link is good. Report modes and set duplex mode. */ 505 if (ste_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 506 if (verbose) 507 printf("link status good "); 508 advert = ste_phy_readreg(sc, STE_PHY_ANAR); 509 ability = ste_phy_readreg(sc, STE_PHY_LPAR); 510 511 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 512 ifm->ifm_media = IFM_ETHER|IFM_100_T4; 513 media |= PHY_BMCR_SPEEDSEL; 514 media &= ~PHY_BMCR_DUPLEX; 515 printf("(100baseT4)\n"); 516 } else if (advert & PHY_ANAR_100BTXFULL && 517 ability & PHY_ANAR_100BTXFULL) { 518 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 519 media |= PHY_BMCR_SPEEDSEL; 520 media |= PHY_BMCR_DUPLEX; 521 printf("(full-duplex, 100Mbps)\n"); 522 } else if (advert & PHY_ANAR_100BTXHALF && 523 ability & PHY_ANAR_100BTXHALF) { 524 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 525 media |= PHY_BMCR_SPEEDSEL; 526 media &= ~PHY_BMCR_DUPLEX; 527 printf("(half-duplex, 100Mbps)\n"); 528 } else if (advert & PHY_ANAR_10BTFULL && 529 ability & PHY_ANAR_10BTFULL) { 530 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 531 media &= ~PHY_BMCR_SPEEDSEL; 532 media |= PHY_BMCR_DUPLEX; 533 printf("(full-duplex, 10Mbps)\n"); 534 } else if (advert & PHY_ANAR_10BTHALF && 535 ability & PHY_ANAR_10BTHALF) { 536 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 537 media &= ~PHY_BMCR_SPEEDSEL; 538 media &= ~PHY_BMCR_DUPLEX; 539 printf("(half-duplex, 10Mbps)\n"); 540 } 541 542 /* Set ASIC's duplex mode to match the PHY. */ 543 if (media & PHY_BMCR_DUPLEX) 544 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 545 else 546 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 547 ste_phy_writereg(sc, PHY_BMCR, media); 548 } else { 549 if (verbose) 550 printf("no carrier (forcing half-duplex, 10Mbps)\n"); 551 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 552 media &= ~PHY_BMCR_SPEEDSEL; 553 media &= ~PHY_BMCR_DUPLEX; 554 ste_phy_writereg(sc, PHY_BMCR, media); 555 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 556 } 557 558 ste_init(sc); 559 560 if (sc->ste_tx_pend) { 561 sc->ste_autoneg = 0; 562 sc->ste_tx_pend = 0; 563 ste_start(ifp); 564 } 565 566 return; 567 } 568 569 static void ste_getmode_mii(sc) 570 struct ste_softc *sc; 571 { 572 u_int16_t bmsr; 573 struct ifnet *ifp; 574 575 ifp = &sc->arpcom.ac_if; 576 577 bmsr = ste_phy_readreg(sc, PHY_BMSR); 578 if (bootverbose) 579 printf("ste%d: PHY status word: %x\n", sc->ste_unit, bmsr); 580 581 /* fallback */ 582 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 583 584 if (bmsr & PHY_BMSR_10BTHALF) { 585 if (bootverbose) 586 printf("ste%d: 10Mbps half-duplex mode supported\n", 587 sc->ste_unit); 588 ifmedia_add(&sc->ifmedia, 589 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 590 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 591 } 592 593 if (bmsr & PHY_BMSR_10BTFULL) { 594 if (bootverbose) 595 printf("ste%d: 10Mbps full-duplex mode supported\n", 596 sc->ste_unit); 597 ifmedia_add(&sc->ifmedia, 598 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 599 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 600 } 601 602 if (bmsr & PHY_BMSR_100BTXHALF) { 603 if (bootverbose) 604 printf("ste%d: 100Mbps half-duplex mode supported\n", 605 sc->ste_unit); 606 ifp->if_baudrate = 100000000; 607 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 608 ifmedia_add(&sc->ifmedia, 609 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 610 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 611 } 612 613 if (bmsr & PHY_BMSR_100BTXFULL) { 614 if (bootverbose) 615 printf("ste%d: 100Mbps full-duplex mode supported\n", 616 sc->ste_unit); 617 ifp->if_baudrate = 100000000; 618 ifmedia_add(&sc->ifmedia, 619 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 620 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 621 } 622 623 /* Some also support 100BaseT4. */ 624 if (bmsr & PHY_BMSR_100BT4) { 625 if (bootverbose) 626 printf("ste%d: 100baseT4 mode supported\n", sc->ste_unit); 627 ifp->if_baudrate = 100000000; 628 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 629 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; 630 #ifdef FORCE_AUTONEG_TFOUR 631 if (bootverbose) 632 printf("ste%d: forcing on autoneg support for BT4\n", 633 sc->ste_unit); 634 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 635 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 636 #endif 637 } 638 639 if (bmsr & PHY_BMSR_CANAUTONEG) { 640 if (bootverbose) 641 printf("ste%d: autoneg supported\n", sc->ste_unit); 642 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 643 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 644 } 645 646 return; 647 } 648 649 /* 650 * Set speed and duplex mode. 651 */ 652 static void ste_setmode_mii(sc, media) 653 struct ste_softc *sc; 654 int media; 655 { 656 u_int16_t bmcr; 657 struct ifnet *ifp; 658 659 ifp = &sc->arpcom.ac_if; 660 661 /* 662 * If an autoneg session is in progress, stop it. 663 */ 664 if (sc->ste_autoneg) { 665 printf("ste%d: canceling autoneg session\n", sc->ste_unit); 666 ifp->if_timer = sc->ste_autoneg = sc->ste_want_auto = 0; 667 bmcr = ste_phy_readreg(sc, PHY_BMCR); 668 bmcr &= ~PHY_BMCR_AUTONEGENBL; 669 ste_phy_writereg(sc, PHY_BMCR, bmcr); 670 } 671 672 printf("ste%d: selecting MII, ", sc->ste_unit); 673 674 bmcr = ste_phy_readreg(sc, PHY_BMCR); 675 676 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| 677 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); 678 679 if (IFM_SUBTYPE(media) == IFM_100_T4) { 680 printf("100Mbps/T4, half-duplex\n"); 681 bmcr |= PHY_BMCR_SPEEDSEL; 682 bmcr &= ~PHY_BMCR_DUPLEX; 683 } 684 685 if (IFM_SUBTYPE(media) == IFM_100_TX) { 686 printf("100Mbps, "); 687 bmcr |= PHY_BMCR_SPEEDSEL; 688 } 689 690 if (IFM_SUBTYPE(media) == IFM_10_T) { 691 printf("10Mbps, "); 692 bmcr &= ~PHY_BMCR_SPEEDSEL; 693 } 694 695 if ((media & IFM_GMASK) == IFM_FDX) { 696 printf("full duplex\n"); 697 bmcr |= PHY_BMCR_DUPLEX; 698 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 699 } else { 700 printf("half duplex\n"); 701 bmcr &= ~PHY_BMCR_DUPLEX; 702 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 703 } 704 705 ste_phy_writereg(sc, PHY_BMCR, bmcr); 706 707 return; 708 } 709 710 static int ste_ifmedia_upd(ifp) 711 struct ifnet *ifp; 712 { 713 struct ste_softc *sc; 714 struct ifmedia *ifm; 715 716 sc = ifp->if_softc; 717 ifm = &sc->ifmedia; 718 719 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 720 return(EINVAL); 721 722 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 723 ste_autoneg_mii(sc, STE_FLAG_SCHEDDELAY, 1); 724 else 725 ste_setmode_mii(sc, ifm->ifm_media); 726 727 return(0); 728 } 729 730 static void ste_ifmedia_sts(ifp, ifmr) 731 struct ifnet *ifp; 732 struct ifmediareq *ifmr; 733 { 734 struct ste_softc *sc; 735 u_int16_t advert = 0, ability = 0; 736 737 sc = ifp->if_softc; 738 739 ifmr->ifm_active = IFM_ETHER; 740 741 if (!(ste_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 742 if (ste_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 743 ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 744 else 745 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 746 if (ste_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 747 ifmr->ifm_active |= IFM_FDX; 748 else 749 ifmr->ifm_active |= IFM_HDX; 750 return; 751 } 752 753 ability = ste_phy_readreg(sc, STE_PHY_LPAR); 754 advert = ste_phy_readreg(sc, STE_PHY_ANAR); 755 if (advert & PHY_ANAR_100BT4 && 756 ability & PHY_ANAR_100BT4) { 757 ifmr->ifm_active = IFM_ETHER|IFM_100_T4; 758 } else if (advert & PHY_ANAR_100BTXFULL && 759 ability & PHY_ANAR_100BTXFULL) { 760 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; 761 } else if (advert & PHY_ANAR_100BTXHALF && 762 ability & PHY_ANAR_100BTXHALF) { 763 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; 764 } else if (advert & PHY_ANAR_10BTFULL && 765 ability & PHY_ANAR_10BTFULL) { 766 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; 767 } else if (advert & PHY_ANAR_10BTHALF && 768 ability & PHY_ANAR_10BTHALF) { 769 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; 770 } 771 772 return; 773 } 774 775 static void ste_wait(sc) 776 struct ste_softc *sc; 777 { 778 register int i; 779 780 for (i = 0; i < STE_TIMEOUT; i++) { 781 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 782 break; 783 } 784 785 if (i == STE_TIMEOUT) 786 printf("ste%d: command never completed!\n", sc->ste_unit); 787 788 return; 789 } 790 791 /* 792 * The EEPROM is slow: give it time to come ready after issuing 793 * it a command. 794 */ 795 static int ste_eeprom_wait(sc) 796 struct ste_softc *sc; 797 { 798 int i; 799 800 DELAY(1000); 801 802 for (i = 0; i < 100; i++) { 803 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 804 DELAY(1000); 805 else 806 break; 807 } 808 809 if (i == 100) { 810 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 811 return(1); 812 } 813 814 return(0); 815 } 816 817 /* 818 * Read a sequence of words from the EEPROM. Note that ethernet address 819 * data is stored in the EEPROM in network byte order. 820 */ 821 static int ste_read_eeprom(sc, dest, off, cnt, swap) 822 struct ste_softc *sc; 823 caddr_t dest; 824 int off; 825 int cnt; 826 int swap; 827 { 828 int err = 0, i; 829 u_int16_t word = 0, *ptr; 830 831 if (ste_eeprom_wait(sc)) 832 return(1); 833 834 for (i = 0; i < cnt; i++) { 835 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 836 err = ste_eeprom_wait(sc); 837 if (err) 838 break; 839 word = CSR_READ_2(sc, STE_EEPROM_DATA); 840 ptr = (u_int16_t *)(dest + (i * 2)); 841 if (swap) 842 *ptr = ntohs(word); 843 else 844 *ptr = word; 845 } 846 847 return(err ? 1 : 0); 848 } 849 850 static u_int8_t ste_calchash(addr) 851 caddr_t addr; 852 { 853 854 u_int32_t crc, carry; 855 int i, j; 856 u_int8_t c; 857 858 /* Compute CRC for the address value. */ 859 crc = 0xFFFFFFFF; /* initial value */ 860 861 for (i = 0; i < 6; i++) { 862 c = *(addr + i); 863 for (j = 0; j < 8; j++) { 864 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 865 crc <<= 1; 866 c >>= 1; 867 if (carry) 868 crc = (crc ^ 0x04c11db6) | carry; 869 } 870 } 871 872 /* return the filter bit position */ 873 return(crc & 0x0000003F); 874 } 875 876 static void ste_setmulti(sc) 877 struct ste_softc *sc; 878 { 879 struct ifnet *ifp; 880 int h = 0; 881 u_int32_t hashes[2] = { 0, 0 }; 882 struct ifmultiaddr *ifma; 883 884 ifp = &sc->arpcom.ac_if; 885 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 886 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 887 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 888 return; 889 } 890 891 /* first, zot all the existing hash bits */ 892 CSR_WRITE_4(sc, STE_MAR0, 0); 893 CSR_WRITE_4(sc, STE_MAR1, 0); 894 895 /* now program new ones */ 896 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 897 ifma = ifma->ifma_link.le_next) { 898 if (ifma->ifma_addr->sa_family != AF_LINK) 899 continue; 900 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 901 if (h < 32) 902 hashes[0] |= (1 << h); 903 else 904 hashes[1] |= (1 << (h - 32)); 905 } 906 907 CSR_WRITE_4(sc, STE_MAR0, hashes[0]); 908 CSR_WRITE_4(sc, STE_MAR1, hashes[1]); 909 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 910 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 911 912 return; 913 } 914 915 static void ste_intr(xsc) 916 void *xsc; 917 { 918 struct ste_softc *sc; 919 struct ifnet *ifp; 920 u_int16_t status; 921 922 sc = xsc; 923 ifp = &sc->arpcom.ac_if; 924 925 /* See if this is really our interrupt. */ 926 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 927 return; 928 929 for (;;) { 930 status = CSR_READ_2(sc, STE_ISR_ACK); 931 932 if (!(status & STE_INTRS)) 933 break; 934 935 if (status & STE_ISR_RX_DMADONE) 936 ste_rxeof(sc); 937 938 if (status & STE_ISR_TX_DMADONE) 939 ste_txeof(sc); 940 941 if (status & STE_ISR_TX_DONE) 942 ste_txeoc(sc); 943 944 if (status & STE_ISR_STATS_OFLOW) { 945 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 946 ste_stats_update(sc); 947 } 948 949 if (status & STE_ISR_HOSTERR) { 950 ste_reset(sc); 951 ste_init(sc); 952 } 953 } 954 955 /* Re-enable interrupts */ 956 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 957 958 if (ifp->if_snd.ifq_head != NULL) 959 ste_start(ifp); 960 961 return; 962 } 963 964 /* 965 * A frame has been uploaded: pass the resulting mbuf chain up to 966 * the higher level protocols. 967 */ 968 static void ste_rxeof(sc) 969 struct ste_softc *sc; 970 { 971 struct ether_header *eh; 972 struct mbuf *m; 973 struct ifnet *ifp; 974 struct ste_chain_onefrag *cur_rx; 975 int total_len = 0; 976 u_int32_t rxstat; 977 978 ifp = &sc->arpcom.ac_if; 979 980 again: 981 982 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 983 cur_rx = sc->ste_cdata.ste_rx_head; 984 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 985 986 /* 987 * If an error occurs, update stats, clear the 988 * status word and leave the mbuf cluster in place: 989 * it should simply get re-used next time this descriptor 990 * comes up in the ring. 991 */ 992 if (rxstat & STE_RXSTAT_FRAME_ERR) { 993 ifp->if_ierrors++; 994 cur_rx->ste_ptr->ste_status = 0; 995 continue; 996 } 997 998 /* 999 * If there error bit was not set, the upload complete 1000 * bit should be set which means we have a valid packet. 1001 * If not, something truly strange has happened. 1002 */ 1003 if (!(rxstat & STE_RXSTAT_DMADONE)) { 1004 printf("ste%d: bad receive status -- packet dropped", 1005 sc->ste_unit); 1006 ifp->if_ierrors++; 1007 cur_rx->ste_ptr->ste_status = 0; 1008 continue; 1009 } 1010 1011 /* No errors; receive the packet. */ 1012 m = cur_rx->ste_mbuf; 1013 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 1014 1015 /* 1016 * Try to conjure up a new mbuf cluster. If that 1017 * fails, it means we have an out of memory condition and 1018 * should leave the buffer in place and continue. This will 1019 * result in a lost packet, but there's little else we 1020 * can do in this situation. 1021 */ 1022 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1023 ifp->if_ierrors++; 1024 cur_rx->ste_ptr->ste_status = 0; 1025 continue; 1026 } 1027 1028 ifp->if_ipackets++; 1029 eh = mtod(m, struct ether_header *); 1030 m->m_pkthdr.rcvif = ifp; 1031 m->m_pkthdr.len = m->m_len = total_len; 1032 1033 #if NBPFILTER > 0 1034 /* Handle BPF listeners. Let the BPF user see the packet. */ 1035 if (ifp->if_bpf) 1036 bpf_mtap(ifp, m); 1037 #endif 1038 1039 #ifdef BRIDGE 1040 if (do_bridge) { 1041 struct ifnet *bdg_ifp ; 1042 bdg_ifp = bridge_in(m); 1043 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 1044 bdg_forward(&m, bdg_ifp); 1045 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 1046 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 1047 m_freem(m); 1048 continue; 1049 } 1050 } 1051 #endif 1052 1053 #if NBPFILTER > 0 1054 /* 1055 * Don't pass packet up to the ether_input() layer unless it's 1056 * a broadcast packet, multicast packet, matches our ethernet 1057 * address or the interface is in promiscuous mode. 1058 */ 1059 if (ifp->if_bpf) { 1060 if (ifp->if_flags & IFF_PROMISC && 1061 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1062 ETHER_ADDR_LEN) && (eh->ether_dhost[0] & 1) == 0)){ 1063 m_freem(m); 1064 continue; 1065 } 1066 } 1067 #endif 1068 1069 /* Remove header from mbuf and pass it on. */ 1070 m_adj(m, sizeof(struct ether_header)); 1071 ether_input(ifp, eh, m); 1072 } 1073 1074 /* 1075 * Handle the 'end of channel' condition. When the upload 1076 * engine hits the end of the RX ring, it will stall. This 1077 * is our cue to flush the RX ring, reload the uplist pointer 1078 * register and unstall the engine. 1079 * XXX This is actually a little goofy. With the ThunderLAN 1080 * chip, you get an interrupt when the receiver hits the end 1081 * of the receive ring, which tells you exactly when you 1082 * you need to reload the ring pointer. Here we have to 1083 * fake it. I'm mad at myself for not being clever enough 1084 * to avoid the use of a goto here. 1085 */ 1086 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 1087 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 1088 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1089 ste_wait(sc); 1090 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1091 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1092 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 1093 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1094 goto again; 1095 } 1096 1097 return; 1098 } 1099 1100 static void ste_txeoc(sc) 1101 struct ste_softc *sc; 1102 { 1103 u_int8_t txstat; 1104 struct ifnet *ifp; 1105 1106 ifp = &sc->arpcom.ac_if; 1107 1108 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 1109 STE_TXSTATUS_TXDONE) { 1110 if (txstat & STE_TXSTATUS_UNDERRUN || 1111 txstat & STE_TXSTATUS_EXCESSCOLLS || 1112 txstat & STE_TXSTATUS_RECLAIMERR) { 1113 ifp->if_oerrors++; 1114 printf("ste%d: transmission error: %x\n", 1115 sc->ste_unit, txstat); 1116 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_TX_RESET); 1117 1118 if (sc->ste_cdata.ste_tx_head != NULL) 1119 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1120 vtophys(sc->ste_cdata.ste_tx_head->ste_ptr)); 1121 if (txstat & STE_TXSTATUS_UNDERRUN && 1122 sc->ste_tx_thresh < STE_PACKET_SIZE) { 1123 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 1124 printf("ste%d: tx underrun, increasing tx" 1125 " start threshold to %d bytes\n", 1126 sc->ste_unit, sc->ste_tx_thresh); 1127 } 1128 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1129 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 1130 (STE_PACKET_SIZE >> 4)); 1131 } 1132 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1133 if (CSR_READ_4(sc, STE_TX_DMALIST_PTR)) 1134 CSR_WRITE_4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1135 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 1136 } 1137 1138 return; 1139 } 1140 1141 static void ste_txeof(sc) 1142 struct ste_softc *sc; 1143 { 1144 struct ste_chain *cur_tx; 1145 struct ifnet *ifp; 1146 1147 ifp = &sc->arpcom.ac_if; 1148 1149 /* Clear the timeout timer. */ 1150 ifp->if_timer = 0; 1151 1152 while(sc->ste_cdata.ste_tx_head != NULL) { 1153 cur_tx = sc->ste_cdata.ste_tx_head; 1154 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 1155 break; 1156 sc->ste_cdata.ste_tx_head = cur_tx->ste_next; 1157 1158 m_freem(cur_tx->ste_mbuf); 1159 cur_tx->ste_mbuf = NULL; 1160 ifp->if_opackets++; 1161 1162 cur_tx->ste_next = sc->ste_cdata.ste_tx_free; 1163 sc->ste_cdata.ste_tx_free = cur_tx; 1164 } 1165 1166 if (sc->ste_cdata.ste_tx_head == NULL) { 1167 ifp->if_flags &= ~IFF_OACTIVE; 1168 sc->ste_cdata.ste_tx_tail = NULL; 1169 if (sc->ste_want_auto) 1170 ste_autoneg_mii(sc, STE_FLAG_SCHEDDELAY, 1); 1171 } else { 1172 if (CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_TXDMA_STOPPED || 1173 !CSR_READ_4(sc, STE_TX_DMALIST_PTR)) { 1174 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1175 vtophys(sc->ste_cdata.ste_tx_head->ste_ptr)); 1176 CSR_WRITE_4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1177 } 1178 } 1179 1180 return; 1181 } 1182 1183 static void ste_stats_update(xsc) 1184 void *xsc; 1185 { 1186 struct ste_softc *sc; 1187 struct ste_stats stats; 1188 struct ifnet *ifp; 1189 int i, s; 1190 u_int8_t *p; 1191 1192 s = splimp(); 1193 1194 sc = xsc; 1195 ifp = &sc->arpcom.ac_if; 1196 p = (u_int8_t *)&stats; 1197 1198 for (i = 0; i < sizeof(stats); i++) { 1199 *p = CSR_READ_1(sc, STE_STATS + i); 1200 p++; 1201 } 1202 1203 ifp->if_collisions += stats.ste_single_colls + 1204 stats.ste_multi_colls + stats.ste_late_colls; 1205 1206 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1207 splx(s); 1208 1209 return; 1210 } 1211 1212 1213 /* 1214 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 1215 * IDs against our list and return a device name if we find a match. 1216 */ 1217 static const char *ste_probe(config_id, device_id) 1218 pcici_t config_id; 1219 pcidi_t device_id; 1220 { 1221 struct ste_type *t; 1222 1223 t = ste_devs; 1224 1225 while(t->ste_name != NULL) { 1226 if ((device_id & 0xFFFF) == t->ste_vid && 1227 ((device_id >> 16) & 0xFFFF) == t->ste_did) { 1228 return(t->ste_name); 1229 } 1230 t++; 1231 } 1232 1233 return(NULL); 1234 } 1235 1236 /* 1237 * Attach the interface. Allocate softc structures, do ifmedia 1238 * setup and ethernet/BPF attach. 1239 */ 1240 static void 1241 ste_attach(config_id, unit) 1242 pcici_t config_id; 1243 int unit; 1244 { 1245 int s, i; 1246 #ifndef STE_USEIOSPACE 1247 vm_offset_t pbase, vbase; 1248 #endif 1249 u_int32_t command; 1250 struct ste_softc *sc; 1251 struct ifnet *ifp; 1252 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1253 struct ste_type *p; 1254 u_int16_t phy_vid, phy_did, phy_sts; 1255 1256 s = splimp(); 1257 1258 sc = malloc(sizeof(struct ste_softc), M_DEVBUF, M_NOWAIT); 1259 if (sc == NULL) { 1260 printf("ste%d: no memory for softc struct!\n", unit); 1261 goto fail; 1262 } 1263 bzero(sc, sizeof(struct ste_softc)); 1264 1265 /* 1266 * Handle power management nonsense. 1267 */ 1268 command = pci_conf_read(config_id, STE_PCI_CAPID) & 0x000000FF; 1269 if (command == 0x01) { 1270 1271 command = pci_conf_read(config_id, STE_PCI_PWRMGMTCTRL); 1272 if (command & STE_PSTATE_MASK) { 1273 u_int32_t iobase, membase, irq; 1274 1275 /* Save important PCI config data. */ 1276 iobase = pci_conf_read(config_id, STE_PCI_LOIO); 1277 membase = pci_conf_read(config_id, STE_PCI_LOMEM); 1278 irq = pci_conf_read(config_id, STE_PCI_INTLINE); 1279 1280 /* Reset the power state. */ 1281 printf("ste%d: chip is in D%d power mode " 1282 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 1283 command &= 0xFFFFFFFC; 1284 pci_conf_write(config_id, STE_PCI_PWRMGMTCTRL, command); 1285 1286 /* Restore PCI config data. */ 1287 pci_conf_write(config_id, STE_PCI_LOIO, iobase); 1288 pci_conf_write(config_id, STE_PCI_LOMEM, membase); 1289 pci_conf_write(config_id, STE_PCI_INTLINE, irq); 1290 } 1291 } 1292 1293 /* 1294 * Map control/status registers. 1295 */ 1296 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1297 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1298 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1299 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1300 1301 #ifdef STE_USEIOSPACE 1302 if (!(command & PCIM_CMD_PORTEN)) { 1303 printf("ste%d: failed to enable I/O ports!\n", unit); 1304 free(sc, M_DEVBUF); 1305 goto fail; 1306 } 1307 1308 if (!pci_map_port(config_id, STE_PCI_LOIO, 1309 (pci_port_t *)&(sc->ste_bhandle))) { 1310 printf ("ste%d: couldn't map ports\n", unit); 1311 goto fail; 1312 } 1313 1314 sc->ste_btag = STE_BUS_SPACE_IO; 1315 #else 1316 if (!(command & PCIM_CMD_MEMEN)) { 1317 printf("ste%d: failed to enable memory mapping!\n", unit); 1318 goto fail; 1319 } 1320 1321 if (!pci_map_mem(config_id, STE_PCI_LOMEM, &vbase, &pbase)) { 1322 printf ("ste%d: couldn't map memory\n", unit); 1323 goto fail; 1324 } 1325 sc->ste_btag = STE_BUS_SPACE_MEM; 1326 sc->ste_bhandle = vbase; 1327 #endif 1328 1329 /* Allocate interrupt */ 1330 if (!pci_map_int(config_id, ste_intr, sc, &net_imask)) { 1331 printf("ste%d: couldn't map interrupt\n", unit); 1332 goto fail; 1333 } 1334 1335 callout_handle_init(&sc->ste_stat_ch); 1336 1337 /* Reset the adapter. */ 1338 ste_reset(sc); 1339 1340 /* 1341 * Get station address from the EEPROM. 1342 */ 1343 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1344 STE_EEADDR_NODE0, 3, 0)) { 1345 printf("ste%d: failed to read station address\n", unit); 1346 free(sc, M_DEVBUF); 1347 goto fail; 1348 } 1349 1350 /* 1351 * A Sundance chip was detected. Inform the world. 1352 */ 1353 printf("ste%d: Ethernet address: %6D\n", unit, 1354 sc->arpcom.ac_enaddr, ":"); 1355 1356 sc->ste_unit = unit; 1357 1358 /* Allocate the descriptor queues. */ 1359 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1360 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1361 1362 if (sc->ste_ldata == NULL) { 1363 free(sc, M_DEVBUF); 1364 printf("ste%d: no memory for list buffers!\n", unit); 1365 goto fail; 1366 } 1367 1368 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1369 1370 if (bootverbose) 1371 printf("ste%d: probing for a PHY\n", sc->ste_unit); 1372 for (i = STE_PHYADDR_MIN; i < STE_PHYADDR_MAX + 1; i++) { 1373 if (bootverbose) 1374 printf("ste%d: checking address: %d\n", 1375 sc->ste_unit, i); 1376 sc->ste_phy_addr = i; 1377 ste_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 1378 DELAY(500); 1379 while(ste_phy_readreg(sc, PHY_BMCR) 1380 & PHY_BMCR_RESET); 1381 if ((phy_sts = ste_phy_readreg(sc, PHY_BMSR))) 1382 break; 1383 } 1384 if (phy_sts) { 1385 phy_vid = ste_phy_readreg(sc, STE_PHY_VENID); 1386 phy_did = ste_phy_readreg(sc, STE_PHY_DEVID); 1387 if (bootverbose) 1388 printf("ste%d: found PHY at address %d, ", 1389 sc->ste_unit, sc->ste_phy_addr); 1390 if (bootverbose) 1391 printf("vendor id: %x device id: %x\n", 1392 phy_vid, phy_did); 1393 p = ste_phys; 1394 while(p->ste_vid) { 1395 if (phy_vid == p->ste_vid && 1396 (phy_did | 0x000F) == p->ste_did) { 1397 sc->ste_pinfo = p; 1398 break; 1399 } 1400 p++; 1401 } 1402 if (sc->ste_pinfo == NULL) 1403 sc->ste_pinfo = &ste_phys[PHY_UNKNOWN]; 1404 if (bootverbose) 1405 printf("ste%d: PHY type: %s\n", 1406 sc->ste_unit, sc->ste_pinfo->ste_name); 1407 } else { 1408 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1409 free(sc->ste_ldata, M_DEVBUF); 1410 free(sc, M_DEVBUF); 1411 goto fail; 1412 } 1413 1414 ifp = &sc->arpcom.ac_if; 1415 ifp->if_softc = sc; 1416 ifp->if_unit = unit; 1417 ifp->if_name = "ste"; 1418 ifp->if_mtu = ETHERMTU; 1419 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1420 ifp->if_ioctl = ste_ioctl; 1421 ifp->if_output = ether_output; 1422 ifp->if_start = ste_start; 1423 ifp->if_watchdog = ste_watchdog; 1424 ifp->if_init = ste_init; 1425 ifp->if_baudrate = 10000000; 1426 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1427 1428 /* 1429 * Do ifmedia setup. 1430 */ 1431 ifmedia_init(&sc->ifmedia, 0, ste_ifmedia_upd, ste_ifmedia_sts); 1432 1433 ste_getmode_mii(sc); 1434 ste_autoneg_mii(sc, STE_FLAG_FORCEDELAY, 1); 1435 media = sc->ifmedia.ifm_media; 1436 ste_stop(sc); 1437 1438 ifmedia_set(&sc->ifmedia, media); 1439 1440 /* 1441 * Call MI attach routines. 1442 */ 1443 1444 if_attach(ifp); 1445 ether_ifattach(ifp); 1446 1447 #if NBPFILTER > 0 1448 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1449 #endif 1450 1451 at_shutdown(ste_shutdown, sc, SHUTDOWN_POST_SYNC); 1452 1453 fail: 1454 splx(s); 1455 return; 1456 } 1457 1458 static int ste_newbuf(sc, c, m) 1459 struct ste_softc *sc; 1460 struct ste_chain_onefrag *c; 1461 struct mbuf *m; 1462 { 1463 struct mbuf *m_new = NULL; 1464 1465 if (m == NULL) { 1466 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1467 if (m_new == NULL) { 1468 printf("ste%d: no memory for rx list -- " 1469 "packet dropped\n", sc->ste_unit); 1470 return(ENOBUFS); 1471 } 1472 MCLGET(m_new, M_DONTWAIT); 1473 if (!(m_new->m_flags & M_EXT)) { 1474 printf("ste%d: no memory for rx list -- " 1475 "packet dropped\n", sc->ste_unit); 1476 m_freem(m_new); 1477 return(ENOBUFS); 1478 } 1479 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1480 } else { 1481 m_new = m; 1482 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1483 m_new->m_data = m_new->m_ext.ext_buf; 1484 } 1485 1486 m_adj(m_new, ETHER_ALIGN); 1487 1488 c->ste_mbuf = m_new; 1489 c->ste_ptr->ste_status = 0; 1490 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1491 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1492 1493 return(0); 1494 } 1495 1496 static int ste_init_rx_list(sc) 1497 struct ste_softc *sc; 1498 { 1499 struct ste_chain_data *cd; 1500 struct ste_list_data *ld; 1501 int i; 1502 1503 cd = &sc->ste_cdata; 1504 ld = sc->ste_ldata; 1505 1506 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1507 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1508 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1509 return(ENOBUFS); 1510 if (i == (STE_RX_LIST_CNT - 1)) { 1511 cd->ste_rx_chain[i].ste_next = 1512 &cd->ste_rx_chain[0]; 1513 ld->ste_rx_list[i].ste_next = 1514 vtophys(&ld->ste_rx_list[0]); 1515 } else { 1516 cd->ste_rx_chain[i].ste_next = 1517 &cd->ste_rx_chain[i + 1]; 1518 ld->ste_rx_list[i].ste_next = 1519 vtophys(&ld->ste_rx_list[i + 1]); 1520 } 1521 1522 } 1523 1524 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1525 1526 return(0); 1527 } 1528 1529 static void ste_init_tx_list(sc) 1530 struct ste_softc *sc; 1531 { 1532 struct ste_chain_data *cd; 1533 struct ste_list_data *ld; 1534 int i; 1535 1536 cd = &sc->ste_cdata; 1537 ld = sc->ste_ldata; 1538 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1539 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1540 if (i == (STE_TX_LIST_CNT - 1)) 1541 cd->ste_tx_chain[i].ste_next = NULL; 1542 else 1543 cd->ste_tx_chain[i].ste_next = 1544 &cd->ste_tx_chain[i + 1]; 1545 } 1546 1547 cd->ste_tx_free = &cd->ste_tx_chain[0]; 1548 cd->ste_tx_tail = cd->ste_tx_head = NULL; 1549 1550 return; 1551 } 1552 1553 static void ste_init(xsc) 1554 void *xsc; 1555 { 1556 struct ste_softc *sc; 1557 int i, s; 1558 u_int16_t phy_bmcr = 0; 1559 struct ifnet *ifp; 1560 1561 sc = xsc; 1562 ifp = &sc->arpcom.ac_if; 1563 1564 if (sc->ste_autoneg) 1565 return; 1566 1567 s = splimp(); 1568 1569 if (sc->ste_pinfo != NULL) 1570 phy_bmcr = ste_phy_readreg(sc, PHY_BMCR); 1571 1572 ste_stop(sc); 1573 1574 /* Init our MAC address */ 1575 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1576 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1577 } 1578 1579 /* Init RX list */ 1580 if (ste_init_rx_list(sc) == ENOBUFS) { 1581 printf("ste%d: initialization failed: no " 1582 "memory for RX buffers\n", sc->ste_unit); 1583 ste_stop(sc); 1584 splx(s); 1585 return; 1586 } 1587 1588 /* Init TX descriptors */ 1589 ste_init_tx_list(sc); 1590 1591 /* Set the TX freethresh value */ 1592 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1593 1594 /* Set the TX start threshold for best performance. */ 1595 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1596 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1597 1598 /* Set the TX reclaim threshold. */ 1599 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1600 1601 /* Set up the RX filter. */ 1602 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1603 1604 /* If we want promiscuous mode, set the allframes bit. */ 1605 if (ifp->if_flags & IFF_PROMISC) { 1606 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1607 } else { 1608 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1609 } 1610 1611 /* Set capture broadcast bit to accept broadcast frames. */ 1612 if (ifp->if_flags & IFF_BROADCAST) { 1613 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1614 } else { 1615 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1616 } 1617 1618 ste_setmulti(sc); 1619 1620 /* Load the address of the RX list. */ 1621 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1622 ste_wait(sc); 1623 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1624 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1625 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1626 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1627 1628 /* Enable receiver and transmitter */ 1629 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1630 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1631 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1632 1633 /* Enable stats counters. */ 1634 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1635 1636 /* Enable interrupts. */ 1637 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1638 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1639 1640 if (sc->ste_pinfo != NULL) 1641 ste_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1642 if (phy_bmcr & PHY_BMCR_DUPLEX) 1643 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 1644 1645 ifp->if_flags |= IFF_RUNNING; 1646 ifp->if_flags &= ~IFF_OACTIVE; 1647 1648 splx(s); 1649 1650 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1651 1652 return; 1653 } 1654 1655 static void ste_stop(sc) 1656 struct ste_softc *sc; 1657 { 1658 int i; 1659 struct ifnet *ifp; 1660 1661 ifp = &sc->arpcom.ac_if; 1662 1663 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1664 1665 CSR_WRITE_2(sc, STE_IMR, 0); 1666 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1667 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1668 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1669 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1670 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1671 ste_wait(sc); 1672 1673 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1674 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1675 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1676 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1677 } 1678 } 1679 1680 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1681 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1682 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1683 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1684 } 1685 } 1686 1687 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1688 1689 return; 1690 } 1691 1692 static void ste_reset(sc) 1693 struct ste_softc *sc; 1694 { 1695 int i; 1696 1697 STE_SETBIT4(sc, STE_ASICCTL, 1698 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1699 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1700 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1701 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1702 STE_ASICCTL_EXTRESET_RESET); 1703 1704 DELAY(100000); 1705 1706 for (i = 0; i < STE_TIMEOUT; i++) { 1707 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1708 break; 1709 } 1710 1711 if (i == STE_TIMEOUT) 1712 printf("ste%d: global reset never completed\n", sc->ste_unit); 1713 1714 #ifdef foo 1715 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_RX_RESET); 1716 for (i = 0; i < STE_TIMEOUT; i++) { 1717 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RX_RESET)) 1718 break; 1719 } 1720 1721 if (i == STE_TIMEOUT) 1722 printf("ste%d: RX reset never completed\n", sc->ste_unit); 1723 1724 DELAY(100000); 1725 1726 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_TX_RESET); 1727 for (i = 0; i < STE_TIMEOUT; i++) { 1728 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_TX_RESET)) 1729 break; 1730 } 1731 1732 if (i == STE_TIMEOUT) 1733 printf("ste%d: TX reset never completed\n", sc->ste_unit); 1734 1735 DELAY(100000); 1736 #endif 1737 1738 return; 1739 } 1740 1741 static int ste_ioctl(ifp, command, data) 1742 struct ifnet *ifp; 1743 u_long command; 1744 caddr_t data; 1745 { 1746 struct ste_softc *sc; 1747 struct ifreq *ifr; 1748 int error = 0, s; 1749 1750 s = splimp(); 1751 1752 sc = ifp->if_softc; 1753 ifr = (struct ifreq *)data; 1754 1755 switch(command) { 1756 case SIOCSIFADDR: 1757 case SIOCGIFADDR: 1758 case SIOCSIFMTU: 1759 error = ether_ioctl(ifp, command, data); 1760 break; 1761 case SIOCSIFFLAGS: 1762 if (ifp->if_flags & IFF_UP) { 1763 ste_init(sc); 1764 } else { 1765 if (ifp->if_flags & IFF_RUNNING) 1766 ste_stop(sc); 1767 } 1768 error = 0; 1769 break; 1770 case SIOCADDMULTI: 1771 case SIOCDELMULTI: 1772 ste_setmulti(sc); 1773 error = 0; 1774 break; 1775 case SIOCGIFMEDIA: 1776 case SIOCSIFMEDIA: 1777 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1778 break; 1779 default: 1780 error = EINVAL; 1781 break; 1782 } 1783 1784 splx(s); 1785 1786 return(error); 1787 } 1788 1789 static int ste_encap(sc, c, m_head) 1790 struct ste_softc *sc; 1791 struct ste_chain *c; 1792 struct mbuf *m_head; 1793 { 1794 int frag = 0; 1795 struct ste_frag *f = NULL; 1796 int total_len; 1797 struct mbuf *m; 1798 1799 m = m_head; 1800 total_len = 0; 1801 1802 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1803 if (m->m_len != 0) { 1804 if (frag == STE_MAXFRAGS) 1805 break; 1806 total_len += m->m_len; 1807 f = &c->ste_ptr->ste_frags[frag]; 1808 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1809 f->ste_len = m->m_len; 1810 frag++; 1811 } 1812 } 1813 1814 if (m != NULL) { 1815 struct mbuf *m_new = NULL; 1816 1817 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1818 if (m_new == NULL) { 1819 printf("ste%d: no memory for " 1820 "tx list", sc->ste_unit); 1821 return(1); 1822 } 1823 if (m_head->m_pkthdr.len > MHLEN) { 1824 MCLGET(m_new, M_DONTWAIT); 1825 if (!(m_new->m_flags & M_EXT)) { 1826 m_freem(m_new); 1827 printf("ste%d: no memory for " 1828 "tx list", sc->ste_unit); 1829 return(1); 1830 } 1831 } 1832 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1833 mtod(m_new, caddr_t)); 1834 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1835 m_freem(m_head); 1836 m_head = m_new; 1837 f = &c->ste_ptr->ste_frags[0]; 1838 f->ste_addr = vtophys(mtod(m_new, caddr_t)); 1839 f->ste_len = total_len = m_new->m_len; 1840 frag = 1; 1841 } 1842 1843 c->ste_mbuf = m_head; 1844 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1845 c->ste_ptr->ste_ctl = total_len; 1846 c->ste_ptr->ste_next = 0; 1847 1848 return(0); 1849 } 1850 1851 static void ste_start(ifp) 1852 struct ifnet *ifp; 1853 { 1854 struct ste_softc *sc; 1855 struct mbuf *m_head = NULL; 1856 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1857 1858 sc = ifp->if_softc; 1859 1860 if (sc->ste_autoneg) { 1861 sc->ste_tx_pend = 1; 1862 return; 1863 } 1864 1865 if (sc->ste_cdata.ste_tx_free == NULL) { 1866 ifp->if_flags |= IFF_OACTIVE; 1867 return; 1868 } 1869 1870 start_tx = sc->ste_cdata.ste_tx_free; 1871 1872 while(sc->ste_cdata.ste_tx_free != NULL) { 1873 IF_DEQUEUE(&ifp->if_snd, m_head); 1874 if (m_head == NULL) 1875 break; 1876 1877 cur_tx = sc->ste_cdata.ste_tx_free; 1878 sc->ste_cdata.ste_tx_free = cur_tx->ste_next; 1879 1880 cur_tx->ste_next = NULL; 1881 1882 ste_encap(sc, cur_tx, m_head); 1883 1884 if (prev != NULL) { 1885 prev->ste_next = cur_tx; 1886 prev->ste_ptr->ste_next = vtophys(cur_tx->ste_ptr); 1887 } 1888 prev = cur_tx; 1889 1890 #if NBPFILTER > 0 1891 /* 1892 * If there's a BPF listener, bounce a copt of this frame 1893 * to him. 1894 */ 1895 if (ifp->if_bpf) 1896 bpf_mtap(ifp, cur_tx->ste_mbuf); 1897 #endif 1898 } 1899 1900 if (cur_tx == NULL) 1901 return; 1902 1903 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1904 1905 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1906 ste_wait(sc); 1907 1908 if (sc->ste_cdata.ste_tx_head != NULL) { 1909 sc->ste_cdata.ste_tx_tail->ste_next = start_tx; 1910 sc->ste_cdata.ste_tx_tail->ste_ptr->ste_next = 1911 vtophys(start_tx->ste_ptr); 1912 sc->ste_cdata.ste_tx_tail->ste_ptr->ste_ctl &= 1913 ~STE_TXCTL_DMAINTR; 1914 sc->ste_cdata.ste_tx_tail = cur_tx; 1915 } else { 1916 sc->ste_cdata.ste_tx_head = start_tx; 1917 sc->ste_cdata.ste_tx_tail = cur_tx; 1918 } 1919 1920 if (!CSR_READ_4(sc, STE_TX_DMALIST_PTR)) 1921 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1922 vtophys(start_tx->ste_ptr)); 1923 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1924 1925 ifp->if_timer = 5; 1926 1927 return; 1928 } 1929 1930 static void ste_watchdog(ifp) 1931 struct ifnet *ifp; 1932 { 1933 struct ste_softc *sc; 1934 1935 sc = ifp->if_softc; 1936 1937 if (sc->ste_autoneg) { 1938 ste_autoneg_mii(sc, STE_FLAG_DELAYTIMEO, 1); 1939 if (!(ifp->if_flags & IFF_UP)) 1940 ste_stop(sc); 1941 return; 1942 } 1943 1944 ifp->if_oerrors++; 1945 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1946 1947 if (sc->ste_pinfo != NULL) { 1948 if (!(ste_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1949 printf("ste%d: no carrier - transceiver " 1950 "cable problem?\n", sc->ste_unit); 1951 } 1952 1953 ste_txeoc(sc); 1954 ste_txeof(sc); 1955 ste_rxeof(sc); 1956 ste_reset(sc); 1957 ste_init(sc); 1958 1959 if (ifp->if_snd.ifq_head != NULL) 1960 ste_start(ifp); 1961 1962 return; 1963 } 1964 1965 static void ste_shutdown(howto, arg) 1966 int howto; 1967 void *arg; 1968 { 1969 struct ste_softc *sc; 1970 1971 sc = arg; 1972 ste_stop(sc); 1973 1974 return; 1975 } 1976 1977 static struct pci_device ste_device = { 1978 "ste", 1979 ste_probe, 1980 ste_attach, 1981 &ste_count, 1982 NULL 1983 }; 1984 #ifdef COMPAT_PCI_DRIVER 1985 COMPAT_PCI_DRIVER(ste, ste_device); 1986 #else 1987 DATA_SET(pcidevice_set, ste_device); 1988 #endif /* COMPAT_PCI_DRIVER */
Cache object: 28040c260df65e4d4ad8ee84d44b6de1
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