The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/pci/if_ste.c

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 /*
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD$
   33  */
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/sockio.h>
   38 #include <sys/mbuf.h>
   39 #include <sys/malloc.h>
   40 #include <sys/kernel.h>
   41 #include <sys/socket.h>
   42 #include <sys/sysctl.h>
   43 
   44 #include <net/if.h>
   45 #include <net/if_arp.h>
   46 #include <net/ethernet.h>
   47 #include <net/if_dl.h>
   48 #include <net/if_media.h>
   49 #include <net/if_vlan_var.h>
   50 
   51 #include <net/bpf.h>
   52 
   53 #include <vm/vm.h>              /* for vtophys */
   54 #include <vm/pmap.h>            /* for vtophys */
   55 #include <machine/clock.h>      /* for DELAY */
   56 #include <machine/bus_memio.h>
   57 #include <machine/bus_pio.h>
   58 #include <machine/bus.h>
   59 #include <machine/resource.h>
   60 #include <sys/bus.h>
   61 #include <sys/rman.h>
   62 
   63 #include <dev/mii/mii.h>
   64 #include <dev/mii/miivar.h>
   65 
   66 #include <pci/pcireg.h>
   67 #include <pci/pcivar.h>
   68 
   69 /* "controller miibus0" required.  See GENERIC if you get errors here. */
   70 #include "miibus_if.h"
   71 
   72 #define STE_USEIOSPACE
   73 
   74 #include <pci/if_stereg.h>
   75 
   76 #if !defined(lint)
   77 static const char rcsid[] =
   78   "$FreeBSD$";
   79 #endif
   80 
   81 /*
   82  * Various supported device vendors/types and their names.
   83  */
   84 static struct ste_type ste_devs[] = {
   85         { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
   86         { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" },
   87         { 0, 0, NULL }
   88 };
   89 
   90 static int ste_probe            __P((device_t));
   91 static int ste_attach           __P((device_t));
   92 static int ste_detach           __P((device_t));
   93 static void ste_init            __P((void *));
   94 static void ste_intr            __P((void *));
   95 static void ste_rxeoc           __P((struct ste_softc *));
   96 static void ste_rxeof           __P((struct ste_softc *));
   97 static void ste_txeoc           __P((struct ste_softc *));
   98 static void ste_txeof           __P((struct ste_softc *));
   99 static void ste_stats_update    __P((void *));
  100 static void ste_stop            __P((struct ste_softc *));
  101 static void ste_reset           __P((struct ste_softc *));
  102 static int ste_ioctl            __P((struct ifnet *, u_long, caddr_t));
  103 static int ste_encap            __P((struct ste_softc *, struct ste_chain *,
  104                                         struct mbuf *));
  105 static void ste_start           __P((struct ifnet *));
  106 static void ste_watchdog        __P((struct ifnet *));
  107 static void ste_shutdown        __P((device_t));
  108 static int ste_newbuf           __P((struct ste_softc *,
  109                                         struct ste_chain_onefrag *,
  110                                         struct mbuf *));
  111 static int ste_ifmedia_upd      __P((struct ifnet *));
  112 static void ste_ifmedia_sts     __P((struct ifnet *, struct ifmediareq *));
  113 
  114 static void ste_mii_sync        __P((struct ste_softc *));
  115 static void ste_mii_send        __P((struct ste_softc *, u_int32_t, int));
  116 static int ste_mii_readreg      __P((struct ste_softc *,
  117                                         struct ste_mii_frame *));
  118 static int ste_mii_writereg     __P((struct ste_softc *,
  119                                         struct ste_mii_frame *));
  120 static int ste_miibus_readreg   __P((device_t, int, int));
  121 static int ste_miibus_writereg  __P((device_t, int, int, int));
  122 static void ste_miibus_statchg  __P((device_t));
  123 
  124 static int ste_eeprom_wait      __P((struct ste_softc *));
  125 static int ste_read_eeprom      __P((struct ste_softc *, caddr_t, int,
  126                                                         int, int));
  127 static void ste_wait            __P((struct ste_softc *));
  128 static u_int8_t ste_calchash    __P((caddr_t));
  129 static void ste_setmulti        __P((struct ste_softc *));
  130 static int ste_init_rx_list     __P((struct ste_softc *));
  131 static void ste_init_tx_list    __P((struct ste_softc *));
  132 
  133 #ifdef STE_USEIOSPACE
  134 #define STE_RES                 SYS_RES_IOPORT
  135 #define STE_RID                 STE_PCI_LOIO
  136 #else
  137 #define STE_RES                 SYS_RES_MEMORY
  138 #define STE_RID                 STE_PCI_LOMEM
  139 #endif
  140 
  141 static device_method_t ste_methods[] = {
  142         /* Device interface */
  143         DEVMETHOD(device_probe,         ste_probe),
  144         DEVMETHOD(device_attach,        ste_attach),
  145         DEVMETHOD(device_detach,        ste_detach),
  146         DEVMETHOD(device_shutdown,      ste_shutdown),
  147 
  148         /* bus interface */
  149         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  150         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  151 
  152         /* MII interface */
  153         DEVMETHOD(miibus_readreg,       ste_miibus_readreg),
  154         DEVMETHOD(miibus_writereg,      ste_miibus_writereg),
  155         DEVMETHOD(miibus_statchg,       ste_miibus_statchg),
  156 
  157         { 0, 0 }
  158 };
  159 
  160 static driver_t ste_driver = {
  161         "ste",
  162         ste_methods,
  163         sizeof(struct ste_softc)
  164 };
  165 
  166 static devclass_t ste_devclass;
  167 
  168 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0);
  169 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
  170 
  171 SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters");
  172 
  173 static int ste_rxsyncs;
  174 SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, "");
  175 
  176 #define STE_SETBIT4(sc, reg, x)                         \
  177         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
  178 
  179 #define STE_CLRBIT4(sc, reg, x)                         \
  180         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
  181 
  182 #define STE_SETBIT2(sc, reg, x)                         \
  183         CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
  184 
  185 #define STE_CLRBIT2(sc, reg, x)                         \
  186         CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
  187 
  188 #define STE_SETBIT1(sc, reg, x)                         \
  189         CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
  190 
  191 #define STE_CLRBIT1(sc, reg, x)                         \
  192         CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
  193 
  194 
  195 #define MII_SET(x)              STE_SETBIT1(sc, STE_PHYCTL, x)
  196 #define MII_CLR(x)              STE_CLRBIT1(sc, STE_PHYCTL, x) 
  197 
  198 /*
  199  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  200  */
  201 static void ste_mii_sync(sc)
  202         struct ste_softc                *sc;
  203 {
  204         register int            i;
  205 
  206         MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
  207 
  208         for (i = 0; i < 32; i++) {
  209                 MII_SET(STE_PHYCTL_MCLK);
  210                 DELAY(1);
  211                 MII_CLR(STE_PHYCTL_MCLK);
  212                 DELAY(1);
  213         }
  214 
  215         return;
  216 }
  217 
  218 /*
  219  * Clock a series of bits through the MII.
  220  */
  221 static void ste_mii_send(sc, bits, cnt)
  222         struct ste_softc                *sc;
  223         u_int32_t               bits;
  224         int                     cnt;
  225 {
  226         int                     i;
  227 
  228         MII_CLR(STE_PHYCTL_MCLK);
  229 
  230         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  231                 if (bits & i) {
  232                         MII_SET(STE_PHYCTL_MDATA);
  233                 } else {
  234                         MII_CLR(STE_PHYCTL_MDATA);
  235                 }
  236                 DELAY(1);
  237                 MII_CLR(STE_PHYCTL_MCLK);
  238                 DELAY(1);
  239                 MII_SET(STE_PHYCTL_MCLK);
  240         }
  241 }
  242 
  243 /*
  244  * Read an PHY register through the MII.
  245  */
  246 static int ste_mii_readreg(sc, frame)
  247         struct ste_softc                *sc;
  248         struct ste_mii_frame    *frame;
  249         
  250 {
  251         int                     i, ack, s;
  252 
  253         s = splimp();
  254 
  255         /*
  256          * Set up frame for RX.
  257          */
  258         frame->mii_stdelim = STE_MII_STARTDELIM;
  259         frame->mii_opcode = STE_MII_READOP;
  260         frame->mii_turnaround = 0;
  261         frame->mii_data = 0;
  262         
  263         CSR_WRITE_2(sc, STE_PHYCTL, 0);
  264         /*
  265          * Turn on data xmit.
  266          */
  267         MII_SET(STE_PHYCTL_MDIR);
  268 
  269         ste_mii_sync(sc);
  270 
  271         /*
  272          * Send command/address info.
  273          */
  274         ste_mii_send(sc, frame->mii_stdelim, 2);
  275         ste_mii_send(sc, frame->mii_opcode, 2);
  276         ste_mii_send(sc, frame->mii_phyaddr, 5);
  277         ste_mii_send(sc, frame->mii_regaddr, 5);
  278 
  279         /* Turn off xmit. */
  280         MII_CLR(STE_PHYCTL_MDIR);
  281 
  282         /* Idle bit */
  283         MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
  284         DELAY(1);
  285         MII_SET(STE_PHYCTL_MCLK);
  286         DELAY(1);
  287 
  288         /* Check for ack */
  289         MII_CLR(STE_PHYCTL_MCLK);
  290         DELAY(1);
  291         ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
  292         MII_SET(STE_PHYCTL_MCLK);
  293         DELAY(1);
  294 
  295         /*
  296          * Now try reading data bits. If the ack failed, we still
  297          * need to clock through 16 cycles to keep the PHY(s) in sync.
  298          */
  299         if (ack) {
  300                 for(i = 0; i < 16; i++) {
  301                         MII_CLR(STE_PHYCTL_MCLK);
  302                         DELAY(1);
  303                         MII_SET(STE_PHYCTL_MCLK);
  304                         DELAY(1);
  305                 }
  306                 goto fail;
  307         }
  308 
  309         for (i = 0x8000; i; i >>= 1) {
  310                 MII_CLR(STE_PHYCTL_MCLK);
  311                 DELAY(1);
  312                 if (!ack) {
  313                         if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
  314                                 frame->mii_data |= i;
  315                         DELAY(1);
  316                 }
  317                 MII_SET(STE_PHYCTL_MCLK);
  318                 DELAY(1);
  319         }
  320 
  321 fail:
  322 
  323         MII_CLR(STE_PHYCTL_MCLK);
  324         DELAY(1);
  325         MII_SET(STE_PHYCTL_MCLK);
  326         DELAY(1);
  327 
  328         splx(s);
  329 
  330         if (ack)
  331                 return(1);
  332         return(0);
  333 }
  334 
  335 /*
  336  * Write to a PHY register through the MII.
  337  */
  338 static int ste_mii_writereg(sc, frame)
  339         struct ste_softc                *sc;
  340         struct ste_mii_frame    *frame;
  341         
  342 {
  343         int                     s;
  344 
  345         s = splimp();
  346         /*
  347          * Set up frame for TX.
  348          */
  349 
  350         frame->mii_stdelim = STE_MII_STARTDELIM;
  351         frame->mii_opcode = STE_MII_WRITEOP;
  352         frame->mii_turnaround = STE_MII_TURNAROUND;
  353         
  354         /*
  355          * Turn on data output.
  356          */
  357         MII_SET(STE_PHYCTL_MDIR);
  358 
  359         ste_mii_sync(sc);
  360 
  361         ste_mii_send(sc, frame->mii_stdelim, 2);
  362         ste_mii_send(sc, frame->mii_opcode, 2);
  363         ste_mii_send(sc, frame->mii_phyaddr, 5);
  364         ste_mii_send(sc, frame->mii_regaddr, 5);
  365         ste_mii_send(sc, frame->mii_turnaround, 2);
  366         ste_mii_send(sc, frame->mii_data, 16);
  367 
  368         /* Idle bit. */
  369         MII_SET(STE_PHYCTL_MCLK);
  370         DELAY(1);
  371         MII_CLR(STE_PHYCTL_MCLK);
  372         DELAY(1);
  373 
  374         /*
  375          * Turn off xmit.
  376          */
  377         MII_CLR(STE_PHYCTL_MDIR);
  378 
  379         splx(s);
  380 
  381         return(0);
  382 }
  383 
  384 static int ste_miibus_readreg(dev, phy, reg)
  385         device_t                dev;
  386         int                     phy, reg;
  387 {
  388         struct ste_softc        *sc;
  389         struct ste_mii_frame    frame;
  390 
  391         sc = device_get_softc(dev);
  392 
  393         if ( sc->ste_one_phy && phy != 0 )
  394                 return (0);
  395 
  396         bzero((char *)&frame, sizeof(frame));
  397 
  398         frame.mii_phyaddr = phy;
  399         frame.mii_regaddr = reg;
  400         ste_mii_readreg(sc, &frame);
  401 
  402         return(frame.mii_data);
  403 }
  404 
  405 static int ste_miibus_writereg(dev, phy, reg, data)
  406         device_t                dev;
  407         int                     phy, reg, data;
  408 {
  409         struct ste_softc        *sc;
  410         struct ste_mii_frame    frame;
  411 
  412         sc = device_get_softc(dev);
  413         bzero((char *)&frame, sizeof(frame));
  414 
  415         frame.mii_phyaddr = phy;
  416         frame.mii_regaddr = reg;
  417         frame.mii_data = data;
  418 
  419         ste_mii_writereg(sc, &frame);
  420 
  421         return(0);
  422 }
  423 
  424 static void ste_miibus_statchg(dev)
  425         device_t                dev;
  426 {
  427         struct ste_softc        *sc;
  428         struct mii_data         *mii;
  429         int                     i;
  430 
  431         sc = device_get_softc(dev);
  432         mii = device_get_softc(sc->ste_miibus);
  433 
  434         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
  435                 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
  436         } else {
  437                 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
  438         }
  439 
  440         STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET |
  441                     STE_ASICCTL_TX_RESET);
  442         for (i = 0; i < STE_TIMEOUT; i++) {
  443                 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
  444                         break;
  445         }
  446         if (i == STE_TIMEOUT)
  447                 printf("ste%d: rx reset never completed\n", sc->ste_unit);
  448 
  449         return;
  450 }
  451  
  452 static int ste_ifmedia_upd(ifp)
  453         struct ifnet            *ifp;
  454 {
  455         struct ste_softc        *sc;
  456         struct mii_data         *mii;
  457 
  458         sc = ifp->if_softc;
  459         mii = device_get_softc(sc->ste_miibus);
  460         sc->ste_link = 0;
  461         if (mii->mii_instance) {
  462                 struct mii_softc        *miisc;
  463                 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
  464                     miisc = LIST_NEXT(miisc, mii_list))
  465                         mii_phy_reset(miisc);
  466         }
  467         mii_mediachg(mii);
  468 
  469         return(0);
  470 }
  471 
  472 static void ste_ifmedia_sts(ifp, ifmr)
  473         struct ifnet            *ifp;
  474         struct ifmediareq       *ifmr;
  475 {
  476         struct ste_softc        *sc;
  477         struct mii_data         *mii;
  478 
  479         sc = ifp->if_softc;
  480         mii = device_get_softc(sc->ste_miibus);
  481 
  482         mii_pollstat(mii);
  483         ifmr->ifm_active = mii->mii_media_active;
  484         ifmr->ifm_status = mii->mii_media_status;
  485 
  486         return;
  487 }
  488 
  489 static void ste_wait(sc)
  490         struct ste_softc                *sc;
  491 {
  492         register int            i;
  493 
  494         for (i = 0; i < STE_TIMEOUT; i++) {
  495                 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
  496                         break;
  497         }
  498 
  499         if (i == STE_TIMEOUT)
  500                 printf("ste%d: command never completed!\n", sc->ste_unit);
  501 
  502         return;
  503 }
  504 
  505 /*
  506  * The EEPROM is slow: give it time to come ready after issuing
  507  * it a command.
  508  */
  509 static int ste_eeprom_wait(sc)
  510         struct ste_softc                *sc;
  511 {
  512         int                     i;
  513 
  514         DELAY(1000);
  515 
  516         for (i = 0; i < 100; i++) {
  517                 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
  518                         DELAY(1000);
  519                 else
  520                         break;
  521         }
  522 
  523         if (i == 100) {
  524                 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit);
  525                 return(1);
  526         }
  527 
  528         return(0);
  529 }
  530 
  531 /*
  532  * Read a sequence of words from the EEPROM. Note that ethernet address
  533  * data is stored in the EEPROM in network byte order.
  534  */
  535 static int ste_read_eeprom(sc, dest, off, cnt, swap)
  536         struct ste_softc                *sc;
  537         caddr_t                 dest;
  538         int                     off;
  539         int                     cnt;
  540         int                     swap;
  541 {
  542         int                     err = 0, i;
  543         u_int16_t               word = 0, *ptr;
  544 
  545         if (ste_eeprom_wait(sc))
  546                 return(1);
  547 
  548         for (i = 0; i < cnt; i++) {
  549                 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
  550                 err = ste_eeprom_wait(sc);
  551                 if (err)
  552                         break;
  553                 word = CSR_READ_2(sc, STE_EEPROM_DATA);
  554                 ptr = (u_int16_t *)(dest + (i * 2));
  555                 if (swap)
  556                         *ptr = ntohs(word);
  557                 else
  558                         *ptr = word;    
  559         }
  560 
  561         return(err ? 1 : 0);
  562 }
  563 
  564 static u_int8_t ste_calchash(addr)
  565         caddr_t                 addr;
  566 {
  567 
  568         u_int32_t               crc, carry;
  569         int                     i, j;
  570         u_int8_t                c;
  571 
  572         /* Compute CRC for the address value. */
  573         crc = 0xFFFFFFFF; /* initial value */
  574 
  575         for (i = 0; i < 6; i++) {
  576                 c = *(addr + i);
  577                 for (j = 0; j < 8; j++) {
  578                         carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
  579                         crc <<= 1;
  580                         c >>= 1;
  581                         if (carry)
  582                                 crc = (crc ^ 0x04c11db6) | carry;
  583                 }
  584         }
  585 
  586         /* return the filter bit position */
  587         return(crc & 0x0000003F);
  588 }
  589 
  590 static void ste_setmulti(sc)
  591         struct ste_softc        *sc;
  592 {
  593         struct ifnet            *ifp;
  594         int                     h = 0;
  595         u_int32_t               hashes[2] = { 0, 0 };
  596         struct ifmultiaddr      *ifma;
  597 
  598         ifp = &sc->arpcom.ac_if;
  599         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  600                 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
  601                 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
  602                 return;
  603         }
  604 
  605         /* first, zot all the existing hash bits */
  606         CSR_WRITE_2(sc, STE_MAR0, 0);
  607         CSR_WRITE_2(sc, STE_MAR1, 0);
  608         CSR_WRITE_2(sc, STE_MAR2, 0);
  609         CSR_WRITE_2(sc, STE_MAR3, 0);
  610 
  611         /* now program new ones */
  612         for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
  613             ifma = ifma->ifma_link.le_next) {
  614                 if (ifma->ifma_addr->sa_family != AF_LINK)
  615                         continue;
  616                 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  617                 if (h < 32)
  618                         hashes[0] |= (1 << h);
  619                 else
  620                         hashes[1] |= (1 << (h - 32));
  621         }
  622 
  623         CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
  624         CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
  625         CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
  626         CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
  627         STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
  628         STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
  629 
  630         return;
  631 }
  632 
  633 #ifdef DEVICE_POLLING
  634 static poll_handler_t ste_poll;
  635 
  636 static void
  637 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
  638 {
  639         struct ste_softc *sc = ifp->if_softc;
  640 
  641         if (!(ifp->if_capenable & IFCAP_POLLING)) {
  642                 ether_poll_deregister(ifp);
  643                 cmd = POLL_DEREGISTER;
  644         }
  645         if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
  646                 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
  647                 return;
  648         }
  649 
  650         sc->rxcycles = count;
  651         if (cmd == POLL_AND_CHECK_STATUS)
  652                 ste_rxeoc(sc);
  653         ste_rxeof(sc);
  654         ste_txeof(sc);
  655         if (ifp->if_snd.ifq_head != NULL)
  656                 ste_start(ifp);
  657 
  658         if (cmd == POLL_AND_CHECK_STATUS) {
  659                 u_int16_t status;
  660 
  661                 status = CSR_READ_2(sc, STE_ISR_ACK);
  662 
  663                 if (status & STE_ISR_TX_DONE)
  664                         ste_txeoc(sc);
  665 
  666                 if (status & STE_ISR_STATS_OFLOW) {
  667                         untimeout(ste_stats_update, sc, sc->ste_stat_ch);
  668                         ste_stats_update(sc);
  669                 }
  670 
  671                 if (status & STE_ISR_LINKEVENT)
  672                         mii_pollstat(device_get_softc(sc->ste_miibus));
  673 
  674                 if (status & STE_ISR_HOSTERR) {
  675                         ste_reset(sc);
  676                         ste_init(sc);
  677                 }
  678         }
  679 }
  680 #endif /* DEVICE_POLLING */
  681 
  682 static void ste_intr(xsc)
  683         void                    *xsc;
  684 {
  685         struct ste_softc        *sc;
  686         struct ifnet            *ifp;
  687         u_int16_t               status;
  688 
  689         sc = xsc;
  690         ifp = &sc->arpcom.ac_if;
  691 
  692 #ifdef DEVICE_POLLING
  693         if (ifp->if_ipending & IFF_POLLING)
  694                 return;
  695         if ((ifp->if_capenable & IFCAP_POLLING) &&
  696             ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */
  697                 CSR_WRITE_2(sc, STE_IMR, 0);
  698                 ste_poll(ifp, 0, 1);
  699                 return;
  700         }
  701 #endif /* DEVICE_POLLING */
  702 
  703         /* See if this is really our interrupt. */
  704         if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH))
  705                 return;
  706 
  707         for (;;) {
  708                 status = CSR_READ_2(sc, STE_ISR_ACK);
  709 
  710                 if (!(status & STE_INTRS))
  711                         break;
  712 
  713                 if (status & STE_ISR_RX_DMADONE) {
  714                         ste_rxeoc(sc);
  715                         ste_rxeof(sc);
  716                 }
  717 
  718                 if (status & STE_ISR_TX_DMADONE)
  719                         ste_txeof(sc);
  720 
  721                 if (status & STE_ISR_TX_DONE)
  722                         ste_txeoc(sc);
  723 
  724                 if (status & STE_ISR_STATS_OFLOW) {
  725                         untimeout(ste_stats_update, sc, sc->ste_stat_ch);
  726                         ste_stats_update(sc);
  727                 }
  728 
  729                 if (status & STE_ISR_LINKEVENT)
  730                         mii_pollstat(device_get_softc(sc->ste_miibus));
  731 
  732                 if (status & STE_ISR_HOSTERR) {
  733                         ste_reset(sc);
  734                         ste_init(sc);
  735                 }
  736         }
  737 
  738         /* Re-enable interrupts */
  739         CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
  740 
  741         if (ifp->if_snd.ifq_head != NULL)
  742                 ste_start(ifp);
  743 
  744         return;
  745 }
  746 
  747 static void
  748 ste_rxeoc(struct ste_softc *sc)
  749 {
  750         struct ste_chain_onefrag *cur_rx;
  751 
  752         if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
  753                 cur_rx = sc->ste_cdata.ste_rx_head;
  754                 do {
  755                         cur_rx = cur_rx->ste_next;
  756                         /* If the ring is empty, just return. */
  757                         if (cur_rx == sc->ste_cdata.ste_rx_head)
  758                                 return;
  759                 } while (cur_rx->ste_ptr->ste_status == 0);
  760                 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
  761                         /* We've fallen behind the chip: catch it. */
  762                         sc->ste_cdata.ste_rx_head = cur_rx;
  763                         ++ste_rxsyncs;
  764                 }
  765         }
  766 }
  767 
  768 /*
  769  * A frame has been uploaded: pass the resulting mbuf chain up to
  770  * the higher level protocols.
  771  */
  772 static void ste_rxeof(sc)
  773         struct ste_softc                *sc;
  774 {
  775         struct ether_header     *eh;
  776         struct mbuf             *m;
  777         struct ifnet            *ifp;
  778         struct ste_chain_onefrag        *cur_rx;
  779         int                     total_len = 0, count=0;
  780         u_int32_t               rxstat;
  781 
  782         ifp = &sc->arpcom.ac_if;
  783 
  784         while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
  785               & STE_RXSTAT_DMADONE) {
  786 #ifdef DEVICE_POLLING
  787                 if (ifp->if_ipending & IFF_POLLING) {
  788                         if (sc->rxcycles <= 0)
  789                                 break;
  790                         sc->rxcycles--;
  791                 }
  792 #endif /* DEVICE_POLLING */
  793                 if ((STE_RX_LIST_CNT - count) < 3) {
  794                         break;
  795                 }
  796 
  797                 cur_rx = sc->ste_cdata.ste_rx_head;
  798                 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
  799  
  800                 /*
  801                  * If an error occurs, update stats, clear the
  802                  * status word and leave the mbuf cluster in place:
  803                  * it should simply get re-used next time this descriptor
  804                  * comes up in the ring.
  805                  */
  806                 if (rxstat & STE_RXSTAT_FRAME_ERR) {
  807                         ifp->if_ierrors++;
  808                         cur_rx->ste_ptr->ste_status = 0;
  809                         continue;
  810                 }
  811 
  812                 /*
  813                  * If there error bit was not set, the upload complete
  814                  * bit should be set which means we have a valid packet.
  815                  * If not, something truly strange has happened.
  816                  */
  817                 if (!(rxstat & STE_RXSTAT_DMADONE)) {
  818                         printf("ste%d: bad receive status -- packet dropped",
  819                                                         sc->ste_unit);
  820                         ifp->if_ierrors++;
  821                         cur_rx->ste_ptr->ste_status = 0;
  822                         continue;
  823                 }
  824 
  825                 /* No errors; receive the packet. */    
  826                 m = cur_rx->ste_mbuf;
  827                 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
  828 
  829                 /*
  830                  * Try to conjure up a new mbuf cluster. If that
  831                  * fails, it means we have an out of memory condition and
  832                  * should leave the buffer in place and continue. This will
  833                  * result in a lost packet, but there's little else we
  834                  * can do in this situation.
  835                  */
  836                 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
  837                         ifp->if_ierrors++;
  838                         cur_rx->ste_ptr->ste_status = 0;
  839                         continue;
  840                 }
  841 
  842                 ifp->if_ipackets++;
  843                 eh = mtod(m, struct ether_header *);
  844                 m->m_pkthdr.rcvif = ifp;
  845                 m->m_pkthdr.len = m->m_len = total_len;
  846 
  847                 /* Remove header from mbuf and pass it on. */
  848                 m_adj(m, sizeof(struct ether_header));
  849                 ether_input(ifp, eh, m);
  850                 
  851                 cur_rx->ste_ptr->ste_status = 0;
  852                 count++;
  853         }
  854 
  855         return;
  856 }
  857 
  858 static void ste_txeoc(sc)
  859         struct ste_softc        *sc;
  860 {
  861         u_int8_t                txstat;
  862         struct ifnet            *ifp;
  863 
  864         ifp = &sc->arpcom.ac_if;
  865 
  866         while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
  867             STE_TXSTATUS_TXDONE) {
  868                 if (txstat & STE_TXSTATUS_UNDERRUN ||
  869                     txstat & STE_TXSTATUS_EXCESSCOLLS ||
  870                     txstat & STE_TXSTATUS_RECLAIMERR) {
  871                         ifp->if_oerrors++;
  872                         printf("ste%d: transmission error: %x\n",
  873                             sc->ste_unit, txstat);
  874 
  875                         ste_reset(sc);
  876                         ste_init(sc);
  877 
  878                         if (txstat & STE_TXSTATUS_UNDERRUN &&
  879                             sc->ste_tx_thresh < STE_PACKET_SIZE) {
  880                                 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
  881                                 printf("ste%d: tx underrun, increasing tx"
  882                                     " start threshold to %d bytes\n",
  883                                     sc->ste_unit, sc->ste_tx_thresh);
  884                         }
  885                         CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
  886                         CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
  887                             (STE_PACKET_SIZE >> 4));
  888                 }
  889                 ste_init(sc);
  890                 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
  891         }
  892 
  893         return;
  894 }
  895 
  896 static void ste_txeof(sc)
  897         struct ste_softc        *sc;
  898 {
  899         struct ste_chain        *cur_tx;
  900         struct ifnet            *ifp;
  901         int                     idx;
  902 
  903         ifp = &sc->arpcom.ac_if;
  904 
  905         idx = sc->ste_cdata.ste_tx_cons;
  906         while(idx != sc->ste_cdata.ste_tx_prod) {
  907                 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
  908 
  909                 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
  910                         break;
  911 
  912                 m_freem(cur_tx->ste_mbuf);
  913                 cur_tx->ste_mbuf = NULL;
  914                 ifp->if_flags &= ~IFF_OACTIVE;
  915                 ifp->if_opackets++;
  916 
  917                 STE_INC(idx, STE_TX_LIST_CNT);
  918         }
  919 
  920         sc->ste_cdata.ste_tx_cons = idx;
  921         if (idx == sc->ste_cdata.ste_tx_prod)
  922                 ifp->if_timer = 0;
  923 }
  924 
  925 static void ste_stats_update(xsc)
  926         void                    *xsc;
  927 {
  928         struct ste_softc        *sc;
  929         struct ifnet            *ifp;
  930         struct mii_data         *mii;
  931         int                     s;
  932 
  933         s = splimp();
  934 
  935         sc = xsc;
  936         ifp = &sc->arpcom.ac_if;
  937         mii = device_get_softc(sc->ste_miibus);
  938 
  939         ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
  940             + CSR_READ_1(sc, STE_MULTI_COLLS)
  941             + CSR_READ_1(sc, STE_SINGLE_COLLS);
  942 
  943         if (!sc->ste_link) {
  944                 mii_pollstat(mii);
  945                 if (mii->mii_media_status & IFM_ACTIVE &&
  946                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
  947                         sc->ste_link++;
  948                         /* 
  949                          * we don't get a call-back on re-init so do it 
  950                          * otherwise we get stuck in the wrong link state
  951                          */
  952                         ste_miibus_statchg(sc->ste_dev);
  953                         if (ifp->if_snd.ifq_head != NULL)
  954                                 ste_start(ifp);
  955                 }
  956         }
  957 
  958         sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
  959         splx(s);
  960 
  961         return;
  962 }
  963 
  964 
  965 /*
  966  * Probe for a Sundance ST201 chip. Check the PCI vendor and device
  967  * IDs against our list and return a device name if we find a match.
  968  */
  969 static int ste_probe(dev)
  970         device_t                dev;
  971 {
  972         struct ste_type         *t;
  973 
  974         t = ste_devs;
  975 
  976         while(t->ste_name != NULL) {
  977                 if ((pci_get_vendor(dev) == t->ste_vid) &&
  978                     (pci_get_device(dev) == t->ste_did)) {
  979                         device_set_desc(dev, t->ste_name);
  980                         return(0);
  981                 }
  982                 t++;
  983         }
  984 
  985         return(ENXIO);
  986 }
  987 
  988 /*
  989  * Attach the interface. Allocate softc structures, do ifmedia
  990  * setup and ethernet/BPF attach.
  991  */
  992 static int ste_attach(dev)
  993         device_t                dev;
  994 {
  995         int                     s;
  996         u_int32_t               command;
  997         struct ste_softc        *sc;
  998         struct ifnet            *ifp;
  999         int                     unit, error = 0, rid;
 1000 
 1001         s = splimp();
 1002 
 1003         sc = device_get_softc(dev);
 1004         unit = device_get_unit(dev);
 1005         bzero(sc, sizeof(struct ste_softc));
 1006         sc->ste_dev = dev;
 1007 
 1008         /*
 1009          * Only use one PHY since this chip reports multiple
 1010          * Note on the DFE-550 the PHY is at 1 on the DFE-580
 1011          * it is at 0 & 1.  It is rev 0x12.
 1012          */
 1013         if (pci_get_vendor(dev) == DL_VENDORID &&
 1014             pci_get_device(dev) == DL_DEVICEID_550TX &&
 1015             pci_get_revid(dev) == 0x12 )
 1016                 sc->ste_one_phy = 1;
 1017 
 1018         /*
 1019          * Handle power management nonsense.
 1020          */
 1021         command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF;
 1022         if (command == 0x01) {
 1023 
 1024                 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4);
 1025                 if (command & STE_PSTATE_MASK) {
 1026                         u_int32_t               iobase, membase, irq;
 1027 
 1028                         /* Save important PCI config data. */
 1029                         iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
 1030                         membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
 1031                         irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
 1032 
 1033                         /* Reset the power state. */
 1034                         printf("ste%d: chip is in D%d power mode "
 1035                         "-- setting to D0\n", unit, command & STE_PSTATE_MASK);
 1036                         command &= 0xFFFFFFFC;
 1037                         pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4);
 1038 
 1039                         /* Restore PCI config data. */
 1040                         pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
 1041                         pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
 1042                         pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
 1043                 }
 1044         }
 1045 
 1046         /*
 1047          * Map control/status registers.
 1048          */
 1049         command = pci_read_config(dev, PCIR_COMMAND, 4);
 1050         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
 1051         pci_write_config(dev, PCIR_COMMAND, command, 4);
 1052         command = pci_read_config(dev, PCIR_COMMAND, 4);
 1053 
 1054 #ifdef STE_USEIOSPACE
 1055         if (!(command & PCIM_CMD_PORTEN)) {
 1056                 printf("ste%d: failed to enable I/O ports!\n", unit);
 1057                 error = ENXIO;
 1058                 goto fail;
 1059         }
 1060 #else
 1061         if (!(command & PCIM_CMD_MEMEN)) {
 1062                 printf("ste%d: failed to enable memory mapping!\n", unit);
 1063                 error = ENXIO;
 1064                 goto fail;
 1065         }
 1066 #endif
 1067 
 1068         rid = STE_RID;
 1069         sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid,
 1070             0, ~0, 1, RF_ACTIVE);
 1071 
 1072         if (sc->ste_res == NULL) {
 1073                 printf ("ste%d: couldn't map ports/memory\n", unit);
 1074                 error = ENXIO;
 1075                 goto fail;
 1076         }
 1077 
 1078         sc->ste_btag = rman_get_bustag(sc->ste_res);
 1079         sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
 1080 
 1081         rid = 0;
 1082         sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
 1083             RF_SHAREABLE | RF_ACTIVE);
 1084 
 1085         if (sc->ste_irq == NULL) {
 1086                 printf("ste%d: couldn't map interrupt\n", unit);
 1087                 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
 1088                 error = ENXIO;
 1089                 goto fail;
 1090         }
 1091 
 1092         error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET,
 1093             ste_intr, sc, &sc->ste_intrhand);
 1094 
 1095         if (error) {
 1096                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
 1097                 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
 1098                 printf("ste%d: couldn't set up irq\n", unit);
 1099                 goto fail;
 1100         }
 1101 
 1102         callout_handle_init(&sc->ste_stat_ch);
 1103 
 1104         /* Reset the adapter. */
 1105         ste_reset(sc);
 1106 
 1107         /*
 1108          * Get station address from the EEPROM.
 1109          */
 1110         if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
 1111             STE_EEADDR_NODE0, 3, 0)) {
 1112                 printf("ste%d: failed to read station address\n", unit);
 1113                 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
 1114                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
 1115                 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
 1116                 error = ENXIO;;
 1117                 goto fail;
 1118         }
 1119 
 1120         /*
 1121          * A Sundance chip was detected. Inform the world.
 1122          */
 1123         printf("ste%d: Ethernet address: %6D\n", unit,
 1124             sc->arpcom.ac_enaddr, ":");
 1125 
 1126         sc->ste_unit = unit;
 1127 
 1128         /* Allocate the descriptor queues. */
 1129         sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
 1130             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 1131 
 1132         if (sc->ste_ldata == NULL) {
 1133                 printf("ste%d: no memory for list buffers!\n", unit);
 1134                 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
 1135                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
 1136                 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
 1137                 error = ENXIO;
 1138                 goto fail;
 1139         }
 1140 
 1141         bzero(sc->ste_ldata, sizeof(struct ste_list_data));
 1142 
 1143         /* Do MII setup. */
 1144         if (mii_phy_probe(dev, &sc->ste_miibus,
 1145                 ste_ifmedia_upd, ste_ifmedia_sts)) {
 1146                 printf("ste%d: MII without any phy!\n", sc->ste_unit);
 1147                 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
 1148                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
 1149                 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
 1150                 contigfree(sc->ste_ldata,
 1151                     sizeof(struct ste_list_data), M_DEVBUF);
 1152                 error = ENXIO;
 1153                 goto fail;
 1154         }
 1155 
 1156         ifp = &sc->arpcom.ac_if;
 1157         ifp->if_softc = sc;
 1158         ifp->if_unit = unit;
 1159         ifp->if_name = "ste";
 1160         ifp->if_mtu = ETHERMTU;
 1161         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1162         ifp->if_ioctl = ste_ioctl;
 1163         ifp->if_output = ether_output;
 1164         ifp->if_start = ste_start;
 1165         ifp->if_watchdog = ste_watchdog;
 1166         ifp->if_init = ste_init;
 1167         ifp->if_baudrate = 10000000;
 1168         ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1;
 1169 
 1170         sc->ste_tx_thresh = STE_TXSTART_THRESH;
 1171 
 1172         /*
 1173          * Call MI attach routine.
 1174          */
 1175         ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
 1176 
 1177         /*
 1178          * Tell the upper layer(s) we support long frames.
 1179          */
 1180         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 1181 
 1182 #ifdef DEVICE_POLLING
 1183         ifp->if_capabilities |= IFCAP_POLLING;
 1184 #endif
 1185         ifp->if_capenable = ifp->if_capabilities;
 1186  
 1187 fail:
 1188         splx(s);
 1189         return(error);
 1190 }
 1191 
 1192 static int ste_detach(dev)
 1193         device_t                dev;
 1194 {
 1195         struct ste_softc        *sc;
 1196         struct ifnet            *ifp;
 1197         int                     s;
 1198 
 1199         s = splimp();
 1200 
 1201         sc = device_get_softc(dev);
 1202         ifp = &sc->arpcom.ac_if;
 1203 
 1204         ste_stop(sc);
 1205         ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
 1206 
 1207         bus_generic_detach(dev);
 1208         device_delete_child(dev, sc->ste_miibus);
 1209 
 1210         bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
 1211         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
 1212         bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
 1213 
 1214         contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF);
 1215 
 1216         splx(s);
 1217 
 1218         return(0);
 1219 }
 1220 
 1221 static int ste_newbuf(sc, c, m)
 1222         struct ste_softc        *sc;
 1223         struct ste_chain_onefrag        *c;
 1224         struct mbuf             *m;
 1225 {
 1226         struct mbuf             *m_new = NULL;
 1227 
 1228         if (m == NULL) {
 1229                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1230                 if (m_new == NULL)
 1231                         return(ENOBUFS);
 1232                 MCLGET(m_new, M_DONTWAIT);
 1233                 if (!(m_new->m_flags & M_EXT)) {
 1234                         m_freem(m_new);
 1235                         return(ENOBUFS);
 1236                 }
 1237                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 1238         } else {
 1239                 m_new = m;
 1240                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 1241                 m_new->m_data = m_new->m_ext.ext_buf;
 1242         }
 1243 
 1244         m_adj(m_new, ETHER_ALIGN);
 1245 
 1246         c->ste_mbuf = m_new;
 1247         c->ste_ptr->ste_status = 0;
 1248         c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
 1249         c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST;
 1250 
 1251         return(0);
 1252 }
 1253 
 1254 static int ste_init_rx_list(sc)
 1255         struct ste_softc        *sc;
 1256 {
 1257         struct ste_chain_data   *cd;
 1258         struct ste_list_data    *ld;
 1259         int                     i;
 1260 
 1261         cd = &sc->ste_cdata;
 1262         ld = sc->ste_ldata;
 1263 
 1264         for (i = 0; i < STE_RX_LIST_CNT; i++) {
 1265                 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
 1266                 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
 1267                         return(ENOBUFS);
 1268                 if (i == (STE_RX_LIST_CNT - 1)) {
 1269                         cd->ste_rx_chain[i].ste_next =
 1270                             &cd->ste_rx_chain[0];
 1271                         ld->ste_rx_list[i].ste_next =
 1272                             vtophys(&ld->ste_rx_list[0]);
 1273                 } else {
 1274                         cd->ste_rx_chain[i].ste_next =
 1275                             &cd->ste_rx_chain[i + 1];
 1276                         ld->ste_rx_list[i].ste_next =
 1277                             vtophys(&ld->ste_rx_list[i + 1]);
 1278                 }
 1279                 ld->ste_rx_list[i].ste_status = 0;
 1280         }
 1281 
 1282         cd->ste_rx_head = &cd->ste_rx_chain[0];
 1283 
 1284         return(0);
 1285 }
 1286 
 1287 static void ste_init_tx_list(sc)
 1288         struct ste_softc        *sc;
 1289 {
 1290         struct ste_chain_data   *cd;
 1291         struct ste_list_data    *ld;
 1292         int                     i;
 1293 
 1294         cd = &sc->ste_cdata;
 1295         ld = sc->ste_ldata;
 1296         for (i = 0; i < STE_TX_LIST_CNT; i++) {
 1297                 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
 1298                 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
 1299                 cd->ste_tx_chain[i].ste_ptr->ste_ctl  = 0;
 1300                 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
 1301                 if (i == (STE_TX_LIST_CNT - 1))
 1302                         cd->ste_tx_chain[i].ste_next =
 1303                             &cd->ste_tx_chain[0];
 1304                 else
 1305                         cd->ste_tx_chain[i].ste_next =
 1306                             &cd->ste_tx_chain[i + 1];
 1307         }
 1308 
 1309         cd->ste_tx_prod = 0;
 1310         cd->ste_tx_cons = 0;
 1311 
 1312         return;
 1313 }
 1314 
 1315 static void ste_init(xsc)
 1316         void                    *xsc;
 1317 {
 1318         struct ste_softc        *sc;
 1319         int                     i, s;
 1320         struct ifnet            *ifp;
 1321         struct mii_data         *mii;
 1322 
 1323         s = splimp();
 1324 
 1325         sc = xsc;
 1326         ifp = &sc->arpcom.ac_if;
 1327         mii = device_get_softc(sc->ste_miibus);
 1328 
 1329         ste_stop(sc);
 1330 
 1331         /* Init our MAC address */
 1332         for (i = 0; i < ETHER_ADDR_LEN; i++) {
 1333                 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
 1334         }
 1335 
 1336         /* Init RX list */
 1337         if (ste_init_rx_list(sc) == ENOBUFS) {
 1338                 printf("ste%d: initialization failed: no "
 1339                     "memory for RX buffers\n", sc->ste_unit);
 1340                 ste_stop(sc);
 1341                 splx(s);
 1342                 return;
 1343         }
 1344 
 1345         /* Set RX polling interval */
 1346         CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
 1347 
 1348         /* Init TX descriptors */
 1349         ste_init_tx_list(sc);
 1350 
 1351         /* Set the TX freethresh value */
 1352         CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
 1353 
 1354         /* Set the TX start threshold for best performance. */
 1355         CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
 1356 
 1357         /* Set the TX reclaim threshold. */
 1358         CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
 1359 
 1360         /* Set up the RX filter. */
 1361         CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
 1362 
 1363         /* If we want promiscuous mode, set the allframes bit. */
 1364         if (ifp->if_flags & IFF_PROMISC) {
 1365                 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
 1366         } else {
 1367                 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
 1368         }
 1369 
 1370         /* Set capture broadcast bit to accept broadcast frames. */
 1371         if (ifp->if_flags & IFF_BROADCAST) {
 1372                 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
 1373         } else {
 1374                 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
 1375         }
 1376 
 1377         ste_setmulti(sc);
 1378 
 1379         /* Load the address of the RX list. */
 1380         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
 1381         ste_wait(sc);
 1382         CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
 1383             vtophys(&sc->ste_ldata->ste_rx_list[0]));
 1384         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
 1385         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
 1386 
 1387         /* Set TX polling interval (defer until we TX first packet */
 1388         CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
 1389 
 1390         /* Load address of the TX list */
 1391         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
 1392         ste_wait(sc);
 1393         CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
 1394         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
 1395         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
 1396         ste_wait(sc);
 1397         sc->ste_tx_prev = NULL;
 1398 
 1399         /* Enable receiver and transmitter */
 1400         CSR_WRITE_2(sc, STE_MACCTL0, 0);
 1401         CSR_WRITE_2(sc, STE_MACCTL1, 0);
 1402         STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
 1403         STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
 1404 
 1405         /* Enable stats counters. */
 1406         STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
 1407 
 1408         CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
 1409 #ifdef DEVICE_POLLING
 1410         /* Disable interrupts if we are polling. */
 1411         if (ifp->if_ipending & IFF_POLLING)
 1412                 CSR_WRITE_2(sc, STE_IMR, 0);
 1413         else   
 1414 #endif /* DEVICE_POLLING */
 1415         /* Enable interrupts. */
 1416         CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
 1417 
 1418         /* Accept VLAN length packets */
 1419         CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN);
 1420 
 1421         ste_ifmedia_upd(ifp);
 1422 
 1423         ifp->if_flags |= IFF_RUNNING;
 1424         ifp->if_flags &= ~IFF_OACTIVE;
 1425 
 1426         splx(s);
 1427 
 1428         sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
 1429 
 1430         return;
 1431 }
 1432 
 1433 static void ste_stop(sc)
 1434         struct ste_softc        *sc;
 1435 {
 1436         int                     i;
 1437         struct ifnet            *ifp;
 1438 
 1439         ifp = &sc->arpcom.ac_if;
 1440 
 1441         untimeout(ste_stats_update, sc, sc->ste_stat_ch);
 1442         ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
 1443 #ifdef DEVICE_POLLING
 1444         ether_poll_deregister(ifp);
 1445 #endif /* DEVICE_POLLING */
 1446 
 1447         CSR_WRITE_2(sc, STE_IMR, 0);
 1448         STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
 1449         STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
 1450         STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
 1451         STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
 1452         STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
 1453         ste_wait(sc);
 1454         /* 
 1455          * Try really hard to stop the RX engine or under heavy RX 
 1456          * data chip will write into de-allocated memory.
 1457          */
 1458         ste_reset(sc);
 1459 
 1460         sc->ste_link = 0;
 1461 
 1462         for (i = 0; i < STE_RX_LIST_CNT; i++) {
 1463                 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
 1464                         m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
 1465                         sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
 1466                 }
 1467         }
 1468 
 1469         for (i = 0; i < STE_TX_LIST_CNT; i++) {
 1470                 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
 1471                         m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
 1472                         sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
 1473                 }
 1474         }
 1475 
 1476         bzero(sc->ste_ldata, sizeof(struct ste_list_data));
 1477 
 1478         return;
 1479 }
 1480 
 1481 static void ste_reset(sc)
 1482         struct ste_softc        *sc;
 1483 {
 1484         int                     i;
 1485 
 1486         STE_SETBIT4(sc, STE_ASICCTL,
 1487             STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
 1488             STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
 1489             STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
 1490             STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
 1491             STE_ASICCTL_EXTRESET_RESET);
 1492 
 1493         DELAY(100000);
 1494 
 1495         for (i = 0; i < STE_TIMEOUT; i++) {
 1496                 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
 1497                         break;
 1498         }
 1499 
 1500         if (i == STE_TIMEOUT)
 1501                 printf("ste%d: global reset never completed\n", sc->ste_unit);
 1502 
 1503         return;
 1504 }
 1505 
 1506 static int ste_ioctl(ifp, command, data)
 1507         struct ifnet            *ifp;
 1508         u_long                  command;
 1509         caddr_t                 data;
 1510 {
 1511         struct ste_softc        *sc;
 1512         struct ifreq            *ifr;
 1513         struct mii_data         *mii;
 1514         int                     error = 0, s;
 1515 
 1516         s = splimp();
 1517 
 1518         sc = ifp->if_softc;
 1519         ifr = (struct ifreq *)data;
 1520 
 1521         switch(command) {
 1522         case SIOCSIFADDR:
 1523         case SIOCGIFADDR:
 1524         case SIOCSIFMTU:
 1525                 error = ether_ioctl(ifp, command, data);
 1526                 break;
 1527         case SIOCSIFFLAGS:
 1528                 if (ifp->if_flags & IFF_UP) {
 1529                         if (ifp->if_flags & IFF_RUNNING &&
 1530                             ifp->if_flags & IFF_PROMISC &&
 1531                             !(sc->ste_if_flags & IFF_PROMISC)) {
 1532                                 STE_SETBIT1(sc, STE_RX_MODE,
 1533                                     STE_RXMODE_PROMISC);
 1534                         } else if (ifp->if_flags & IFF_RUNNING &&
 1535                             !(ifp->if_flags & IFF_PROMISC) &&
 1536                             sc->ste_if_flags & IFF_PROMISC) {
 1537                                 STE_CLRBIT1(sc, STE_RX_MODE,
 1538                                     STE_RXMODE_PROMISC);
 1539                         } 
 1540                         if (ifp->if_flags & IFF_RUNNING &&
 1541                             (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI)
 1542                                 ste_setmulti(sc);
 1543                         if (!(ifp->if_flags & IFF_RUNNING)) {
 1544                                 sc->ste_tx_thresh = STE_TXSTART_THRESH;
 1545                                 ste_init(sc);
 1546                         }
 1547                 } else {
 1548                         if (ifp->if_flags & IFF_RUNNING)
 1549                                 ste_stop(sc);
 1550                 }
 1551                 sc->ste_if_flags = ifp->if_flags;
 1552                 error = 0;
 1553                 break;
 1554         case SIOCADDMULTI:
 1555         case SIOCDELMULTI:
 1556                 ste_setmulti(sc);
 1557                 error = 0;
 1558                 break;
 1559         case SIOCGIFMEDIA:
 1560         case SIOCSIFMEDIA:
 1561                 mii = device_get_softc(sc->ste_miibus);
 1562                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1563                 break;
 1564         case SIOCSIFCAP:
 1565                 ifp->if_capenable = ifr->ifr_reqcap;
 1566                 break;
 1567         default:
 1568                 error = EINVAL;
 1569                 break;
 1570         }
 1571 
 1572         splx(s);
 1573 
 1574         return(error);
 1575 }
 1576 
 1577 static int ste_encap(sc, c, m_head)
 1578         struct ste_softc        *sc;
 1579         struct ste_chain        *c;
 1580         struct mbuf             *m_head;
 1581 {
 1582         int                     frag = 0;
 1583         struct ste_frag         *f = NULL;
 1584         struct mbuf             *m;
 1585         struct ste_desc         *d;
 1586         int                     total_len = 0;
 1587 
 1588         d = c->ste_ptr;
 1589         d->ste_ctl = 0;
 1590 
 1591 encap_retry:
 1592         for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
 1593                 if (m->m_len != 0) {
 1594                         if (frag == STE_MAXFRAGS)
 1595                                 break;
 1596                         total_len += m->m_len;
 1597                         f = &d->ste_frags[frag];
 1598                         f->ste_addr = vtophys(mtod(m, vm_offset_t));
 1599                         f->ste_len = m->m_len;
 1600                         frag++;
 1601                 }
 1602         }
 1603 
 1604         if (m != NULL) {
 1605                 struct mbuf *mn;
 1606 
 1607                 /*
 1608                  * We ran out of segments. We have to recopy this
 1609                  * mbuf chain first. Bail out if we can't get the
 1610                  * new buffers.
 1611                  */
 1612                 mn = m_defrag(m_head, M_DONTWAIT);
 1613                 if (mn == NULL) {
 1614                         m_freem(m_head);
 1615                         return ENOMEM;
 1616                 }
 1617                 m_head = mn;
 1618                 goto encap_retry;
 1619         }
 1620 
 1621         c->ste_mbuf = m_head;
 1622         d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
 1623         d->ste_ctl = 1;
 1624 
 1625         return(0);
 1626 }
 1627 
 1628 static void ste_start(ifp)
 1629         struct ifnet            *ifp;
 1630 {
 1631         struct ste_softc        *sc;
 1632         struct mbuf             *m_head = NULL;
 1633         struct ste_chain        *cur_tx;
 1634         int                     idx;
 1635 
 1636         sc = ifp->if_softc;
 1637 
 1638         if (!sc->ste_link)
 1639                 return;
 1640 
 1641         if (ifp->if_flags & IFF_OACTIVE)
 1642                 return;
 1643 
 1644         idx = sc->ste_cdata.ste_tx_prod;
 1645 
 1646         while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
 1647                 /*
 1648                  * We cannot re-use the last (free) descriptor;
 1649                  * the chip may not have read its ste_next yet.
 1650                  */
 1651                 if (STE_NEXT(idx, STE_TX_LIST_CNT) ==
 1652                     sc->ste_cdata.ste_tx_cons) {
 1653                         ifp->if_flags |= IFF_OACTIVE;
 1654                         break;
 1655                 }
 1656 
 1657                 IF_DEQUEUE(&ifp->if_snd, m_head);
 1658                 if (m_head == NULL)
 1659                         break;
 1660 
 1661                 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
 1662 
 1663                 if (ste_encap(sc, cur_tx, m_head) != 0)
 1664                         break;
 1665 
 1666                 cur_tx->ste_ptr->ste_next = 0;
 1667 
 1668                 if (sc->ste_tx_prev == NULL) {
 1669                         cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
 1670                         /* Load address of the TX list */
 1671                         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
 1672                         ste_wait(sc);
 1673 
 1674                         CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
 1675                             vtophys(&sc->ste_ldata->ste_tx_list[0]));
 1676 
 1677                         /* Set TX polling interval to start TX engine */
 1678                         CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
 1679                   
 1680                         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
 1681                         ste_wait(sc);
 1682                 }else{
 1683                         cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
 1684                         sc->ste_tx_prev->ste_ptr->ste_next
 1685                                 = cur_tx->ste_phys;
 1686                 }
 1687 
 1688                 sc->ste_tx_prev = cur_tx;
 1689 
 1690                 /*
 1691                  * If there's a BPF listener, bounce a copy of this frame
 1692                  * to him.
 1693                  */
 1694                 if (ifp->if_bpf)
 1695                         bpf_mtap(ifp, cur_tx->ste_mbuf);
 1696 
 1697                 STE_INC(idx, STE_TX_LIST_CNT);
 1698                 ifp->if_timer = 5;
 1699         }
 1700         sc->ste_cdata.ste_tx_prod = idx;
 1701 
 1702         return;
 1703 }
 1704 
 1705 static void ste_watchdog(ifp)
 1706         struct ifnet            *ifp;
 1707 {
 1708         struct ste_softc        *sc;
 1709 
 1710         sc = ifp->if_softc;
 1711 
 1712         ifp->if_oerrors++;
 1713         printf("ste%d: watchdog timeout\n", sc->ste_unit);
 1714 
 1715         ste_txeoc(sc);
 1716         ste_txeof(sc);
 1717         ste_rxeoc(sc);
 1718         ste_rxeof(sc);
 1719         ste_reset(sc);
 1720         ste_init(sc);
 1721 
 1722         if (ifp->if_snd.ifq_head != NULL)
 1723                 ste_start(ifp);
 1724 
 1725         return;
 1726 }
 1727 
 1728 static void ste_shutdown(dev)
 1729         device_t                dev;
 1730 {
 1731         struct ste_softc        *sc;
 1732 
 1733         sc = device_get_softc(dev);
 1734 
 1735         ste_stop(sc);
 1736 
 1737         return;
 1738 }

Cache object: e96c057b7b3029cae98adde8def9b154


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.