Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_ste.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: releng/5.0/sys/pci/if_ste.c 108566 2003-01-02 20:02:44Z phk $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 43 #include <net/if.h> 44 #include <net/if_arp.h> 45 #include <net/ethernet.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 #include <net/if_vlan_var.h> 49 50 #include <net/bpf.h> 51 52 #include <vm/vm.h> /* for vtophys */ 53 #include <vm/pmap.h> /* for vtophys */ 54 #include <machine/bus_memio.h> 55 #include <machine/bus_pio.h> 56 #include <machine/bus.h> 57 #include <machine/resource.h> 58 #include <sys/bus.h> 59 #include <sys/rman.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #include <pci/pcireg.h> 65 #include <pci/pcivar.h> 66 67 /* "controller miibus0" required. See GENERIC if you get errors here. */ 68 #include "miibus_if.h" 69 70 #define STE_USEIOSPACE 71 72 #include <pci/if_stereg.h> 73 74 MODULE_DEPEND(ste, miibus, 1, 1, 1); 75 76 #if !defined(lint) 77 static const char rcsid[] = 78 "$FreeBSD: releng/5.0/sys/pci/if_ste.c 108566 2003-01-02 20:02:44Z phk $"; 79 #endif 80 81 /* 82 * Various supported device vendors/types and their names. 83 */ 84 static struct ste_type ste_devs[] = { 85 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 86 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 87 { 0, 0, NULL } 88 }; 89 90 static int ste_probe (device_t); 91 static int ste_attach (device_t); 92 static int ste_detach (device_t); 93 static void ste_init (void *); 94 static void ste_intr (void *); 95 static void ste_rxeof (struct ste_softc *); 96 static void ste_txeoc (struct ste_softc *); 97 static void ste_txeof (struct ste_softc *); 98 static void ste_stats_update (void *); 99 static void ste_stop (struct ste_softc *); 100 static void ste_reset (struct ste_softc *); 101 static int ste_ioctl (struct ifnet *, u_long, caddr_t); 102 static int ste_encap (struct ste_softc *, struct ste_chain *, 103 struct mbuf *); 104 static void ste_start (struct ifnet *); 105 static void ste_watchdog (struct ifnet *); 106 static void ste_shutdown (device_t); 107 static int ste_newbuf (struct ste_softc *, 108 struct ste_chain_onefrag *, 109 struct mbuf *); 110 static int ste_ifmedia_upd (struct ifnet *); 111 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 113 static void ste_mii_sync (struct ste_softc *); 114 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 115 static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 116 static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 117 static int ste_miibus_readreg (device_t, int, int); 118 static int ste_miibus_writereg (device_t, int, int, int); 119 static void ste_miibus_statchg (device_t); 120 121 static int ste_eeprom_wait (struct ste_softc *); 122 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 123 static void ste_wait (struct ste_softc *); 124 static u_int8_t ste_calchash (caddr_t); 125 static void ste_setmulti (struct ste_softc *); 126 static int ste_init_rx_list (struct ste_softc *); 127 static void ste_init_tx_list (struct ste_softc *); 128 129 #ifdef STE_USEIOSPACE 130 #define STE_RES SYS_RES_IOPORT 131 #define STE_RID STE_PCI_LOIO 132 #else 133 #define STE_RES SYS_RES_MEMORY 134 #define STE_RID STE_PCI_LOMEM 135 #endif 136 137 static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154 }; 155 156 static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160 }; 161 162 static devclass_t ste_devclass; 163 164 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 165 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167 #define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 169 170 #define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 172 173 #define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 175 176 #define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 178 179 #define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 181 182 #define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 184 185 186 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189 /* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192 static void 193 ste_mii_sync(sc) 194 struct ste_softc *sc; 195 { 196 register int i; 197 198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 199 200 for (i = 0; i < 32; i++) { 201 MII_SET(STE_PHYCTL_MCLK); 202 DELAY(1); 203 MII_CLR(STE_PHYCTL_MCLK); 204 DELAY(1); 205 } 206 207 return; 208 } 209 210 /* 211 * Clock a series of bits through the MII. 212 */ 213 static void 214 ste_mii_send(sc, bits, cnt) 215 struct ste_softc *sc; 216 u_int32_t bits; 217 int cnt; 218 { 219 int i; 220 221 MII_CLR(STE_PHYCTL_MCLK); 222 223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 224 if (bits & i) { 225 MII_SET(STE_PHYCTL_MDATA); 226 } else { 227 MII_CLR(STE_PHYCTL_MDATA); 228 } 229 DELAY(1); 230 MII_CLR(STE_PHYCTL_MCLK); 231 DELAY(1); 232 MII_SET(STE_PHYCTL_MCLK); 233 } 234 } 235 236 /* 237 * Read an PHY register through the MII. 238 */ 239 static int 240 ste_mii_readreg(sc, frame) 241 struct ste_softc *sc; 242 struct ste_mii_frame *frame; 243 244 { 245 int i, ack; 246 247 STE_LOCK(sc); 248 249 /* 250 * Set up frame for RX. 251 */ 252 frame->mii_stdelim = STE_MII_STARTDELIM; 253 frame->mii_opcode = STE_MII_READOP; 254 frame->mii_turnaround = 0; 255 frame->mii_data = 0; 256 257 CSR_WRITE_2(sc, STE_PHYCTL, 0); 258 /* 259 * Turn on data xmit. 260 */ 261 MII_SET(STE_PHYCTL_MDIR); 262 263 ste_mii_sync(sc); 264 265 /* 266 * Send command/address info. 267 */ 268 ste_mii_send(sc, frame->mii_stdelim, 2); 269 ste_mii_send(sc, frame->mii_opcode, 2); 270 ste_mii_send(sc, frame->mii_phyaddr, 5); 271 ste_mii_send(sc, frame->mii_regaddr, 5); 272 273 /* Turn off xmit. */ 274 MII_CLR(STE_PHYCTL_MDIR); 275 276 /* Idle bit */ 277 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 278 DELAY(1); 279 MII_SET(STE_PHYCTL_MCLK); 280 DELAY(1); 281 282 /* Check for ack */ 283 MII_CLR(STE_PHYCTL_MCLK); 284 DELAY(1); 285 MII_SET(STE_PHYCTL_MCLK); 286 DELAY(1); 287 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 288 289 /* 290 * Now try reading data bits. If the ack failed, we still 291 * need to clock through 16 cycles to keep the PHY(s) in sync. 292 */ 293 if (ack) { 294 for(i = 0; i < 16; i++) { 295 MII_CLR(STE_PHYCTL_MCLK); 296 DELAY(1); 297 MII_SET(STE_PHYCTL_MCLK); 298 DELAY(1); 299 } 300 goto fail; 301 } 302 303 for (i = 0x8000; i; i >>= 1) { 304 MII_CLR(STE_PHYCTL_MCLK); 305 DELAY(1); 306 if (!ack) { 307 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 308 frame->mii_data |= i; 309 DELAY(1); 310 } 311 MII_SET(STE_PHYCTL_MCLK); 312 DELAY(1); 313 } 314 315 fail: 316 317 MII_CLR(STE_PHYCTL_MCLK); 318 DELAY(1); 319 MII_SET(STE_PHYCTL_MCLK); 320 DELAY(1); 321 322 STE_UNLOCK(sc); 323 324 if (ack) 325 return(1); 326 return(0); 327 } 328 329 /* 330 * Write to a PHY register through the MII. 331 */ 332 static int 333 ste_mii_writereg(sc, frame) 334 struct ste_softc *sc; 335 struct ste_mii_frame *frame; 336 337 { 338 STE_LOCK(sc); 339 340 /* 341 * Set up frame for TX. 342 */ 343 344 frame->mii_stdelim = STE_MII_STARTDELIM; 345 frame->mii_opcode = STE_MII_WRITEOP; 346 frame->mii_turnaround = STE_MII_TURNAROUND; 347 348 /* 349 * Turn on data output. 350 */ 351 MII_SET(STE_PHYCTL_MDIR); 352 353 ste_mii_sync(sc); 354 355 ste_mii_send(sc, frame->mii_stdelim, 2); 356 ste_mii_send(sc, frame->mii_opcode, 2); 357 ste_mii_send(sc, frame->mii_phyaddr, 5); 358 ste_mii_send(sc, frame->mii_regaddr, 5); 359 ste_mii_send(sc, frame->mii_turnaround, 2); 360 ste_mii_send(sc, frame->mii_data, 16); 361 362 /* Idle bit. */ 363 MII_SET(STE_PHYCTL_MCLK); 364 DELAY(1); 365 MII_CLR(STE_PHYCTL_MCLK); 366 DELAY(1); 367 368 /* 369 * Turn off xmit. 370 */ 371 MII_CLR(STE_PHYCTL_MDIR); 372 373 STE_UNLOCK(sc); 374 375 return(0); 376 } 377 378 static int 379 ste_miibus_readreg(dev, phy, reg) 380 device_t dev; 381 int phy, reg; 382 { 383 struct ste_softc *sc; 384 struct ste_mii_frame frame; 385 386 sc = device_get_softc(dev); 387 388 if ( sc->ste_one_phy && phy != 0 ) 389 return (0); 390 391 bzero((char *)&frame, sizeof(frame)); 392 393 frame.mii_phyaddr = phy; 394 frame.mii_regaddr = reg; 395 ste_mii_readreg(sc, &frame); 396 397 return(frame.mii_data); 398 } 399 400 static int 401 ste_miibus_writereg(dev, phy, reg, data) 402 device_t dev; 403 int phy, reg, data; 404 { 405 struct ste_softc *sc; 406 struct ste_mii_frame frame; 407 408 sc = device_get_softc(dev); 409 bzero((char *)&frame, sizeof(frame)); 410 411 frame.mii_phyaddr = phy; 412 frame.mii_regaddr = reg; 413 frame.mii_data = data; 414 415 ste_mii_writereg(sc, &frame); 416 417 return(0); 418 } 419 420 static void 421 ste_miibus_statchg(dev) 422 device_t dev; 423 { 424 struct ste_softc *sc; 425 struct mii_data *mii; 426 427 sc = device_get_softc(dev); 428 STE_LOCK(sc); 429 mii = device_get_softc(sc->ste_miibus); 430 431 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 432 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } else { 434 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 435 } 436 STE_UNLOCK(sc); 437 438 return; 439 } 440 441 static int 442 ste_ifmedia_upd(ifp) 443 struct ifnet *ifp; 444 { 445 struct ste_softc *sc; 446 struct mii_data *mii; 447 448 sc = ifp->if_softc; 449 mii = device_get_softc(sc->ste_miibus); 450 sc->ste_link = 0; 451 if (mii->mii_instance) { 452 struct mii_softc *miisc; 453 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 454 mii_phy_reset(miisc); 455 } 456 mii_mediachg(mii); 457 458 return(0); 459 } 460 461 static void 462 ste_ifmedia_sts(ifp, ifmr) 463 struct ifnet *ifp; 464 struct ifmediareq *ifmr; 465 { 466 struct ste_softc *sc; 467 struct mii_data *mii; 468 469 sc = ifp->if_softc; 470 mii = device_get_softc(sc->ste_miibus); 471 472 mii_pollstat(mii); 473 ifmr->ifm_active = mii->mii_media_active; 474 ifmr->ifm_status = mii->mii_media_status; 475 476 return; 477 } 478 479 static void 480 ste_wait(sc) 481 struct ste_softc *sc; 482 { 483 register int i; 484 485 for (i = 0; i < STE_TIMEOUT; i++) { 486 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 487 break; 488 } 489 490 if (i == STE_TIMEOUT) 491 printf("ste%d: command never completed!\n", sc->ste_unit); 492 493 return; 494 } 495 496 /* 497 * The EEPROM is slow: give it time to come ready after issuing 498 * it a command. 499 */ 500 static int 501 ste_eeprom_wait(sc) 502 struct ste_softc *sc; 503 { 504 int i; 505 506 DELAY(1000); 507 508 for (i = 0; i < 100; i++) { 509 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 510 DELAY(1000); 511 else 512 break; 513 } 514 515 if (i == 100) { 516 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 517 return(1); 518 } 519 520 return(0); 521 } 522 523 /* 524 * Read a sequence of words from the EEPROM. Note that ethernet address 525 * data is stored in the EEPROM in network byte order. 526 */ 527 static int 528 ste_read_eeprom(sc, dest, off, cnt, swap) 529 struct ste_softc *sc; 530 caddr_t dest; 531 int off; 532 int cnt; 533 int swap; 534 { 535 int err = 0, i; 536 u_int16_t word = 0, *ptr; 537 538 if (ste_eeprom_wait(sc)) 539 return(1); 540 541 for (i = 0; i < cnt; i++) { 542 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 543 err = ste_eeprom_wait(sc); 544 if (err) 545 break; 546 word = CSR_READ_2(sc, STE_EEPROM_DATA); 547 ptr = (u_int16_t *)(dest + (i * 2)); 548 if (swap) 549 *ptr = ntohs(word); 550 else 551 *ptr = word; 552 } 553 554 return(err ? 1 : 0); 555 } 556 557 static u_int8_t 558 ste_calchash(addr) 559 caddr_t addr; 560 { 561 562 u_int32_t crc, carry; 563 int i, j; 564 u_int8_t c; 565 566 /* Compute CRC for the address value. */ 567 crc = 0xFFFFFFFF; /* initial value */ 568 569 for (i = 0; i < 6; i++) { 570 c = *(addr + i); 571 for (j = 0; j < 8; j++) { 572 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 573 crc <<= 1; 574 c >>= 1; 575 if (carry) 576 crc = (crc ^ 0x04c11db6) | carry; 577 } 578 } 579 580 /* return the filter bit position */ 581 return(crc & 0x0000003F); 582 } 583 584 static void 585 ste_setmulti(sc) 586 struct ste_softc *sc; 587 { 588 struct ifnet *ifp; 589 int h = 0; 590 u_int32_t hashes[2] = { 0, 0 }; 591 struct ifmultiaddr *ifma; 592 593 ifp = &sc->arpcom.ac_if; 594 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 595 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 596 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 597 return; 598 } 599 600 /* first, zot all the existing hash bits */ 601 CSR_WRITE_2(sc, STE_MAR0, 0); 602 CSR_WRITE_2(sc, STE_MAR1, 0); 603 CSR_WRITE_2(sc, STE_MAR2, 0); 604 CSR_WRITE_2(sc, STE_MAR3, 0); 605 606 /* now program new ones */ 607 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 608 if (ifma->ifma_addr->sa_family != AF_LINK) 609 continue; 610 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 611 if (h < 32) 612 hashes[0] |= (1 << h); 613 else 614 hashes[1] |= (1 << (h - 32)); 615 } 616 617 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 619 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 620 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 621 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 622 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 623 624 return; 625 } 626 627 static void 628 ste_intr(xsc) 629 void *xsc; 630 { 631 struct ste_softc *sc; 632 struct ifnet *ifp; 633 u_int16_t status; 634 635 sc = xsc; 636 STE_LOCK(sc); 637 ifp = &sc->arpcom.ac_if; 638 639 /* See if this is really our interrupt. */ 640 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 641 STE_UNLOCK(sc); 642 return; 643 } 644 645 for (;;) { 646 status = CSR_READ_2(sc, STE_ISR_ACK); 647 648 if (!(status & STE_INTRS)) 649 break; 650 651 if (status & STE_ISR_RX_DMADONE) 652 ste_rxeof(sc); 653 654 if (status & STE_ISR_TX_DMADONE) 655 ste_txeof(sc); 656 657 if (status & STE_ISR_TX_DONE) 658 ste_txeoc(sc); 659 660 if (status & STE_ISR_STATS_OFLOW) { 661 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 662 ste_stats_update(sc); 663 } 664 665 if (status & STE_ISR_LINKEVENT) 666 mii_pollstat(device_get_softc(sc->ste_miibus)); 667 668 669 if (status & STE_ISR_HOSTERR) { 670 ste_reset(sc); 671 ste_init(sc); 672 } 673 } 674 675 /* Re-enable interrupts */ 676 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 677 678 if (ifp->if_snd.ifq_head != NULL) 679 ste_start(ifp); 680 681 STE_UNLOCK(sc); 682 683 return; 684 } 685 686 /* 687 * A frame has been uploaded: pass the resulting mbuf chain up to 688 * the higher level protocols. 689 */ 690 static void 691 ste_rxeof(sc) 692 struct ste_softc *sc; 693 { 694 struct mbuf *m; 695 struct ifnet *ifp; 696 struct ste_chain_onefrag *cur_rx; 697 int total_len = 0, count=0; 698 u_int32_t rxstat; 699 700 ifp = &sc->arpcom.ac_if; 701 702 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 703 & STE_RXSTAT_DMADONE) { 704 if ((STE_RX_LIST_CNT - count) < 3) { 705 break; 706 } 707 708 cur_rx = sc->ste_cdata.ste_rx_head; 709 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 710 711 /* 712 * If an error occurs, update stats, clear the 713 * status word and leave the mbuf cluster in place: 714 * it should simply get re-used next time this descriptor 715 * comes up in the ring. 716 */ 717 if (rxstat & STE_RXSTAT_FRAME_ERR) { 718 ifp->if_ierrors++; 719 cur_rx->ste_ptr->ste_status = 0; 720 continue; 721 } 722 723 /* 724 * If there error bit was not set, the upload complete 725 * bit should be set which means we have a valid packet. 726 * If not, something truly strange has happened. 727 */ 728 if (!(rxstat & STE_RXSTAT_DMADONE)) { 729 printf("ste%d: bad receive status -- packet dropped\n", 730 sc->ste_unit); 731 ifp->if_ierrors++; 732 cur_rx->ste_ptr->ste_status = 0; 733 continue; 734 } 735 736 /* No errors; receive the packet. */ 737 m = cur_rx->ste_mbuf; 738 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 739 740 /* 741 * Try to conjure up a new mbuf cluster. If that 742 * fails, it means we have an out of memory condition and 743 * should leave the buffer in place and continue. This will 744 * result in a lost packet, but there's little else we 745 * can do in this situation. 746 */ 747 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 748 ifp->if_ierrors++; 749 cur_rx->ste_ptr->ste_status = 0; 750 continue; 751 } 752 753 m->m_pkthdr.rcvif = ifp; 754 m->m_pkthdr.len = m->m_len = total_len; 755 756 ifp->if_ipackets++; 757 (*ifp->if_input)(ifp, m); 758 759 cur_rx->ste_ptr->ste_status = 0; 760 count++; 761 } 762 763 return; 764 } 765 766 static void 767 ste_txeoc(sc) 768 struct ste_softc *sc; 769 { 770 u_int8_t txstat; 771 struct ifnet *ifp; 772 773 ifp = &sc->arpcom.ac_if; 774 775 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 776 STE_TXSTATUS_TXDONE) { 777 if (txstat & STE_TXSTATUS_UNDERRUN || 778 txstat & STE_TXSTATUS_EXCESSCOLLS || 779 txstat & STE_TXSTATUS_RECLAIMERR) { 780 ifp->if_oerrors++; 781 printf("ste%d: transmission error: %x\n", 782 sc->ste_unit, txstat); 783 784 ste_reset(sc); 785 ste_init(sc); 786 787 if (txstat & STE_TXSTATUS_UNDERRUN && 788 sc->ste_tx_thresh < STE_PACKET_SIZE) { 789 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 790 printf("ste%d: tx underrun, increasing tx" 791 " start threshold to %d bytes\n", 792 sc->ste_unit, sc->ste_tx_thresh); 793 } 794 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 795 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 796 (STE_PACKET_SIZE >> 4)); 797 } 798 ste_init(sc); 799 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 800 } 801 802 return; 803 } 804 805 static void 806 ste_txeof(sc) 807 struct ste_softc *sc; 808 { 809 struct ste_chain *cur_tx = NULL; 810 struct ifnet *ifp; 811 int idx; 812 813 ifp = &sc->arpcom.ac_if; 814 815 idx = sc->ste_cdata.ste_tx_cons; 816 while(idx != sc->ste_cdata.ste_tx_prod) { 817 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 818 819 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 820 break; 821 822 if (cur_tx->ste_mbuf != NULL) { 823 m_freem(cur_tx->ste_mbuf); 824 cur_tx->ste_mbuf = NULL; 825 } 826 827 ifp->if_opackets++; 828 829 sc->ste_cdata.ste_tx_cnt--; 830 STE_INC(idx, STE_TX_LIST_CNT); 831 ifp->if_timer = 0; 832 } 833 834 sc->ste_cdata.ste_tx_cons = idx; 835 836 if (cur_tx != NULL) 837 ifp->if_flags &= ~IFF_OACTIVE; 838 839 return; 840 } 841 842 static void 843 ste_stats_update(xsc) 844 void *xsc; 845 { 846 struct ste_softc *sc; 847 struct ifnet *ifp; 848 struct mii_data *mii; 849 850 sc = xsc; 851 STE_LOCK(sc); 852 853 ifp = &sc->arpcom.ac_if; 854 mii = device_get_softc(sc->ste_miibus); 855 856 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 857 + CSR_READ_1(sc, STE_MULTI_COLLS) 858 + CSR_READ_1(sc, STE_SINGLE_COLLS); 859 860 if (!sc->ste_link) { 861 mii_pollstat(mii); 862 if (mii->mii_media_status & IFM_ACTIVE && 863 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 864 sc->ste_link++; 865 /* 866 * we don't get a call-back on re-init so do it 867 * otherwise we get stuck in the wrong link state 868 */ 869 ste_miibus_statchg(sc->ste_dev); 870 if (ifp->if_snd.ifq_head != NULL) 871 ste_start(ifp); 872 } 873 } 874 875 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 876 STE_UNLOCK(sc); 877 878 return; 879 } 880 881 882 /* 883 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 884 * IDs against our list and return a device name if we find a match. 885 */ 886 static int 887 ste_probe(dev) 888 device_t dev; 889 { 890 struct ste_type *t; 891 892 t = ste_devs; 893 894 while(t->ste_name != NULL) { 895 if ((pci_get_vendor(dev) == t->ste_vid) && 896 (pci_get_device(dev) == t->ste_did)) { 897 device_set_desc(dev, t->ste_name); 898 return(0); 899 } 900 t++; 901 } 902 903 return(ENXIO); 904 } 905 906 /* 907 * Attach the interface. Allocate softc structures, do ifmedia 908 * setup and ethernet/BPF attach. 909 */ 910 static int 911 ste_attach(dev) 912 device_t dev; 913 { 914 u_int32_t command; 915 struct ste_softc *sc; 916 struct ifnet *ifp; 917 int unit, error = 0, rid; 918 919 sc = device_get_softc(dev); 920 unit = device_get_unit(dev); 921 bzero(sc, sizeof(struct ste_softc)); 922 sc->ste_dev = dev; 923 924 /* 925 * Only use one PHY since this chip reports multiple 926 * Note on the DFE-550 the PHY is at 1 on the DFE-580 927 * it is at 0 & 1. It is rev 0x12. 928 */ 929 if (pci_get_vendor(dev) == DL_VENDORID && 930 pci_get_device(dev) == DL_DEVICEID_DL10050 && 931 pci_get_revid(dev) == 0x12 ) 932 sc->ste_one_phy = 1; 933 934 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 935 MTX_DEF | MTX_RECURSE); 936 STE_LOCK(sc); 937 938 /* 939 * Handle power management nonsense. 940 */ 941 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 942 u_int32_t iobase, membase, irq; 943 944 /* Save important PCI config data. */ 945 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 946 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 947 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 948 949 /* Reset the power state. */ 950 printf("ste%d: chip is in D%d power mode " 951 "-- setting to D0\n", unit, 952 pci_get_powerstate(dev)); 953 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 954 955 /* Restore PCI config data. */ 956 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 957 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 958 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 959 } 960 961 /* 962 * Map control/status registers. 963 */ 964 pci_enable_busmaster(dev); 965 pci_enable_io(dev, SYS_RES_IOPORT); 966 pci_enable_io(dev, SYS_RES_MEMORY); 967 command = pci_read_config(dev, PCIR_COMMAND, 4); 968 969 #ifdef STE_USEIOSPACE 970 if (!(command & PCIM_CMD_PORTEN)) { 971 printf("ste%d: failed to enable I/O ports!\n", unit); 972 error = ENXIO; 973 goto fail; 974 } 975 #else 976 if (!(command & PCIM_CMD_MEMEN)) { 977 printf("ste%d: failed to enable memory mapping!\n", unit); 978 error = ENXIO; 979 goto fail; 980 } 981 #endif 982 983 rid = STE_RID; 984 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 985 0, ~0, 1, RF_ACTIVE); 986 987 if (sc->ste_res == NULL) { 988 printf ("ste%d: couldn't map ports/memory\n", unit); 989 error = ENXIO; 990 goto fail; 991 } 992 993 sc->ste_btag = rman_get_bustag(sc->ste_res); 994 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 995 996 rid = 0; 997 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 998 RF_SHAREABLE | RF_ACTIVE); 999 1000 if (sc->ste_irq == NULL) { 1001 printf("ste%d: couldn't map interrupt\n", unit); 1002 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1003 error = ENXIO; 1004 goto fail; 1005 } 1006 1007 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1008 ste_intr, sc, &sc->ste_intrhand); 1009 1010 if (error) { 1011 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1012 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1013 printf("ste%d: couldn't set up irq\n", unit); 1014 goto fail; 1015 } 1016 1017 callout_handle_init(&sc->ste_stat_ch); 1018 1019 /* Reset the adapter. */ 1020 ste_reset(sc); 1021 1022 /* 1023 * Get station address from the EEPROM. 1024 */ 1025 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1026 STE_EEADDR_NODE0, 3, 0)) { 1027 printf("ste%d: failed to read station address\n", unit); 1028 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1029 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1030 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1031 error = ENXIO;; 1032 goto fail; 1033 } 1034 1035 /* 1036 * A Sundance chip was detected. Inform the world. 1037 */ 1038 printf("ste%d: Ethernet address: %6D\n", unit, 1039 sc->arpcom.ac_enaddr, ":"); 1040 1041 sc->ste_unit = unit; 1042 1043 /* Allocate the descriptor queues. */ 1044 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1045 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1046 1047 if (sc->ste_ldata == NULL) { 1048 printf("ste%d: no memory for list buffers!\n", unit); 1049 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1050 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1051 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1052 error = ENXIO; 1053 goto fail; 1054 } 1055 1056 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1057 1058 /* Do MII setup. */ 1059 if (mii_phy_probe(dev, &sc->ste_miibus, 1060 ste_ifmedia_upd, ste_ifmedia_sts)) { 1061 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1062 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1063 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1064 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1065 contigfree(sc->ste_ldata, 1066 sizeof(struct ste_list_data), M_DEVBUF); 1067 error = ENXIO; 1068 goto fail; 1069 } 1070 1071 ifp = &sc->arpcom.ac_if; 1072 ifp->if_softc = sc; 1073 ifp->if_unit = unit; 1074 ifp->if_name = "ste"; 1075 ifp->if_mtu = ETHERMTU; 1076 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1077 ifp->if_ioctl = ste_ioctl; 1078 ifp->if_output = ether_output; 1079 ifp->if_start = ste_start; 1080 ifp->if_watchdog = ste_watchdog; 1081 ifp->if_init = ste_init; 1082 ifp->if_baudrate = 10000000; 1083 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1084 1085 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1086 1087 /* 1088 * Call MI attach routine. 1089 */ 1090 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1091 1092 /* 1093 * Tell the upper layer(s) we support long frames. 1094 */ 1095 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1096 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1097 1098 STE_UNLOCK(sc); 1099 return(0); 1100 1101 fail: 1102 STE_UNLOCK(sc); 1103 mtx_destroy(&sc->ste_mtx); 1104 return(error); 1105 } 1106 1107 static int 1108 ste_detach(dev) 1109 device_t dev; 1110 { 1111 struct ste_softc *sc; 1112 struct ifnet *ifp; 1113 1114 sc = device_get_softc(dev); 1115 STE_LOCK(sc); 1116 ifp = &sc->arpcom.ac_if; 1117 1118 ste_stop(sc); 1119 ether_ifdetach(ifp); 1120 1121 bus_generic_detach(dev); 1122 device_delete_child(dev, sc->ste_miibus); 1123 1124 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1125 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1126 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1127 1128 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1129 1130 STE_UNLOCK(sc); 1131 mtx_destroy(&sc->ste_mtx); 1132 1133 return(0); 1134 } 1135 1136 static int 1137 ste_newbuf(sc, c, m) 1138 struct ste_softc *sc; 1139 struct ste_chain_onefrag *c; 1140 struct mbuf *m; 1141 { 1142 struct mbuf *m_new = NULL; 1143 1144 if (m == NULL) { 1145 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1146 if (m_new == NULL) 1147 return(ENOBUFS); 1148 MCLGET(m_new, M_DONTWAIT); 1149 if (!(m_new->m_flags & M_EXT)) { 1150 m_freem(m_new); 1151 return(ENOBUFS); 1152 } 1153 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1154 } else { 1155 m_new = m; 1156 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1157 m_new->m_data = m_new->m_ext.ext_buf; 1158 } 1159 1160 m_adj(m_new, ETHER_ALIGN); 1161 1162 c->ste_mbuf = m_new; 1163 c->ste_ptr->ste_status = 0; 1164 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1165 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1166 1167 return(0); 1168 } 1169 1170 static int 1171 ste_init_rx_list(sc) 1172 struct ste_softc *sc; 1173 { 1174 struct ste_chain_data *cd; 1175 struct ste_list_data *ld; 1176 int i; 1177 1178 cd = &sc->ste_cdata; 1179 ld = sc->ste_ldata; 1180 1181 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1182 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1183 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1184 return(ENOBUFS); 1185 if (i == (STE_RX_LIST_CNT - 1)) { 1186 cd->ste_rx_chain[i].ste_next = 1187 &cd->ste_rx_chain[0]; 1188 ld->ste_rx_list[i].ste_next = 1189 vtophys(&ld->ste_rx_list[0]); 1190 } else { 1191 cd->ste_rx_chain[i].ste_next = 1192 &cd->ste_rx_chain[i + 1]; 1193 ld->ste_rx_list[i].ste_next = 1194 vtophys(&ld->ste_rx_list[i + 1]); 1195 } 1196 ld->ste_rx_list[i].ste_status = 0; 1197 } 1198 1199 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1200 1201 return(0); 1202 } 1203 1204 static void 1205 ste_init_tx_list(sc) 1206 struct ste_softc *sc; 1207 { 1208 struct ste_chain_data *cd; 1209 struct ste_list_data *ld; 1210 int i; 1211 1212 cd = &sc->ste_cdata; 1213 ld = sc->ste_ldata; 1214 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1215 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1216 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1217 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1218 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1219 if (i == (STE_TX_LIST_CNT - 1)) 1220 cd->ste_tx_chain[i].ste_next = 1221 &cd->ste_tx_chain[0]; 1222 else 1223 cd->ste_tx_chain[i].ste_next = 1224 &cd->ste_tx_chain[i + 1]; 1225 if (i == 0) 1226 cd->ste_tx_chain[i].ste_prev = 1227 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1228 else 1229 cd->ste_tx_chain[i].ste_prev = 1230 &cd->ste_tx_chain[i - 1]; 1231 } 1232 1233 cd->ste_tx_prod = 0; 1234 cd->ste_tx_cons = 0; 1235 cd->ste_tx_cnt = 0; 1236 1237 return; 1238 } 1239 1240 static void 1241 ste_init(xsc) 1242 void *xsc; 1243 { 1244 struct ste_softc *sc; 1245 int i; 1246 struct ifnet *ifp; 1247 struct mii_data *mii; 1248 1249 sc = xsc; 1250 STE_LOCK(sc); 1251 ifp = &sc->arpcom.ac_if; 1252 mii = device_get_softc(sc->ste_miibus); 1253 1254 ste_stop(sc); 1255 1256 /* Init our MAC address */ 1257 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1258 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1259 } 1260 1261 /* Init RX list */ 1262 if (ste_init_rx_list(sc) == ENOBUFS) { 1263 printf("ste%d: initialization failed: no " 1264 "memory for RX buffers\n", sc->ste_unit); 1265 ste_stop(sc); 1266 STE_UNLOCK(sc); 1267 return; 1268 } 1269 1270 /* Set RX polling interval */ 1271 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1272 1273 /* Init TX descriptors */ 1274 ste_init_tx_list(sc); 1275 1276 /* Set the TX freethresh value */ 1277 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1278 1279 /* Set the TX start threshold for best performance. */ 1280 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1281 1282 /* Set the TX reclaim threshold. */ 1283 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1284 1285 /* Set up the RX filter. */ 1286 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1287 1288 /* If we want promiscuous mode, set the allframes bit. */ 1289 if (ifp->if_flags & IFF_PROMISC) { 1290 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1291 } else { 1292 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1293 } 1294 1295 /* Set capture broadcast bit to accept broadcast frames. */ 1296 if (ifp->if_flags & IFF_BROADCAST) { 1297 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1298 } else { 1299 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1300 } 1301 1302 ste_setmulti(sc); 1303 1304 /* Load the address of the RX list. */ 1305 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1306 ste_wait(sc); 1307 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1308 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1309 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1310 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1311 1312 /* Set TX polling interval (defer until we TX first packet */ 1313 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1314 1315 /* Load address of the TX list */ 1316 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1317 ste_wait(sc); 1318 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1319 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1320 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1321 ste_wait(sc); 1322 sc->ste_tx_prev_idx=-1; 1323 1324 /* Enable receiver and transmitter */ 1325 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1326 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1327 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1328 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1329 1330 /* Enable stats counters. */ 1331 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1332 1333 /* Enable interrupts. */ 1334 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1335 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1336 1337 /* Accept VLAN length packets */ 1338 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1339 1340 ste_ifmedia_upd(ifp); 1341 1342 ifp->if_flags |= IFF_RUNNING; 1343 ifp->if_flags &= ~IFF_OACTIVE; 1344 1345 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1346 STE_UNLOCK(sc); 1347 1348 return; 1349 } 1350 1351 static void 1352 ste_stop(sc) 1353 struct ste_softc *sc; 1354 { 1355 int i; 1356 struct ifnet *ifp; 1357 1358 STE_LOCK(sc); 1359 ifp = &sc->arpcom.ac_if; 1360 1361 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1362 1363 CSR_WRITE_2(sc, STE_IMR, 0); 1364 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1365 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1366 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1367 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1368 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1369 ste_wait(sc); 1370 /* 1371 * Try really hard to stop the RX engine or under heavy RX 1372 * data chip will write into de-allocated memory. 1373 */ 1374 ste_reset(sc); 1375 1376 sc->ste_link = 0; 1377 1378 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1379 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1380 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1381 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1382 } 1383 } 1384 1385 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1386 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1387 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1388 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1389 } 1390 } 1391 1392 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1393 1394 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1395 STE_UNLOCK(sc); 1396 1397 return; 1398 } 1399 1400 static void 1401 ste_reset(sc) 1402 struct ste_softc *sc; 1403 { 1404 int i; 1405 1406 STE_SETBIT4(sc, STE_ASICCTL, 1407 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1408 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1409 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1410 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1411 STE_ASICCTL_EXTRESET_RESET); 1412 1413 DELAY(100000); 1414 1415 for (i = 0; i < STE_TIMEOUT; i++) { 1416 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1417 break; 1418 } 1419 1420 if (i == STE_TIMEOUT) 1421 printf("ste%d: global reset never completed\n", sc->ste_unit); 1422 1423 return; 1424 } 1425 1426 static int 1427 ste_ioctl(ifp, command, data) 1428 struct ifnet *ifp; 1429 u_long command; 1430 caddr_t data; 1431 { 1432 struct ste_softc *sc; 1433 struct ifreq *ifr; 1434 struct mii_data *mii; 1435 int error = 0; 1436 1437 sc = ifp->if_softc; 1438 STE_LOCK(sc); 1439 ifr = (struct ifreq *)data; 1440 1441 switch(command) { 1442 case SIOCSIFFLAGS: 1443 if (ifp->if_flags & IFF_UP) { 1444 if (ifp->if_flags & IFF_RUNNING && 1445 ifp->if_flags & IFF_PROMISC && 1446 !(sc->ste_if_flags & IFF_PROMISC)) { 1447 STE_SETBIT1(sc, STE_RX_MODE, 1448 STE_RXMODE_PROMISC); 1449 } else if (ifp->if_flags & IFF_RUNNING && 1450 !(ifp->if_flags & IFF_PROMISC) && 1451 sc->ste_if_flags & IFF_PROMISC) { 1452 STE_CLRBIT1(sc, STE_RX_MODE, 1453 STE_RXMODE_PROMISC); 1454 } 1455 if (!(ifp->if_flags & IFF_RUNNING)) { 1456 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1457 ste_init(sc); 1458 } 1459 } else { 1460 if (ifp->if_flags & IFF_RUNNING) 1461 ste_stop(sc); 1462 } 1463 sc->ste_if_flags = ifp->if_flags; 1464 error = 0; 1465 break; 1466 case SIOCADDMULTI: 1467 case SIOCDELMULTI: 1468 ste_setmulti(sc); 1469 error = 0; 1470 break; 1471 case SIOCGIFMEDIA: 1472 case SIOCSIFMEDIA: 1473 mii = device_get_softc(sc->ste_miibus); 1474 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1475 break; 1476 default: 1477 error = ether_ioctl(ifp, command, data); 1478 break; 1479 } 1480 1481 STE_UNLOCK(sc); 1482 1483 return(error); 1484 } 1485 1486 static int 1487 ste_encap(sc, c, m_head) 1488 struct ste_softc *sc; 1489 struct ste_chain *c; 1490 struct mbuf *m_head; 1491 { 1492 int frag = 0; 1493 struct ste_frag *f = NULL; 1494 struct mbuf *m; 1495 struct ste_desc *d; 1496 int total_len = 0; 1497 1498 d = c->ste_ptr; 1499 d->ste_ctl = 0; 1500 1501 encap_retry: 1502 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1503 if (m->m_len != 0) { 1504 if (frag == STE_MAXFRAGS) 1505 break; 1506 total_len += m->m_len; 1507 f = &d->ste_frags[frag]; 1508 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1509 f->ste_len = m->m_len; 1510 frag++; 1511 } 1512 } 1513 1514 if (m != NULL) { 1515 struct mbuf *mn; 1516 1517 /* 1518 * We ran out of segments. We have to recopy this 1519 * mbuf chain first. Bail out if we can't get the 1520 * new buffers. Code borrowed from if_fxp.c 1521 */ 1522 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1523 if (mn == NULL) { 1524 m_freem(m_head); 1525 return ENOMEM; 1526 } 1527 if (m_head->m_pkthdr.len > MHLEN) { 1528 MCLGET(mn, M_DONTWAIT); 1529 if ((mn->m_flags & M_EXT) == 0) { 1530 m_freem(mn); 1531 m_freem(m_head); 1532 return ENOMEM; 1533 } 1534 } 1535 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1536 mtod(mn, caddr_t)); 1537 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1538 m_freem(m_head); 1539 m_head = mn; 1540 goto encap_retry; 1541 } 1542 1543 c->ste_mbuf = m_head; 1544 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1545 d->ste_ctl = 1; 1546 1547 return(0); 1548 } 1549 1550 static void 1551 ste_start(ifp) 1552 struct ifnet *ifp; 1553 { 1554 struct ste_softc *sc; 1555 struct mbuf *m_head = NULL; 1556 struct ste_chain *cur_tx = NULL; 1557 int idx; 1558 1559 sc = ifp->if_softc; 1560 STE_LOCK(sc); 1561 1562 if (!sc->ste_link) { 1563 STE_UNLOCK(sc); 1564 return; 1565 } 1566 1567 if (ifp->if_flags & IFF_OACTIVE) { 1568 STE_UNLOCK(sc); 1569 return; 1570 } 1571 1572 idx = sc->ste_cdata.ste_tx_prod; 1573 1574 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1575 1576 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1577 ifp->if_flags |= IFF_OACTIVE; 1578 break; 1579 } 1580 1581 IF_DEQUEUE(&ifp->if_snd, m_head); 1582 if (m_head == NULL) 1583 break; 1584 1585 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1586 1587 if (ste_encap(sc, cur_tx, m_head) != 0) 1588 break; 1589 1590 cur_tx->ste_ptr->ste_next = 0; 1591 1592 if(sc->ste_tx_prev_idx < 0){ 1593 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1594 /* Load address of the TX list */ 1595 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1596 ste_wait(sc); 1597 1598 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1599 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1600 1601 /* Set TX polling interval to start TX engine */ 1602 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1603 1604 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1605 ste_wait(sc); 1606 }else{ 1607 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1608 sc->ste_cdata.ste_tx_chain[ 1609 sc->ste_tx_prev_idx].ste_ptr->ste_next 1610 = cur_tx->ste_phys; 1611 } 1612 1613 sc->ste_tx_prev_idx=idx; 1614 1615 /* 1616 * If there's a BPF listener, bounce a copy of this frame 1617 * to him. 1618 */ 1619 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1620 1621 STE_INC(idx, STE_TX_LIST_CNT); 1622 sc->ste_cdata.ste_tx_cnt++; 1623 ifp->if_timer = 5; 1624 sc->ste_cdata.ste_tx_prod = idx; 1625 } 1626 1627 STE_UNLOCK(sc); 1628 1629 return; 1630 } 1631 1632 static void 1633 ste_watchdog(ifp) 1634 struct ifnet *ifp; 1635 { 1636 struct ste_softc *sc; 1637 1638 sc = ifp->if_softc; 1639 STE_LOCK(sc); 1640 1641 ifp->if_oerrors++; 1642 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1643 1644 ste_txeoc(sc); 1645 ste_txeof(sc); 1646 ste_rxeof(sc); 1647 ste_reset(sc); 1648 ste_init(sc); 1649 1650 if (ifp->if_snd.ifq_head != NULL) 1651 ste_start(ifp); 1652 STE_UNLOCK(sc); 1653 1654 return; 1655 } 1656 1657 static void 1658 ste_shutdown(dev) 1659 device_t dev; 1660 { 1661 struct ste_softc *sc; 1662 1663 sc = device_get_softc(dev); 1664 1665 ste_stop(sc); 1666 1667 return; 1668 }
Cache object: c549fc1425d6c74d02172bd9e2faccd1
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