Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_ste.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/5.1/sys/pci/if_ste.c 113812 2003-04-21 18:34:04Z imp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/ethernet.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 #include <net/if_vlan_var.h> 50 51 #include <net/bpf.h> 52 53 #include <vm/vm.h> /* for vtophys */ 54 #include <vm/pmap.h> /* for vtophys */ 55 #include <machine/bus_memio.h> 56 #include <machine/bus_pio.h> 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #include <pci/pcireg.h> 66 #include <pci/pcivar.h> 67 68 /* "controller miibus0" required. See GENERIC if you get errors here. */ 69 #include "miibus_if.h" 70 71 #define STE_USEIOSPACE 72 73 #include <pci/if_stereg.h> 74 75 MODULE_DEPEND(ste, pci, 1, 1, 1); 76 MODULE_DEPEND(ste, ether, 1, 1, 1); 77 MODULE_DEPEND(ste, miibus, 1, 1, 1); 78 79 /* 80 * Various supported device vendors/types and their names. 81 */ 82 static struct ste_type ste_devs[] = { 83 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 84 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 85 { 0, 0, NULL } 86 }; 87 88 static int ste_probe (device_t); 89 static int ste_attach (device_t); 90 static int ste_detach (device_t); 91 static void ste_init (void *); 92 static void ste_intr (void *); 93 static void ste_rxeof (struct ste_softc *); 94 static void ste_txeoc (struct ste_softc *); 95 static void ste_txeof (struct ste_softc *); 96 static void ste_stats_update (void *); 97 static void ste_stop (struct ste_softc *); 98 static void ste_reset (struct ste_softc *); 99 static int ste_ioctl (struct ifnet *, u_long, caddr_t); 100 static int ste_encap (struct ste_softc *, struct ste_chain *, 101 struct mbuf *); 102 static void ste_start (struct ifnet *); 103 static void ste_watchdog (struct ifnet *); 104 static void ste_shutdown (device_t); 105 static int ste_newbuf (struct ste_softc *, 106 struct ste_chain_onefrag *, 107 struct mbuf *); 108 static int ste_ifmedia_upd (struct ifnet *); 109 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 111 static void ste_mii_sync (struct ste_softc *); 112 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 113 static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 114 static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 115 static int ste_miibus_readreg (device_t, int, int); 116 static int ste_miibus_writereg (device_t, int, int, int); 117 static void ste_miibus_statchg (device_t); 118 119 static int ste_eeprom_wait (struct ste_softc *); 120 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 121 static void ste_wait (struct ste_softc *); 122 static u_int8_t ste_calchash (caddr_t); 123 static void ste_setmulti (struct ste_softc *); 124 static int ste_init_rx_list (struct ste_softc *); 125 static void ste_init_tx_list (struct ste_softc *); 126 127 #ifdef STE_USEIOSPACE 128 #define STE_RES SYS_RES_IOPORT 129 #define STE_RID STE_PCI_LOIO 130 #else 131 #define STE_RES SYS_RES_MEMORY 132 #define STE_RID STE_PCI_LOMEM 133 #endif 134 135 static device_method_t ste_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ste_probe), 138 DEVMETHOD(device_attach, ste_attach), 139 DEVMETHOD(device_detach, ste_detach), 140 DEVMETHOD(device_shutdown, ste_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 148 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 149 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 150 151 { 0, 0 } 152 }; 153 154 static driver_t ste_driver = { 155 "ste", 156 ste_methods, 157 sizeof(struct ste_softc) 158 }; 159 160 static devclass_t ste_devclass; 161 162 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 163 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 164 165 #define STE_SETBIT4(sc, reg, x) \ 166 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 167 168 #define STE_CLRBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 170 171 #define STE_SETBIT2(sc, reg, x) \ 172 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 173 174 #define STE_CLRBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 176 177 #define STE_SETBIT1(sc, reg, x) \ 178 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 179 180 #define STE_CLRBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 182 183 184 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 185 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 186 187 /* 188 * Sync the PHYs by setting data bit and strobing the clock 32 times. 189 */ 190 static void 191 ste_mii_sync(sc) 192 struct ste_softc *sc; 193 { 194 register int i; 195 196 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 197 198 for (i = 0; i < 32; i++) { 199 MII_SET(STE_PHYCTL_MCLK); 200 DELAY(1); 201 MII_CLR(STE_PHYCTL_MCLK); 202 DELAY(1); 203 } 204 205 return; 206 } 207 208 /* 209 * Clock a series of bits through the MII. 210 */ 211 static void 212 ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216 { 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232 } 233 234 /* 235 * Read an PHY register through the MII. 236 */ 237 static int 238 ste_mii_readreg(sc, frame) 239 struct ste_softc *sc; 240 struct ste_mii_frame *frame; 241 242 { 243 int i, ack; 244 245 STE_LOCK(sc); 246 247 /* 248 * Set up frame for RX. 249 */ 250 frame->mii_stdelim = STE_MII_STARTDELIM; 251 frame->mii_opcode = STE_MII_READOP; 252 frame->mii_turnaround = 0; 253 frame->mii_data = 0; 254 255 CSR_WRITE_2(sc, STE_PHYCTL, 0); 256 /* 257 * Turn on data xmit. 258 */ 259 MII_SET(STE_PHYCTL_MDIR); 260 261 ste_mii_sync(sc); 262 263 /* 264 * Send command/address info. 265 */ 266 ste_mii_send(sc, frame->mii_stdelim, 2); 267 ste_mii_send(sc, frame->mii_opcode, 2); 268 ste_mii_send(sc, frame->mii_phyaddr, 5); 269 ste_mii_send(sc, frame->mii_regaddr, 5); 270 271 /* Turn off xmit. */ 272 MII_CLR(STE_PHYCTL_MDIR); 273 274 /* Idle bit */ 275 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 276 DELAY(1); 277 MII_SET(STE_PHYCTL_MCLK); 278 DELAY(1); 279 280 /* Check for ack */ 281 MII_CLR(STE_PHYCTL_MCLK); 282 DELAY(1); 283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* 288 * Now try reading data bits. If the ack failed, we still 289 * need to clock through 16 cycles to keep the PHY(s) in sync. 290 */ 291 if (ack) { 292 for(i = 0; i < 16; i++) { 293 MII_CLR(STE_PHYCTL_MCLK); 294 DELAY(1); 295 MII_SET(STE_PHYCTL_MCLK); 296 DELAY(1); 297 } 298 goto fail; 299 } 300 301 for (i = 0x8000; i; i >>= 1) { 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 if (!ack) { 305 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 306 frame->mii_data |= i; 307 DELAY(1); 308 } 309 MII_SET(STE_PHYCTL_MCLK); 310 DELAY(1); 311 } 312 313 fail: 314 315 MII_CLR(STE_PHYCTL_MCLK); 316 DELAY(1); 317 MII_SET(STE_PHYCTL_MCLK); 318 DELAY(1); 319 320 STE_UNLOCK(sc); 321 322 if (ack) 323 return(1); 324 return(0); 325 } 326 327 /* 328 * Write to a PHY register through the MII. 329 */ 330 static int 331 ste_mii_writereg(sc, frame) 332 struct ste_softc *sc; 333 struct ste_mii_frame *frame; 334 335 { 336 STE_LOCK(sc); 337 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 STE_UNLOCK(sc); 372 373 return(0); 374 } 375 376 static int 377 ste_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380 { 381 struct ste_softc *sc; 382 struct ste_mii_frame frame; 383 384 sc = device_get_softc(dev); 385 386 if ( sc->ste_one_phy && phy != 0 ) 387 return (0); 388 389 bzero((char *)&frame, sizeof(frame)); 390 391 frame.mii_phyaddr = phy; 392 frame.mii_regaddr = reg; 393 ste_mii_readreg(sc, &frame); 394 395 return(frame.mii_data); 396 } 397 398 static int 399 ste_miibus_writereg(dev, phy, reg, data) 400 device_t dev; 401 int phy, reg, data; 402 { 403 struct ste_softc *sc; 404 struct ste_mii_frame frame; 405 406 sc = device_get_softc(dev); 407 bzero((char *)&frame, sizeof(frame)); 408 409 frame.mii_phyaddr = phy; 410 frame.mii_regaddr = reg; 411 frame.mii_data = data; 412 413 ste_mii_writereg(sc, &frame); 414 415 return(0); 416 } 417 418 static void 419 ste_miibus_statchg(dev) 420 device_t dev; 421 { 422 struct ste_softc *sc; 423 struct mii_data *mii; 424 425 sc = device_get_softc(dev); 426 STE_LOCK(sc); 427 mii = device_get_softc(sc->ste_miibus); 428 429 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 430 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } else { 432 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } 434 STE_UNLOCK(sc); 435 436 return; 437 } 438 439 static int 440 ste_ifmedia_upd(ifp) 441 struct ifnet *ifp; 442 { 443 struct ste_softc *sc; 444 struct mii_data *mii; 445 446 sc = ifp->if_softc; 447 mii = device_get_softc(sc->ste_miibus); 448 sc->ste_link = 0; 449 if (mii->mii_instance) { 450 struct mii_softc *miisc; 451 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 452 mii_phy_reset(miisc); 453 } 454 mii_mediachg(mii); 455 456 return(0); 457 } 458 459 static void 460 ste_ifmedia_sts(ifp, ifmr) 461 struct ifnet *ifp; 462 struct ifmediareq *ifmr; 463 { 464 struct ste_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 mii = device_get_softc(sc->ste_miibus); 469 470 mii_pollstat(mii); 471 ifmr->ifm_active = mii->mii_media_active; 472 ifmr->ifm_status = mii->mii_media_status; 473 474 return; 475 } 476 477 static void 478 ste_wait(sc) 479 struct ste_softc *sc; 480 { 481 register int i; 482 483 for (i = 0; i < STE_TIMEOUT; i++) { 484 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 485 break; 486 } 487 488 if (i == STE_TIMEOUT) 489 printf("ste%d: command never completed!\n", sc->ste_unit); 490 491 return; 492 } 493 494 /* 495 * The EEPROM is slow: give it time to come ready after issuing 496 * it a command. 497 */ 498 static int 499 ste_eeprom_wait(sc) 500 struct ste_softc *sc; 501 { 502 int i; 503 504 DELAY(1000); 505 506 for (i = 0; i < 100; i++) { 507 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 508 DELAY(1000); 509 else 510 break; 511 } 512 513 if (i == 100) { 514 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 515 return(1); 516 } 517 518 return(0); 519 } 520 521 /* 522 * Read a sequence of words from the EEPROM. Note that ethernet address 523 * data is stored in the EEPROM in network byte order. 524 */ 525 static int 526 ste_read_eeprom(sc, dest, off, cnt, swap) 527 struct ste_softc *sc; 528 caddr_t dest; 529 int off; 530 int cnt; 531 int swap; 532 { 533 int err = 0, i; 534 u_int16_t word = 0, *ptr; 535 536 if (ste_eeprom_wait(sc)) 537 return(1); 538 539 for (i = 0; i < cnt; i++) { 540 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 541 err = ste_eeprom_wait(sc); 542 if (err) 543 break; 544 word = CSR_READ_2(sc, STE_EEPROM_DATA); 545 ptr = (u_int16_t *)(dest + (i * 2)); 546 if (swap) 547 *ptr = ntohs(word); 548 else 549 *ptr = word; 550 } 551 552 return(err ? 1 : 0); 553 } 554 555 static u_int8_t 556 ste_calchash(addr) 557 caddr_t addr; 558 { 559 560 u_int32_t crc, carry; 561 int i, j; 562 u_int8_t c; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xFFFFFFFF; /* initial value */ 566 567 for (i = 0; i < 6; i++) { 568 c = *(addr + i); 569 for (j = 0; j < 8; j++) { 570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 571 crc <<= 1; 572 c >>= 1; 573 if (carry) 574 crc = (crc ^ 0x04c11db6) | carry; 575 } 576 } 577 578 /* return the filter bit position */ 579 return(crc & 0x0000003F); 580 } 581 582 static void 583 ste_setmulti(sc) 584 struct ste_softc *sc; 585 { 586 struct ifnet *ifp; 587 int h = 0; 588 u_int32_t hashes[2] = { 0, 0 }; 589 struct ifmultiaddr *ifma; 590 591 ifp = &sc->arpcom.ac_if; 592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 593 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 594 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 595 return; 596 } 597 598 /* first, zot all the existing hash bits */ 599 CSR_WRITE_2(sc, STE_MAR0, 0); 600 CSR_WRITE_2(sc, STE_MAR1, 0); 601 CSR_WRITE_2(sc, STE_MAR2, 0); 602 CSR_WRITE_2(sc, STE_MAR3, 0); 603 604 /* now program new ones */ 605 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 606 if (ifma->ifma_addr->sa_family != AF_LINK) 607 continue; 608 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 609 if (h < 32) 610 hashes[0] |= (1 << h); 611 else 612 hashes[1] |= (1 << (h - 32)); 613 } 614 615 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 617 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 619 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 620 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 621 622 return; 623 } 624 625 static void 626 ste_intr(xsc) 627 void *xsc; 628 { 629 struct ste_softc *sc; 630 struct ifnet *ifp; 631 u_int16_t status; 632 633 sc = xsc; 634 STE_LOCK(sc); 635 ifp = &sc->arpcom.ac_if; 636 637 /* See if this is really our interrupt. */ 638 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 639 STE_UNLOCK(sc); 640 return; 641 } 642 643 for (;;) { 644 status = CSR_READ_2(sc, STE_ISR_ACK); 645 646 if (!(status & STE_INTRS)) 647 break; 648 649 if (status & STE_ISR_RX_DMADONE) 650 ste_rxeof(sc); 651 652 if (status & STE_ISR_TX_DMADONE) 653 ste_txeof(sc); 654 655 if (status & STE_ISR_TX_DONE) 656 ste_txeoc(sc); 657 658 if (status & STE_ISR_STATS_OFLOW) { 659 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 660 ste_stats_update(sc); 661 } 662 663 if (status & STE_ISR_LINKEVENT) 664 mii_pollstat(device_get_softc(sc->ste_miibus)); 665 666 667 if (status & STE_ISR_HOSTERR) { 668 ste_reset(sc); 669 ste_init(sc); 670 } 671 } 672 673 /* Re-enable interrupts */ 674 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 675 676 if (ifp->if_snd.ifq_head != NULL) 677 ste_start(ifp); 678 679 STE_UNLOCK(sc); 680 681 return; 682 } 683 684 /* 685 * A frame has been uploaded: pass the resulting mbuf chain up to 686 * the higher level protocols. 687 */ 688 static void 689 ste_rxeof(sc) 690 struct ste_softc *sc; 691 { 692 struct mbuf *m; 693 struct ifnet *ifp; 694 struct ste_chain_onefrag *cur_rx; 695 int total_len = 0, count=0; 696 u_int32_t rxstat; 697 698 ifp = &sc->arpcom.ac_if; 699 700 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 701 & STE_RXSTAT_DMADONE) { 702 if ((STE_RX_LIST_CNT - count) < 3) { 703 break; 704 } 705 706 cur_rx = sc->ste_cdata.ste_rx_head; 707 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 708 709 /* 710 * If an error occurs, update stats, clear the 711 * status word and leave the mbuf cluster in place: 712 * it should simply get re-used next time this descriptor 713 * comes up in the ring. 714 */ 715 if (rxstat & STE_RXSTAT_FRAME_ERR) { 716 ifp->if_ierrors++; 717 cur_rx->ste_ptr->ste_status = 0; 718 continue; 719 } 720 721 /* 722 * If there error bit was not set, the upload complete 723 * bit should be set which means we have a valid packet. 724 * If not, something truly strange has happened. 725 */ 726 if (!(rxstat & STE_RXSTAT_DMADONE)) { 727 printf("ste%d: bad receive status -- packet dropped\n", 728 sc->ste_unit); 729 ifp->if_ierrors++; 730 cur_rx->ste_ptr->ste_status = 0; 731 continue; 732 } 733 734 /* No errors; receive the packet. */ 735 m = cur_rx->ste_mbuf; 736 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 737 738 /* 739 * Try to conjure up a new mbuf cluster. If that 740 * fails, it means we have an out of memory condition and 741 * should leave the buffer in place and continue. This will 742 * result in a lost packet, but there's little else we 743 * can do in this situation. 744 */ 745 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 746 ifp->if_ierrors++; 747 cur_rx->ste_ptr->ste_status = 0; 748 continue; 749 } 750 751 m->m_pkthdr.rcvif = ifp; 752 m->m_pkthdr.len = m->m_len = total_len; 753 754 ifp->if_ipackets++; 755 (*ifp->if_input)(ifp, m); 756 757 cur_rx->ste_ptr->ste_status = 0; 758 count++; 759 } 760 761 return; 762 } 763 764 static void 765 ste_txeoc(sc) 766 struct ste_softc *sc; 767 { 768 u_int8_t txstat; 769 struct ifnet *ifp; 770 771 ifp = &sc->arpcom.ac_if; 772 773 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 774 STE_TXSTATUS_TXDONE) { 775 if (txstat & STE_TXSTATUS_UNDERRUN || 776 txstat & STE_TXSTATUS_EXCESSCOLLS || 777 txstat & STE_TXSTATUS_RECLAIMERR) { 778 ifp->if_oerrors++; 779 printf("ste%d: transmission error: %x\n", 780 sc->ste_unit, txstat); 781 782 ste_reset(sc); 783 ste_init(sc); 784 785 if (txstat & STE_TXSTATUS_UNDERRUN && 786 sc->ste_tx_thresh < STE_PACKET_SIZE) { 787 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 788 printf("ste%d: tx underrun, increasing tx" 789 " start threshold to %d bytes\n", 790 sc->ste_unit, sc->ste_tx_thresh); 791 } 792 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 793 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 794 (STE_PACKET_SIZE >> 4)); 795 } 796 ste_init(sc); 797 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 798 } 799 800 return; 801 } 802 803 static void 804 ste_txeof(sc) 805 struct ste_softc *sc; 806 { 807 struct ste_chain *cur_tx = NULL; 808 struct ifnet *ifp; 809 int idx; 810 811 ifp = &sc->arpcom.ac_if; 812 813 idx = sc->ste_cdata.ste_tx_cons; 814 while(idx != sc->ste_cdata.ste_tx_prod) { 815 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 816 817 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 818 break; 819 820 if (cur_tx->ste_mbuf != NULL) { 821 m_freem(cur_tx->ste_mbuf); 822 cur_tx->ste_mbuf = NULL; 823 } 824 825 ifp->if_opackets++; 826 827 sc->ste_cdata.ste_tx_cnt--; 828 STE_INC(idx, STE_TX_LIST_CNT); 829 ifp->if_timer = 0; 830 } 831 832 sc->ste_cdata.ste_tx_cons = idx; 833 834 if (cur_tx != NULL) 835 ifp->if_flags &= ~IFF_OACTIVE; 836 837 return; 838 } 839 840 static void 841 ste_stats_update(xsc) 842 void *xsc; 843 { 844 struct ste_softc *sc; 845 struct ifnet *ifp; 846 struct mii_data *mii; 847 848 sc = xsc; 849 STE_LOCK(sc); 850 851 ifp = &sc->arpcom.ac_if; 852 mii = device_get_softc(sc->ste_miibus); 853 854 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 855 + CSR_READ_1(sc, STE_MULTI_COLLS) 856 + CSR_READ_1(sc, STE_SINGLE_COLLS); 857 858 if (!sc->ste_link) { 859 mii_pollstat(mii); 860 if (mii->mii_media_status & IFM_ACTIVE && 861 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 862 sc->ste_link++; 863 /* 864 * we don't get a call-back on re-init so do it 865 * otherwise we get stuck in the wrong link state 866 */ 867 ste_miibus_statchg(sc->ste_dev); 868 if (ifp->if_snd.ifq_head != NULL) 869 ste_start(ifp); 870 } 871 } 872 873 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 874 STE_UNLOCK(sc); 875 876 return; 877 } 878 879 880 /* 881 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 882 * IDs against our list and return a device name if we find a match. 883 */ 884 static int 885 ste_probe(dev) 886 device_t dev; 887 { 888 struct ste_type *t; 889 890 t = ste_devs; 891 892 while(t->ste_name != NULL) { 893 if ((pci_get_vendor(dev) == t->ste_vid) && 894 (pci_get_device(dev) == t->ste_did)) { 895 device_set_desc(dev, t->ste_name); 896 return(0); 897 } 898 t++; 899 } 900 901 return(ENXIO); 902 } 903 904 /* 905 * Attach the interface. Allocate softc structures, do ifmedia 906 * setup and ethernet/BPF attach. 907 */ 908 static int 909 ste_attach(dev) 910 device_t dev; 911 { 912 struct ste_softc *sc; 913 struct ifnet *ifp; 914 int unit, error = 0, rid; 915 916 sc = device_get_softc(dev); 917 unit = device_get_unit(dev); 918 sc->ste_dev = dev; 919 920 /* 921 * Only use one PHY since this chip reports multiple 922 * Note on the DFE-550 the PHY is at 1 on the DFE-580 923 * it is at 0 & 1. It is rev 0x12. 924 */ 925 if (pci_get_vendor(dev) == DL_VENDORID && 926 pci_get_device(dev) == DL_DEVICEID_DL10050 && 927 pci_get_revid(dev) == 0x12 ) 928 sc->ste_one_phy = 1; 929 930 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 931 MTX_DEF | MTX_RECURSE); 932 933 /* 934 * Handle power management nonsense. 935 */ 936 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 937 u_int32_t iobase, membase, irq; 938 939 /* Save important PCI config data. */ 940 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 941 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 942 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 943 944 /* Reset the power state. */ 945 printf("ste%d: chip is in D%d power mode " 946 "-- setting to D0\n", unit, 947 pci_get_powerstate(dev)); 948 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 949 950 /* Restore PCI config data. */ 951 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 952 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 953 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 954 } 955 956 /* 957 * Map control/status registers. 958 */ 959 pci_enable_busmaster(dev); 960 961 rid = STE_RID; 962 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 963 0, ~0, 1, RF_ACTIVE); 964 965 if (sc->ste_res == NULL) { 966 printf ("ste%d: couldn't map ports/memory\n", unit); 967 error = ENXIO; 968 goto fail; 969 } 970 971 sc->ste_btag = rman_get_bustag(sc->ste_res); 972 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 973 974 /* Allocate interrupt */ 975 rid = 0; 976 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 977 RF_SHAREABLE | RF_ACTIVE); 978 979 if (sc->ste_irq == NULL) { 980 printf("ste%d: couldn't map interrupt\n", unit); 981 error = ENXIO; 982 goto fail; 983 } 984 985 callout_handle_init(&sc->ste_stat_ch); 986 987 /* Reset the adapter. */ 988 ste_reset(sc); 989 990 /* 991 * Get station address from the EEPROM. 992 */ 993 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 994 STE_EEADDR_NODE0, 3, 0)) { 995 printf("ste%d: failed to read station address\n", unit); 996 error = ENXIO;; 997 goto fail; 998 } 999 1000 /* 1001 * A Sundance chip was detected. Inform the world. 1002 */ 1003 printf("ste%d: Ethernet address: %6D\n", unit, 1004 sc->arpcom.ac_enaddr, ":"); 1005 1006 sc->ste_unit = unit; 1007 1008 /* Allocate the descriptor queues. */ 1009 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1010 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1011 1012 if (sc->ste_ldata == NULL) { 1013 printf("ste%d: no memory for list buffers!\n", unit); 1014 error = ENXIO; 1015 goto fail; 1016 } 1017 1018 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1019 1020 /* Do MII setup. */ 1021 if (mii_phy_probe(dev, &sc->ste_miibus, 1022 ste_ifmedia_upd, ste_ifmedia_sts)) { 1023 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1024 error = ENXIO; 1025 goto fail; 1026 } 1027 1028 ifp = &sc->arpcom.ac_if; 1029 ifp->if_softc = sc; 1030 ifp->if_unit = unit; 1031 ifp->if_name = "ste"; 1032 ifp->if_mtu = ETHERMTU; 1033 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1034 ifp->if_ioctl = ste_ioctl; 1035 ifp->if_output = ether_output; 1036 ifp->if_start = ste_start; 1037 ifp->if_watchdog = ste_watchdog; 1038 ifp->if_init = ste_init; 1039 ifp->if_baudrate = 10000000; 1040 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1041 1042 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1043 1044 /* 1045 * Call MI attach routine. 1046 */ 1047 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1048 1049 /* 1050 * Tell the upper layer(s) we support long frames. 1051 */ 1052 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1053 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1054 1055 /* Hook interrupt last to avoid having to lock softc */ 1056 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1057 ste_intr, sc, &sc->ste_intrhand); 1058 1059 if (error) { 1060 printf("ste%d: couldn't set up irq\n", unit); 1061 ether_ifdetach(ifp); 1062 goto fail; 1063 } 1064 1065 fail: 1066 if (error) 1067 ste_detach(dev); 1068 1069 return(error); 1070 } 1071 1072 /* 1073 * Shutdown hardware and free up resources. This can be called any 1074 * time after the mutex has been initialized. It is called in both 1075 * the error case in attach and the normal detach case so it needs 1076 * to be careful about only freeing resources that have actually been 1077 * allocated. 1078 */ 1079 static int 1080 ste_detach(dev) 1081 device_t dev; 1082 { 1083 struct ste_softc *sc; 1084 struct ifnet *ifp; 1085 1086 sc = device_get_softc(dev); 1087 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1088 STE_LOCK(sc); 1089 ifp = &sc->arpcom.ac_if; 1090 1091 /* These should only be active if attach succeeded */ 1092 if (device_is_attached(dev)) { 1093 ste_stop(sc); 1094 ether_ifdetach(ifp); 1095 } 1096 if (sc->ste_miibus) 1097 device_delete_child(dev, sc->ste_miibus); 1098 bus_generic_detach(dev); 1099 1100 if (sc->ste_intrhand) 1101 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1102 if (sc->ste_irq) 1103 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1104 if (sc->ste_res) 1105 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1106 1107 if (sc->ste_ldata) { 1108 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1109 M_DEVBUF); 1110 } 1111 1112 STE_UNLOCK(sc); 1113 mtx_destroy(&sc->ste_mtx); 1114 1115 return(0); 1116 } 1117 1118 static int 1119 ste_newbuf(sc, c, m) 1120 struct ste_softc *sc; 1121 struct ste_chain_onefrag *c; 1122 struct mbuf *m; 1123 { 1124 struct mbuf *m_new = NULL; 1125 1126 if (m == NULL) { 1127 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1128 if (m_new == NULL) 1129 return(ENOBUFS); 1130 MCLGET(m_new, M_DONTWAIT); 1131 if (!(m_new->m_flags & M_EXT)) { 1132 m_freem(m_new); 1133 return(ENOBUFS); 1134 } 1135 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1136 } else { 1137 m_new = m; 1138 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1139 m_new->m_data = m_new->m_ext.ext_buf; 1140 } 1141 1142 m_adj(m_new, ETHER_ALIGN); 1143 1144 c->ste_mbuf = m_new; 1145 c->ste_ptr->ste_status = 0; 1146 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1147 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1148 1149 return(0); 1150 } 1151 1152 static int 1153 ste_init_rx_list(sc) 1154 struct ste_softc *sc; 1155 { 1156 struct ste_chain_data *cd; 1157 struct ste_list_data *ld; 1158 int i; 1159 1160 cd = &sc->ste_cdata; 1161 ld = sc->ste_ldata; 1162 1163 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1164 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1165 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1166 return(ENOBUFS); 1167 if (i == (STE_RX_LIST_CNT - 1)) { 1168 cd->ste_rx_chain[i].ste_next = 1169 &cd->ste_rx_chain[0]; 1170 ld->ste_rx_list[i].ste_next = 1171 vtophys(&ld->ste_rx_list[0]); 1172 } else { 1173 cd->ste_rx_chain[i].ste_next = 1174 &cd->ste_rx_chain[i + 1]; 1175 ld->ste_rx_list[i].ste_next = 1176 vtophys(&ld->ste_rx_list[i + 1]); 1177 } 1178 ld->ste_rx_list[i].ste_status = 0; 1179 } 1180 1181 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1182 1183 return(0); 1184 } 1185 1186 static void 1187 ste_init_tx_list(sc) 1188 struct ste_softc *sc; 1189 { 1190 struct ste_chain_data *cd; 1191 struct ste_list_data *ld; 1192 int i; 1193 1194 cd = &sc->ste_cdata; 1195 ld = sc->ste_ldata; 1196 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1197 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1198 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1199 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1200 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1201 if (i == (STE_TX_LIST_CNT - 1)) 1202 cd->ste_tx_chain[i].ste_next = 1203 &cd->ste_tx_chain[0]; 1204 else 1205 cd->ste_tx_chain[i].ste_next = 1206 &cd->ste_tx_chain[i + 1]; 1207 if (i == 0) 1208 cd->ste_tx_chain[i].ste_prev = 1209 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1210 else 1211 cd->ste_tx_chain[i].ste_prev = 1212 &cd->ste_tx_chain[i - 1]; 1213 } 1214 1215 cd->ste_tx_prod = 0; 1216 cd->ste_tx_cons = 0; 1217 cd->ste_tx_cnt = 0; 1218 1219 return; 1220 } 1221 1222 static void 1223 ste_init(xsc) 1224 void *xsc; 1225 { 1226 struct ste_softc *sc; 1227 int i; 1228 struct ifnet *ifp; 1229 struct mii_data *mii; 1230 1231 sc = xsc; 1232 STE_LOCK(sc); 1233 ifp = &sc->arpcom.ac_if; 1234 mii = device_get_softc(sc->ste_miibus); 1235 1236 ste_stop(sc); 1237 1238 /* Init our MAC address */ 1239 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1240 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1241 } 1242 1243 /* Init RX list */ 1244 if (ste_init_rx_list(sc) == ENOBUFS) { 1245 printf("ste%d: initialization failed: no " 1246 "memory for RX buffers\n", sc->ste_unit); 1247 ste_stop(sc); 1248 STE_UNLOCK(sc); 1249 return; 1250 } 1251 1252 /* Set RX polling interval */ 1253 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1254 1255 /* Init TX descriptors */ 1256 ste_init_tx_list(sc); 1257 1258 /* Set the TX freethresh value */ 1259 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1260 1261 /* Set the TX start threshold for best performance. */ 1262 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1263 1264 /* Set the TX reclaim threshold. */ 1265 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1266 1267 /* Set up the RX filter. */ 1268 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1269 1270 /* If we want promiscuous mode, set the allframes bit. */ 1271 if (ifp->if_flags & IFF_PROMISC) { 1272 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1273 } else { 1274 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1275 } 1276 1277 /* Set capture broadcast bit to accept broadcast frames. */ 1278 if (ifp->if_flags & IFF_BROADCAST) { 1279 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1280 } else { 1281 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1282 } 1283 1284 ste_setmulti(sc); 1285 1286 /* Load the address of the RX list. */ 1287 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1288 ste_wait(sc); 1289 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1290 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1291 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1292 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1293 1294 /* Set TX polling interval (defer until we TX first packet */ 1295 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1296 1297 /* Load address of the TX list */ 1298 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1299 ste_wait(sc); 1300 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1301 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1302 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1303 ste_wait(sc); 1304 sc->ste_tx_prev_idx=-1; 1305 1306 /* Enable receiver and transmitter */ 1307 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1308 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1309 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1310 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1311 1312 /* Enable stats counters. */ 1313 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1314 1315 /* Enable interrupts. */ 1316 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1317 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1318 1319 /* Accept VLAN length packets */ 1320 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1321 1322 ste_ifmedia_upd(ifp); 1323 1324 ifp->if_flags |= IFF_RUNNING; 1325 ifp->if_flags &= ~IFF_OACTIVE; 1326 1327 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1328 STE_UNLOCK(sc); 1329 1330 return; 1331 } 1332 1333 static void 1334 ste_stop(sc) 1335 struct ste_softc *sc; 1336 { 1337 int i; 1338 struct ifnet *ifp; 1339 1340 STE_LOCK(sc); 1341 ifp = &sc->arpcom.ac_if; 1342 1343 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1344 1345 CSR_WRITE_2(sc, STE_IMR, 0); 1346 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1347 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1348 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1349 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1350 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1351 ste_wait(sc); 1352 /* 1353 * Try really hard to stop the RX engine or under heavy RX 1354 * data chip will write into de-allocated memory. 1355 */ 1356 ste_reset(sc); 1357 1358 sc->ste_link = 0; 1359 1360 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1361 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1362 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1363 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1364 } 1365 } 1366 1367 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1368 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1369 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1370 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1371 } 1372 } 1373 1374 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1375 1376 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1377 STE_UNLOCK(sc); 1378 1379 return; 1380 } 1381 1382 static void 1383 ste_reset(sc) 1384 struct ste_softc *sc; 1385 { 1386 int i; 1387 1388 STE_SETBIT4(sc, STE_ASICCTL, 1389 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1390 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1391 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1392 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1393 STE_ASICCTL_EXTRESET_RESET); 1394 1395 DELAY(100000); 1396 1397 for (i = 0; i < STE_TIMEOUT; i++) { 1398 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1399 break; 1400 } 1401 1402 if (i == STE_TIMEOUT) 1403 printf("ste%d: global reset never completed\n", sc->ste_unit); 1404 1405 return; 1406 } 1407 1408 static int 1409 ste_ioctl(ifp, command, data) 1410 struct ifnet *ifp; 1411 u_long command; 1412 caddr_t data; 1413 { 1414 struct ste_softc *sc; 1415 struct ifreq *ifr; 1416 struct mii_data *mii; 1417 int error = 0; 1418 1419 sc = ifp->if_softc; 1420 STE_LOCK(sc); 1421 ifr = (struct ifreq *)data; 1422 1423 switch(command) { 1424 case SIOCSIFFLAGS: 1425 if (ifp->if_flags & IFF_UP) { 1426 if (ifp->if_flags & IFF_RUNNING && 1427 ifp->if_flags & IFF_PROMISC && 1428 !(sc->ste_if_flags & IFF_PROMISC)) { 1429 STE_SETBIT1(sc, STE_RX_MODE, 1430 STE_RXMODE_PROMISC); 1431 } else if (ifp->if_flags & IFF_RUNNING && 1432 !(ifp->if_flags & IFF_PROMISC) && 1433 sc->ste_if_flags & IFF_PROMISC) { 1434 STE_CLRBIT1(sc, STE_RX_MODE, 1435 STE_RXMODE_PROMISC); 1436 } 1437 if (!(ifp->if_flags & IFF_RUNNING)) { 1438 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1439 ste_init(sc); 1440 } 1441 } else { 1442 if (ifp->if_flags & IFF_RUNNING) 1443 ste_stop(sc); 1444 } 1445 sc->ste_if_flags = ifp->if_flags; 1446 error = 0; 1447 break; 1448 case SIOCADDMULTI: 1449 case SIOCDELMULTI: 1450 ste_setmulti(sc); 1451 error = 0; 1452 break; 1453 case SIOCGIFMEDIA: 1454 case SIOCSIFMEDIA: 1455 mii = device_get_softc(sc->ste_miibus); 1456 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1457 break; 1458 default: 1459 error = ether_ioctl(ifp, command, data); 1460 break; 1461 } 1462 1463 STE_UNLOCK(sc); 1464 1465 return(error); 1466 } 1467 1468 static int 1469 ste_encap(sc, c, m_head) 1470 struct ste_softc *sc; 1471 struct ste_chain *c; 1472 struct mbuf *m_head; 1473 { 1474 int frag = 0; 1475 struct ste_frag *f = NULL; 1476 struct mbuf *m; 1477 struct ste_desc *d; 1478 int total_len = 0; 1479 1480 d = c->ste_ptr; 1481 d->ste_ctl = 0; 1482 1483 encap_retry: 1484 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1485 if (m->m_len != 0) { 1486 if (frag == STE_MAXFRAGS) 1487 break; 1488 total_len += m->m_len; 1489 f = &d->ste_frags[frag]; 1490 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1491 f->ste_len = m->m_len; 1492 frag++; 1493 } 1494 } 1495 1496 if (m != NULL) { 1497 struct mbuf *mn; 1498 1499 /* 1500 * We ran out of segments. We have to recopy this 1501 * mbuf chain first. Bail out if we can't get the 1502 * new buffers. Code borrowed from if_fxp.c 1503 */ 1504 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1505 if (mn == NULL) { 1506 m_freem(m_head); 1507 return ENOMEM; 1508 } 1509 if (m_head->m_pkthdr.len > MHLEN) { 1510 MCLGET(mn, M_DONTWAIT); 1511 if ((mn->m_flags & M_EXT) == 0) { 1512 m_freem(mn); 1513 m_freem(m_head); 1514 return ENOMEM; 1515 } 1516 } 1517 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1518 mtod(mn, caddr_t)); 1519 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1520 m_freem(m_head); 1521 m_head = mn; 1522 goto encap_retry; 1523 } 1524 1525 c->ste_mbuf = m_head; 1526 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1527 d->ste_ctl = 1; 1528 1529 return(0); 1530 } 1531 1532 static void 1533 ste_start(ifp) 1534 struct ifnet *ifp; 1535 { 1536 struct ste_softc *sc; 1537 struct mbuf *m_head = NULL; 1538 struct ste_chain *cur_tx = NULL; 1539 int idx; 1540 1541 sc = ifp->if_softc; 1542 STE_LOCK(sc); 1543 1544 if (!sc->ste_link) { 1545 STE_UNLOCK(sc); 1546 return; 1547 } 1548 1549 if (ifp->if_flags & IFF_OACTIVE) { 1550 STE_UNLOCK(sc); 1551 return; 1552 } 1553 1554 idx = sc->ste_cdata.ste_tx_prod; 1555 1556 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1557 1558 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1559 ifp->if_flags |= IFF_OACTIVE; 1560 break; 1561 } 1562 1563 IF_DEQUEUE(&ifp->if_snd, m_head); 1564 if (m_head == NULL) 1565 break; 1566 1567 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1568 1569 if (ste_encap(sc, cur_tx, m_head) != 0) 1570 break; 1571 1572 cur_tx->ste_ptr->ste_next = 0; 1573 1574 if(sc->ste_tx_prev_idx < 0){ 1575 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1576 /* Load address of the TX list */ 1577 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1578 ste_wait(sc); 1579 1580 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1581 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1582 1583 /* Set TX polling interval to start TX engine */ 1584 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1585 1586 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1587 ste_wait(sc); 1588 }else{ 1589 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1590 sc->ste_cdata.ste_tx_chain[ 1591 sc->ste_tx_prev_idx].ste_ptr->ste_next 1592 = cur_tx->ste_phys; 1593 } 1594 1595 sc->ste_tx_prev_idx=idx; 1596 1597 /* 1598 * If there's a BPF listener, bounce a copy of this frame 1599 * to him. 1600 */ 1601 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1602 1603 STE_INC(idx, STE_TX_LIST_CNT); 1604 sc->ste_cdata.ste_tx_cnt++; 1605 ifp->if_timer = 5; 1606 sc->ste_cdata.ste_tx_prod = idx; 1607 } 1608 1609 STE_UNLOCK(sc); 1610 1611 return; 1612 } 1613 1614 static void 1615 ste_watchdog(ifp) 1616 struct ifnet *ifp; 1617 { 1618 struct ste_softc *sc; 1619 1620 sc = ifp->if_softc; 1621 STE_LOCK(sc); 1622 1623 ifp->if_oerrors++; 1624 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1625 1626 ste_txeoc(sc); 1627 ste_txeof(sc); 1628 ste_rxeof(sc); 1629 ste_reset(sc); 1630 ste_init(sc); 1631 1632 if (ifp->if_snd.ifq_head != NULL) 1633 ste_start(ifp); 1634 STE_UNLOCK(sc); 1635 1636 return; 1637 } 1638 1639 static void 1640 ste_shutdown(dev) 1641 device_t dev; 1642 { 1643 struct ste_softc *sc; 1644 1645 sc = device_get_softc(dev); 1646 1647 ste_stop(sc); 1648 1649 return; 1650 }
Cache object: e57a8355cf045cbb64875c3ecce5b093
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