Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_ste.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/5.2/sys/pci/if_ste.c 122689 2003-11-14 19:00:32Z sam $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/ethernet.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 #include <net/if_vlan_var.h> 50 51 #include <net/bpf.h> 52 53 #include <vm/vm.h> /* for vtophys */ 54 #include <vm/pmap.h> /* for vtophys */ 55 #include <machine/bus_memio.h> 56 #include <machine/bus_pio.h> 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 /* "controller miibus0" required. See GENERIC if you get errors here. */ 69 #include "miibus_if.h" 70 71 #define STE_USEIOSPACE 72 73 #include <pci/if_stereg.h> 74 75 MODULE_DEPEND(ste, pci, 1, 1, 1); 76 MODULE_DEPEND(ste, ether, 1, 1, 1); 77 MODULE_DEPEND(ste, miibus, 1, 1, 1); 78 79 /* 80 * Various supported device vendors/types and their names. 81 */ 82 static struct ste_type ste_devs[] = { 83 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 84 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 85 { 0, 0, NULL } 86 }; 87 88 static int ste_probe (device_t); 89 static int ste_attach (device_t); 90 static int ste_detach (device_t); 91 static void ste_init (void *); 92 static void ste_intr (void *); 93 static void ste_rxeof (struct ste_softc *); 94 static void ste_txeoc (struct ste_softc *); 95 static void ste_txeof (struct ste_softc *); 96 static void ste_stats_update (void *); 97 static void ste_stop (struct ste_softc *); 98 static void ste_reset (struct ste_softc *); 99 static int ste_ioctl (struct ifnet *, u_long, caddr_t); 100 static int ste_encap (struct ste_softc *, struct ste_chain *, 101 struct mbuf *); 102 static void ste_start (struct ifnet *); 103 static void ste_watchdog (struct ifnet *); 104 static void ste_shutdown (device_t); 105 static int ste_newbuf (struct ste_softc *, 106 struct ste_chain_onefrag *, 107 struct mbuf *); 108 static int ste_ifmedia_upd (struct ifnet *); 109 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 111 static void ste_mii_sync (struct ste_softc *); 112 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 113 static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 114 static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 115 static int ste_miibus_readreg (device_t, int, int); 116 static int ste_miibus_writereg (device_t, int, int, int); 117 static void ste_miibus_statchg (device_t); 118 119 static int ste_eeprom_wait (struct ste_softc *); 120 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 121 static void ste_wait (struct ste_softc *); 122 static u_int32_t ste_mchash (caddr_t); 123 static void ste_setmulti (struct ste_softc *); 124 static int ste_init_rx_list (struct ste_softc *); 125 static void ste_init_tx_list (struct ste_softc *); 126 127 #ifdef STE_USEIOSPACE 128 #define STE_RES SYS_RES_IOPORT 129 #define STE_RID STE_PCI_LOIO 130 #else 131 #define STE_RES SYS_RES_MEMORY 132 #define STE_RID STE_PCI_LOMEM 133 #endif 134 135 static device_method_t ste_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ste_probe), 138 DEVMETHOD(device_attach, ste_attach), 139 DEVMETHOD(device_detach, ste_detach), 140 DEVMETHOD(device_shutdown, ste_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 148 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 149 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 150 151 { 0, 0 } 152 }; 153 154 static driver_t ste_driver = { 155 "ste", 156 ste_methods, 157 sizeof(struct ste_softc) 158 }; 159 160 static devclass_t ste_devclass; 161 162 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 163 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 164 165 #define STE_SETBIT4(sc, reg, x) \ 166 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 167 168 #define STE_CLRBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 170 171 #define STE_SETBIT2(sc, reg, x) \ 172 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 173 174 #define STE_CLRBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 176 177 #define STE_SETBIT1(sc, reg, x) \ 178 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 179 180 #define STE_CLRBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 182 183 184 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 185 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 186 187 /* 188 * Sync the PHYs by setting data bit and strobing the clock 32 times. 189 */ 190 static void 191 ste_mii_sync(sc) 192 struct ste_softc *sc; 193 { 194 register int i; 195 196 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 197 198 for (i = 0; i < 32; i++) { 199 MII_SET(STE_PHYCTL_MCLK); 200 DELAY(1); 201 MII_CLR(STE_PHYCTL_MCLK); 202 DELAY(1); 203 } 204 205 return; 206 } 207 208 /* 209 * Clock a series of bits through the MII. 210 */ 211 static void 212 ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216 { 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232 } 233 234 /* 235 * Read an PHY register through the MII. 236 */ 237 static int 238 ste_mii_readreg(sc, frame) 239 struct ste_softc *sc; 240 struct ste_mii_frame *frame; 241 242 { 243 int i, ack; 244 245 STE_LOCK(sc); 246 247 /* 248 * Set up frame for RX. 249 */ 250 frame->mii_stdelim = STE_MII_STARTDELIM; 251 frame->mii_opcode = STE_MII_READOP; 252 frame->mii_turnaround = 0; 253 frame->mii_data = 0; 254 255 CSR_WRITE_2(sc, STE_PHYCTL, 0); 256 /* 257 * Turn on data xmit. 258 */ 259 MII_SET(STE_PHYCTL_MDIR); 260 261 ste_mii_sync(sc); 262 263 /* 264 * Send command/address info. 265 */ 266 ste_mii_send(sc, frame->mii_stdelim, 2); 267 ste_mii_send(sc, frame->mii_opcode, 2); 268 ste_mii_send(sc, frame->mii_phyaddr, 5); 269 ste_mii_send(sc, frame->mii_regaddr, 5); 270 271 /* Turn off xmit. */ 272 MII_CLR(STE_PHYCTL_MDIR); 273 274 /* Idle bit */ 275 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 276 DELAY(1); 277 MII_SET(STE_PHYCTL_MCLK); 278 DELAY(1); 279 280 /* Check for ack */ 281 MII_CLR(STE_PHYCTL_MCLK); 282 DELAY(1); 283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* 288 * Now try reading data bits. If the ack failed, we still 289 * need to clock through 16 cycles to keep the PHY(s) in sync. 290 */ 291 if (ack) { 292 for(i = 0; i < 16; i++) { 293 MII_CLR(STE_PHYCTL_MCLK); 294 DELAY(1); 295 MII_SET(STE_PHYCTL_MCLK); 296 DELAY(1); 297 } 298 goto fail; 299 } 300 301 for (i = 0x8000; i; i >>= 1) { 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 if (!ack) { 305 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 306 frame->mii_data |= i; 307 DELAY(1); 308 } 309 MII_SET(STE_PHYCTL_MCLK); 310 DELAY(1); 311 } 312 313 fail: 314 315 MII_CLR(STE_PHYCTL_MCLK); 316 DELAY(1); 317 MII_SET(STE_PHYCTL_MCLK); 318 DELAY(1); 319 320 STE_UNLOCK(sc); 321 322 if (ack) 323 return(1); 324 return(0); 325 } 326 327 /* 328 * Write to a PHY register through the MII. 329 */ 330 static int 331 ste_mii_writereg(sc, frame) 332 struct ste_softc *sc; 333 struct ste_mii_frame *frame; 334 335 { 336 STE_LOCK(sc); 337 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 STE_UNLOCK(sc); 372 373 return(0); 374 } 375 376 static int 377 ste_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380 { 381 struct ste_softc *sc; 382 struct ste_mii_frame frame; 383 384 sc = device_get_softc(dev); 385 386 if ( sc->ste_one_phy && phy != 0 ) 387 return (0); 388 389 bzero((char *)&frame, sizeof(frame)); 390 391 frame.mii_phyaddr = phy; 392 frame.mii_regaddr = reg; 393 ste_mii_readreg(sc, &frame); 394 395 return(frame.mii_data); 396 } 397 398 static int 399 ste_miibus_writereg(dev, phy, reg, data) 400 device_t dev; 401 int phy, reg, data; 402 { 403 struct ste_softc *sc; 404 struct ste_mii_frame frame; 405 406 sc = device_get_softc(dev); 407 bzero((char *)&frame, sizeof(frame)); 408 409 frame.mii_phyaddr = phy; 410 frame.mii_regaddr = reg; 411 frame.mii_data = data; 412 413 ste_mii_writereg(sc, &frame); 414 415 return(0); 416 } 417 418 static void 419 ste_miibus_statchg(dev) 420 device_t dev; 421 { 422 struct ste_softc *sc; 423 struct mii_data *mii; 424 425 sc = device_get_softc(dev); 426 STE_LOCK(sc); 427 mii = device_get_softc(sc->ste_miibus); 428 429 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 430 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } else { 432 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } 434 STE_UNLOCK(sc); 435 436 return; 437 } 438 439 static int 440 ste_ifmedia_upd(ifp) 441 struct ifnet *ifp; 442 { 443 struct ste_softc *sc; 444 struct mii_data *mii; 445 446 sc = ifp->if_softc; 447 mii = device_get_softc(sc->ste_miibus); 448 sc->ste_link = 0; 449 if (mii->mii_instance) { 450 struct mii_softc *miisc; 451 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 452 mii_phy_reset(miisc); 453 } 454 mii_mediachg(mii); 455 456 return(0); 457 } 458 459 static void 460 ste_ifmedia_sts(ifp, ifmr) 461 struct ifnet *ifp; 462 struct ifmediareq *ifmr; 463 { 464 struct ste_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 mii = device_get_softc(sc->ste_miibus); 469 470 mii_pollstat(mii); 471 ifmr->ifm_active = mii->mii_media_active; 472 ifmr->ifm_status = mii->mii_media_status; 473 474 return; 475 } 476 477 static void 478 ste_wait(sc) 479 struct ste_softc *sc; 480 { 481 register int i; 482 483 for (i = 0; i < STE_TIMEOUT; i++) { 484 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 485 break; 486 } 487 488 if (i == STE_TIMEOUT) 489 printf("ste%d: command never completed!\n", sc->ste_unit); 490 491 return; 492 } 493 494 /* 495 * The EEPROM is slow: give it time to come ready after issuing 496 * it a command. 497 */ 498 static int 499 ste_eeprom_wait(sc) 500 struct ste_softc *sc; 501 { 502 int i; 503 504 DELAY(1000); 505 506 for (i = 0; i < 100; i++) { 507 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 508 DELAY(1000); 509 else 510 break; 511 } 512 513 if (i == 100) { 514 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 515 return(1); 516 } 517 518 return(0); 519 } 520 521 /* 522 * Read a sequence of words from the EEPROM. Note that ethernet address 523 * data is stored in the EEPROM in network byte order. 524 */ 525 static int 526 ste_read_eeprom(sc, dest, off, cnt, swap) 527 struct ste_softc *sc; 528 caddr_t dest; 529 int off; 530 int cnt; 531 int swap; 532 { 533 int err = 0, i; 534 u_int16_t word = 0, *ptr; 535 536 if (ste_eeprom_wait(sc)) 537 return(1); 538 539 for (i = 0; i < cnt; i++) { 540 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 541 err = ste_eeprom_wait(sc); 542 if (err) 543 break; 544 word = CSR_READ_2(sc, STE_EEPROM_DATA); 545 ptr = (u_int16_t *)(dest + (i * 2)); 546 if (swap) 547 *ptr = ntohs(word); 548 else 549 *ptr = word; 550 } 551 552 return(err ? 1 : 0); 553 } 554 555 static u_int32_t 556 ste_mchash(addr) 557 caddr_t addr; 558 { 559 560 u_int32_t crc, carry; 561 int idx, bit; 562 u_int8_t data; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xFFFFFFFF; /* initial value */ 566 567 for (idx = 0; idx < 6; idx++) { 568 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 569 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 570 crc <<= 1; 571 if (carry) 572 crc = (crc ^ 0x04c11db6) | carry; 573 } 574 } 575 576 /* return the filter bit position */ 577 return(crc & 0x0000003F); 578 } 579 580 static void 581 ste_setmulti(sc) 582 struct ste_softc *sc; 583 { 584 struct ifnet *ifp; 585 int h = 0; 586 u_int32_t hashes[2] = { 0, 0 }; 587 struct ifmultiaddr *ifma; 588 589 ifp = &sc->arpcom.ac_if; 590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 591 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 592 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 593 return; 594 } 595 596 /* first, zot all the existing hash bits */ 597 CSR_WRITE_2(sc, STE_MAR0, 0); 598 CSR_WRITE_2(sc, STE_MAR1, 0); 599 CSR_WRITE_2(sc, STE_MAR2, 0); 600 CSR_WRITE_2(sc, STE_MAR3, 0); 601 602 /* now program new ones */ 603 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 604 if (ifma->ifma_addr->sa_family != AF_LINK) 605 continue; 606 h = ste_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 607 if (h < 32) 608 hashes[0] |= (1 << h); 609 else 610 hashes[1] |= (1 << (h - 32)); 611 } 612 613 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 614 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 615 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 617 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 618 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 619 620 return; 621 } 622 623 static void 624 ste_intr(xsc) 625 void *xsc; 626 { 627 struct ste_softc *sc; 628 struct ifnet *ifp; 629 u_int16_t status; 630 631 sc = xsc; 632 STE_LOCK(sc); 633 ifp = &sc->arpcom.ac_if; 634 635 /* See if this is really our interrupt. */ 636 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 637 STE_UNLOCK(sc); 638 return; 639 } 640 641 for (;;) { 642 status = CSR_READ_2(sc, STE_ISR_ACK); 643 644 if (!(status & STE_INTRS)) 645 break; 646 647 if (status & STE_ISR_RX_DMADONE) 648 ste_rxeof(sc); 649 650 if (status & STE_ISR_TX_DMADONE) 651 ste_txeof(sc); 652 653 if (status & STE_ISR_TX_DONE) 654 ste_txeoc(sc); 655 656 if (status & STE_ISR_STATS_OFLOW) { 657 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 658 ste_stats_update(sc); 659 } 660 661 if (status & STE_ISR_LINKEVENT) 662 mii_pollstat(device_get_softc(sc->ste_miibus)); 663 664 665 if (status & STE_ISR_HOSTERR) { 666 ste_reset(sc); 667 ste_init(sc); 668 } 669 } 670 671 /* Re-enable interrupts */ 672 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 673 674 if (ifp->if_snd.ifq_head != NULL) 675 ste_start(ifp); 676 677 STE_UNLOCK(sc); 678 679 return; 680 } 681 682 /* 683 * A frame has been uploaded: pass the resulting mbuf chain up to 684 * the higher level protocols. 685 */ 686 static void 687 ste_rxeof(sc) 688 struct ste_softc *sc; 689 { 690 struct mbuf *m; 691 struct ifnet *ifp; 692 struct ste_chain_onefrag *cur_rx; 693 int total_len = 0, count=0; 694 u_int32_t rxstat; 695 696 STE_LOCK_ASSERT(sc); 697 698 ifp = &sc->arpcom.ac_if; 699 700 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 701 & STE_RXSTAT_DMADONE) { 702 if ((STE_RX_LIST_CNT - count) < 3) { 703 break; 704 } 705 706 cur_rx = sc->ste_cdata.ste_rx_head; 707 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 708 709 /* 710 * If an error occurs, update stats, clear the 711 * status word and leave the mbuf cluster in place: 712 * it should simply get re-used next time this descriptor 713 * comes up in the ring. 714 */ 715 if (rxstat & STE_RXSTAT_FRAME_ERR) { 716 ifp->if_ierrors++; 717 cur_rx->ste_ptr->ste_status = 0; 718 continue; 719 } 720 721 /* 722 * If there error bit was not set, the upload complete 723 * bit should be set which means we have a valid packet. 724 * If not, something truly strange has happened. 725 */ 726 if (!(rxstat & STE_RXSTAT_DMADONE)) { 727 printf("ste%d: bad receive status -- packet dropped\n", 728 sc->ste_unit); 729 ifp->if_ierrors++; 730 cur_rx->ste_ptr->ste_status = 0; 731 continue; 732 } 733 734 /* No errors; receive the packet. */ 735 m = cur_rx->ste_mbuf; 736 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 737 738 /* 739 * Try to conjure up a new mbuf cluster. If that 740 * fails, it means we have an out of memory condition and 741 * should leave the buffer in place and continue. This will 742 * result in a lost packet, but there's little else we 743 * can do in this situation. 744 */ 745 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 746 ifp->if_ierrors++; 747 cur_rx->ste_ptr->ste_status = 0; 748 continue; 749 } 750 751 m->m_pkthdr.rcvif = ifp; 752 m->m_pkthdr.len = m->m_len = total_len; 753 754 ifp->if_ipackets++; 755 STE_UNLOCK(sc); 756 (*ifp->if_input)(ifp, m); 757 STE_LOCK(sc); 758 759 cur_rx->ste_ptr->ste_status = 0; 760 count++; 761 } 762 763 return; 764 } 765 766 static void 767 ste_txeoc(sc) 768 struct ste_softc *sc; 769 { 770 u_int8_t txstat; 771 struct ifnet *ifp; 772 773 ifp = &sc->arpcom.ac_if; 774 775 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 776 STE_TXSTATUS_TXDONE) { 777 if (txstat & STE_TXSTATUS_UNDERRUN || 778 txstat & STE_TXSTATUS_EXCESSCOLLS || 779 txstat & STE_TXSTATUS_RECLAIMERR) { 780 ifp->if_oerrors++; 781 printf("ste%d: transmission error: %x\n", 782 sc->ste_unit, txstat); 783 784 ste_reset(sc); 785 ste_init(sc); 786 787 if (txstat & STE_TXSTATUS_UNDERRUN && 788 sc->ste_tx_thresh < STE_PACKET_SIZE) { 789 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 790 printf("ste%d: tx underrun, increasing tx" 791 " start threshold to %d bytes\n", 792 sc->ste_unit, sc->ste_tx_thresh); 793 } 794 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 795 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 796 (STE_PACKET_SIZE >> 4)); 797 } 798 ste_init(sc); 799 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 800 } 801 802 return; 803 } 804 805 static void 806 ste_txeof(sc) 807 struct ste_softc *sc; 808 { 809 struct ste_chain *cur_tx = NULL; 810 struct ifnet *ifp; 811 int idx; 812 813 ifp = &sc->arpcom.ac_if; 814 815 idx = sc->ste_cdata.ste_tx_cons; 816 while(idx != sc->ste_cdata.ste_tx_prod) { 817 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 818 819 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 820 break; 821 822 if (cur_tx->ste_mbuf != NULL) { 823 m_freem(cur_tx->ste_mbuf); 824 cur_tx->ste_mbuf = NULL; 825 } 826 827 ifp->if_opackets++; 828 829 sc->ste_cdata.ste_tx_cnt--; 830 STE_INC(idx, STE_TX_LIST_CNT); 831 ifp->if_timer = 0; 832 } 833 834 sc->ste_cdata.ste_tx_cons = idx; 835 836 if (cur_tx != NULL) 837 ifp->if_flags &= ~IFF_OACTIVE; 838 839 return; 840 } 841 842 static void 843 ste_stats_update(xsc) 844 void *xsc; 845 { 846 struct ste_softc *sc; 847 struct ifnet *ifp; 848 struct mii_data *mii; 849 850 sc = xsc; 851 STE_LOCK(sc); 852 853 ifp = &sc->arpcom.ac_if; 854 mii = device_get_softc(sc->ste_miibus); 855 856 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 857 + CSR_READ_1(sc, STE_MULTI_COLLS) 858 + CSR_READ_1(sc, STE_SINGLE_COLLS); 859 860 if (!sc->ste_link) { 861 mii_pollstat(mii); 862 if (mii->mii_media_status & IFM_ACTIVE && 863 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 864 sc->ste_link++; 865 /* 866 * we don't get a call-back on re-init so do it 867 * otherwise we get stuck in the wrong link state 868 */ 869 ste_miibus_statchg(sc->ste_dev); 870 if (ifp->if_snd.ifq_head != NULL) 871 ste_start(ifp); 872 } 873 } 874 875 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 876 STE_UNLOCK(sc); 877 878 return; 879 } 880 881 882 /* 883 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 884 * IDs against our list and return a device name if we find a match. 885 */ 886 static int 887 ste_probe(dev) 888 device_t dev; 889 { 890 struct ste_type *t; 891 892 t = ste_devs; 893 894 while(t->ste_name != NULL) { 895 if ((pci_get_vendor(dev) == t->ste_vid) && 896 (pci_get_device(dev) == t->ste_did)) { 897 device_set_desc(dev, t->ste_name); 898 return(0); 899 } 900 t++; 901 } 902 903 return(ENXIO); 904 } 905 906 /* 907 * Attach the interface. Allocate softc structures, do ifmedia 908 * setup and ethernet/BPF attach. 909 */ 910 static int 911 ste_attach(dev) 912 device_t dev; 913 { 914 struct ste_softc *sc; 915 struct ifnet *ifp; 916 int unit, error = 0, rid; 917 918 sc = device_get_softc(dev); 919 unit = device_get_unit(dev); 920 sc->ste_dev = dev; 921 922 /* 923 * Only use one PHY since this chip reports multiple 924 * Note on the DFE-550 the PHY is at 1 on the DFE-580 925 * it is at 0 & 1. It is rev 0x12. 926 */ 927 if (pci_get_vendor(dev) == DL_VENDORID && 928 pci_get_device(dev) == DL_DEVICEID_DL10050 && 929 pci_get_revid(dev) == 0x12 ) 930 sc->ste_one_phy = 1; 931 932 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 933 MTX_DEF | MTX_RECURSE); 934 #ifndef BURN_BRIDGES 935 /* 936 * Handle power management nonsense. 937 */ 938 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 939 u_int32_t iobase, membase, irq; 940 941 /* Save important PCI config data. */ 942 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 943 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 944 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 945 946 /* Reset the power state. */ 947 printf("ste%d: chip is in D%d power mode " 948 "-- setting to D0\n", unit, 949 pci_get_powerstate(dev)); 950 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 951 952 /* Restore PCI config data. */ 953 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 954 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 955 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 956 } 957 #endif 958 /* 959 * Map control/status registers. 960 */ 961 pci_enable_busmaster(dev); 962 963 rid = STE_RID; 964 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 965 0, ~0, 1, RF_ACTIVE); 966 967 if (sc->ste_res == NULL) { 968 printf ("ste%d: couldn't map ports/memory\n", unit); 969 error = ENXIO; 970 goto fail; 971 } 972 973 sc->ste_btag = rman_get_bustag(sc->ste_res); 974 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 975 976 /* Allocate interrupt */ 977 rid = 0; 978 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 979 RF_SHAREABLE | RF_ACTIVE); 980 981 if (sc->ste_irq == NULL) { 982 printf("ste%d: couldn't map interrupt\n", unit); 983 error = ENXIO; 984 goto fail; 985 } 986 987 callout_handle_init(&sc->ste_stat_ch); 988 989 /* Reset the adapter. */ 990 ste_reset(sc); 991 992 /* 993 * Get station address from the EEPROM. 994 */ 995 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 996 STE_EEADDR_NODE0, 3, 0)) { 997 printf("ste%d: failed to read station address\n", unit); 998 error = ENXIO;; 999 goto fail; 1000 } 1001 1002 /* 1003 * A Sundance chip was detected. Inform the world. 1004 */ 1005 printf("ste%d: Ethernet address: %6D\n", unit, 1006 sc->arpcom.ac_enaddr, ":"); 1007 1008 sc->ste_unit = unit; 1009 1010 /* Allocate the descriptor queues. */ 1011 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1012 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1013 1014 if (sc->ste_ldata == NULL) { 1015 printf("ste%d: no memory for list buffers!\n", unit); 1016 error = ENXIO; 1017 goto fail; 1018 } 1019 1020 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1021 1022 /* Do MII setup. */ 1023 if (mii_phy_probe(dev, &sc->ste_miibus, 1024 ste_ifmedia_upd, ste_ifmedia_sts)) { 1025 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1026 error = ENXIO; 1027 goto fail; 1028 } 1029 1030 ifp = &sc->arpcom.ac_if; 1031 ifp->if_softc = sc; 1032 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1033 ifp->if_mtu = ETHERMTU; 1034 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1035 ifp->if_ioctl = ste_ioctl; 1036 ifp->if_output = ether_output; 1037 ifp->if_start = ste_start; 1038 ifp->if_watchdog = ste_watchdog; 1039 ifp->if_init = ste_init; 1040 ifp->if_baudrate = 10000000; 1041 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1042 1043 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1044 1045 /* 1046 * Call MI attach routine. 1047 */ 1048 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1049 1050 /* 1051 * Tell the upper layer(s) we support long frames. 1052 */ 1053 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1054 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1055 1056 /* Hook interrupt last to avoid having to lock softc */ 1057 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1058 ste_intr, sc, &sc->ste_intrhand); 1059 1060 if (error) { 1061 printf("ste%d: couldn't set up irq\n", unit); 1062 ether_ifdetach(ifp); 1063 goto fail; 1064 } 1065 1066 fail: 1067 if (error) 1068 ste_detach(dev); 1069 1070 return(error); 1071 } 1072 1073 /* 1074 * Shutdown hardware and free up resources. This can be called any 1075 * time after the mutex has been initialized. It is called in both 1076 * the error case in attach and the normal detach case so it needs 1077 * to be careful about only freeing resources that have actually been 1078 * allocated. 1079 */ 1080 static int 1081 ste_detach(dev) 1082 device_t dev; 1083 { 1084 struct ste_softc *sc; 1085 struct ifnet *ifp; 1086 1087 sc = device_get_softc(dev); 1088 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1089 STE_LOCK(sc); 1090 ifp = &sc->arpcom.ac_if; 1091 1092 /* These should only be active if attach succeeded */ 1093 if (device_is_attached(dev)) { 1094 ste_stop(sc); 1095 ether_ifdetach(ifp); 1096 } 1097 if (sc->ste_miibus) 1098 device_delete_child(dev, sc->ste_miibus); 1099 bus_generic_detach(dev); 1100 1101 if (sc->ste_intrhand) 1102 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1103 if (sc->ste_irq) 1104 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1105 if (sc->ste_res) 1106 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1107 1108 if (sc->ste_ldata) { 1109 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1110 M_DEVBUF); 1111 } 1112 1113 STE_UNLOCK(sc); 1114 mtx_destroy(&sc->ste_mtx); 1115 1116 return(0); 1117 } 1118 1119 static int 1120 ste_newbuf(sc, c, m) 1121 struct ste_softc *sc; 1122 struct ste_chain_onefrag *c; 1123 struct mbuf *m; 1124 { 1125 struct mbuf *m_new = NULL; 1126 1127 if (m == NULL) { 1128 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1129 if (m_new == NULL) 1130 return(ENOBUFS); 1131 MCLGET(m_new, M_DONTWAIT); 1132 if (!(m_new->m_flags & M_EXT)) { 1133 m_freem(m_new); 1134 return(ENOBUFS); 1135 } 1136 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1137 } else { 1138 m_new = m; 1139 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1140 m_new->m_data = m_new->m_ext.ext_buf; 1141 } 1142 1143 m_adj(m_new, ETHER_ALIGN); 1144 1145 c->ste_mbuf = m_new; 1146 c->ste_ptr->ste_status = 0; 1147 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1148 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1149 1150 return(0); 1151 } 1152 1153 static int 1154 ste_init_rx_list(sc) 1155 struct ste_softc *sc; 1156 { 1157 struct ste_chain_data *cd; 1158 struct ste_list_data *ld; 1159 int i; 1160 1161 cd = &sc->ste_cdata; 1162 ld = sc->ste_ldata; 1163 1164 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1165 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1166 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1167 return(ENOBUFS); 1168 if (i == (STE_RX_LIST_CNT - 1)) { 1169 cd->ste_rx_chain[i].ste_next = 1170 &cd->ste_rx_chain[0]; 1171 ld->ste_rx_list[i].ste_next = 1172 vtophys(&ld->ste_rx_list[0]); 1173 } else { 1174 cd->ste_rx_chain[i].ste_next = 1175 &cd->ste_rx_chain[i + 1]; 1176 ld->ste_rx_list[i].ste_next = 1177 vtophys(&ld->ste_rx_list[i + 1]); 1178 } 1179 ld->ste_rx_list[i].ste_status = 0; 1180 } 1181 1182 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1183 1184 return(0); 1185 } 1186 1187 static void 1188 ste_init_tx_list(sc) 1189 struct ste_softc *sc; 1190 { 1191 struct ste_chain_data *cd; 1192 struct ste_list_data *ld; 1193 int i; 1194 1195 cd = &sc->ste_cdata; 1196 ld = sc->ste_ldata; 1197 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1198 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1199 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1200 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1201 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1202 if (i == (STE_TX_LIST_CNT - 1)) 1203 cd->ste_tx_chain[i].ste_next = 1204 &cd->ste_tx_chain[0]; 1205 else 1206 cd->ste_tx_chain[i].ste_next = 1207 &cd->ste_tx_chain[i + 1]; 1208 if (i == 0) 1209 cd->ste_tx_chain[i].ste_prev = 1210 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1211 else 1212 cd->ste_tx_chain[i].ste_prev = 1213 &cd->ste_tx_chain[i - 1]; 1214 } 1215 1216 cd->ste_tx_prod = 0; 1217 cd->ste_tx_cons = 0; 1218 cd->ste_tx_cnt = 0; 1219 1220 return; 1221 } 1222 1223 static void 1224 ste_init(xsc) 1225 void *xsc; 1226 { 1227 struct ste_softc *sc; 1228 int i; 1229 struct ifnet *ifp; 1230 1231 sc = xsc; 1232 STE_LOCK(sc); 1233 ifp = &sc->arpcom.ac_if; 1234 1235 ste_stop(sc); 1236 1237 /* Init our MAC address */ 1238 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1239 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1240 } 1241 1242 /* Init RX list */ 1243 if (ste_init_rx_list(sc) == ENOBUFS) { 1244 printf("ste%d: initialization failed: no " 1245 "memory for RX buffers\n", sc->ste_unit); 1246 ste_stop(sc); 1247 STE_UNLOCK(sc); 1248 return; 1249 } 1250 1251 /* Set RX polling interval */ 1252 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1253 1254 /* Init TX descriptors */ 1255 ste_init_tx_list(sc); 1256 1257 /* Set the TX freethresh value */ 1258 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1259 1260 /* Set the TX start threshold for best performance. */ 1261 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1262 1263 /* Set the TX reclaim threshold. */ 1264 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1265 1266 /* Set up the RX filter. */ 1267 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1268 1269 /* If we want promiscuous mode, set the allframes bit. */ 1270 if (ifp->if_flags & IFF_PROMISC) { 1271 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1272 } else { 1273 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1274 } 1275 1276 /* Set capture broadcast bit to accept broadcast frames. */ 1277 if (ifp->if_flags & IFF_BROADCAST) { 1278 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1279 } else { 1280 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1281 } 1282 1283 ste_setmulti(sc); 1284 1285 /* Load the address of the RX list. */ 1286 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1287 ste_wait(sc); 1288 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1289 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1290 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1291 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1292 1293 /* Set TX polling interval (defer until we TX first packet */ 1294 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1295 1296 /* Load address of the TX list */ 1297 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1298 ste_wait(sc); 1299 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1300 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1301 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1302 ste_wait(sc); 1303 sc->ste_tx_prev_idx=-1; 1304 1305 /* Enable receiver and transmitter */ 1306 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1307 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1308 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1309 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1310 1311 /* Enable stats counters. */ 1312 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1313 1314 /* Enable interrupts. */ 1315 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1316 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1317 1318 /* Accept VLAN length packets */ 1319 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1320 1321 ste_ifmedia_upd(ifp); 1322 1323 ifp->if_flags |= IFF_RUNNING; 1324 ifp->if_flags &= ~IFF_OACTIVE; 1325 1326 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1327 STE_UNLOCK(sc); 1328 1329 return; 1330 } 1331 1332 static void 1333 ste_stop(sc) 1334 struct ste_softc *sc; 1335 { 1336 int i; 1337 struct ifnet *ifp; 1338 1339 STE_LOCK(sc); 1340 ifp = &sc->arpcom.ac_if; 1341 1342 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1343 1344 CSR_WRITE_2(sc, STE_IMR, 0); 1345 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1346 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1347 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1348 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1349 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1350 ste_wait(sc); 1351 /* 1352 * Try really hard to stop the RX engine or under heavy RX 1353 * data chip will write into de-allocated memory. 1354 */ 1355 ste_reset(sc); 1356 1357 sc->ste_link = 0; 1358 1359 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1360 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1361 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1362 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1363 } 1364 } 1365 1366 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1367 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1368 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1369 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1370 } 1371 } 1372 1373 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1374 1375 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1376 STE_UNLOCK(sc); 1377 1378 return; 1379 } 1380 1381 static void 1382 ste_reset(sc) 1383 struct ste_softc *sc; 1384 { 1385 int i; 1386 1387 STE_SETBIT4(sc, STE_ASICCTL, 1388 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1389 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1390 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1391 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1392 STE_ASICCTL_EXTRESET_RESET); 1393 1394 DELAY(100000); 1395 1396 for (i = 0; i < STE_TIMEOUT; i++) { 1397 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1398 break; 1399 } 1400 1401 if (i == STE_TIMEOUT) 1402 printf("ste%d: global reset never completed\n", sc->ste_unit); 1403 1404 return; 1405 } 1406 1407 static int 1408 ste_ioctl(ifp, command, data) 1409 struct ifnet *ifp; 1410 u_long command; 1411 caddr_t data; 1412 { 1413 struct ste_softc *sc; 1414 struct ifreq *ifr; 1415 struct mii_data *mii; 1416 int error = 0; 1417 1418 sc = ifp->if_softc; 1419 STE_LOCK(sc); 1420 ifr = (struct ifreq *)data; 1421 1422 switch(command) { 1423 case SIOCSIFFLAGS: 1424 if (ifp->if_flags & IFF_UP) { 1425 if (ifp->if_flags & IFF_RUNNING && 1426 ifp->if_flags & IFF_PROMISC && 1427 !(sc->ste_if_flags & IFF_PROMISC)) { 1428 STE_SETBIT1(sc, STE_RX_MODE, 1429 STE_RXMODE_PROMISC); 1430 } else if (ifp->if_flags & IFF_RUNNING && 1431 !(ifp->if_flags & IFF_PROMISC) && 1432 sc->ste_if_flags & IFF_PROMISC) { 1433 STE_CLRBIT1(sc, STE_RX_MODE, 1434 STE_RXMODE_PROMISC); 1435 } 1436 if (!(ifp->if_flags & IFF_RUNNING)) { 1437 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1438 ste_init(sc); 1439 } 1440 } else { 1441 if (ifp->if_flags & IFF_RUNNING) 1442 ste_stop(sc); 1443 } 1444 sc->ste_if_flags = ifp->if_flags; 1445 error = 0; 1446 break; 1447 case SIOCADDMULTI: 1448 case SIOCDELMULTI: 1449 ste_setmulti(sc); 1450 error = 0; 1451 break; 1452 case SIOCGIFMEDIA: 1453 case SIOCSIFMEDIA: 1454 mii = device_get_softc(sc->ste_miibus); 1455 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1456 break; 1457 default: 1458 error = ether_ioctl(ifp, command, data); 1459 break; 1460 } 1461 1462 STE_UNLOCK(sc); 1463 1464 return(error); 1465 } 1466 1467 static int 1468 ste_encap(sc, c, m_head) 1469 struct ste_softc *sc; 1470 struct ste_chain *c; 1471 struct mbuf *m_head; 1472 { 1473 int frag = 0; 1474 struct ste_frag *f = NULL; 1475 struct mbuf *m; 1476 struct ste_desc *d; 1477 1478 d = c->ste_ptr; 1479 d->ste_ctl = 0; 1480 1481 encap_retry: 1482 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1483 if (m->m_len != 0) { 1484 if (frag == STE_MAXFRAGS) 1485 break; 1486 f = &d->ste_frags[frag]; 1487 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1488 f->ste_len = m->m_len; 1489 frag++; 1490 } 1491 } 1492 1493 if (m != NULL) { 1494 struct mbuf *mn; 1495 1496 /* 1497 * We ran out of segments. We have to recopy this 1498 * mbuf chain first. Bail out if we can't get the 1499 * new buffers. Code borrowed from if_fxp.c 1500 */ 1501 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1502 if (mn == NULL) { 1503 m_freem(m_head); 1504 return ENOMEM; 1505 } 1506 if (m_head->m_pkthdr.len > MHLEN) { 1507 MCLGET(mn, M_DONTWAIT); 1508 if ((mn->m_flags & M_EXT) == 0) { 1509 m_freem(mn); 1510 m_freem(m_head); 1511 return ENOMEM; 1512 } 1513 } 1514 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1515 mtod(mn, caddr_t)); 1516 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1517 m_freem(m_head); 1518 m_head = mn; 1519 goto encap_retry; 1520 } 1521 1522 c->ste_mbuf = m_head; 1523 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1524 d->ste_ctl = 1; 1525 1526 return(0); 1527 } 1528 1529 static void 1530 ste_start(ifp) 1531 struct ifnet *ifp; 1532 { 1533 struct ste_softc *sc; 1534 struct mbuf *m_head = NULL; 1535 struct ste_chain *cur_tx = NULL; 1536 int idx; 1537 1538 sc = ifp->if_softc; 1539 STE_LOCK(sc); 1540 1541 if (!sc->ste_link) { 1542 STE_UNLOCK(sc); 1543 return; 1544 } 1545 1546 if (ifp->if_flags & IFF_OACTIVE) { 1547 STE_UNLOCK(sc); 1548 return; 1549 } 1550 1551 idx = sc->ste_cdata.ste_tx_prod; 1552 1553 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1554 1555 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1556 ifp->if_flags |= IFF_OACTIVE; 1557 break; 1558 } 1559 1560 IF_DEQUEUE(&ifp->if_snd, m_head); 1561 if (m_head == NULL) 1562 break; 1563 1564 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1565 1566 if (ste_encap(sc, cur_tx, m_head) != 0) 1567 break; 1568 1569 cur_tx->ste_ptr->ste_next = 0; 1570 1571 if(sc->ste_tx_prev_idx < 0){ 1572 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1573 /* Load address of the TX list */ 1574 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1575 ste_wait(sc); 1576 1577 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1578 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1579 1580 /* Set TX polling interval to start TX engine */ 1581 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1582 1583 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1584 ste_wait(sc); 1585 }else{ 1586 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1587 sc->ste_cdata.ste_tx_chain[ 1588 sc->ste_tx_prev_idx].ste_ptr->ste_next 1589 = cur_tx->ste_phys; 1590 } 1591 1592 sc->ste_tx_prev_idx=idx; 1593 1594 /* 1595 * If there's a BPF listener, bounce a copy of this frame 1596 * to him. 1597 */ 1598 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1599 1600 STE_INC(idx, STE_TX_LIST_CNT); 1601 sc->ste_cdata.ste_tx_cnt++; 1602 ifp->if_timer = 5; 1603 sc->ste_cdata.ste_tx_prod = idx; 1604 } 1605 1606 STE_UNLOCK(sc); 1607 1608 return; 1609 } 1610 1611 static void 1612 ste_watchdog(ifp) 1613 struct ifnet *ifp; 1614 { 1615 struct ste_softc *sc; 1616 1617 sc = ifp->if_softc; 1618 STE_LOCK(sc); 1619 1620 ifp->if_oerrors++; 1621 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1622 1623 ste_txeoc(sc); 1624 ste_txeof(sc); 1625 ste_rxeof(sc); 1626 ste_reset(sc); 1627 ste_init(sc); 1628 1629 if (ifp->if_snd.ifq_head != NULL) 1630 ste_start(ifp); 1631 STE_UNLOCK(sc); 1632 1633 return; 1634 } 1635 1636 static void 1637 ste_shutdown(dev) 1638 device_t dev; 1639 { 1640 struct ste_softc *sc; 1641 1642 sc = device_get_softc(dev); 1643 1644 ste_stop(sc); 1645 1646 return; 1647 }
Cache object: 0d805a8b3e739bbeec992f96a4a49338
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