Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_ste.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/5.4/sys/pci/if_ste.c 142884 2005-03-01 08:11:52Z imp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_vlan_var.h> 52 53 #include <net/bpf.h> 54 55 #include <vm/vm.h> /* for vtophys */ 56 #include <vm/pmap.h> /* for vtophys */ 57 #include <machine/bus_memio.h> 58 #include <machine/bus_pio.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/bus.h> 62 #include <sys/rman.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 /* "controller miibus0" required. See GENERIC if you get errors here. */ 71 #include "miibus_if.h" 72 73 #define STE_USEIOSPACE 74 75 #include <pci/if_stereg.h> 76 77 MODULE_DEPEND(ste, pci, 1, 1, 1); 78 MODULE_DEPEND(ste, ether, 1, 1, 1); 79 MODULE_DEPEND(ste, miibus, 1, 1, 1); 80 81 /* 82 * Various supported device vendors/types and their names. 83 */ 84 static struct ste_type ste_devs[] = { 85 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 86 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 87 { 0, 0, NULL } 88 }; 89 90 static int ste_probe(device_t); 91 static int ste_attach(device_t); 92 static int ste_detach(device_t); 93 static void ste_init(void *); 94 static void ste_intr(void *); 95 static void ste_rxeoc(struct ste_softc *); 96 static void ste_rxeof(struct ste_softc *); 97 static void ste_txeoc(struct ste_softc *); 98 static void ste_txeof(struct ste_softc *); 99 static void ste_stats_update(void *); 100 static void ste_stop(struct ste_softc *); 101 static void ste_reset(struct ste_softc *); 102 static int ste_ioctl(struct ifnet *, u_long, caddr_t); 103 static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *); 104 static void ste_start(struct ifnet *); 105 static void ste_watchdog(struct ifnet *); 106 static void ste_shutdown(device_t); 107 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *, 108 struct mbuf *); 109 static int ste_ifmedia_upd(struct ifnet *); 110 static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 111 112 static void ste_mii_sync(struct ste_softc *); 113 static void ste_mii_send(struct ste_softc *, u_int32_t, int); 114 static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 115 static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 116 static int ste_miibus_readreg(device_t, int, int); 117 static int ste_miibus_writereg(device_t, int, int, int); 118 static void ste_miibus_statchg(device_t); 119 120 static int ste_eeprom_wait(struct ste_softc *); 121 static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 122 static void ste_wait(struct ste_softc *); 123 static void ste_setmulti(struct ste_softc *); 124 static int ste_init_rx_list(struct ste_softc *); 125 static void ste_init_tx_list(struct ste_softc *); 126 127 #ifdef STE_USEIOSPACE 128 #define STE_RES SYS_RES_IOPORT 129 #define STE_RID STE_PCI_LOIO 130 #else 131 #define STE_RES SYS_RES_MEMORY 132 #define STE_RID STE_PCI_LOMEM 133 #endif 134 135 static device_method_t ste_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ste_probe), 138 DEVMETHOD(device_attach, ste_attach), 139 DEVMETHOD(device_detach, ste_detach), 140 DEVMETHOD(device_shutdown, ste_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 148 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 149 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 150 151 { 0, 0 } 152 }; 153 154 static driver_t ste_driver = { 155 "ste", 156 ste_methods, 157 sizeof(struct ste_softc) 158 }; 159 160 static devclass_t ste_devclass; 161 162 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 163 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 164 165 SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 166 167 static int ste_rxsyncs; 168 SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 169 170 #define STE_SETBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 172 173 #define STE_CLRBIT4(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 175 176 #define STE_SETBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 178 179 #define STE_CLRBIT2(sc, reg, x) \ 180 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 181 182 #define STE_SETBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 184 185 #define STE_CLRBIT1(sc, reg, x) \ 186 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 187 188 189 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 190 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 191 192 /* 193 * Sync the PHYs by setting data bit and strobing the clock 32 times. 194 */ 195 static void 196 ste_mii_sync(sc) 197 struct ste_softc *sc; 198 { 199 register int i; 200 201 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 202 203 for (i = 0; i < 32; i++) { 204 MII_SET(STE_PHYCTL_MCLK); 205 DELAY(1); 206 MII_CLR(STE_PHYCTL_MCLK); 207 DELAY(1); 208 } 209 210 return; 211 } 212 213 /* 214 * Clock a series of bits through the MII. 215 */ 216 static void 217 ste_mii_send(sc, bits, cnt) 218 struct ste_softc *sc; 219 u_int32_t bits; 220 int cnt; 221 { 222 int i; 223 224 MII_CLR(STE_PHYCTL_MCLK); 225 226 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 227 if (bits & i) { 228 MII_SET(STE_PHYCTL_MDATA); 229 } else { 230 MII_CLR(STE_PHYCTL_MDATA); 231 } 232 DELAY(1); 233 MII_CLR(STE_PHYCTL_MCLK); 234 DELAY(1); 235 MII_SET(STE_PHYCTL_MCLK); 236 } 237 } 238 239 /* 240 * Read an PHY register through the MII. 241 */ 242 static int 243 ste_mii_readreg(sc, frame) 244 struct ste_softc *sc; 245 struct ste_mii_frame *frame; 246 247 { 248 int i, ack; 249 250 STE_LOCK(sc); 251 252 /* 253 * Set up frame for RX. 254 */ 255 frame->mii_stdelim = STE_MII_STARTDELIM; 256 frame->mii_opcode = STE_MII_READOP; 257 frame->mii_turnaround = 0; 258 frame->mii_data = 0; 259 260 CSR_WRITE_2(sc, STE_PHYCTL, 0); 261 /* 262 * Turn on data xmit. 263 */ 264 MII_SET(STE_PHYCTL_MDIR); 265 266 ste_mii_sync(sc); 267 268 /* 269 * Send command/address info. 270 */ 271 ste_mii_send(sc, frame->mii_stdelim, 2); 272 ste_mii_send(sc, frame->mii_opcode, 2); 273 ste_mii_send(sc, frame->mii_phyaddr, 5); 274 ste_mii_send(sc, frame->mii_regaddr, 5); 275 276 /* Turn off xmit. */ 277 MII_CLR(STE_PHYCTL_MDIR); 278 279 /* Idle bit */ 280 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 281 DELAY(1); 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 285 /* Check for ack */ 286 MII_CLR(STE_PHYCTL_MCLK); 287 DELAY(1); 288 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 289 MII_SET(STE_PHYCTL_MCLK); 290 DELAY(1); 291 292 /* 293 * Now try reading data bits. If the ack failed, we still 294 * need to clock through 16 cycles to keep the PHY(s) in sync. 295 */ 296 if (ack) { 297 for(i = 0; i < 16; i++) { 298 MII_CLR(STE_PHYCTL_MCLK); 299 DELAY(1); 300 MII_SET(STE_PHYCTL_MCLK); 301 DELAY(1); 302 } 303 goto fail; 304 } 305 306 for (i = 0x8000; i; i >>= 1) { 307 MII_CLR(STE_PHYCTL_MCLK); 308 DELAY(1); 309 if (!ack) { 310 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 311 frame->mii_data |= i; 312 DELAY(1); 313 } 314 MII_SET(STE_PHYCTL_MCLK); 315 DELAY(1); 316 } 317 318 fail: 319 320 MII_CLR(STE_PHYCTL_MCLK); 321 DELAY(1); 322 MII_SET(STE_PHYCTL_MCLK); 323 DELAY(1); 324 325 STE_UNLOCK(sc); 326 327 if (ack) 328 return(1); 329 return(0); 330 } 331 332 /* 333 * Write to a PHY register through the MII. 334 */ 335 static int 336 ste_mii_writereg(sc, frame) 337 struct ste_softc *sc; 338 struct ste_mii_frame *frame; 339 340 { 341 STE_LOCK(sc); 342 343 /* 344 * Set up frame for TX. 345 */ 346 347 frame->mii_stdelim = STE_MII_STARTDELIM; 348 frame->mii_opcode = STE_MII_WRITEOP; 349 frame->mii_turnaround = STE_MII_TURNAROUND; 350 351 /* 352 * Turn on data output. 353 */ 354 MII_SET(STE_PHYCTL_MDIR); 355 356 ste_mii_sync(sc); 357 358 ste_mii_send(sc, frame->mii_stdelim, 2); 359 ste_mii_send(sc, frame->mii_opcode, 2); 360 ste_mii_send(sc, frame->mii_phyaddr, 5); 361 ste_mii_send(sc, frame->mii_regaddr, 5); 362 ste_mii_send(sc, frame->mii_turnaround, 2); 363 ste_mii_send(sc, frame->mii_data, 16); 364 365 /* Idle bit. */ 366 MII_SET(STE_PHYCTL_MCLK); 367 DELAY(1); 368 MII_CLR(STE_PHYCTL_MCLK); 369 DELAY(1); 370 371 /* 372 * Turn off xmit. 373 */ 374 MII_CLR(STE_PHYCTL_MDIR); 375 376 STE_UNLOCK(sc); 377 378 return(0); 379 } 380 381 static int 382 ste_miibus_readreg(dev, phy, reg) 383 device_t dev; 384 int phy, reg; 385 { 386 struct ste_softc *sc; 387 struct ste_mii_frame frame; 388 389 sc = device_get_softc(dev); 390 391 if ( sc->ste_one_phy && phy != 0 ) 392 return (0); 393 394 bzero((char *)&frame, sizeof(frame)); 395 396 frame.mii_phyaddr = phy; 397 frame.mii_regaddr = reg; 398 ste_mii_readreg(sc, &frame); 399 400 return(frame.mii_data); 401 } 402 403 static int 404 ste_miibus_writereg(dev, phy, reg, data) 405 device_t dev; 406 int phy, reg, data; 407 { 408 struct ste_softc *sc; 409 struct ste_mii_frame frame; 410 411 sc = device_get_softc(dev); 412 bzero((char *)&frame, sizeof(frame)); 413 414 frame.mii_phyaddr = phy; 415 frame.mii_regaddr = reg; 416 frame.mii_data = data; 417 418 ste_mii_writereg(sc, &frame); 419 420 return(0); 421 } 422 423 static void 424 ste_miibus_statchg(dev) 425 device_t dev; 426 { 427 struct ste_softc *sc; 428 struct mii_data *mii; 429 430 sc = device_get_softc(dev); 431 STE_LOCK(sc); 432 mii = device_get_softc(sc->ste_miibus); 433 434 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 435 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 436 } else { 437 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 438 } 439 STE_UNLOCK(sc); 440 441 return; 442 } 443 444 static int 445 ste_ifmedia_upd(ifp) 446 struct ifnet *ifp; 447 { 448 struct ste_softc *sc; 449 struct mii_data *mii; 450 451 sc = ifp->if_softc; 452 mii = device_get_softc(sc->ste_miibus); 453 sc->ste_link = 0; 454 if (mii->mii_instance) { 455 struct mii_softc *miisc; 456 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 457 mii_phy_reset(miisc); 458 } 459 mii_mediachg(mii); 460 461 return(0); 462 } 463 464 static void 465 ste_ifmedia_sts(ifp, ifmr) 466 struct ifnet *ifp; 467 struct ifmediareq *ifmr; 468 { 469 struct ste_softc *sc; 470 struct mii_data *mii; 471 472 sc = ifp->if_softc; 473 mii = device_get_softc(sc->ste_miibus); 474 475 mii_pollstat(mii); 476 ifmr->ifm_active = mii->mii_media_active; 477 ifmr->ifm_status = mii->mii_media_status; 478 479 return; 480 } 481 482 static void 483 ste_wait(sc) 484 struct ste_softc *sc; 485 { 486 register int i; 487 488 for (i = 0; i < STE_TIMEOUT; i++) { 489 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 490 break; 491 } 492 493 if (i == STE_TIMEOUT) 494 printf("ste%d: command never completed!\n", sc->ste_unit); 495 496 return; 497 } 498 499 /* 500 * The EEPROM is slow: give it time to come ready after issuing 501 * it a command. 502 */ 503 static int 504 ste_eeprom_wait(sc) 505 struct ste_softc *sc; 506 { 507 int i; 508 509 DELAY(1000); 510 511 for (i = 0; i < 100; i++) { 512 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 513 DELAY(1000); 514 else 515 break; 516 } 517 518 if (i == 100) { 519 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 520 return(1); 521 } 522 523 return(0); 524 } 525 526 /* 527 * Read a sequence of words from the EEPROM. Note that ethernet address 528 * data is stored in the EEPROM in network byte order. 529 */ 530 static int 531 ste_read_eeprom(sc, dest, off, cnt, swap) 532 struct ste_softc *sc; 533 caddr_t dest; 534 int off; 535 int cnt; 536 int swap; 537 { 538 int err = 0, i; 539 u_int16_t word = 0, *ptr; 540 541 if (ste_eeprom_wait(sc)) 542 return(1); 543 544 for (i = 0; i < cnt; i++) { 545 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 546 err = ste_eeprom_wait(sc); 547 if (err) 548 break; 549 word = CSR_READ_2(sc, STE_EEPROM_DATA); 550 ptr = (u_int16_t *)(dest + (i * 2)); 551 if (swap) 552 *ptr = ntohs(word); 553 else 554 *ptr = word; 555 } 556 557 return(err ? 1 : 0); 558 } 559 560 static void 561 ste_setmulti(sc) 562 struct ste_softc *sc; 563 { 564 struct ifnet *ifp; 565 int h = 0; 566 u_int32_t hashes[2] = { 0, 0 }; 567 struct ifmultiaddr *ifma; 568 569 ifp = &sc->arpcom.ac_if; 570 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 571 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 572 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 573 return; 574 } 575 576 /* first, zot all the existing hash bits */ 577 CSR_WRITE_2(sc, STE_MAR0, 0); 578 CSR_WRITE_2(sc, STE_MAR1, 0); 579 CSR_WRITE_2(sc, STE_MAR2, 0); 580 CSR_WRITE_2(sc, STE_MAR3, 0); 581 582 /* now program new ones */ 583 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 584 if (ifma->ifma_addr->sa_family != AF_LINK) 585 continue; 586 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 587 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 588 if (h < 32) 589 hashes[0] |= (1 << h); 590 else 591 hashes[1] |= (1 << (h - 32)); 592 } 593 594 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 595 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 596 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 597 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 598 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 599 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 600 601 return; 602 } 603 604 #ifdef DEVICE_POLLING 605 static poll_handler_t ste_poll; 606 607 static void 608 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 609 { 610 struct ste_softc *sc = ifp->if_softc; 611 612 STE_LOCK(sc); 613 if (!(ifp->if_capenable & IFCAP_POLLING)) { 614 ether_poll_deregister(ifp); 615 cmd = POLL_DEREGISTER; 616 } 617 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 618 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 619 goto done; 620 } 621 622 sc->rxcycles = count; 623 if (cmd == POLL_AND_CHECK_STATUS) 624 ste_rxeoc(sc); 625 ste_rxeof(sc); 626 ste_txeof(sc); 627 if (ifp->if_snd.ifq_head != NULL) 628 ste_start(ifp); 629 630 if (cmd == POLL_AND_CHECK_STATUS) { 631 u_int16_t status; 632 633 status = CSR_READ_2(sc, STE_ISR_ACK); 634 635 if (status & STE_ISR_TX_DONE) 636 ste_txeoc(sc); 637 638 if (status & STE_ISR_STATS_OFLOW) { 639 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 640 ste_stats_update(sc); 641 } 642 643 if (status & STE_ISR_LINKEVENT) 644 mii_pollstat(device_get_softc(sc->ste_miibus)); 645 646 if (status & STE_ISR_HOSTERR) { 647 ste_reset(sc); 648 ste_init(sc); 649 } 650 } 651 done: 652 STE_UNLOCK(sc); 653 } 654 #endif /* DEVICE_POLLING */ 655 656 static void 657 ste_intr(xsc) 658 void *xsc; 659 { 660 struct ste_softc *sc; 661 struct ifnet *ifp; 662 u_int16_t status; 663 664 sc = xsc; 665 STE_LOCK(sc); 666 ifp = &sc->arpcom.ac_if; 667 668 #ifdef DEVICE_POLLING 669 if (ifp->if_flags & IFF_POLLING) 670 goto done; 671 if ((ifp->if_capenable & IFCAP_POLLING) && 672 ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */ 673 CSR_WRITE_2(sc, STE_IMR, 0); 674 ste_poll(ifp, 0, 1); 675 goto done; 676 } 677 #endif /* DEVICE_POLLING */ 678 679 /* See if this is really our interrupt. */ 680 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 681 STE_UNLOCK(sc); 682 return; 683 } 684 685 for (;;) { 686 status = CSR_READ_2(sc, STE_ISR_ACK); 687 688 if (!(status & STE_INTRS)) 689 break; 690 691 if (status & STE_ISR_RX_DMADONE) { 692 ste_rxeoc(sc); 693 ste_rxeof(sc); 694 } 695 696 if (status & STE_ISR_TX_DMADONE) 697 ste_txeof(sc); 698 699 if (status & STE_ISR_TX_DONE) 700 ste_txeoc(sc); 701 702 if (status & STE_ISR_STATS_OFLOW) { 703 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 704 ste_stats_update(sc); 705 } 706 707 if (status & STE_ISR_LINKEVENT) 708 mii_pollstat(device_get_softc(sc->ste_miibus)); 709 710 711 if (status & STE_ISR_HOSTERR) { 712 ste_reset(sc); 713 ste_init(sc); 714 } 715 } 716 717 /* Re-enable interrupts */ 718 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 719 720 if (ifp->if_snd.ifq_head != NULL) 721 ste_start(ifp); 722 723 #ifdef DEVICE_POLLING 724 done: 725 #endif /* DEVICE_POLLING */ 726 STE_UNLOCK(sc); 727 728 return; 729 } 730 731 static void 732 ste_rxeoc(struct ste_softc *sc) 733 { 734 struct ste_chain_onefrag *cur_rx; 735 736 STE_LOCK_ASSERT(sc); 737 738 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 739 cur_rx = sc->ste_cdata.ste_rx_head; 740 do { 741 cur_rx = cur_rx->ste_next; 742 /* If the ring is empty, just return. */ 743 if (cur_rx == sc->ste_cdata.ste_rx_head) 744 return; 745 } while (cur_rx->ste_ptr->ste_status == 0); 746 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 747 /* We've fallen behind the chip: catch it. */ 748 sc->ste_cdata.ste_rx_head = cur_rx; 749 ++ste_rxsyncs; 750 } 751 } 752 } 753 754 /* 755 * A frame has been uploaded: pass the resulting mbuf chain up to 756 * the higher level protocols. 757 */ 758 static void 759 ste_rxeof(sc) 760 struct ste_softc *sc; 761 { 762 struct mbuf *m; 763 struct ifnet *ifp; 764 struct ste_chain_onefrag *cur_rx; 765 int total_len = 0, count=0; 766 u_int32_t rxstat; 767 768 STE_LOCK_ASSERT(sc); 769 770 ifp = &sc->arpcom.ac_if; 771 772 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 773 & STE_RXSTAT_DMADONE) { 774 #ifdef DEVICE_POLLING 775 if (ifp->if_flags & IFF_POLLING) { 776 if (sc->rxcycles <= 0) 777 break; 778 sc->rxcycles--; 779 } 780 #endif /* DEVICE_POLLING */ 781 if ((STE_RX_LIST_CNT - count) < 3) { 782 break; 783 } 784 785 cur_rx = sc->ste_cdata.ste_rx_head; 786 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 787 788 /* 789 * If an error occurs, update stats, clear the 790 * status word and leave the mbuf cluster in place: 791 * it should simply get re-used next time this descriptor 792 * comes up in the ring. 793 */ 794 if (rxstat & STE_RXSTAT_FRAME_ERR) { 795 ifp->if_ierrors++; 796 cur_rx->ste_ptr->ste_status = 0; 797 continue; 798 } 799 800 /* 801 * If there error bit was not set, the upload complete 802 * bit should be set which means we have a valid packet. 803 * If not, something truly strange has happened. 804 */ 805 if (!(rxstat & STE_RXSTAT_DMADONE)) { 806 printf("ste%d: bad receive status -- packet dropped\n", 807 sc->ste_unit); 808 ifp->if_ierrors++; 809 cur_rx->ste_ptr->ste_status = 0; 810 continue; 811 } 812 813 /* No errors; receive the packet. */ 814 m = cur_rx->ste_mbuf; 815 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 816 817 /* 818 * Try to conjure up a new mbuf cluster. If that 819 * fails, it means we have an out of memory condition and 820 * should leave the buffer in place and continue. This will 821 * result in a lost packet, but there's little else we 822 * can do in this situation. 823 */ 824 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 825 ifp->if_ierrors++; 826 cur_rx->ste_ptr->ste_status = 0; 827 continue; 828 } 829 830 m->m_pkthdr.rcvif = ifp; 831 m->m_pkthdr.len = m->m_len = total_len; 832 833 ifp->if_ipackets++; 834 STE_UNLOCK(sc); 835 (*ifp->if_input)(ifp, m); 836 STE_LOCK(sc); 837 838 cur_rx->ste_ptr->ste_status = 0; 839 count++; 840 } 841 842 return; 843 } 844 845 static void 846 ste_txeoc(sc) 847 struct ste_softc *sc; 848 { 849 u_int8_t txstat; 850 struct ifnet *ifp; 851 852 ifp = &sc->arpcom.ac_if; 853 854 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 855 STE_TXSTATUS_TXDONE) { 856 if (txstat & STE_TXSTATUS_UNDERRUN || 857 txstat & STE_TXSTATUS_EXCESSCOLLS || 858 txstat & STE_TXSTATUS_RECLAIMERR) { 859 ifp->if_oerrors++; 860 printf("ste%d: transmission error: %x\n", 861 sc->ste_unit, txstat); 862 863 ste_reset(sc); 864 ste_init(sc); 865 866 if (txstat & STE_TXSTATUS_UNDERRUN && 867 sc->ste_tx_thresh < STE_PACKET_SIZE) { 868 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 869 printf("ste%d: tx underrun, increasing tx" 870 " start threshold to %d bytes\n", 871 sc->ste_unit, sc->ste_tx_thresh); 872 } 873 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 874 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 875 (STE_PACKET_SIZE >> 4)); 876 } 877 ste_init(sc); 878 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 879 } 880 881 return; 882 } 883 884 static void 885 ste_txeof(sc) 886 struct ste_softc *sc; 887 { 888 struct ste_chain *cur_tx; 889 struct ifnet *ifp; 890 int idx; 891 892 ifp = &sc->arpcom.ac_if; 893 894 idx = sc->ste_cdata.ste_tx_cons; 895 while(idx != sc->ste_cdata.ste_tx_prod) { 896 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 897 898 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 899 break; 900 901 m_freem(cur_tx->ste_mbuf); 902 cur_tx->ste_mbuf = NULL; 903 ifp->if_flags &= ~IFF_OACTIVE; 904 ifp->if_opackets++; 905 906 STE_INC(idx, STE_TX_LIST_CNT); 907 } 908 909 sc->ste_cdata.ste_tx_cons = idx; 910 if (idx == sc->ste_cdata.ste_tx_prod) 911 ifp->if_timer = 0; 912 } 913 914 static void 915 ste_stats_update(xsc) 916 void *xsc; 917 { 918 struct ste_softc *sc; 919 struct ifnet *ifp; 920 struct mii_data *mii; 921 922 sc = xsc; 923 STE_LOCK(sc); 924 925 ifp = &sc->arpcom.ac_if; 926 mii = device_get_softc(sc->ste_miibus); 927 928 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 929 + CSR_READ_1(sc, STE_MULTI_COLLS) 930 + CSR_READ_1(sc, STE_SINGLE_COLLS); 931 932 if (!sc->ste_link) { 933 mii_pollstat(mii); 934 if (mii->mii_media_status & IFM_ACTIVE && 935 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 936 sc->ste_link++; 937 /* 938 * we don't get a call-back on re-init so do it 939 * otherwise we get stuck in the wrong link state 940 */ 941 ste_miibus_statchg(sc->ste_dev); 942 if (ifp->if_snd.ifq_head != NULL) 943 ste_start(ifp); 944 } 945 } 946 947 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 948 STE_UNLOCK(sc); 949 950 return; 951 } 952 953 954 /* 955 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 956 * IDs against our list and return a device name if we find a match. 957 */ 958 static int 959 ste_probe(dev) 960 device_t dev; 961 { 962 struct ste_type *t; 963 964 t = ste_devs; 965 966 while(t->ste_name != NULL) { 967 if ((pci_get_vendor(dev) == t->ste_vid) && 968 (pci_get_device(dev) == t->ste_did)) { 969 device_set_desc(dev, t->ste_name); 970 return (BUS_PROBE_DEFAULT); 971 } 972 t++; 973 } 974 975 return(ENXIO); 976 } 977 978 /* 979 * Attach the interface. Allocate softc structures, do ifmedia 980 * setup and ethernet/BPF attach. 981 */ 982 static int 983 ste_attach(dev) 984 device_t dev; 985 { 986 struct ste_softc *sc; 987 struct ifnet *ifp; 988 int unit, error = 0, rid; 989 990 sc = device_get_softc(dev); 991 unit = device_get_unit(dev); 992 sc->ste_dev = dev; 993 994 /* 995 * Only use one PHY since this chip reports multiple 996 * Note on the DFE-550 the PHY is at 1 on the DFE-580 997 * it is at 0 & 1. It is rev 0x12. 998 */ 999 if (pci_get_vendor(dev) == DL_VENDORID && 1000 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1001 pci_get_revid(dev) == 0x12 ) 1002 sc->ste_one_phy = 1; 1003 1004 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1005 MTX_DEF | MTX_RECURSE); 1006 /* 1007 * Map control/status registers. 1008 */ 1009 pci_enable_busmaster(dev); 1010 1011 rid = STE_RID; 1012 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1013 1014 if (sc->ste_res == NULL) { 1015 printf ("ste%d: couldn't map ports/memory\n", unit); 1016 error = ENXIO; 1017 goto fail; 1018 } 1019 1020 sc->ste_btag = rman_get_bustag(sc->ste_res); 1021 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1022 1023 /* Allocate interrupt */ 1024 rid = 0; 1025 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1026 RF_SHAREABLE | RF_ACTIVE); 1027 1028 if (sc->ste_irq == NULL) { 1029 printf("ste%d: couldn't map interrupt\n", unit); 1030 error = ENXIO; 1031 goto fail; 1032 } 1033 1034 callout_handle_init(&sc->ste_stat_ch); 1035 1036 /* Reset the adapter. */ 1037 ste_reset(sc); 1038 1039 /* 1040 * Get station address from the EEPROM. 1041 */ 1042 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1043 STE_EEADDR_NODE0, 3, 0)) { 1044 printf("ste%d: failed to read station address\n", unit); 1045 error = ENXIO;; 1046 goto fail; 1047 } 1048 1049 sc->ste_unit = unit; 1050 1051 /* Allocate the descriptor queues. */ 1052 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1053 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1054 1055 if (sc->ste_ldata == NULL) { 1056 printf("ste%d: no memory for list buffers!\n", unit); 1057 error = ENXIO; 1058 goto fail; 1059 } 1060 1061 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1062 1063 /* Do MII setup. */ 1064 if (mii_phy_probe(dev, &sc->ste_miibus, 1065 ste_ifmedia_upd, ste_ifmedia_sts)) { 1066 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1067 error = ENXIO; 1068 goto fail; 1069 } 1070 1071 ifp = &sc->arpcom.ac_if; 1072 ifp->if_softc = sc; 1073 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1074 ifp->if_mtu = ETHERMTU; 1075 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 1076 IFF_NEEDSGIANT; 1077 ifp->if_ioctl = ste_ioctl; 1078 ifp->if_start = ste_start; 1079 ifp->if_watchdog = ste_watchdog; 1080 ifp->if_init = ste_init; 1081 ifp->if_baudrate = 10000000; 1082 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1083 1084 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1085 1086 /* 1087 * Call MI attach routine. 1088 */ 1089 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1090 1091 /* 1092 * Tell the upper layer(s) we support long frames. 1093 */ 1094 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1095 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1096 #ifdef DEVICE_POLLING 1097 ifp->if_capabilities |= IFCAP_POLLING; 1098 #endif 1099 ifp->if_capenable = ifp->if_capabilities; 1100 1101 /* Hook interrupt last to avoid having to lock softc */ 1102 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1103 ste_intr, sc, &sc->ste_intrhand); 1104 1105 if (error) { 1106 printf("ste%d: couldn't set up irq\n", unit); 1107 ether_ifdetach(ifp); 1108 goto fail; 1109 } 1110 1111 fail: 1112 if (error) 1113 ste_detach(dev); 1114 1115 return(error); 1116 } 1117 1118 /* 1119 * Shutdown hardware and free up resources. This can be called any 1120 * time after the mutex has been initialized. It is called in both 1121 * the error case in attach and the normal detach case so it needs 1122 * to be careful about only freeing resources that have actually been 1123 * allocated. 1124 */ 1125 static int 1126 ste_detach(dev) 1127 device_t dev; 1128 { 1129 struct ste_softc *sc; 1130 struct ifnet *ifp; 1131 1132 sc = device_get_softc(dev); 1133 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1134 STE_LOCK(sc); 1135 ifp = &sc->arpcom.ac_if; 1136 1137 /* These should only be active if attach succeeded */ 1138 if (device_is_attached(dev)) { 1139 ste_stop(sc); 1140 ether_ifdetach(ifp); 1141 } 1142 if (sc->ste_miibus) 1143 device_delete_child(dev, sc->ste_miibus); 1144 bus_generic_detach(dev); 1145 1146 if (sc->ste_intrhand) 1147 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1148 if (sc->ste_irq) 1149 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1150 if (sc->ste_res) 1151 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1152 1153 if (sc->ste_ldata) { 1154 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1155 M_DEVBUF); 1156 } 1157 1158 STE_UNLOCK(sc); 1159 mtx_destroy(&sc->ste_mtx); 1160 1161 return(0); 1162 } 1163 1164 static int 1165 ste_newbuf(sc, c, m) 1166 struct ste_softc *sc; 1167 struct ste_chain_onefrag *c; 1168 struct mbuf *m; 1169 { 1170 struct mbuf *m_new = NULL; 1171 1172 if (m == NULL) { 1173 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1174 if (m_new == NULL) 1175 return(ENOBUFS); 1176 MCLGET(m_new, M_DONTWAIT); 1177 if (!(m_new->m_flags & M_EXT)) { 1178 m_freem(m_new); 1179 return(ENOBUFS); 1180 } 1181 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1182 } else { 1183 m_new = m; 1184 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1185 m_new->m_data = m_new->m_ext.ext_buf; 1186 } 1187 1188 m_adj(m_new, ETHER_ALIGN); 1189 1190 c->ste_mbuf = m_new; 1191 c->ste_ptr->ste_status = 0; 1192 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1193 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1194 1195 return(0); 1196 } 1197 1198 static int 1199 ste_init_rx_list(sc) 1200 struct ste_softc *sc; 1201 { 1202 struct ste_chain_data *cd; 1203 struct ste_list_data *ld; 1204 int i; 1205 1206 cd = &sc->ste_cdata; 1207 ld = sc->ste_ldata; 1208 1209 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1210 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1211 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1212 return(ENOBUFS); 1213 if (i == (STE_RX_LIST_CNT - 1)) { 1214 cd->ste_rx_chain[i].ste_next = 1215 &cd->ste_rx_chain[0]; 1216 ld->ste_rx_list[i].ste_next = 1217 vtophys(&ld->ste_rx_list[0]); 1218 } else { 1219 cd->ste_rx_chain[i].ste_next = 1220 &cd->ste_rx_chain[i + 1]; 1221 ld->ste_rx_list[i].ste_next = 1222 vtophys(&ld->ste_rx_list[i + 1]); 1223 } 1224 ld->ste_rx_list[i].ste_status = 0; 1225 } 1226 1227 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1228 1229 return(0); 1230 } 1231 1232 static void 1233 ste_init_tx_list(sc) 1234 struct ste_softc *sc; 1235 { 1236 struct ste_chain_data *cd; 1237 struct ste_list_data *ld; 1238 int i; 1239 1240 cd = &sc->ste_cdata; 1241 ld = sc->ste_ldata; 1242 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1243 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1244 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1245 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1246 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1247 if (i == (STE_TX_LIST_CNT - 1)) 1248 cd->ste_tx_chain[i].ste_next = 1249 &cd->ste_tx_chain[0]; 1250 else 1251 cd->ste_tx_chain[i].ste_next = 1252 &cd->ste_tx_chain[i + 1]; 1253 } 1254 1255 cd->ste_tx_prod = 0; 1256 cd->ste_tx_cons = 0; 1257 1258 return; 1259 } 1260 1261 static void 1262 ste_init(xsc) 1263 void *xsc; 1264 { 1265 struct ste_softc *sc; 1266 int i; 1267 struct ifnet *ifp; 1268 1269 sc = xsc; 1270 STE_LOCK(sc); 1271 ifp = &sc->arpcom.ac_if; 1272 1273 ste_stop(sc); 1274 1275 /* Init our MAC address */ 1276 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1277 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1278 } 1279 1280 /* Init RX list */ 1281 if (ste_init_rx_list(sc) == ENOBUFS) { 1282 printf("ste%d: initialization failed: no " 1283 "memory for RX buffers\n", sc->ste_unit); 1284 ste_stop(sc); 1285 STE_UNLOCK(sc); 1286 return; 1287 } 1288 1289 /* Set RX polling interval */ 1290 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1291 1292 /* Init TX descriptors */ 1293 ste_init_tx_list(sc); 1294 1295 /* Set the TX freethresh value */ 1296 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1297 1298 /* Set the TX start threshold for best performance. */ 1299 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1300 1301 /* Set the TX reclaim threshold. */ 1302 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1303 1304 /* Set up the RX filter. */ 1305 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1306 1307 /* If we want promiscuous mode, set the allframes bit. */ 1308 if (ifp->if_flags & IFF_PROMISC) { 1309 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1310 } else { 1311 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1312 } 1313 1314 /* Set capture broadcast bit to accept broadcast frames. */ 1315 if (ifp->if_flags & IFF_BROADCAST) { 1316 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1317 } else { 1318 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1319 } 1320 1321 ste_setmulti(sc); 1322 1323 /* Load the address of the RX list. */ 1324 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1325 ste_wait(sc); 1326 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1327 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1328 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1329 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1330 1331 /* Set TX polling interval (defer until we TX first packet */ 1332 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1333 1334 /* Load address of the TX list */ 1335 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1336 ste_wait(sc); 1337 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1338 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1339 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1340 ste_wait(sc); 1341 sc->ste_tx_prev = NULL; 1342 1343 /* Enable receiver and transmitter */ 1344 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1345 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1346 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1347 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1348 1349 /* Enable stats counters. */ 1350 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1351 1352 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1353 #ifdef DEVICE_POLLING 1354 /* Disable interrupts if we are polling. */ 1355 if (ifp->if_flags & IFF_POLLING) 1356 CSR_WRITE_2(sc, STE_IMR, 0); 1357 else 1358 #endif /* DEVICE_POLLING */ 1359 /* Enable interrupts. */ 1360 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1361 1362 /* Accept VLAN length packets */ 1363 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1364 1365 ste_ifmedia_upd(ifp); 1366 1367 ifp->if_flags |= IFF_RUNNING; 1368 ifp->if_flags &= ~IFF_OACTIVE; 1369 1370 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1371 STE_UNLOCK(sc); 1372 1373 return; 1374 } 1375 1376 static void 1377 ste_stop(sc) 1378 struct ste_softc *sc; 1379 { 1380 int i; 1381 struct ifnet *ifp; 1382 1383 STE_LOCK(sc); 1384 ifp = &sc->arpcom.ac_if; 1385 1386 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1387 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1388 #ifdef DEVICE_POLLING 1389 ether_poll_deregister(ifp); 1390 #endif /* DEVICE_POLLING */ 1391 1392 CSR_WRITE_2(sc, STE_IMR, 0); 1393 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1394 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1395 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1396 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1397 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1398 ste_wait(sc); 1399 /* 1400 * Try really hard to stop the RX engine or under heavy RX 1401 * data chip will write into de-allocated memory. 1402 */ 1403 ste_reset(sc); 1404 1405 sc->ste_link = 0; 1406 1407 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1408 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1409 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1410 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1411 } 1412 } 1413 1414 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1415 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1416 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1417 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1418 } 1419 } 1420 1421 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1422 STE_UNLOCK(sc); 1423 1424 return; 1425 } 1426 1427 static void 1428 ste_reset(sc) 1429 struct ste_softc *sc; 1430 { 1431 int i; 1432 1433 STE_SETBIT4(sc, STE_ASICCTL, 1434 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1435 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1436 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1437 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1438 STE_ASICCTL_EXTRESET_RESET); 1439 1440 DELAY(100000); 1441 1442 for (i = 0; i < STE_TIMEOUT; i++) { 1443 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1444 break; 1445 } 1446 1447 if (i == STE_TIMEOUT) 1448 printf("ste%d: global reset never completed\n", sc->ste_unit); 1449 1450 return; 1451 } 1452 1453 static int 1454 ste_ioctl(ifp, command, data) 1455 struct ifnet *ifp; 1456 u_long command; 1457 caddr_t data; 1458 { 1459 struct ste_softc *sc; 1460 struct ifreq *ifr; 1461 struct mii_data *mii; 1462 int error = 0; 1463 1464 sc = ifp->if_softc; 1465 STE_LOCK(sc); 1466 ifr = (struct ifreq *)data; 1467 1468 switch(command) { 1469 case SIOCSIFFLAGS: 1470 if (ifp->if_flags & IFF_UP) { 1471 if (ifp->if_flags & IFF_RUNNING && 1472 ifp->if_flags & IFF_PROMISC && 1473 !(sc->ste_if_flags & IFF_PROMISC)) { 1474 STE_SETBIT1(sc, STE_RX_MODE, 1475 STE_RXMODE_PROMISC); 1476 } else if (ifp->if_flags & IFF_RUNNING && 1477 !(ifp->if_flags & IFF_PROMISC) && 1478 sc->ste_if_flags & IFF_PROMISC) { 1479 STE_CLRBIT1(sc, STE_RX_MODE, 1480 STE_RXMODE_PROMISC); 1481 } 1482 if (ifp->if_flags & IFF_RUNNING && 1483 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1484 ste_setmulti(sc); 1485 if (!(ifp->if_flags & IFF_RUNNING)) { 1486 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1487 ste_init(sc); 1488 } 1489 } else { 1490 if (ifp->if_flags & IFF_RUNNING) 1491 ste_stop(sc); 1492 } 1493 sc->ste_if_flags = ifp->if_flags; 1494 error = 0; 1495 break; 1496 case SIOCADDMULTI: 1497 case SIOCDELMULTI: 1498 ste_setmulti(sc); 1499 error = 0; 1500 break; 1501 case SIOCGIFMEDIA: 1502 case SIOCSIFMEDIA: 1503 mii = device_get_softc(sc->ste_miibus); 1504 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1505 break; 1506 case SIOCSIFCAP: 1507 ifp->if_capenable &= ~IFCAP_POLLING; 1508 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1509 break; 1510 default: 1511 error = ether_ioctl(ifp, command, data); 1512 break; 1513 } 1514 1515 STE_UNLOCK(sc); 1516 1517 return(error); 1518 } 1519 1520 static int 1521 ste_encap(sc, c, m_head) 1522 struct ste_softc *sc; 1523 struct ste_chain *c; 1524 struct mbuf *m_head; 1525 { 1526 int frag = 0; 1527 struct ste_frag *f = NULL; 1528 struct mbuf *m; 1529 struct ste_desc *d; 1530 1531 d = c->ste_ptr; 1532 d->ste_ctl = 0; 1533 1534 encap_retry: 1535 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1536 if (m->m_len != 0) { 1537 if (frag == STE_MAXFRAGS) 1538 break; 1539 f = &d->ste_frags[frag]; 1540 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1541 f->ste_len = m->m_len; 1542 frag++; 1543 } 1544 } 1545 1546 if (m != NULL) { 1547 struct mbuf *mn; 1548 1549 /* 1550 * We ran out of segments. We have to recopy this 1551 * mbuf chain first. Bail out if we can't get the 1552 * new buffers. 1553 */ 1554 mn = m_defrag(m_head, M_DONTWAIT); 1555 if (mn == NULL) { 1556 m_freem(m_head); 1557 return ENOMEM; 1558 } 1559 m_head = mn; 1560 goto encap_retry; 1561 } 1562 1563 c->ste_mbuf = m_head; 1564 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1565 d->ste_ctl = 1; 1566 1567 return(0); 1568 } 1569 1570 static void 1571 ste_start(ifp) 1572 struct ifnet *ifp; 1573 { 1574 struct ste_softc *sc; 1575 struct mbuf *m_head = NULL; 1576 struct ste_chain *cur_tx; 1577 int idx; 1578 1579 sc = ifp->if_softc; 1580 STE_LOCK(sc); 1581 1582 if (!sc->ste_link) { 1583 STE_UNLOCK(sc); 1584 return; 1585 } 1586 1587 if (ifp->if_flags & IFF_OACTIVE) { 1588 STE_UNLOCK(sc); 1589 return; 1590 } 1591 1592 idx = sc->ste_cdata.ste_tx_prod; 1593 1594 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1595 /* 1596 * We cannot re-use the last (free) descriptor; 1597 * the chip may not have read its ste_next yet. 1598 */ 1599 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1600 sc->ste_cdata.ste_tx_cons) { 1601 ifp->if_flags |= IFF_OACTIVE; 1602 break; 1603 } 1604 1605 IF_DEQUEUE(&ifp->if_snd, m_head); 1606 if (m_head == NULL) 1607 break; 1608 1609 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1610 1611 if (ste_encap(sc, cur_tx, m_head) != 0) 1612 break; 1613 1614 cur_tx->ste_ptr->ste_next = 0; 1615 1616 if (sc->ste_tx_prev == NULL) { 1617 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1618 /* Load address of the TX list */ 1619 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1620 ste_wait(sc); 1621 1622 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1623 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1624 1625 /* Set TX polling interval to start TX engine */ 1626 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1627 1628 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1629 ste_wait(sc); 1630 }else{ 1631 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1632 sc->ste_tx_prev->ste_ptr->ste_next 1633 = cur_tx->ste_phys; 1634 } 1635 1636 sc->ste_tx_prev = cur_tx; 1637 1638 /* 1639 * If there's a BPF listener, bounce a copy of this frame 1640 * to him. 1641 */ 1642 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1643 1644 STE_INC(idx, STE_TX_LIST_CNT); 1645 ifp->if_timer = 5; 1646 } 1647 sc->ste_cdata.ste_tx_prod = idx; 1648 1649 STE_UNLOCK(sc); 1650 1651 return; 1652 } 1653 1654 static void 1655 ste_watchdog(ifp) 1656 struct ifnet *ifp; 1657 { 1658 struct ste_softc *sc; 1659 1660 sc = ifp->if_softc; 1661 STE_LOCK(sc); 1662 1663 ifp->if_oerrors++; 1664 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1665 1666 ste_txeoc(sc); 1667 ste_txeof(sc); 1668 ste_rxeoc(sc); 1669 ste_rxeof(sc); 1670 ste_reset(sc); 1671 ste_init(sc); 1672 1673 if (ifp->if_snd.ifq_head != NULL) 1674 ste_start(ifp); 1675 STE_UNLOCK(sc); 1676 1677 return; 1678 } 1679 1680 static void 1681 ste_shutdown(dev) 1682 device_t dev; 1683 { 1684 struct ste_softc *sc; 1685 1686 sc = device_get_softc(dev); 1687 1688 ste_stop(sc); 1689 1690 return; 1691 }
Cache object: 66041606fd9751228beb114aa5b62585
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