FreeBSD/Linux Kernel Cross Reference
sys/pci/if_ste.c
1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/6.0/sys/pci/if_ste.c 151140 2005-10-09 04:11:20Z delphij $");
35
36 #ifdef HAVE_KERNEL_OPTION_HEADERS
37 #include "opt_device_polling.h"
38 #endif
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/sockio.h>
43 #include <sys/mbuf.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49
50 #include <net/if.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
57
58 #include <net/bpf.h>
59
60 #include <vm/vm.h> /* for vtophys */
61 #include <vm/pmap.h> /* for vtophys */
62 #include <machine/bus.h>
63 #include <machine/resource.h>
64 #include <sys/bus.h>
65 #include <sys/rman.h>
66
67 #include <dev/mii/mii.h>
68 #include <dev/mii/miivar.h>
69
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
72
73 /* "controller miibus0" required. See GENERIC if you get errors here. */
74 #include "miibus_if.h"
75
76 #define STE_USEIOSPACE
77
78 #include <pci/if_stereg.h>
79
80 MODULE_DEPEND(ste, pci, 1, 1, 1);
81 MODULE_DEPEND(ste, ether, 1, 1, 1);
82 MODULE_DEPEND(ste, miibus, 1, 1, 1);
83
84 /*
85 * Various supported device vendors/types and their names.
86 */
87 static struct ste_type ste_devs[] = {
88 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
89 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
90 { 0, 0, NULL }
91 };
92
93 static int ste_probe(device_t);
94 static int ste_attach(device_t);
95 static int ste_detach(device_t);
96 static void ste_init(void *);
97 static void ste_init_locked(struct ste_softc *);
98 static void ste_intr(void *);
99 static void ste_rxeoc(struct ste_softc *);
100 static void ste_rxeof(struct ste_softc *);
101 static void ste_txeoc(struct ste_softc *);
102 static void ste_txeof(struct ste_softc *);
103 static void ste_stats_update(void *);
104 static void ste_stop(struct ste_softc *);
105 static void ste_reset(struct ste_softc *);
106 static int ste_ioctl(struct ifnet *, u_long, caddr_t);
107 static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *);
108 static void ste_start(struct ifnet *);
109 static void ste_start_locked(struct ifnet *);
110 static void ste_watchdog(struct ifnet *);
111 static void ste_shutdown(device_t);
112 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *,
113 struct mbuf *);
114 static int ste_ifmedia_upd(struct ifnet *);
115 static void ste_ifmedia_upd_locked(struct ifnet *);
116 static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
117
118 static void ste_mii_sync(struct ste_softc *);
119 static void ste_mii_send(struct ste_softc *, u_int32_t, int);
120 static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *);
121 static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *);
122 static int ste_miibus_readreg(device_t, int, int);
123 static int ste_miibus_writereg(device_t, int, int, int);
124 static void ste_miibus_statchg(device_t);
125
126 static int ste_eeprom_wait(struct ste_softc *);
127 static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int);
128 static void ste_wait(struct ste_softc *);
129 static void ste_setmulti(struct ste_softc *);
130 static int ste_init_rx_list(struct ste_softc *);
131 static void ste_init_tx_list(struct ste_softc *);
132
133 #ifdef STE_USEIOSPACE
134 #define STE_RES SYS_RES_IOPORT
135 #define STE_RID STE_PCI_LOIO
136 #else
137 #define STE_RES SYS_RES_MEMORY
138 #define STE_RID STE_PCI_LOMEM
139 #endif
140
141 static device_method_t ste_methods[] = {
142 /* Device interface */
143 DEVMETHOD(device_probe, ste_probe),
144 DEVMETHOD(device_attach, ste_attach),
145 DEVMETHOD(device_detach, ste_detach),
146 DEVMETHOD(device_shutdown, ste_shutdown),
147
148 /* bus interface */
149 DEVMETHOD(bus_print_child, bus_generic_print_child),
150 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
151
152 /* MII interface */
153 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
154 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
155 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
156
157 { 0, 0 }
158 };
159
160 static driver_t ste_driver = {
161 "ste",
162 ste_methods,
163 sizeof(struct ste_softc)
164 };
165
166 static devclass_t ste_devclass;
167
168 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
169 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
170
171 SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters");
172
173 static int ste_rxsyncs;
174 SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, "");
175
176 #define STE_SETBIT4(sc, reg, x) \
177 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
178
179 #define STE_CLRBIT4(sc, reg, x) \
180 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
181
182 #define STE_SETBIT2(sc, reg, x) \
183 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
184
185 #define STE_CLRBIT2(sc, reg, x) \
186 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
187
188 #define STE_SETBIT1(sc, reg, x) \
189 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
190
191 #define STE_CLRBIT1(sc, reg, x) \
192 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
193
194
195 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
196 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
197
198 /*
199 * Sync the PHYs by setting data bit and strobing the clock 32 times.
200 */
201 static void
202 ste_mii_sync(sc)
203 struct ste_softc *sc;
204 {
205 register int i;
206
207 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
208
209 for (i = 0; i < 32; i++) {
210 MII_SET(STE_PHYCTL_MCLK);
211 DELAY(1);
212 MII_CLR(STE_PHYCTL_MCLK);
213 DELAY(1);
214 }
215
216 return;
217 }
218
219 /*
220 * Clock a series of bits through the MII.
221 */
222 static void
223 ste_mii_send(sc, bits, cnt)
224 struct ste_softc *sc;
225 u_int32_t bits;
226 int cnt;
227 {
228 int i;
229
230 MII_CLR(STE_PHYCTL_MCLK);
231
232 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
233 if (bits & i) {
234 MII_SET(STE_PHYCTL_MDATA);
235 } else {
236 MII_CLR(STE_PHYCTL_MDATA);
237 }
238 DELAY(1);
239 MII_CLR(STE_PHYCTL_MCLK);
240 DELAY(1);
241 MII_SET(STE_PHYCTL_MCLK);
242 }
243 }
244
245 /*
246 * Read an PHY register through the MII.
247 */
248 static int
249 ste_mii_readreg(sc, frame)
250 struct ste_softc *sc;
251 struct ste_mii_frame *frame;
252
253 {
254 int i, ack;
255
256 /*
257 * Set up frame for RX.
258 */
259 frame->mii_stdelim = STE_MII_STARTDELIM;
260 frame->mii_opcode = STE_MII_READOP;
261 frame->mii_turnaround = 0;
262 frame->mii_data = 0;
263
264 CSR_WRITE_2(sc, STE_PHYCTL, 0);
265 /*
266 * Turn on data xmit.
267 */
268 MII_SET(STE_PHYCTL_MDIR);
269
270 ste_mii_sync(sc);
271
272 /*
273 * Send command/address info.
274 */
275 ste_mii_send(sc, frame->mii_stdelim, 2);
276 ste_mii_send(sc, frame->mii_opcode, 2);
277 ste_mii_send(sc, frame->mii_phyaddr, 5);
278 ste_mii_send(sc, frame->mii_regaddr, 5);
279
280 /* Turn off xmit. */
281 MII_CLR(STE_PHYCTL_MDIR);
282
283 /* Idle bit */
284 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
285 DELAY(1);
286 MII_SET(STE_PHYCTL_MCLK);
287 DELAY(1);
288
289 /* Check for ack */
290 MII_CLR(STE_PHYCTL_MCLK);
291 DELAY(1);
292 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
293 MII_SET(STE_PHYCTL_MCLK);
294 DELAY(1);
295
296 /*
297 * Now try reading data bits. If the ack failed, we still
298 * need to clock through 16 cycles to keep the PHY(s) in sync.
299 */
300 if (ack) {
301 for(i = 0; i < 16; i++) {
302 MII_CLR(STE_PHYCTL_MCLK);
303 DELAY(1);
304 MII_SET(STE_PHYCTL_MCLK);
305 DELAY(1);
306 }
307 goto fail;
308 }
309
310 for (i = 0x8000; i; i >>= 1) {
311 MII_CLR(STE_PHYCTL_MCLK);
312 DELAY(1);
313 if (!ack) {
314 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
315 frame->mii_data |= i;
316 DELAY(1);
317 }
318 MII_SET(STE_PHYCTL_MCLK);
319 DELAY(1);
320 }
321
322 fail:
323
324 MII_CLR(STE_PHYCTL_MCLK);
325 DELAY(1);
326 MII_SET(STE_PHYCTL_MCLK);
327 DELAY(1);
328
329 if (ack)
330 return(1);
331 return(0);
332 }
333
334 /*
335 * Write to a PHY register through the MII.
336 */
337 static int
338 ste_mii_writereg(sc, frame)
339 struct ste_softc *sc;
340 struct ste_mii_frame *frame;
341
342 {
343
344 /*
345 * Set up frame for TX.
346 */
347
348 frame->mii_stdelim = STE_MII_STARTDELIM;
349 frame->mii_opcode = STE_MII_WRITEOP;
350 frame->mii_turnaround = STE_MII_TURNAROUND;
351
352 /*
353 * Turn on data output.
354 */
355 MII_SET(STE_PHYCTL_MDIR);
356
357 ste_mii_sync(sc);
358
359 ste_mii_send(sc, frame->mii_stdelim, 2);
360 ste_mii_send(sc, frame->mii_opcode, 2);
361 ste_mii_send(sc, frame->mii_phyaddr, 5);
362 ste_mii_send(sc, frame->mii_regaddr, 5);
363 ste_mii_send(sc, frame->mii_turnaround, 2);
364 ste_mii_send(sc, frame->mii_data, 16);
365
366 /* Idle bit. */
367 MII_SET(STE_PHYCTL_MCLK);
368 DELAY(1);
369 MII_CLR(STE_PHYCTL_MCLK);
370 DELAY(1);
371
372 /*
373 * Turn off xmit.
374 */
375 MII_CLR(STE_PHYCTL_MDIR);
376
377 return(0);
378 }
379
380 static int
381 ste_miibus_readreg(dev, phy, reg)
382 device_t dev;
383 int phy, reg;
384 {
385 struct ste_softc *sc;
386 struct ste_mii_frame frame;
387
388 sc = device_get_softc(dev);
389
390 if ( sc->ste_one_phy && phy != 0 )
391 return (0);
392
393 bzero((char *)&frame, sizeof(frame));
394
395 frame.mii_phyaddr = phy;
396 frame.mii_regaddr = reg;
397 ste_mii_readreg(sc, &frame);
398
399 return(frame.mii_data);
400 }
401
402 static int
403 ste_miibus_writereg(dev, phy, reg, data)
404 device_t dev;
405 int phy, reg, data;
406 {
407 struct ste_softc *sc;
408 struct ste_mii_frame frame;
409
410 sc = device_get_softc(dev);
411 bzero((char *)&frame, sizeof(frame));
412
413 frame.mii_phyaddr = phy;
414 frame.mii_regaddr = reg;
415 frame.mii_data = data;
416
417 ste_mii_writereg(sc, &frame);
418
419 return(0);
420 }
421
422 static void
423 ste_miibus_statchg(dev)
424 device_t dev;
425 {
426 struct ste_softc *sc;
427 struct mii_data *mii;
428
429 sc = device_get_softc(dev);
430
431 mii = device_get_softc(sc->ste_miibus);
432
433 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
434 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
435 } else {
436 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
437 }
438
439 return;
440 }
441
442 static int
443 ste_ifmedia_upd(ifp)
444 struct ifnet *ifp;
445 {
446 struct ste_softc *sc;
447
448 sc = ifp->if_softc;
449 STE_LOCK(sc);
450 ste_ifmedia_upd_locked(ifp);
451 STE_UNLOCK(sc);
452
453 return(0);
454 }
455
456 static void
457 ste_ifmedia_upd_locked(ifp)
458 struct ifnet *ifp;
459 {
460 struct ste_softc *sc;
461 struct mii_data *mii;
462
463 sc = ifp->if_softc;
464 STE_LOCK_ASSERT(sc);
465 mii = device_get_softc(sc->ste_miibus);
466 sc->ste_link = 0;
467 if (mii->mii_instance) {
468 struct mii_softc *miisc;
469 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
470 mii_phy_reset(miisc);
471 }
472 mii_mediachg(mii);
473 }
474
475 static void
476 ste_ifmedia_sts(ifp, ifmr)
477 struct ifnet *ifp;
478 struct ifmediareq *ifmr;
479 {
480 struct ste_softc *sc;
481 struct mii_data *mii;
482
483 sc = ifp->if_softc;
484 mii = device_get_softc(sc->ste_miibus);
485
486 STE_LOCK(sc);
487 mii_pollstat(mii);
488 ifmr->ifm_active = mii->mii_media_active;
489 ifmr->ifm_status = mii->mii_media_status;
490 STE_UNLOCK(sc);
491
492 return;
493 }
494
495 static void
496 ste_wait(sc)
497 struct ste_softc *sc;
498 {
499 register int i;
500
501 for (i = 0; i < STE_TIMEOUT; i++) {
502 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
503 break;
504 }
505
506 if (i == STE_TIMEOUT)
507 if_printf(sc->ste_ifp, "command never completed!\n");
508
509 return;
510 }
511
512 /*
513 * The EEPROM is slow: give it time to come ready after issuing
514 * it a command.
515 */
516 static int
517 ste_eeprom_wait(sc)
518 struct ste_softc *sc;
519 {
520 int i;
521
522 DELAY(1000);
523
524 for (i = 0; i < 100; i++) {
525 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
526 DELAY(1000);
527 else
528 break;
529 }
530
531 if (i == 100) {
532 if_printf(sc->ste_ifp, "eeprom failed to come ready\n");
533 return(1);
534 }
535
536 return(0);
537 }
538
539 /*
540 * Read a sequence of words from the EEPROM. Note that ethernet address
541 * data is stored in the EEPROM in network byte order.
542 */
543 static int
544 ste_read_eeprom(sc, dest, off, cnt, swap)
545 struct ste_softc *sc;
546 caddr_t dest;
547 int off;
548 int cnt;
549 int swap;
550 {
551 int err = 0, i;
552 u_int16_t word = 0, *ptr;
553
554 if (ste_eeprom_wait(sc))
555 return(1);
556
557 for (i = 0; i < cnt; i++) {
558 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
559 err = ste_eeprom_wait(sc);
560 if (err)
561 break;
562 word = CSR_READ_2(sc, STE_EEPROM_DATA);
563 ptr = (u_int16_t *)(dest + (i * 2));
564 if (swap)
565 *ptr = ntohs(word);
566 else
567 *ptr = word;
568 }
569
570 return(err ? 1 : 0);
571 }
572
573 static void
574 ste_setmulti(sc)
575 struct ste_softc *sc;
576 {
577 struct ifnet *ifp;
578 int h = 0;
579 u_int32_t hashes[2] = { 0, 0 };
580 struct ifmultiaddr *ifma;
581
582 ifp = sc->ste_ifp;
583 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
584 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
585 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
586 return;
587 }
588
589 /* first, zot all the existing hash bits */
590 CSR_WRITE_2(sc, STE_MAR0, 0);
591 CSR_WRITE_2(sc, STE_MAR1, 0);
592 CSR_WRITE_2(sc, STE_MAR2, 0);
593 CSR_WRITE_2(sc, STE_MAR3, 0);
594
595 /* now program new ones */
596 IF_ADDR_LOCK(ifp);
597 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
598 if (ifma->ifma_addr->sa_family != AF_LINK)
599 continue;
600 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
601 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F;
602 if (h < 32)
603 hashes[0] |= (1 << h);
604 else
605 hashes[1] |= (1 << (h - 32));
606 }
607 IF_ADDR_UNLOCK(ifp);
608
609 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
610 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
611 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
612 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
613 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
614 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
615
616 return;
617 }
618
619 #ifdef DEVICE_POLLING
620 static poll_handler_t ste_poll, ste_poll_locked;
621
622 static void
623 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
624 {
625 struct ste_softc *sc = ifp->if_softc;
626
627 STE_LOCK(sc);
628 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
629 ste_poll_locked(ifp, cmd, count);
630 STE_UNLOCK(sc);
631 }
632
633 static void
634 ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
635 {
636 struct ste_softc *sc = ifp->if_softc;
637
638 STE_LOCK_ASSERT(sc);
639
640 sc->rxcycles = count;
641 if (cmd == POLL_AND_CHECK_STATUS)
642 ste_rxeoc(sc);
643 ste_rxeof(sc);
644 ste_txeof(sc);
645 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
646 ste_start_locked(ifp);
647
648 if (cmd == POLL_AND_CHECK_STATUS) {
649 u_int16_t status;
650
651 status = CSR_READ_2(sc, STE_ISR_ACK);
652
653 if (status & STE_ISR_TX_DONE)
654 ste_txeoc(sc);
655
656 if (status & STE_ISR_STATS_OFLOW) {
657 callout_stop(&sc->ste_stat_callout);
658 ste_stats_update(sc);
659 }
660
661 if (status & STE_ISR_LINKEVENT)
662 mii_pollstat(device_get_softc(sc->ste_miibus));
663
664 if (status & STE_ISR_HOSTERR) {
665 ste_reset(sc);
666 ste_init_locked(sc);
667 }
668 }
669 }
670 #endif /* DEVICE_POLLING */
671
672 static void
673 ste_intr(xsc)
674 void *xsc;
675 {
676 struct ste_softc *sc;
677 struct ifnet *ifp;
678 u_int16_t status;
679
680 sc = xsc;
681 STE_LOCK(sc);
682 ifp = sc->ste_ifp;
683
684 #ifdef DEVICE_POLLING
685 if (ifp->if_capenable & IFCAP_POLLING) {
686 STE_UNLOCK(sc);
687 return;
688 }
689 #endif
690
691 /* See if this is really our interrupt. */
692 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) {
693 STE_UNLOCK(sc);
694 return;
695 }
696
697 for (;;) {
698 status = CSR_READ_2(sc, STE_ISR_ACK);
699
700 if (!(status & STE_INTRS))
701 break;
702
703 if (status & STE_ISR_RX_DMADONE) {
704 ste_rxeoc(sc);
705 ste_rxeof(sc);
706 }
707
708 if (status & STE_ISR_TX_DMADONE)
709 ste_txeof(sc);
710
711 if (status & STE_ISR_TX_DONE)
712 ste_txeoc(sc);
713
714 if (status & STE_ISR_STATS_OFLOW) {
715 callout_stop(&sc->ste_stat_callout);
716 ste_stats_update(sc);
717 }
718
719 if (status & STE_ISR_LINKEVENT)
720 mii_pollstat(device_get_softc(sc->ste_miibus));
721
722
723 if (status & STE_ISR_HOSTERR) {
724 ste_reset(sc);
725 ste_init_locked(sc);
726 }
727 }
728
729 /* Re-enable interrupts */
730 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
731
732 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
733 ste_start_locked(ifp);
734
735 STE_UNLOCK(sc);
736
737 return;
738 }
739
740 static void
741 ste_rxeoc(struct ste_softc *sc)
742 {
743 struct ste_chain_onefrag *cur_rx;
744
745 STE_LOCK_ASSERT(sc);
746
747 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
748 cur_rx = sc->ste_cdata.ste_rx_head;
749 do {
750 cur_rx = cur_rx->ste_next;
751 /* If the ring is empty, just return. */
752 if (cur_rx == sc->ste_cdata.ste_rx_head)
753 return;
754 } while (cur_rx->ste_ptr->ste_status == 0);
755 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
756 /* We've fallen behind the chip: catch it. */
757 sc->ste_cdata.ste_rx_head = cur_rx;
758 ++ste_rxsyncs;
759 }
760 }
761 }
762
763 /*
764 * A frame has been uploaded: pass the resulting mbuf chain up to
765 * the higher level protocols.
766 */
767 static void
768 ste_rxeof(sc)
769 struct ste_softc *sc;
770 {
771 struct mbuf *m;
772 struct ifnet *ifp;
773 struct ste_chain_onefrag *cur_rx;
774 int total_len = 0, count=0;
775 u_int32_t rxstat;
776
777 STE_LOCK_ASSERT(sc);
778
779 ifp = sc->ste_ifp;
780
781 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
782 & STE_RXSTAT_DMADONE) {
783 #ifdef DEVICE_POLLING
784 if (ifp->if_capenable & IFCAP_POLLING) {
785 if (sc->rxcycles <= 0)
786 break;
787 sc->rxcycles--;
788 }
789 #endif
790 if ((STE_RX_LIST_CNT - count) < 3) {
791 break;
792 }
793
794 cur_rx = sc->ste_cdata.ste_rx_head;
795 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
796
797 /*
798 * If an error occurs, update stats, clear the
799 * status word and leave the mbuf cluster in place:
800 * it should simply get re-used next time this descriptor
801 * comes up in the ring.
802 */
803 if (rxstat & STE_RXSTAT_FRAME_ERR) {
804 ifp->if_ierrors++;
805 cur_rx->ste_ptr->ste_status = 0;
806 continue;
807 }
808
809 /*
810 * If there error bit was not set, the upload complete
811 * bit should be set which means we have a valid packet.
812 * If not, something truly strange has happened.
813 */
814 if (!(rxstat & STE_RXSTAT_DMADONE)) {
815 if_printf(ifp,
816 "bad receive status -- packet dropped\n");
817 ifp->if_ierrors++;
818 cur_rx->ste_ptr->ste_status = 0;
819 continue;
820 }
821
822 /* No errors; receive the packet. */
823 m = cur_rx->ste_mbuf;
824 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
825
826 /*
827 * Try to conjure up a new mbuf cluster. If that
828 * fails, it means we have an out of memory condition and
829 * should leave the buffer in place and continue. This will
830 * result in a lost packet, but there's little else we
831 * can do in this situation.
832 */
833 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
834 ifp->if_ierrors++;
835 cur_rx->ste_ptr->ste_status = 0;
836 continue;
837 }
838
839 m->m_pkthdr.rcvif = ifp;
840 m->m_pkthdr.len = m->m_len = total_len;
841
842 ifp->if_ipackets++;
843 STE_UNLOCK(sc);
844 (*ifp->if_input)(ifp, m);
845 STE_LOCK(sc);
846
847 cur_rx->ste_ptr->ste_status = 0;
848 count++;
849 }
850
851 return;
852 }
853
854 static void
855 ste_txeoc(sc)
856 struct ste_softc *sc;
857 {
858 u_int8_t txstat;
859 struct ifnet *ifp;
860
861 ifp = sc->ste_ifp;
862
863 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
864 STE_TXSTATUS_TXDONE) {
865 if (txstat & STE_TXSTATUS_UNDERRUN ||
866 txstat & STE_TXSTATUS_EXCESSCOLLS ||
867 txstat & STE_TXSTATUS_RECLAIMERR) {
868 ifp->if_oerrors++;
869 if_printf(ifp, "transmission error: %x\n", txstat);
870
871 ste_reset(sc);
872 ste_init_locked(sc);
873
874 if (txstat & STE_TXSTATUS_UNDERRUN &&
875 sc->ste_tx_thresh < STE_PACKET_SIZE) {
876 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
877 if_printf(ifp, "tx underrun, increasing tx"
878 " start threshold to %d bytes\n",
879 sc->ste_tx_thresh);
880 }
881 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
882 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
883 (STE_PACKET_SIZE >> 4));
884 }
885 ste_init_locked(sc);
886 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
887 }
888
889 return;
890 }
891
892 static void
893 ste_txeof(sc)
894 struct ste_softc *sc;
895 {
896 struct ste_chain *cur_tx;
897 struct ifnet *ifp;
898 int idx;
899
900 ifp = sc->ste_ifp;
901
902 idx = sc->ste_cdata.ste_tx_cons;
903 while(idx != sc->ste_cdata.ste_tx_prod) {
904 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
905
906 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
907 break;
908
909 m_freem(cur_tx->ste_mbuf);
910 cur_tx->ste_mbuf = NULL;
911 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
912 ifp->if_opackets++;
913
914 STE_INC(idx, STE_TX_LIST_CNT);
915 }
916
917 sc->ste_cdata.ste_tx_cons = idx;
918 if (idx == sc->ste_cdata.ste_tx_prod)
919 ifp->if_timer = 0;
920 }
921
922 static void
923 ste_stats_update(xsc)
924 void *xsc;
925 {
926 struct ste_softc *sc;
927 struct ifnet *ifp;
928 struct mii_data *mii;
929
930 sc = xsc;
931 STE_LOCK_ASSERT(sc);
932
933 ifp = sc->ste_ifp;
934 mii = device_get_softc(sc->ste_miibus);
935
936 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
937 + CSR_READ_1(sc, STE_MULTI_COLLS)
938 + CSR_READ_1(sc, STE_SINGLE_COLLS);
939
940 if (!sc->ste_link) {
941 mii_pollstat(mii);
942 if (mii->mii_media_status & IFM_ACTIVE &&
943 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
944 sc->ste_link++;
945 /*
946 * we don't get a call-back on re-init so do it
947 * otherwise we get stuck in the wrong link state
948 */
949 ste_miibus_statchg(sc->ste_dev);
950 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
951 ste_start_locked(ifp);
952 }
953 }
954
955 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc);
956
957 return;
958 }
959
960
961 /*
962 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
963 * IDs against our list and return a device name if we find a match.
964 */
965 static int
966 ste_probe(dev)
967 device_t dev;
968 {
969 struct ste_type *t;
970
971 t = ste_devs;
972
973 while(t->ste_name != NULL) {
974 if ((pci_get_vendor(dev) == t->ste_vid) &&
975 (pci_get_device(dev) == t->ste_did)) {
976 device_set_desc(dev, t->ste_name);
977 return (BUS_PROBE_DEFAULT);
978 }
979 t++;
980 }
981
982 return(ENXIO);
983 }
984
985 /*
986 * Attach the interface. Allocate softc structures, do ifmedia
987 * setup and ethernet/BPF attach.
988 */
989 static int
990 ste_attach(dev)
991 device_t dev;
992 {
993 struct ste_softc *sc;
994 struct ifnet *ifp;
995 int error = 0, rid;
996 u_char eaddr[6];
997
998 sc = device_get_softc(dev);
999 sc->ste_dev = dev;
1000
1001 /*
1002 * Only use one PHY since this chip reports multiple
1003 * Note on the DFE-550 the PHY is at 1 on the DFE-580
1004 * it is at 0 & 1. It is rev 0x12.
1005 */
1006 if (pci_get_vendor(dev) == DL_VENDORID &&
1007 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
1008 pci_get_revid(dev) == 0x12 )
1009 sc->ste_one_phy = 1;
1010
1011 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1012 MTX_DEF);
1013 /*
1014 * Map control/status registers.
1015 */
1016 pci_enable_busmaster(dev);
1017
1018 rid = STE_RID;
1019 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE);
1020
1021 if (sc->ste_res == NULL) {
1022 device_printf(dev, "couldn't map ports/memory\n");
1023 error = ENXIO;
1024 goto fail;
1025 }
1026
1027 sc->ste_btag = rman_get_bustag(sc->ste_res);
1028 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
1029
1030 /* Allocate interrupt */
1031 rid = 0;
1032 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1033 RF_SHAREABLE | RF_ACTIVE);
1034
1035 if (sc->ste_irq == NULL) {
1036 device_printf(dev, "couldn't map interrupt\n");
1037 error = ENXIO;
1038 goto fail;
1039 }
1040
1041 callout_init_mtx(&sc->ste_stat_callout, &sc->ste_mtx, 0);
1042
1043 /* Reset the adapter. */
1044 ste_reset(sc);
1045
1046 /*
1047 * Get station address from the EEPROM.
1048 */
1049 if (ste_read_eeprom(sc, eaddr,
1050 STE_EEADDR_NODE0, 3, 0)) {
1051 device_printf(dev, "failed to read station address\n");
1052 error = ENXIO;;
1053 goto fail;
1054 }
1055
1056 /* Allocate the descriptor queues. */
1057 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1058 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1059
1060 if (sc->ste_ldata == NULL) {
1061 device_printf(dev, "no memory for list buffers!\n");
1062 error = ENXIO;
1063 goto fail;
1064 }
1065
1066 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1067
1068 ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
1069 if (ifp == NULL) {
1070 device_printf(dev, "can not if_alloc()\n");
1071 error = ENOSPC;
1072 goto fail;
1073 }
1074
1075 /* Do MII setup. */
1076 if (mii_phy_probe(dev, &sc->ste_miibus,
1077 ste_ifmedia_upd, ste_ifmedia_sts)) {
1078 device_printf(dev, "MII without any phy!\n");
1079 error = ENXIO;
1080 goto fail;
1081 }
1082
1083 ifp->if_softc = sc;
1084 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1085 ifp->if_mtu = ETHERMTU;
1086 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1087 ifp->if_ioctl = ste_ioctl;
1088 ifp->if_start = ste_start;
1089 ifp->if_watchdog = ste_watchdog;
1090 ifp->if_init = ste_init;
1091 ifp->if_baudrate = 10000000;
1092 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1093 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
1094 IFQ_SET_READY(&ifp->if_snd);
1095
1096 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1097
1098 /*
1099 * Call MI attach routine.
1100 */
1101 ether_ifattach(ifp, eaddr);
1102
1103 /*
1104 * Tell the upper layer(s) we support long frames.
1105 */
1106 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1107 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1108 ifp->if_capenable = ifp->if_capabilities;
1109 #ifdef DEVICE_POLLING
1110 ifp->if_capabilities |= IFCAP_POLLING;
1111 #endif
1112
1113 /* Hook interrupt last to avoid having to lock softc */
1114 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
1115 ste_intr, sc, &sc->ste_intrhand);
1116
1117 if (error) {
1118 device_printf(dev, "couldn't set up irq\n");
1119 ether_ifdetach(ifp);
1120 goto fail;
1121 }
1122
1123 fail:
1124 if (error)
1125 ste_detach(dev);
1126
1127 return(error);
1128 }
1129
1130 /*
1131 * Shutdown hardware and free up resources. This can be called any
1132 * time after the mutex has been initialized. It is called in both
1133 * the error case in attach and the normal detach case so it needs
1134 * to be careful about only freeing resources that have actually been
1135 * allocated.
1136 */
1137 static int
1138 ste_detach(dev)
1139 device_t dev;
1140 {
1141 struct ste_softc *sc;
1142 struct ifnet *ifp;
1143
1144 sc = device_get_softc(dev);
1145 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1146 ifp = sc->ste_ifp;
1147
1148 #ifdef DEVICE_POLLING
1149 if (ifp->if_capenable & IFCAP_POLLING)
1150 ether_poll_deregister(ifp);
1151 #endif
1152
1153 /* These should only be active if attach succeeded */
1154 if (device_is_attached(dev)) {
1155 STE_LOCK(sc);
1156 ste_stop(sc);
1157 STE_UNLOCK(sc);
1158 callout_drain(&sc->ste_stat_callout);
1159 ether_ifdetach(ifp);
1160 }
1161 if (ifp)
1162 if_free(ifp);
1163 if (sc->ste_miibus)
1164 device_delete_child(dev, sc->ste_miibus);
1165 bus_generic_detach(dev);
1166
1167 if (sc->ste_intrhand)
1168 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1169 if (sc->ste_irq)
1170 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1171 if (sc->ste_res)
1172 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1173
1174 if (sc->ste_ldata) {
1175 contigfree(sc->ste_ldata, sizeof(struct ste_list_data),
1176 M_DEVBUF);
1177 }
1178
1179 mtx_destroy(&sc->ste_mtx);
1180
1181 return(0);
1182 }
1183
1184 static int
1185 ste_newbuf(sc, c, m)
1186 struct ste_softc *sc;
1187 struct ste_chain_onefrag *c;
1188 struct mbuf *m;
1189 {
1190 struct mbuf *m_new = NULL;
1191
1192 if (m == NULL) {
1193 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1194 if (m_new == NULL)
1195 return(ENOBUFS);
1196 MCLGET(m_new, M_DONTWAIT);
1197 if (!(m_new->m_flags & M_EXT)) {
1198 m_freem(m_new);
1199 return(ENOBUFS);
1200 }
1201 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1202 } else {
1203 m_new = m;
1204 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1205 m_new->m_data = m_new->m_ext.ext_buf;
1206 }
1207
1208 m_adj(m_new, ETHER_ALIGN);
1209
1210 c->ste_mbuf = m_new;
1211 c->ste_ptr->ste_status = 0;
1212 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1213 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST;
1214
1215 return(0);
1216 }
1217
1218 static int
1219 ste_init_rx_list(sc)
1220 struct ste_softc *sc;
1221 {
1222 struct ste_chain_data *cd;
1223 struct ste_list_data *ld;
1224 int i;
1225
1226 cd = &sc->ste_cdata;
1227 ld = sc->ste_ldata;
1228
1229 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1230 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1231 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1232 return(ENOBUFS);
1233 if (i == (STE_RX_LIST_CNT - 1)) {
1234 cd->ste_rx_chain[i].ste_next =
1235 &cd->ste_rx_chain[0];
1236 ld->ste_rx_list[i].ste_next =
1237 vtophys(&ld->ste_rx_list[0]);
1238 } else {
1239 cd->ste_rx_chain[i].ste_next =
1240 &cd->ste_rx_chain[i + 1];
1241 ld->ste_rx_list[i].ste_next =
1242 vtophys(&ld->ste_rx_list[i + 1]);
1243 }
1244 ld->ste_rx_list[i].ste_status = 0;
1245 }
1246
1247 cd->ste_rx_head = &cd->ste_rx_chain[0];
1248
1249 return(0);
1250 }
1251
1252 static void
1253 ste_init_tx_list(sc)
1254 struct ste_softc *sc;
1255 {
1256 struct ste_chain_data *cd;
1257 struct ste_list_data *ld;
1258 int i;
1259
1260 cd = &sc->ste_cdata;
1261 ld = sc->ste_ldata;
1262 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1263 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1264 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1265 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1266 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1267 if (i == (STE_TX_LIST_CNT - 1))
1268 cd->ste_tx_chain[i].ste_next =
1269 &cd->ste_tx_chain[0];
1270 else
1271 cd->ste_tx_chain[i].ste_next =
1272 &cd->ste_tx_chain[i + 1];
1273 }
1274
1275 cd->ste_tx_prod = 0;
1276 cd->ste_tx_cons = 0;
1277
1278 return;
1279 }
1280
1281 static void
1282 ste_init(xsc)
1283 void *xsc;
1284 {
1285 struct ste_softc *sc;
1286
1287 sc = xsc;
1288 STE_LOCK(sc);
1289 ste_init_locked(sc);
1290 STE_UNLOCK(sc);
1291 }
1292
1293 static void
1294 ste_init_locked(sc)
1295 struct ste_softc *sc;
1296 {
1297 int i;
1298 struct ifnet *ifp;
1299
1300 STE_LOCK_ASSERT(sc);
1301 ifp = sc->ste_ifp;
1302
1303 ste_stop(sc);
1304
1305 /* Init our MAC address */
1306 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1307 CSR_WRITE_1(sc, STE_PAR0 + i, IFP2ENADDR(sc->ste_ifp)[i]);
1308 }
1309
1310 /* Init RX list */
1311 if (ste_init_rx_list(sc) == ENOBUFS) {
1312 if_printf(ifp,
1313 "initialization failed: no memory for RX buffers\n");
1314 ste_stop(sc);
1315 return;
1316 }
1317
1318 /* Set RX polling interval */
1319 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1320
1321 /* Init TX descriptors */
1322 ste_init_tx_list(sc);
1323
1324 /* Set the TX freethresh value */
1325 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1326
1327 /* Set the TX start threshold for best performance. */
1328 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1329
1330 /* Set the TX reclaim threshold. */
1331 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1332
1333 /* Set up the RX filter. */
1334 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1335
1336 /* If we want promiscuous mode, set the allframes bit. */
1337 if (ifp->if_flags & IFF_PROMISC) {
1338 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1339 } else {
1340 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1341 }
1342
1343 /* Set capture broadcast bit to accept broadcast frames. */
1344 if (ifp->if_flags & IFF_BROADCAST) {
1345 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1346 } else {
1347 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1348 }
1349
1350 ste_setmulti(sc);
1351
1352 /* Load the address of the RX list. */
1353 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1354 ste_wait(sc);
1355 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1356 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1357 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1358 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1359
1360 /* Set TX polling interval (defer until we TX first packet */
1361 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1362
1363 /* Load address of the TX list */
1364 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1365 ste_wait(sc);
1366 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1367 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1368 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1369 ste_wait(sc);
1370 sc->ste_tx_prev = NULL;
1371
1372 /* Enable receiver and transmitter */
1373 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1374 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1375 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1376 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1377
1378 /* Enable stats counters. */
1379 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1380
1381 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1382 #ifdef DEVICE_POLLING
1383 /* Disable interrupts if we are polling. */
1384 if (ifp->if_capenable & IFCAP_POLLING)
1385 CSR_WRITE_2(sc, STE_IMR, 0);
1386 else
1387 #endif
1388 /* Enable interrupts. */
1389 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1390
1391 /* Accept VLAN length packets */
1392 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1393
1394 ste_ifmedia_upd_locked(ifp);
1395
1396 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1397 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1398
1399 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc);
1400
1401 return;
1402 }
1403
1404 static void
1405 ste_stop(sc)
1406 struct ste_softc *sc;
1407 {
1408 int i;
1409 struct ifnet *ifp;
1410
1411 STE_LOCK_ASSERT(sc);
1412 ifp = sc->ste_ifp;
1413
1414 callout_stop(&sc->ste_stat_callout);
1415 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1416
1417 CSR_WRITE_2(sc, STE_IMR, 0);
1418 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1419 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1420 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1421 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1422 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1423 ste_wait(sc);
1424 /*
1425 * Try really hard to stop the RX engine or under heavy RX
1426 * data chip will write into de-allocated memory.
1427 */
1428 ste_reset(sc);
1429
1430 sc->ste_link = 0;
1431
1432 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1433 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1434 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1435 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1436 }
1437 }
1438
1439 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1440 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1441 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1442 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1443 }
1444 }
1445
1446 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1447
1448 return;
1449 }
1450
1451 static void
1452 ste_reset(sc)
1453 struct ste_softc *sc;
1454 {
1455 int i;
1456
1457 STE_SETBIT4(sc, STE_ASICCTL,
1458 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1459 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1460 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1461 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1462 STE_ASICCTL_EXTRESET_RESET);
1463
1464 DELAY(100000);
1465
1466 for (i = 0; i < STE_TIMEOUT; i++) {
1467 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1468 break;
1469 }
1470
1471 if (i == STE_TIMEOUT)
1472 if_printf(sc->ste_ifp, "global reset never completed\n");
1473
1474 return;
1475 }
1476
1477 static int
1478 ste_ioctl(ifp, command, data)
1479 struct ifnet *ifp;
1480 u_long command;
1481 caddr_t data;
1482 {
1483 struct ste_softc *sc;
1484 struct ifreq *ifr;
1485 struct mii_data *mii;
1486 int error = 0;
1487
1488 sc = ifp->if_softc;
1489 ifr = (struct ifreq *)data;
1490
1491 switch(command) {
1492 case SIOCSIFFLAGS:
1493 STE_LOCK(sc);
1494 if (ifp->if_flags & IFF_UP) {
1495 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1496 ifp->if_flags & IFF_PROMISC &&
1497 !(sc->ste_if_flags & IFF_PROMISC)) {
1498 STE_SETBIT1(sc, STE_RX_MODE,
1499 STE_RXMODE_PROMISC);
1500 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1501 !(ifp->if_flags & IFF_PROMISC) &&
1502 sc->ste_if_flags & IFF_PROMISC) {
1503 STE_CLRBIT1(sc, STE_RX_MODE,
1504 STE_RXMODE_PROMISC);
1505 }
1506 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1507 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI)
1508 ste_setmulti(sc);
1509 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1510 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1511 ste_init_locked(sc);
1512 }
1513 } else {
1514 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1515 ste_stop(sc);
1516 }
1517 sc->ste_if_flags = ifp->if_flags;
1518 STE_UNLOCK(sc);
1519 error = 0;
1520 break;
1521 case SIOCADDMULTI:
1522 case SIOCDELMULTI:
1523 STE_LOCK(sc);
1524 ste_setmulti(sc);
1525 STE_UNLOCK(sc);
1526 error = 0;
1527 break;
1528 case SIOCGIFMEDIA:
1529 case SIOCSIFMEDIA:
1530 mii = device_get_softc(sc->ste_miibus);
1531 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1532 break;
1533 case SIOCSIFCAP:
1534 #ifdef DEVICE_POLLING
1535 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1536 !(ifp->if_capenable & IFCAP_POLLING)) {
1537 error = ether_poll_register(ste_poll, ifp);
1538 if (error)
1539 return(error);
1540 STE_LOCK(sc);
1541 /* Disable interrupts */
1542 CSR_WRITE_2(sc, STE_IMR, 0);
1543 ifp->if_capenable |= IFCAP_POLLING;
1544 STE_UNLOCK(sc);
1545 return (error);
1546
1547 }
1548 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1549 ifp->if_capenable & IFCAP_POLLING) {
1550 error = ether_poll_deregister(ifp);
1551 /* Enable interrupts. */
1552 STE_LOCK(sc);
1553 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1554 ifp->if_capenable &= ~IFCAP_POLLING;
1555 STE_UNLOCK(sc);
1556 return (error);
1557 }
1558 #endif /* DEVICE_POLLING */
1559 break;
1560 default:
1561 error = ether_ioctl(ifp, command, data);
1562 break;
1563 }
1564
1565 return(error);
1566 }
1567
1568 static int
1569 ste_encap(sc, c, m_head)
1570 struct ste_softc *sc;
1571 struct ste_chain *c;
1572 struct mbuf *m_head;
1573 {
1574 int frag = 0;
1575 struct ste_frag *f = NULL;
1576 struct mbuf *m;
1577 struct ste_desc *d;
1578
1579 d = c->ste_ptr;
1580 d->ste_ctl = 0;
1581
1582 encap_retry:
1583 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1584 if (m->m_len != 0) {
1585 if (frag == STE_MAXFRAGS)
1586 break;
1587 f = &d->ste_frags[frag];
1588 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1589 f->ste_len = m->m_len;
1590 frag++;
1591 }
1592 }
1593
1594 if (m != NULL) {
1595 struct mbuf *mn;
1596
1597 /*
1598 * We ran out of segments. We have to recopy this
1599 * mbuf chain first. Bail out if we can't get the
1600 * new buffers.
1601 */
1602 mn = m_defrag(m_head, M_DONTWAIT);
1603 if (mn == NULL) {
1604 m_freem(m_head);
1605 return ENOMEM;
1606 }
1607 m_head = mn;
1608 goto encap_retry;
1609 }
1610
1611 c->ste_mbuf = m_head;
1612 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1613 d->ste_ctl = 1;
1614
1615 return(0);
1616 }
1617
1618 static void
1619 ste_start(ifp)
1620 struct ifnet *ifp;
1621 {
1622 struct ste_softc *sc;
1623
1624 sc = ifp->if_softc;
1625 STE_LOCK(sc);
1626 ste_start_locked(ifp);
1627 STE_UNLOCK(sc);
1628 }
1629
1630 static void
1631 ste_start_locked(ifp)
1632 struct ifnet *ifp;
1633 {
1634 struct ste_softc *sc;
1635 struct mbuf *m_head = NULL;
1636 struct ste_chain *cur_tx;
1637 int idx;
1638
1639 sc = ifp->if_softc;
1640 STE_LOCK_ASSERT(sc);
1641
1642 if (!sc->ste_link)
1643 return;
1644
1645 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1646 return;
1647
1648 idx = sc->ste_cdata.ste_tx_prod;
1649
1650 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1651 /*
1652 * We cannot re-use the last (free) descriptor;
1653 * the chip may not have read its ste_next yet.
1654 */
1655 if (STE_NEXT(idx, STE_TX_LIST_CNT) ==
1656 sc->ste_cdata.ste_tx_cons) {
1657 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1658 break;
1659 }
1660
1661 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1662 if (m_head == NULL)
1663 break;
1664
1665 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1666
1667 if (ste_encap(sc, cur_tx, m_head) != 0)
1668 break;
1669
1670 cur_tx->ste_ptr->ste_next = 0;
1671
1672 if (sc->ste_tx_prev == NULL) {
1673 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1674 /* Load address of the TX list */
1675 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1676 ste_wait(sc);
1677
1678 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1679 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1680
1681 /* Set TX polling interval to start TX engine */
1682 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1683
1684 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1685 ste_wait(sc);
1686 }else{
1687 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1688 sc->ste_tx_prev->ste_ptr->ste_next
1689 = cur_tx->ste_phys;
1690 }
1691
1692 sc->ste_tx_prev = cur_tx;
1693
1694 /*
1695 * If there's a BPF listener, bounce a copy of this frame
1696 * to him.
1697 */
1698 BPF_MTAP(ifp, cur_tx->ste_mbuf);
1699
1700 STE_INC(idx, STE_TX_LIST_CNT);
1701 ifp->if_timer = 5;
1702 }
1703 sc->ste_cdata.ste_tx_prod = idx;
1704
1705 return;
1706 }
1707
1708 static void
1709 ste_watchdog(ifp)
1710 struct ifnet *ifp;
1711 {
1712 struct ste_softc *sc;
1713
1714 sc = ifp->if_softc;
1715 STE_LOCK(sc);
1716
1717 ifp->if_oerrors++;
1718 if_printf(ifp, "watchdog timeout\n");
1719
1720 ste_txeoc(sc);
1721 ste_txeof(sc);
1722 ste_rxeoc(sc);
1723 ste_rxeof(sc);
1724 ste_reset(sc);
1725 ste_init_locked(sc);
1726
1727 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1728 ste_start_locked(ifp);
1729 STE_UNLOCK(sc);
1730
1731 return;
1732 }
1733
1734 static void
1735 ste_shutdown(dev)
1736 device_t dev;
1737 {
1738 struct ste_softc *sc;
1739
1740 sc = device_get_softc(dev);
1741
1742 STE_LOCK(sc);
1743 ste_stop(sc);
1744 STE_UNLOCK(sc);
1745
1746 return;
1747 }
Cache object: 3f9fd5025c9bdaf4bc46ced5cd2191e8
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