Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_ste.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #ifdef HAVE_KERNEL_OPTION_HEADERS 37 #include "opt_device_polling.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <net/bpf.h> 59 60 #include <vm/vm.h> /* for vtophys */ 61 #include <vm/pmap.h> /* for vtophys */ 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/bus.h> 65 #include <sys/rman.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 73 /* "controller miibus0" required. See GENERIC if you get errors here. */ 74 #include "miibus_if.h" 75 76 #define STE_USEIOSPACE 77 78 #include <pci/if_stereg.h> 79 80 MODULE_DEPEND(ste, pci, 1, 1, 1); 81 MODULE_DEPEND(ste, ether, 1, 1, 1); 82 MODULE_DEPEND(ste, miibus, 1, 1, 1); 83 84 /* 85 * Various supported device vendors/types and their names. 86 */ 87 static struct ste_type ste_devs[] = { 88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 91 { 0, 0, NULL } 92 }; 93 94 static int ste_probe(device_t); 95 static int ste_attach(device_t); 96 static int ste_detach(device_t); 97 static void ste_init(void *); 98 static void ste_init_locked(struct ste_softc *); 99 static void ste_intr(void *); 100 static void ste_rxeoc(struct ste_softc *); 101 static void ste_rxeof(struct ste_softc *); 102 static void ste_txeoc(struct ste_softc *); 103 static void ste_txeof(struct ste_softc *); 104 static void ste_stats_update(void *); 105 static void ste_stop(struct ste_softc *); 106 static void ste_reset(struct ste_softc *); 107 static int ste_ioctl(struct ifnet *, u_long, caddr_t); 108 static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *); 109 static void ste_start(struct ifnet *); 110 static void ste_start_locked(struct ifnet *); 111 static void ste_watchdog(struct ifnet *); 112 static void ste_shutdown(device_t); 113 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *, 114 struct mbuf *); 115 static int ste_ifmedia_upd(struct ifnet *); 116 static void ste_ifmedia_upd_locked(struct ifnet *); 117 static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 119 static void ste_mii_sync(struct ste_softc *); 120 static void ste_mii_send(struct ste_softc *, u_int32_t, int); 121 static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 122 static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 123 static int ste_miibus_readreg(device_t, int, int); 124 static int ste_miibus_writereg(device_t, int, int, int); 125 static void ste_miibus_statchg(device_t); 126 127 static int ste_eeprom_wait(struct ste_softc *); 128 static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 129 static void ste_wait(struct ste_softc *); 130 static void ste_setmulti(struct ste_softc *); 131 static int ste_init_rx_list(struct ste_softc *); 132 static void ste_init_tx_list(struct ste_softc *); 133 134 #ifdef STE_USEIOSPACE 135 #define STE_RES SYS_RES_IOPORT 136 #define STE_RID STE_PCI_LOIO 137 #else 138 #define STE_RES SYS_RES_MEMORY 139 #define STE_RID STE_PCI_LOMEM 140 #endif 141 142 static device_method_t ste_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_probe, ste_probe), 145 DEVMETHOD(device_attach, ste_attach), 146 DEVMETHOD(device_detach, ste_detach), 147 DEVMETHOD(device_shutdown, ste_shutdown), 148 149 /* bus interface */ 150 DEVMETHOD(bus_print_child, bus_generic_print_child), 151 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 152 153 /* MII interface */ 154 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 155 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 156 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 157 158 { 0, 0 } 159 }; 160 161 static driver_t ste_driver = { 162 "ste", 163 ste_methods, 164 sizeof(struct ste_softc) 165 }; 166 167 static devclass_t ste_devclass; 168 169 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 170 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 171 172 SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 173 174 static int ste_rxsyncs; 175 SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 176 177 #define STE_SETBIT4(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 179 180 #define STE_CLRBIT4(sc, reg, x) \ 181 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 182 183 #define STE_SETBIT2(sc, reg, x) \ 184 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 185 186 #define STE_CLRBIT2(sc, reg, x) \ 187 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 188 189 #define STE_SETBIT1(sc, reg, x) \ 190 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 191 192 #define STE_CLRBIT1(sc, reg, x) \ 193 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 194 195 196 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 197 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 198 199 /* 200 * Sync the PHYs by setting data bit and strobing the clock 32 times. 201 */ 202 static void 203 ste_mii_sync(sc) 204 struct ste_softc *sc; 205 { 206 register int i; 207 208 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 209 210 for (i = 0; i < 32; i++) { 211 MII_SET(STE_PHYCTL_MCLK); 212 DELAY(1); 213 MII_CLR(STE_PHYCTL_MCLK); 214 DELAY(1); 215 } 216 217 return; 218 } 219 220 /* 221 * Clock a series of bits through the MII. 222 */ 223 static void 224 ste_mii_send(sc, bits, cnt) 225 struct ste_softc *sc; 226 u_int32_t bits; 227 int cnt; 228 { 229 int i; 230 231 MII_CLR(STE_PHYCTL_MCLK); 232 233 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 234 if (bits & i) { 235 MII_SET(STE_PHYCTL_MDATA); 236 } else { 237 MII_CLR(STE_PHYCTL_MDATA); 238 } 239 DELAY(1); 240 MII_CLR(STE_PHYCTL_MCLK); 241 DELAY(1); 242 MII_SET(STE_PHYCTL_MCLK); 243 } 244 } 245 246 /* 247 * Read an PHY register through the MII. 248 */ 249 static int 250 ste_mii_readreg(sc, frame) 251 struct ste_softc *sc; 252 struct ste_mii_frame *frame; 253 254 { 255 int i, ack; 256 257 /* 258 * Set up frame for RX. 259 */ 260 frame->mii_stdelim = STE_MII_STARTDELIM; 261 frame->mii_opcode = STE_MII_READOP; 262 frame->mii_turnaround = 0; 263 frame->mii_data = 0; 264 265 CSR_WRITE_2(sc, STE_PHYCTL, 0); 266 /* 267 * Turn on data xmit. 268 */ 269 MII_SET(STE_PHYCTL_MDIR); 270 271 ste_mii_sync(sc); 272 273 /* 274 * Send command/address info. 275 */ 276 ste_mii_send(sc, frame->mii_stdelim, 2); 277 ste_mii_send(sc, frame->mii_opcode, 2); 278 ste_mii_send(sc, frame->mii_phyaddr, 5); 279 ste_mii_send(sc, frame->mii_regaddr, 5); 280 281 /* Turn off xmit. */ 282 MII_CLR(STE_PHYCTL_MDIR); 283 284 /* Idle bit */ 285 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 286 DELAY(1); 287 MII_SET(STE_PHYCTL_MCLK); 288 DELAY(1); 289 290 /* Check for ack */ 291 MII_CLR(STE_PHYCTL_MCLK); 292 DELAY(1); 293 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 294 MII_SET(STE_PHYCTL_MCLK); 295 DELAY(1); 296 297 /* 298 * Now try reading data bits. If the ack failed, we still 299 * need to clock through 16 cycles to keep the PHY(s) in sync. 300 */ 301 if (ack) { 302 for(i = 0; i < 16; i++) { 303 MII_CLR(STE_PHYCTL_MCLK); 304 DELAY(1); 305 MII_SET(STE_PHYCTL_MCLK); 306 DELAY(1); 307 } 308 goto fail; 309 } 310 311 for (i = 0x8000; i; i >>= 1) { 312 MII_CLR(STE_PHYCTL_MCLK); 313 DELAY(1); 314 if (!ack) { 315 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 316 frame->mii_data |= i; 317 DELAY(1); 318 } 319 MII_SET(STE_PHYCTL_MCLK); 320 DELAY(1); 321 } 322 323 fail: 324 325 MII_CLR(STE_PHYCTL_MCLK); 326 DELAY(1); 327 MII_SET(STE_PHYCTL_MCLK); 328 DELAY(1); 329 330 if (ack) 331 return(1); 332 return(0); 333 } 334 335 /* 336 * Write to a PHY register through the MII. 337 */ 338 static int 339 ste_mii_writereg(sc, frame) 340 struct ste_softc *sc; 341 struct ste_mii_frame *frame; 342 343 { 344 345 /* 346 * Set up frame for TX. 347 */ 348 349 frame->mii_stdelim = STE_MII_STARTDELIM; 350 frame->mii_opcode = STE_MII_WRITEOP; 351 frame->mii_turnaround = STE_MII_TURNAROUND; 352 353 /* 354 * Turn on data output. 355 */ 356 MII_SET(STE_PHYCTL_MDIR); 357 358 ste_mii_sync(sc); 359 360 ste_mii_send(sc, frame->mii_stdelim, 2); 361 ste_mii_send(sc, frame->mii_opcode, 2); 362 ste_mii_send(sc, frame->mii_phyaddr, 5); 363 ste_mii_send(sc, frame->mii_regaddr, 5); 364 ste_mii_send(sc, frame->mii_turnaround, 2); 365 ste_mii_send(sc, frame->mii_data, 16); 366 367 /* Idle bit. */ 368 MII_SET(STE_PHYCTL_MCLK); 369 DELAY(1); 370 MII_CLR(STE_PHYCTL_MCLK); 371 DELAY(1); 372 373 /* 374 * Turn off xmit. 375 */ 376 MII_CLR(STE_PHYCTL_MDIR); 377 378 return(0); 379 } 380 381 static int 382 ste_miibus_readreg(dev, phy, reg) 383 device_t dev; 384 int phy, reg; 385 { 386 struct ste_softc *sc; 387 struct ste_mii_frame frame; 388 389 sc = device_get_softc(dev); 390 391 if ( sc->ste_one_phy && phy != 0 ) 392 return (0); 393 394 bzero((char *)&frame, sizeof(frame)); 395 396 frame.mii_phyaddr = phy; 397 frame.mii_regaddr = reg; 398 ste_mii_readreg(sc, &frame); 399 400 return(frame.mii_data); 401 } 402 403 static int 404 ste_miibus_writereg(dev, phy, reg, data) 405 device_t dev; 406 int phy, reg, data; 407 { 408 struct ste_softc *sc; 409 struct ste_mii_frame frame; 410 411 sc = device_get_softc(dev); 412 bzero((char *)&frame, sizeof(frame)); 413 414 frame.mii_phyaddr = phy; 415 frame.mii_regaddr = reg; 416 frame.mii_data = data; 417 418 ste_mii_writereg(sc, &frame); 419 420 return(0); 421 } 422 423 static void 424 ste_miibus_statchg(dev) 425 device_t dev; 426 { 427 struct ste_softc *sc; 428 struct mii_data *mii; 429 430 sc = device_get_softc(dev); 431 432 mii = device_get_softc(sc->ste_miibus); 433 434 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 435 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 436 } else { 437 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 438 } 439 440 return; 441 } 442 443 static int 444 ste_ifmedia_upd(ifp) 445 struct ifnet *ifp; 446 { 447 struct ste_softc *sc; 448 449 sc = ifp->if_softc; 450 STE_LOCK(sc); 451 ste_ifmedia_upd_locked(ifp); 452 STE_UNLOCK(sc); 453 454 return(0); 455 } 456 457 static void 458 ste_ifmedia_upd_locked(ifp) 459 struct ifnet *ifp; 460 { 461 struct ste_softc *sc; 462 struct mii_data *mii; 463 464 sc = ifp->if_softc; 465 STE_LOCK_ASSERT(sc); 466 mii = device_get_softc(sc->ste_miibus); 467 sc->ste_link = 0; 468 if (mii->mii_instance) { 469 struct mii_softc *miisc; 470 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 471 mii_phy_reset(miisc); 472 } 473 mii_mediachg(mii); 474 } 475 476 static void 477 ste_ifmedia_sts(ifp, ifmr) 478 struct ifnet *ifp; 479 struct ifmediareq *ifmr; 480 { 481 struct ste_softc *sc; 482 struct mii_data *mii; 483 484 sc = ifp->if_softc; 485 mii = device_get_softc(sc->ste_miibus); 486 487 STE_LOCK(sc); 488 mii_pollstat(mii); 489 ifmr->ifm_active = mii->mii_media_active; 490 ifmr->ifm_status = mii->mii_media_status; 491 STE_UNLOCK(sc); 492 493 return; 494 } 495 496 static void 497 ste_wait(sc) 498 struct ste_softc *sc; 499 { 500 register int i; 501 502 for (i = 0; i < STE_TIMEOUT; i++) { 503 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 504 break; 505 } 506 507 if (i == STE_TIMEOUT) 508 if_printf(sc->ste_ifp, "command never completed!\n"); 509 510 return; 511 } 512 513 /* 514 * The EEPROM is slow: give it time to come ready after issuing 515 * it a command. 516 */ 517 static int 518 ste_eeprom_wait(sc) 519 struct ste_softc *sc; 520 { 521 int i; 522 523 DELAY(1000); 524 525 for (i = 0; i < 100; i++) { 526 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 527 DELAY(1000); 528 else 529 break; 530 } 531 532 if (i == 100) { 533 if_printf(sc->ste_ifp, "eeprom failed to come ready\n"); 534 return(1); 535 } 536 537 return(0); 538 } 539 540 /* 541 * Read a sequence of words from the EEPROM. Note that ethernet address 542 * data is stored in the EEPROM in network byte order. 543 */ 544 static int 545 ste_read_eeprom(sc, dest, off, cnt, swap) 546 struct ste_softc *sc; 547 caddr_t dest; 548 int off; 549 int cnt; 550 int swap; 551 { 552 int err = 0, i; 553 u_int16_t word = 0, *ptr; 554 555 if (ste_eeprom_wait(sc)) 556 return(1); 557 558 for (i = 0; i < cnt; i++) { 559 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 560 err = ste_eeprom_wait(sc); 561 if (err) 562 break; 563 word = CSR_READ_2(sc, STE_EEPROM_DATA); 564 ptr = (u_int16_t *)(dest + (i * 2)); 565 if (swap) 566 *ptr = ntohs(word); 567 else 568 *ptr = word; 569 } 570 571 return(err ? 1 : 0); 572 } 573 574 static void 575 ste_setmulti(sc) 576 struct ste_softc *sc; 577 { 578 struct ifnet *ifp; 579 int h = 0; 580 u_int32_t hashes[2] = { 0, 0 }; 581 struct ifmultiaddr *ifma; 582 583 ifp = sc->ste_ifp; 584 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 585 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 586 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 587 return; 588 } 589 590 /* first, zot all the existing hash bits */ 591 CSR_WRITE_2(sc, STE_MAR0, 0); 592 CSR_WRITE_2(sc, STE_MAR1, 0); 593 CSR_WRITE_2(sc, STE_MAR2, 0); 594 CSR_WRITE_2(sc, STE_MAR3, 0); 595 596 /* now program new ones */ 597 IF_ADDR_LOCK(ifp); 598 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 599 if (ifma->ifma_addr->sa_family != AF_LINK) 600 continue; 601 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 602 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 603 if (h < 32) 604 hashes[0] |= (1 << h); 605 else 606 hashes[1] |= (1 << (h - 32)); 607 } 608 IF_ADDR_UNLOCK(ifp); 609 610 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 611 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 612 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 613 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 614 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 615 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 616 617 return; 618 } 619 620 #ifdef DEVICE_POLLING 621 static poll_handler_t ste_poll, ste_poll_locked; 622 623 static void 624 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 625 { 626 struct ste_softc *sc = ifp->if_softc; 627 628 STE_LOCK(sc); 629 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 630 ste_poll_locked(ifp, cmd, count); 631 STE_UNLOCK(sc); 632 } 633 634 static void 635 ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 636 { 637 struct ste_softc *sc = ifp->if_softc; 638 639 STE_LOCK_ASSERT(sc); 640 641 sc->rxcycles = count; 642 if (cmd == POLL_AND_CHECK_STATUS) 643 ste_rxeoc(sc); 644 ste_rxeof(sc); 645 ste_txeof(sc); 646 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 647 ste_start_locked(ifp); 648 649 if (cmd == POLL_AND_CHECK_STATUS) { 650 u_int16_t status; 651 652 status = CSR_READ_2(sc, STE_ISR_ACK); 653 654 if (status & STE_ISR_TX_DONE) 655 ste_txeoc(sc); 656 657 if (status & STE_ISR_STATS_OFLOW) { 658 callout_stop(&sc->ste_stat_callout); 659 ste_stats_update(sc); 660 } 661 662 if (status & STE_ISR_LINKEVENT) 663 mii_pollstat(device_get_softc(sc->ste_miibus)); 664 665 if (status & STE_ISR_HOSTERR) { 666 ste_reset(sc); 667 ste_init_locked(sc); 668 } 669 } 670 } 671 #endif /* DEVICE_POLLING */ 672 673 static void 674 ste_intr(xsc) 675 void *xsc; 676 { 677 struct ste_softc *sc; 678 struct ifnet *ifp; 679 u_int16_t status; 680 681 sc = xsc; 682 STE_LOCK(sc); 683 ifp = sc->ste_ifp; 684 685 #ifdef DEVICE_POLLING 686 if (ifp->if_capenable & IFCAP_POLLING) { 687 STE_UNLOCK(sc); 688 return; 689 } 690 #endif 691 692 /* See if this is really our interrupt. */ 693 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 694 STE_UNLOCK(sc); 695 return; 696 } 697 698 for (;;) { 699 status = CSR_READ_2(sc, STE_ISR_ACK); 700 701 if (!(status & STE_INTRS)) 702 break; 703 704 if (status & STE_ISR_RX_DMADONE) { 705 ste_rxeoc(sc); 706 ste_rxeof(sc); 707 } 708 709 if (status & STE_ISR_TX_DMADONE) 710 ste_txeof(sc); 711 712 if (status & STE_ISR_TX_DONE) 713 ste_txeoc(sc); 714 715 if (status & STE_ISR_STATS_OFLOW) { 716 callout_stop(&sc->ste_stat_callout); 717 ste_stats_update(sc); 718 } 719 720 if (status & STE_ISR_LINKEVENT) 721 mii_pollstat(device_get_softc(sc->ste_miibus)); 722 723 724 if (status & STE_ISR_HOSTERR) { 725 ste_reset(sc); 726 ste_init_locked(sc); 727 } 728 } 729 730 /* Re-enable interrupts */ 731 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 732 733 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 734 ste_start_locked(ifp); 735 736 STE_UNLOCK(sc); 737 738 return; 739 } 740 741 static void 742 ste_rxeoc(struct ste_softc *sc) 743 { 744 struct ste_chain_onefrag *cur_rx; 745 746 STE_LOCK_ASSERT(sc); 747 748 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 749 cur_rx = sc->ste_cdata.ste_rx_head; 750 do { 751 cur_rx = cur_rx->ste_next; 752 /* If the ring is empty, just return. */ 753 if (cur_rx == sc->ste_cdata.ste_rx_head) 754 return; 755 } while (cur_rx->ste_ptr->ste_status == 0); 756 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 757 /* We've fallen behind the chip: catch it. */ 758 sc->ste_cdata.ste_rx_head = cur_rx; 759 ++ste_rxsyncs; 760 } 761 } 762 } 763 764 /* 765 * A frame has been uploaded: pass the resulting mbuf chain up to 766 * the higher level protocols. 767 */ 768 static void 769 ste_rxeof(sc) 770 struct ste_softc *sc; 771 { 772 struct mbuf *m; 773 struct ifnet *ifp; 774 struct ste_chain_onefrag *cur_rx; 775 int total_len = 0, count=0; 776 u_int32_t rxstat; 777 778 STE_LOCK_ASSERT(sc); 779 780 ifp = sc->ste_ifp; 781 782 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 783 & STE_RXSTAT_DMADONE) { 784 #ifdef DEVICE_POLLING 785 if (ifp->if_capenable & IFCAP_POLLING) { 786 if (sc->rxcycles <= 0) 787 break; 788 sc->rxcycles--; 789 } 790 #endif 791 if ((STE_RX_LIST_CNT - count) < 3) { 792 break; 793 } 794 795 cur_rx = sc->ste_cdata.ste_rx_head; 796 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 797 798 /* 799 * If an error occurs, update stats, clear the 800 * status word and leave the mbuf cluster in place: 801 * it should simply get re-used next time this descriptor 802 * comes up in the ring. 803 */ 804 if (rxstat & STE_RXSTAT_FRAME_ERR) { 805 ifp->if_ierrors++; 806 cur_rx->ste_ptr->ste_status = 0; 807 continue; 808 } 809 810 /* 811 * If there error bit was not set, the upload complete 812 * bit should be set which means we have a valid packet. 813 * If not, something truly strange has happened. 814 */ 815 if (!(rxstat & STE_RXSTAT_DMADONE)) { 816 if_printf(ifp, 817 "bad receive status -- packet dropped\n"); 818 ifp->if_ierrors++; 819 cur_rx->ste_ptr->ste_status = 0; 820 continue; 821 } 822 823 /* No errors; receive the packet. */ 824 m = cur_rx->ste_mbuf; 825 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 826 827 /* 828 * Try to conjure up a new mbuf cluster. If that 829 * fails, it means we have an out of memory condition and 830 * should leave the buffer in place and continue. This will 831 * result in a lost packet, but there's little else we 832 * can do in this situation. 833 */ 834 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 835 ifp->if_ierrors++; 836 cur_rx->ste_ptr->ste_status = 0; 837 continue; 838 } 839 840 m->m_pkthdr.rcvif = ifp; 841 m->m_pkthdr.len = m->m_len = total_len; 842 843 ifp->if_ipackets++; 844 STE_UNLOCK(sc); 845 (*ifp->if_input)(ifp, m); 846 STE_LOCK(sc); 847 848 cur_rx->ste_ptr->ste_status = 0; 849 count++; 850 } 851 852 return; 853 } 854 855 static void 856 ste_txeoc(sc) 857 struct ste_softc *sc; 858 { 859 u_int8_t txstat; 860 struct ifnet *ifp; 861 862 ifp = sc->ste_ifp; 863 864 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 865 STE_TXSTATUS_TXDONE) { 866 if (txstat & STE_TXSTATUS_UNDERRUN || 867 txstat & STE_TXSTATUS_EXCESSCOLLS || 868 txstat & STE_TXSTATUS_RECLAIMERR) { 869 ifp->if_oerrors++; 870 if_printf(ifp, "transmission error: %x\n", txstat); 871 872 ste_reset(sc); 873 ste_init_locked(sc); 874 875 if (txstat & STE_TXSTATUS_UNDERRUN && 876 sc->ste_tx_thresh < STE_PACKET_SIZE) { 877 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 878 if_printf(ifp, "tx underrun, increasing tx" 879 " start threshold to %d bytes\n", 880 sc->ste_tx_thresh); 881 } 882 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 883 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 884 (STE_PACKET_SIZE >> 4)); 885 } 886 ste_init_locked(sc); 887 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 888 } 889 890 return; 891 } 892 893 static void 894 ste_txeof(sc) 895 struct ste_softc *sc; 896 { 897 struct ste_chain *cur_tx; 898 struct ifnet *ifp; 899 int idx; 900 901 ifp = sc->ste_ifp; 902 903 idx = sc->ste_cdata.ste_tx_cons; 904 while(idx != sc->ste_cdata.ste_tx_prod) { 905 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 906 907 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 908 break; 909 910 m_freem(cur_tx->ste_mbuf); 911 cur_tx->ste_mbuf = NULL; 912 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 913 ifp->if_opackets++; 914 915 STE_INC(idx, STE_TX_LIST_CNT); 916 } 917 918 sc->ste_cdata.ste_tx_cons = idx; 919 if (idx == sc->ste_cdata.ste_tx_prod) 920 ifp->if_timer = 0; 921 } 922 923 static void 924 ste_stats_update(xsc) 925 void *xsc; 926 { 927 struct ste_softc *sc; 928 struct ifnet *ifp; 929 struct mii_data *mii; 930 931 sc = xsc; 932 STE_LOCK_ASSERT(sc); 933 934 ifp = sc->ste_ifp; 935 mii = device_get_softc(sc->ste_miibus); 936 937 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 938 + CSR_READ_1(sc, STE_MULTI_COLLS) 939 + CSR_READ_1(sc, STE_SINGLE_COLLS); 940 941 if (!sc->ste_link) { 942 mii_pollstat(mii); 943 if (mii->mii_media_status & IFM_ACTIVE && 944 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 945 sc->ste_link++; 946 /* 947 * we don't get a call-back on re-init so do it 948 * otherwise we get stuck in the wrong link state 949 */ 950 ste_miibus_statchg(sc->ste_dev); 951 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 952 ste_start_locked(ifp); 953 } 954 } 955 956 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 957 958 return; 959 } 960 961 962 /* 963 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 964 * IDs against our list and return a device name if we find a match. 965 */ 966 static int 967 ste_probe(dev) 968 device_t dev; 969 { 970 struct ste_type *t; 971 972 t = ste_devs; 973 974 while(t->ste_name != NULL) { 975 if ((pci_get_vendor(dev) == t->ste_vid) && 976 (pci_get_device(dev) == t->ste_did)) { 977 device_set_desc(dev, t->ste_name); 978 return (BUS_PROBE_DEFAULT); 979 } 980 t++; 981 } 982 983 return(ENXIO); 984 } 985 986 /* 987 * Attach the interface. Allocate softc structures, do ifmedia 988 * setup and ethernet/BPF attach. 989 */ 990 static int 991 ste_attach(dev) 992 device_t dev; 993 { 994 struct ste_softc *sc; 995 struct ifnet *ifp; 996 int error = 0, rid; 997 u_char eaddr[6]; 998 999 sc = device_get_softc(dev); 1000 sc->ste_dev = dev; 1001 1002 /* 1003 * Only use one PHY since this chip reports multiple 1004 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1005 * it is at 0 & 1. It is rev 0x12. 1006 */ 1007 if (pci_get_vendor(dev) == DL_VENDORID && 1008 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1009 pci_get_revid(dev) == 0x12 ) 1010 sc->ste_one_phy = 1; 1011 1012 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1013 MTX_DEF); 1014 /* 1015 * Map control/status registers. 1016 */ 1017 pci_enable_busmaster(dev); 1018 1019 rid = STE_RID; 1020 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1021 1022 if (sc->ste_res == NULL) { 1023 device_printf(dev, "couldn't map ports/memory\n"); 1024 error = ENXIO; 1025 goto fail; 1026 } 1027 1028 sc->ste_btag = rman_get_bustag(sc->ste_res); 1029 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1030 1031 /* Allocate interrupt */ 1032 rid = 0; 1033 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1034 RF_SHAREABLE | RF_ACTIVE); 1035 1036 if (sc->ste_irq == NULL) { 1037 device_printf(dev, "couldn't map interrupt\n"); 1038 error = ENXIO; 1039 goto fail; 1040 } 1041 1042 callout_init_mtx(&sc->ste_stat_callout, &sc->ste_mtx, 0); 1043 1044 /* Reset the adapter. */ 1045 ste_reset(sc); 1046 1047 /* 1048 * Get station address from the EEPROM. 1049 */ 1050 if (ste_read_eeprom(sc, eaddr, 1051 STE_EEADDR_NODE0, 3, 0)) { 1052 device_printf(dev, "failed to read station address\n"); 1053 error = ENXIO;; 1054 goto fail; 1055 } 1056 1057 /* Allocate the descriptor queues. */ 1058 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1059 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1060 1061 if (sc->ste_ldata == NULL) { 1062 device_printf(dev, "no memory for list buffers!\n"); 1063 error = ENXIO; 1064 goto fail; 1065 } 1066 1067 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1068 1069 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1070 if (ifp == NULL) { 1071 device_printf(dev, "can not if_alloc()\n"); 1072 error = ENOSPC; 1073 goto fail; 1074 } 1075 1076 /* Do MII setup. */ 1077 if (mii_phy_probe(dev, &sc->ste_miibus, 1078 ste_ifmedia_upd, ste_ifmedia_sts)) { 1079 device_printf(dev, "MII without any phy!\n"); 1080 error = ENXIO; 1081 goto fail; 1082 } 1083 1084 ifp->if_softc = sc; 1085 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1086 ifp->if_mtu = ETHERMTU; 1087 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1088 ifp->if_ioctl = ste_ioctl; 1089 ifp->if_start = ste_start; 1090 ifp->if_watchdog = ste_watchdog; 1091 ifp->if_init = ste_init; 1092 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1093 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1094 IFQ_SET_READY(&ifp->if_snd); 1095 1096 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1097 1098 /* 1099 * Call MI attach routine. 1100 */ 1101 ether_ifattach(ifp, eaddr); 1102 1103 /* 1104 * Tell the upper layer(s) we support long frames. 1105 */ 1106 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1107 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1108 ifp->if_capenable = ifp->if_capabilities; 1109 #ifdef DEVICE_POLLING 1110 ifp->if_capabilities |= IFCAP_POLLING; 1111 #endif 1112 1113 /* Hook interrupt last to avoid having to lock softc */ 1114 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1115 ste_intr, sc, &sc->ste_intrhand); 1116 1117 if (error) { 1118 device_printf(dev, "couldn't set up irq\n"); 1119 ether_ifdetach(ifp); 1120 goto fail; 1121 } 1122 1123 fail: 1124 if (error) 1125 ste_detach(dev); 1126 1127 return(error); 1128 } 1129 1130 /* 1131 * Shutdown hardware and free up resources. This can be called any 1132 * time after the mutex has been initialized. It is called in both 1133 * the error case in attach and the normal detach case so it needs 1134 * to be careful about only freeing resources that have actually been 1135 * allocated. 1136 */ 1137 static int 1138 ste_detach(dev) 1139 device_t dev; 1140 { 1141 struct ste_softc *sc; 1142 struct ifnet *ifp; 1143 1144 sc = device_get_softc(dev); 1145 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1146 ifp = sc->ste_ifp; 1147 1148 #ifdef DEVICE_POLLING 1149 if (ifp->if_capenable & IFCAP_POLLING) 1150 ether_poll_deregister(ifp); 1151 #endif 1152 1153 /* These should only be active if attach succeeded */ 1154 if (device_is_attached(dev)) { 1155 STE_LOCK(sc); 1156 ste_stop(sc); 1157 STE_UNLOCK(sc); 1158 callout_drain(&sc->ste_stat_callout); 1159 ether_ifdetach(ifp); 1160 } 1161 if (ifp) 1162 if_free(ifp); 1163 if (sc->ste_miibus) 1164 device_delete_child(dev, sc->ste_miibus); 1165 bus_generic_detach(dev); 1166 1167 if (sc->ste_intrhand) 1168 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1169 if (sc->ste_irq) 1170 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1171 if (sc->ste_res) 1172 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1173 1174 if (sc->ste_ldata) { 1175 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1176 M_DEVBUF); 1177 } 1178 1179 mtx_destroy(&sc->ste_mtx); 1180 1181 return(0); 1182 } 1183 1184 static int 1185 ste_newbuf(sc, c, m) 1186 struct ste_softc *sc; 1187 struct ste_chain_onefrag *c; 1188 struct mbuf *m; 1189 { 1190 struct mbuf *m_new = NULL; 1191 1192 if (m == NULL) { 1193 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1194 if (m_new == NULL) 1195 return(ENOBUFS); 1196 MCLGET(m_new, M_DONTWAIT); 1197 if (!(m_new->m_flags & M_EXT)) { 1198 m_freem(m_new); 1199 return(ENOBUFS); 1200 } 1201 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1202 } else { 1203 m_new = m; 1204 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1205 m_new->m_data = m_new->m_ext.ext_buf; 1206 } 1207 1208 m_adj(m_new, ETHER_ALIGN); 1209 1210 c->ste_mbuf = m_new; 1211 c->ste_ptr->ste_status = 0; 1212 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1213 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1214 1215 return(0); 1216 } 1217 1218 static int 1219 ste_init_rx_list(sc) 1220 struct ste_softc *sc; 1221 { 1222 struct ste_chain_data *cd; 1223 struct ste_list_data *ld; 1224 int i; 1225 1226 cd = &sc->ste_cdata; 1227 ld = sc->ste_ldata; 1228 1229 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1230 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1231 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1232 return(ENOBUFS); 1233 if (i == (STE_RX_LIST_CNT - 1)) { 1234 cd->ste_rx_chain[i].ste_next = 1235 &cd->ste_rx_chain[0]; 1236 ld->ste_rx_list[i].ste_next = 1237 vtophys(&ld->ste_rx_list[0]); 1238 } else { 1239 cd->ste_rx_chain[i].ste_next = 1240 &cd->ste_rx_chain[i + 1]; 1241 ld->ste_rx_list[i].ste_next = 1242 vtophys(&ld->ste_rx_list[i + 1]); 1243 } 1244 ld->ste_rx_list[i].ste_status = 0; 1245 } 1246 1247 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1248 1249 return(0); 1250 } 1251 1252 static void 1253 ste_init_tx_list(sc) 1254 struct ste_softc *sc; 1255 { 1256 struct ste_chain_data *cd; 1257 struct ste_list_data *ld; 1258 int i; 1259 1260 cd = &sc->ste_cdata; 1261 ld = sc->ste_ldata; 1262 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1263 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1264 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1265 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1266 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1267 if (i == (STE_TX_LIST_CNT - 1)) 1268 cd->ste_tx_chain[i].ste_next = 1269 &cd->ste_tx_chain[0]; 1270 else 1271 cd->ste_tx_chain[i].ste_next = 1272 &cd->ste_tx_chain[i + 1]; 1273 } 1274 1275 cd->ste_tx_prod = 0; 1276 cd->ste_tx_cons = 0; 1277 1278 return; 1279 } 1280 1281 static void 1282 ste_init(xsc) 1283 void *xsc; 1284 { 1285 struct ste_softc *sc; 1286 1287 sc = xsc; 1288 STE_LOCK(sc); 1289 ste_init_locked(sc); 1290 STE_UNLOCK(sc); 1291 } 1292 1293 static void 1294 ste_init_locked(sc) 1295 struct ste_softc *sc; 1296 { 1297 int i; 1298 struct ifnet *ifp; 1299 1300 STE_LOCK_ASSERT(sc); 1301 ifp = sc->ste_ifp; 1302 1303 ste_stop(sc); 1304 1305 /* Init our MAC address */ 1306 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1307 CSR_WRITE_2(sc, STE_PAR0 + i, 1308 ((IFP2ENADDR(sc->ste_ifp)[i] & 0xff) | 1309 IFP2ENADDR(sc->ste_ifp)[i + 1] << 8)); 1310 } 1311 1312 /* Init RX list */ 1313 if (ste_init_rx_list(sc) == ENOBUFS) { 1314 if_printf(ifp, 1315 "initialization failed: no memory for RX buffers\n"); 1316 ste_stop(sc); 1317 return; 1318 } 1319 1320 /* Set RX polling interval */ 1321 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1322 1323 /* Init TX descriptors */ 1324 ste_init_tx_list(sc); 1325 1326 /* Set the TX freethresh value */ 1327 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1328 1329 /* Set the TX start threshold for best performance. */ 1330 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1331 1332 /* Set the TX reclaim threshold. */ 1333 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1334 1335 /* Set up the RX filter. */ 1336 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1337 1338 /* If we want promiscuous mode, set the allframes bit. */ 1339 if (ifp->if_flags & IFF_PROMISC) { 1340 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1341 } else { 1342 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1343 } 1344 1345 /* Set capture broadcast bit to accept broadcast frames. */ 1346 if (ifp->if_flags & IFF_BROADCAST) { 1347 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1348 } else { 1349 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1350 } 1351 1352 ste_setmulti(sc); 1353 1354 /* Load the address of the RX list. */ 1355 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1356 ste_wait(sc); 1357 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1358 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1359 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1360 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1361 1362 /* Set TX polling interval (defer until we TX first packet */ 1363 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1364 1365 /* Load address of the TX list */ 1366 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1367 ste_wait(sc); 1368 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1369 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1370 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1371 ste_wait(sc); 1372 sc->ste_tx_prev = NULL; 1373 1374 /* Enable receiver and transmitter */ 1375 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1376 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1377 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1378 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1379 1380 /* Enable stats counters. */ 1381 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1382 1383 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1384 #ifdef DEVICE_POLLING 1385 /* Disable interrupts if we are polling. */ 1386 if (ifp->if_capenable & IFCAP_POLLING) 1387 CSR_WRITE_2(sc, STE_IMR, 0); 1388 else 1389 #endif 1390 /* Enable interrupts. */ 1391 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1392 1393 /* Accept VLAN length packets */ 1394 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1395 1396 ste_ifmedia_upd_locked(ifp); 1397 1398 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1399 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1400 1401 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 1402 1403 return; 1404 } 1405 1406 static void 1407 ste_stop(sc) 1408 struct ste_softc *sc; 1409 { 1410 int i; 1411 struct ifnet *ifp; 1412 1413 STE_LOCK_ASSERT(sc); 1414 ifp = sc->ste_ifp; 1415 1416 callout_stop(&sc->ste_stat_callout); 1417 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1418 1419 CSR_WRITE_2(sc, STE_IMR, 0); 1420 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1421 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1422 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1423 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1424 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1425 ste_wait(sc); 1426 /* 1427 * Try really hard to stop the RX engine or under heavy RX 1428 * data chip will write into de-allocated memory. 1429 */ 1430 ste_reset(sc); 1431 1432 sc->ste_link = 0; 1433 1434 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1435 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1436 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1437 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1438 } 1439 } 1440 1441 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1442 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1443 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1444 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1445 } 1446 } 1447 1448 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1449 1450 return; 1451 } 1452 1453 static void 1454 ste_reset(sc) 1455 struct ste_softc *sc; 1456 { 1457 int i; 1458 1459 STE_SETBIT4(sc, STE_ASICCTL, 1460 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1461 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1462 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1463 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1464 STE_ASICCTL_EXTRESET_RESET); 1465 1466 DELAY(100000); 1467 1468 for (i = 0; i < STE_TIMEOUT; i++) { 1469 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1470 break; 1471 } 1472 1473 if (i == STE_TIMEOUT) 1474 if_printf(sc->ste_ifp, "global reset never completed\n"); 1475 1476 return; 1477 } 1478 1479 static int 1480 ste_ioctl(ifp, command, data) 1481 struct ifnet *ifp; 1482 u_long command; 1483 caddr_t data; 1484 { 1485 struct ste_softc *sc; 1486 struct ifreq *ifr; 1487 struct mii_data *mii; 1488 int error = 0; 1489 1490 sc = ifp->if_softc; 1491 ifr = (struct ifreq *)data; 1492 1493 switch(command) { 1494 case SIOCSIFFLAGS: 1495 STE_LOCK(sc); 1496 if (ifp->if_flags & IFF_UP) { 1497 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1498 ifp->if_flags & IFF_PROMISC && 1499 !(sc->ste_if_flags & IFF_PROMISC)) { 1500 STE_SETBIT1(sc, STE_RX_MODE, 1501 STE_RXMODE_PROMISC); 1502 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1503 !(ifp->if_flags & IFF_PROMISC) && 1504 sc->ste_if_flags & IFF_PROMISC) { 1505 STE_CLRBIT1(sc, STE_RX_MODE, 1506 STE_RXMODE_PROMISC); 1507 } 1508 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1509 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1510 ste_setmulti(sc); 1511 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1512 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1513 ste_init_locked(sc); 1514 } 1515 } else { 1516 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1517 ste_stop(sc); 1518 } 1519 sc->ste_if_flags = ifp->if_flags; 1520 STE_UNLOCK(sc); 1521 error = 0; 1522 break; 1523 case SIOCADDMULTI: 1524 case SIOCDELMULTI: 1525 STE_LOCK(sc); 1526 ste_setmulti(sc); 1527 STE_UNLOCK(sc); 1528 error = 0; 1529 break; 1530 case SIOCGIFMEDIA: 1531 case SIOCSIFMEDIA: 1532 mii = device_get_softc(sc->ste_miibus); 1533 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1534 break; 1535 case SIOCSIFCAP: 1536 #ifdef DEVICE_POLLING 1537 if (ifr->ifr_reqcap & IFCAP_POLLING && 1538 !(ifp->if_capenable & IFCAP_POLLING)) { 1539 error = ether_poll_register(ste_poll, ifp); 1540 if (error) 1541 return(error); 1542 STE_LOCK(sc); 1543 /* Disable interrupts */ 1544 CSR_WRITE_2(sc, STE_IMR, 0); 1545 ifp->if_capenable |= IFCAP_POLLING; 1546 STE_UNLOCK(sc); 1547 return (error); 1548 1549 } 1550 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1551 ifp->if_capenable & IFCAP_POLLING) { 1552 error = ether_poll_deregister(ifp); 1553 /* Enable interrupts. */ 1554 STE_LOCK(sc); 1555 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1556 ifp->if_capenable &= ~IFCAP_POLLING; 1557 STE_UNLOCK(sc); 1558 return (error); 1559 } 1560 #endif /* DEVICE_POLLING */ 1561 break; 1562 default: 1563 error = ether_ioctl(ifp, command, data); 1564 break; 1565 } 1566 1567 return(error); 1568 } 1569 1570 static int 1571 ste_encap(sc, c, m_head) 1572 struct ste_softc *sc; 1573 struct ste_chain *c; 1574 struct mbuf *m_head; 1575 { 1576 int frag = 0; 1577 struct ste_frag *f = NULL; 1578 struct mbuf *m; 1579 struct ste_desc *d; 1580 1581 d = c->ste_ptr; 1582 d->ste_ctl = 0; 1583 1584 encap_retry: 1585 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1586 if (m->m_len != 0) { 1587 if (frag == STE_MAXFRAGS) 1588 break; 1589 f = &d->ste_frags[frag]; 1590 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1591 f->ste_len = m->m_len; 1592 frag++; 1593 } 1594 } 1595 1596 if (m != NULL) { 1597 struct mbuf *mn; 1598 1599 /* 1600 * We ran out of segments. We have to recopy this 1601 * mbuf chain first. Bail out if we can't get the 1602 * new buffers. 1603 */ 1604 mn = m_defrag(m_head, M_DONTWAIT); 1605 if (mn == NULL) { 1606 m_freem(m_head); 1607 return ENOMEM; 1608 } 1609 m_head = mn; 1610 goto encap_retry; 1611 } 1612 1613 c->ste_mbuf = m_head; 1614 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1615 d->ste_ctl = 1; 1616 1617 return(0); 1618 } 1619 1620 static void 1621 ste_start(ifp) 1622 struct ifnet *ifp; 1623 { 1624 struct ste_softc *sc; 1625 1626 sc = ifp->if_softc; 1627 STE_LOCK(sc); 1628 ste_start_locked(ifp); 1629 STE_UNLOCK(sc); 1630 } 1631 1632 static void 1633 ste_start_locked(ifp) 1634 struct ifnet *ifp; 1635 { 1636 struct ste_softc *sc; 1637 struct mbuf *m_head = NULL; 1638 struct ste_chain *cur_tx; 1639 int idx; 1640 1641 sc = ifp->if_softc; 1642 STE_LOCK_ASSERT(sc); 1643 1644 if (!sc->ste_link) 1645 return; 1646 1647 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1648 return; 1649 1650 idx = sc->ste_cdata.ste_tx_prod; 1651 1652 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1653 /* 1654 * We cannot re-use the last (free) descriptor; 1655 * the chip may not have read its ste_next yet. 1656 */ 1657 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1658 sc->ste_cdata.ste_tx_cons) { 1659 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1660 break; 1661 } 1662 1663 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1664 if (m_head == NULL) 1665 break; 1666 1667 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1668 1669 if (ste_encap(sc, cur_tx, m_head) != 0) 1670 break; 1671 1672 cur_tx->ste_ptr->ste_next = 0; 1673 1674 if (sc->ste_tx_prev == NULL) { 1675 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1676 /* Load address of the TX list */ 1677 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1678 ste_wait(sc); 1679 1680 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1681 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1682 1683 /* Set TX polling interval to start TX engine */ 1684 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1685 1686 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1687 ste_wait(sc); 1688 }else{ 1689 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1690 sc->ste_tx_prev->ste_ptr->ste_next 1691 = cur_tx->ste_phys; 1692 } 1693 1694 sc->ste_tx_prev = cur_tx; 1695 1696 /* 1697 * If there's a BPF listener, bounce a copy of this frame 1698 * to him. 1699 */ 1700 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1701 1702 STE_INC(idx, STE_TX_LIST_CNT); 1703 ifp->if_timer = 5; 1704 } 1705 sc->ste_cdata.ste_tx_prod = idx; 1706 1707 return; 1708 } 1709 1710 static void 1711 ste_watchdog(ifp) 1712 struct ifnet *ifp; 1713 { 1714 struct ste_softc *sc; 1715 1716 sc = ifp->if_softc; 1717 STE_LOCK(sc); 1718 1719 ifp->if_oerrors++; 1720 if_printf(ifp, "watchdog timeout\n"); 1721 1722 ste_txeoc(sc); 1723 ste_txeof(sc); 1724 ste_rxeoc(sc); 1725 ste_rxeof(sc); 1726 ste_reset(sc); 1727 ste_init_locked(sc); 1728 1729 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1730 ste_start_locked(ifp); 1731 STE_UNLOCK(sc); 1732 1733 return; 1734 } 1735 1736 static void 1737 ste_shutdown(dev) 1738 device_t dev; 1739 { 1740 struct ste_softc *sc; 1741 1742 sc = device_get_softc(dev); 1743 1744 STE_LOCK(sc); 1745 ste_stop(sc); 1746 STE_UNLOCK(sc); 1747 1748 return; 1749 }
Cache object: 036f63306db20f0eb92a872555e84299
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