The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_stereg.h

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    1 /*-
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD$
   33  */
   34 
   35 /*
   36  * Sundance PCI device/vendor ID for the
   37  * ST201 chip.
   38  */
   39 #define ST_VENDORID             0x13F0
   40 #define ST_DEVICEID_ST201_1     0x0200
   41 #define ST_DEVICEID_ST201_2     0x0201
   42 
   43 /*
   44  * D-Link PCI device/vendor ID for the DL10050[AB] chip
   45  */
   46 #define DL_VENDORID             0x1186
   47 #define DL_DEVICEID_DL10050     0x1002
   48 
   49 /*
   50  * Register definitions for the Sundance Technologies ST201 PCI
   51  * fast ethernet controller. The register space is 128 bytes long and
   52  * can be accessed using either PCI I/O space or PCI memory mapping.
   53  * There are 32-bit, 16-bit and 8-bit registers.
   54  */
   55 
   56 #define STE_DMACTL              0x00
   57 #define STE_TX_DMALIST_PTR      0x04
   58 #define STE_TX_DMABURST_THRESH  0x08
   59 #define STE_TX_DMAURG_THRESH    0x09
   60 #define STE_TX_DMAPOLL_PERIOD   0x0A
   61 #define STE_RX_DMASTATUS        0x0C
   62 #define STE_RX_DMALIST_PTR      0x10
   63 #define STE_RX_DMABURST_THRESH  0x14
   64 #define STE_RX_DMAURG_THRESH    0x15
   65 #define STE_RX_DMAPOLL_PERIOD   0x16
   66 #define STE_DEBUGCTL            0x1A
   67 #define STE_ASICCTL             0x30
   68 #define STE_EEPROM_DATA         0x34
   69 #define STE_EEPROM_CTL          0x36
   70 #define STE_FIFOCTL             0x3A
   71 #define STE_TX_STARTTHRESH      0x3C
   72 #define STE_RX_EARLYTHRESH      0x3E
   73 #define STE_EXT_ROMADDR         0x40
   74 #define STE_EXT_ROMDATA         0x44
   75 #define STE_WAKE_EVENT          0x45
   76 #define STE_TX_STATUS           0x46
   77 #define STE_TX_FRAMEID          0x47
   78 #define STE_COUNTDOWN           0x48
   79 #define STE_ISR_ACK             0x4A
   80 #define STE_IMR                 0x4C
   81 #define STE_ISR                 0x4E
   82 #define STE_MACCTL0             0x50
   83 #define STE_MACCTL1             0x52
   84 #define STE_PAR0                0x54
   85 #define STE_PAR1                0x56
   86 #define STE_PAR2                0x58
   87 #define STE_MAX_FRAMELEN        0x5A
   88 #define STE_RX_MODE             0x5C
   89 #define STE_TX_RECLAIM_THRESH   0x5D
   90 #define STE_PHYCTL              0x5E
   91 #define STE_MAR0                0x60
   92 #define STE_MAR1                0x62
   93 #define STE_MAR2                0x64
   94 #define STE_MAR3                0x66
   95 #define STE_STATS               0x68
   96 
   97 #define STE_LATE_COLLS  0x75
   98 #define STE_MULTI_COLLS 0x76
   99 #define STE_SINGLE_COLLS 0x77   
  100 
  101 #define STE_DMACTL_RXDMA_STOPPED        0x00000001
  102 #define STE_DMACTL_TXDMA_CMPREQ         0x00000002
  103 #define STE_DMACTL_TXDMA_STOPPED        0x00000004
  104 #define STE_DMACTL_RXDMA_COMPLETE       0x00000008
  105 #define STE_DMACTL_TXDMA_COMPLETE       0x00000010
  106 #define STE_DMACTL_RXDMA_STALL          0x00000100
  107 #define STE_DMACTL_RXDMA_UNSTALL        0x00000200
  108 #define STE_DMACTL_TXDMA_STALL          0x00000400
  109 #define STE_DMACTL_TXDMA_UNSTALL        0x00000800
  110 #define STE_DMACTL_TXDMA_INPROG         0x00004000
  111 #define STE_DMACTL_DMA_HALTINPROG       0x00008000
  112 #define STE_DMACTL_RXEARLY_ENABLE       0x00020000
  113 #define STE_DMACTL_COUNTDOWN_SPEED      0x00040000
  114 #define STE_DMACTL_COUNTDOWN_MODE       0x00080000
  115 #define STE_DMACTL_MWI_DISABLE          0x00100000
  116 #define STE_DMACTL_RX_DISCARD_OFLOWS    0x00400000
  117 #define STE_DMACTL_COUNTDOWN_ENABLE     0x00800000
  118 #define STE_DMACTL_TARGET_ABORT         0x40000000
  119 #define STE_DMACTL_MASTER_ABORT         0x80000000
  120 
  121 /*
  122  * TX DMA burst thresh is the number of 32-byte blocks that
  123  * must be loaded into the TX Fifo before a TXDMA burst request
  124  * will be issued.
  125  */
  126 #define STE_TXDMABURST_THRESH           0x1F
  127 
  128 /*
  129  * The number of 32-byte blocks in the TX FIFO falls below the
  130  * TX DMA urgent threshold, a TX DMA urgent request will be
  131  * generated.
  132  */
  133 #define STE_TXDMAURG_THRESH             0x3F
  134 
  135 /*
  136  * Number of 320ns intervals between polls of the TXDMA next
  137  * descriptor pointer (if we're using polling mode).
  138  */
  139 #define STE_TXDMA_POLL_PERIOD           0x7F
  140 
  141 #define STE_RX_DMASTATUS_FRAMELEN       0x00001FFF
  142 #define STE_RX_DMASTATUS_RXERR          0x00004000
  143 #define STE_RX_DMASTATUS_DMADONE        0x00008000
  144 #define STE_RX_DMASTATUS_FIFO_OFLOW     0x00010000
  145 #define STE_RX_DMASTATUS_RUNT           0x00020000
  146 #define STE_RX_DMASTATUS_ALIGNERR       0x00040000
  147 #define STE_RX_DMASTATUS_CRCERR         0x00080000
  148 #define STE_RX_DMASTATUS_GIANT          0x00100000
  149 #define STE_RX_DMASTATUS_DRIBBLE        0x00800000
  150 #define STE_RX_DMASTATUS_DMA_OFLOW      0x01000000
  151 
  152 /*
  153  * RX DMA burst thresh is the number of 32-byte blocks that
  154  * must be present in the RX FIFO before a RXDMA bus master
  155  * request will be issued.
  156  */
  157 #define STE_RXDMABURST_THRESH           0xFF
  158 
  159 /*
  160  * The number of 32-byte blocks in the RX FIFO falls below the
  161  * RX DMA urgent threshold, a RX DMA urgent request will be
  162  * generated.
  163  */
  164 #define STE_RXDMAURG_THRESH             0x1F
  165 
  166 /*
  167  * Number of 320ns intervals between polls of the RXDMA complete
  168  * bit in the status field on the current RX descriptor (if we're
  169  * using polling mode).
  170  */
  171 #define STE_RXDMA_POLL_PERIOD           0x7F
  172 
  173 #define STE_DEBUGCTL_GPIO0_CTL          0x0001
  174 #define STE_DEBUGCTL_GPIO1_CTL          0x0002
  175 #define STE_DEBUGCTL_GPIO0_DATA         0x0004
  176 #define STE_DEBUGCTL_GPIO1_DATA         0x0008
  177 
  178 #define STE_ASICCTL_ROMSIZE             0x00000002
  179 #define STE_ASICCTL_TX_LARGEPKTS        0x00000004
  180 #define STE_ASICCTL_RX_LARGEPKTS        0x00000008
  181 #define STE_ASICCTL_EXTROM_DISABLE      0x00000010
  182 #define STE_ASICCTL_PHYSPEED_10         0x00000020
  183 #define STE_ASICCTL_PHYSPEED_100        0x00000040
  184 #define STE_ASICCTL_PHYMEDIA            0x00000080
  185 #define STE_ASICCTL_FORCEDCONFIG        0x00000700
  186 #define STE_ASICCTL_D3RESET_DISABLE     0x00000800
  187 #define STE_ASICCTL_SPEEDUPMODE         0x00002000
  188 #define STE_ASICCTL_LEDMODE             0x00004000
  189 #define STE_ASICCTL_RSTOUT_POLARITY     0x00008000
  190 #define STE_ASICCTL_GLOBAL_RESET        0x00010000
  191 #define STE_ASICCTL_RX_RESET            0x00020000
  192 #define STE_ASICCTL_TX_RESET            0x00040000
  193 #define STE_ASICCTL_DMA_RESET           0x00080000
  194 #define STE_ASICCTL_FIFO_RESET          0x00100000
  195 #define STE_ASICCTL_NETWORK_RESET       0x00200000
  196 #define STE_ASICCTL_HOST_RESET          0x00400000
  197 #define STE_ASICCTL_AUTOINIT_RESET      0x00800000
  198 #define STE_ASICCTL_EXTRESET_RESET      0x01000000
  199 #define STE_ASICCTL_SOFTINTR            0x02000000
  200 #define STE_ASICCTL_RESET_BUSY          0x04000000
  201 
  202 #define STE_ASICCTL1_GLOBAL_RESET       0x0001
  203 #define STE_ASICCTL1_RX_RESET           0x0002
  204 #define STE_ASICCTL1_TX_RESET           0x0004
  205 #define STE_ASICCTL1_DMA_RESET          0x0008
  206 #define STE_ASICCTL1_FIFO_RESET         0x0010
  207 #define STE_ASICCTL1_NETWORK_RESET      0x0020
  208 #define STE_ASICCTL1_HOST_RESET         0x0040
  209 #define STE_ASICCTL1_AUTOINIT_RESET     0x0080
  210 #define STE_ASICCTL1_EXTRESET_RESET     0x0100
  211 #define STE_ASICCTL1_SOFTINTR           0x0200
  212 #define STE_ASICCTL1_RESET_BUSY         0x0400
  213 
  214 #define STE_EECTL_ADDR                  0x00FF
  215 #define STE_EECTL_OPCODE                0x0300
  216 #define STE_EECTL_BUSY                  0x1000
  217 
  218 #define STE_EEOPCODE_WRITE              0x0100
  219 #define STE_EEOPCODE_READ               0x0200
  220 #define STE_EEOPCODE_ERASE              0x0300
  221 
  222 #define STE_FIFOCTL_RAMTESTMODE         0x0001
  223 #define STE_FIFOCTL_OVERRUNMODE         0x0200
  224 #define STE_FIFOCTL_RXFIFOFULL          0x0800
  225 #define STE_FIFOCTL_TX_BUSY             0x4000
  226 #define STE_FIFOCTL_RX_BUSY             0x8000
  227 
  228 /*
  229  * The number of bytes that must in present in the TX FIFO before
  230  * transmission begins. Value should be in increments of 4 bytes.
  231  */
  232 #define STE_TXSTART_THRESH              0x1FFC
  233 
  234 /*
  235  * Number of bytes that must be present in the RX FIFO before
  236  * an RX EARLY interrupt is generated.
  237  */
  238 #define STE_RXEARLY_THRESH              0x1FFC
  239 
  240 #define STE_WAKEEVENT_WAKEPKT_ENB       0x01
  241 #define STE_WAKEEVENT_MAGICPKT_ENB      0x02
  242 #define STE_WAKEEVENT_LINKEVT_ENB       0x04
  243 #define STE_WAKEEVENT_WAKEPOLARITY      0x08
  244 #define STE_WAKEEVENT_WAKEPKTEVENT      0x10
  245 #define STE_WAKEEVENT_MAGICPKTEVENT     0x20
  246 #define STE_WAKEEVENT_LINKEVENT         0x40
  247 #define STE_WAKEEVENT_WAKEONLAN_ENB     0x80
  248 
  249 #define STE_TXSTATUS_RECLAIMERR         0x02
  250 #define STE_TXSTATUS_STATSOFLOW         0x04
  251 #define STE_TXSTATUS_EXCESSCOLLS        0x08
  252 #define STE_TXSTATUS_UNDERRUN           0x10
  253 #define STE_TXSTATUS_TXINTR_REQ         0x40
  254 #define STE_TXSTATUS_TXDONE             0x80
  255 
  256 #define STE_ISRACK_INTLATCH             0x0001
  257 #define STE_ISRACK_HOSTERR              0x0002
  258 #define STE_ISRACK_TX_DONE              0x0004
  259 #define STE_ISRACK_MACCTL_FRAME         0x0008
  260 #define STE_ISRACK_RX_DONE              0x0010
  261 #define STE_ISRACK_RX_EARLY             0x0020
  262 #define STE_ISRACK_SOFTINTR             0x0040
  263 #define STE_ISRACK_STATS_OFLOW          0x0080
  264 #define STE_ISRACK_LINKEVENT            0x0100
  265 #define STE_ISRACK_TX_DMADONE           0x0200
  266 #define STE_ISRACK_RX_DMADONE           0x0400
  267 
  268 #define STE_IMR_HOSTERR                 0x0002
  269 #define STE_IMR_TX_DONE                 0x0004
  270 #define STE_IMR_MACCTL_FRAME            0x0008
  271 #define STE_IMR_RX_DONE                 0x0010
  272 #define STE_IMR_RX_EARLY                0x0020
  273 #define STE_IMR_SOFTINTR                0x0040
  274 #define STE_IMR_STATS_OFLOW             0x0080
  275 #define STE_IMR_LINKEVENT               0x0100
  276 #define STE_IMR_TX_DMADONE              0x0200
  277 #define STE_IMR_RX_DMADONE              0x0400
  278 
  279 #define STE_INTRS                                       \
  280         (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \
  281         STE_IMR_TX_DONE|STE_IMR_HOSTERR| \
  282         STE_IMR_LINKEVENT)
  283 
  284 #define STE_ISR_INTLATCH                0x0001
  285 #define STE_ISR_HOSTERR                 0x0002
  286 #define STE_ISR_TX_DONE                 0x0004
  287 #define STE_ISR_MACCTL_FRAME            0x0008
  288 #define STE_ISR_RX_DONE                 0x0010
  289 #define STE_ISR_RX_EARLY                0x0020
  290 #define STE_ISR_SOFTINTR                0x0040
  291 #define STE_ISR_STATS_OFLOW             0x0080
  292 #define STE_ISR_LINKEVENT               0x0100
  293 #define STE_ISR_TX_DMADONE              0x0200
  294 #define STE_ISR_RX_DMADONE              0x0400
  295 
  296 /*
  297  * Note: the Sundance manual gives the impression that the's
  298  * only one 32-bit MACCTL register. In fact, there are two
  299  * 16-bit registers side by side, and you have to access them
  300  * separately.
  301  */
  302 #define STE_MACCTL0_IPG                 0x0003
  303 #define STE_MACCTL0_FULLDUPLEX          0x0020
  304 #define STE_MACCTL0_RX_GIANTS           0x0040
  305 #define STE_MACCTL0_FLOWCTL_ENABLE      0x0100
  306 #define STE_MACCTL0_RX_FCS              0x0200
  307 #define STE_MACCTL0_FIFOLOOPBK          0x0400
  308 #define STE_MACCTL0_MACLOOPBK           0x0800
  309 
  310 #define STE_MACCTL1_COLLDETECT          0x0001
  311 #define STE_MACCTL1_CARRSENSE           0x0002
  312 #define STE_MACCTL1_TX_BUSY             0x0004
  313 #define STE_MACCTL1_TX_ERROR            0x0008
  314 #define STE_MACCTL1_STATS_ENABLE        0x0020
  315 #define STE_MACCTL1_STATS_DISABLE       0x0040
  316 #define STE_MACCTL1_STATS_ENABLED       0x0080
  317 #define STE_MACCTL1_TX_ENABLE           0x0100
  318 #define STE_MACCTL1_TX_DISABLE          0x0200
  319 #define STE_MACCTL1_TX_ENABLED          0x0400
  320 #define STE_MACCTL1_RX_ENABLE           0x0800
  321 #define STE_MACCTL1_RX_DISABLE          0x1000
  322 #define STE_MACCTL1_RX_ENABLED          0x2000
  323 #define STE_MACCTL1_PAUSED              0x4000
  324 
  325 #define STE_IPG_96BT                    0x00000000
  326 #define STE_IPG_128BT                   0x00000001
  327 #define STE_IPG_224BT                   0x00000002
  328 #define STE_IPG_544BT                   0x00000003
  329 
  330 #define STE_RXMODE_UNICAST              0x01
  331 #define STE_RXMODE_ALLMULTI             0x02
  332 #define STE_RXMODE_BROADCAST            0x04
  333 #define STE_RXMODE_PROMISC              0x08
  334 #define STE_RXMODE_MULTIHASH            0x10
  335 #define STE_RXMODE_ALLIPMULTI           0x20
  336 
  337 #define STE_PHYCTL_MCLK                 0x01
  338 #define STE_PHYCTL_MDATA                0x02
  339 #define STE_PHYCTL_MDIR                 0x04
  340 #define STE_PHYCTL_CLK25_DISABLE        0x08
  341 #define STE_PHYCTL_DUPLEXPOLARITY       0x10
  342 #define STE_PHYCTL_DUPLEXSTAT           0x20
  343 #define STE_PHYCTL_SPEEDSTAT            0x40
  344 #define STE_PHYCTL_LINKSTAT             0x80
  345 
  346 /*
  347  * EEPROM offsets.
  348  */
  349 #define STE_EEADDR_CONFIGPARM           0x00
  350 #define STE_EEADDR_ASICCTL              0x02
  351 #define STE_EEADDR_SUBSYS_ID            0x04
  352 #define STE_EEADDR_SUBVEN_ID            0x08
  353 
  354 #define STE_EEADDR_NODE0                0x10
  355 #define STE_EEADDR_NODE1                0x12
  356 #define STE_EEADDR_NODE2                0x14
  357 
  358 /* PCI registers */
  359 #define STE_PCI_VENDOR_ID               0x00
  360 #define STE_PCI_DEVICE_ID               0x02
  361 #define STE_PCI_COMMAND                 0x04
  362 #define STE_PCI_STATUS                  0x06
  363 #define STE_PCI_CLASSCODE               0x09
  364 #define STE_PCI_LATENCY_TIMER           0x0D
  365 #define STE_PCI_HEADER_TYPE             0x0E
  366 #define STE_PCI_LOIO                    0x10
  367 #define STE_PCI_LOMEM                   0x14
  368 #define STE_PCI_BIOSROM                 0x30
  369 #define STE_PCI_INTLINE                 0x3C
  370 #define STE_PCI_INTPIN                  0x3D
  371 #define STE_PCI_MINGNT                  0x3E
  372 #define STE_PCI_MINLAT                  0x0F
  373 
  374 #define STE_PCI_CAPID                   0x50 /* 8 bits */
  375 #define STE_PCI_NEXTPTR                 0x51 /* 8 bits */
  376 #define STE_PCI_PWRMGMTCAP              0x52 /* 16 bits */
  377 #define STE_PCI_PWRMGMTCTRL             0x54 /* 16 bits */
  378 
  379 #define STE_PSTATE_MASK                 0x0003
  380 #define STE_PSTATE_D0                   0x0000
  381 #define STE_PSTATE_D1                   0x0002
  382 #define STE_PSTATE_D2                   0x0002
  383 #define STE_PSTATE_D3                   0x0003
  384 #define STE_PME_EN                      0x0010
  385 #define STE_PME_STATUS                  0x8000
  386 
  387 
  388 struct ste_stats {
  389         u_int32_t               ste_rx_bytes;
  390         u_int32_t               ste_tx_bytes;
  391         u_int16_t               ste_tx_frames;
  392         u_int16_t               ste_rx_frames;
  393         u_int8_t                ste_carrsense_errs;
  394         u_int8_t                ste_late_colls;
  395         u_int8_t                ste_multi_colls;
  396         u_int8_t                ste_single_colls;
  397         u_int8_t                ste_tx_frames_defered;
  398         u_int8_t                ste_rx_lost_frames;
  399         u_int8_t                ste_tx_excess_defers;
  400         u_int8_t                ste_tx_abort_excess_colls;
  401         u_int8_t                ste_tx_bcast_frames;
  402         u_int8_t                ste_rx_bcast_frames;
  403         u_int8_t                ste_tx_mcast_frames;
  404         u_int8_t                ste_rx_mcast_frames;
  405 };
  406 
  407 struct ste_frag {
  408         u_int32_t               ste_addr;
  409         u_int32_t               ste_len;
  410 };
  411 
  412 #define STE_FRAG_LAST           0x80000000
  413 #define STE_FRAG_LEN            0x00001FFF
  414 
  415 #define STE_MAXFRAGS    8
  416 
  417 struct ste_desc {
  418         u_int32_t               ste_next;
  419         u_int32_t               ste_ctl;
  420         struct ste_frag         ste_frags[STE_MAXFRAGS];
  421 };
  422 
  423 struct ste_desc_onefrag {
  424         u_int32_t               ste_next;
  425         u_int32_t               ste_status;
  426         struct ste_frag         ste_frag;
  427 };
  428 
  429 #define STE_TXCTL_WORDALIGN     0x00000003
  430 #define STE_TXCTL_FRAMEID       0x000003FC
  431 #define STE_TXCTL_NOCRC         0x00002000
  432 #define STE_TXCTL_TXINTR        0x00008000
  433 #define STE_TXCTL_DMADONE       0x00010000
  434 #define STE_TXCTL_DMAINTR       0x80000000
  435 
  436 #define STE_RXSTAT_FRAMELEN     0x00001FFF
  437 #define STE_RXSTAT_FRAME_ERR    0x00004000
  438 #define STE_RXSTAT_DMADONE      0x00008000
  439 #define STE_RXSTAT_FIFO_OFLOW   0x00010000
  440 #define STE_RXSTAT_RUNT         0x00020000
  441 #define STE_RXSTAT_ALIGNERR     0x00040000
  442 #define STE_RXSTAT_CRCERR       0x00080000
  443 #define STE_RXSTAT_GIANT        0x00100000
  444 #define STE_RXSTAT_DRIBBLEBITS  0x00800000
  445 #define STE_RXSTAT_DMA_OFLOW    0x01000000
  446 #define STE_RXATAT_ONEBUF       0x10000000
  447 
  448 /*
  449  * register space access macros
  450  */
  451 #define CSR_WRITE_4(sc, reg, val)       \
  452         bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val)
  453 #define CSR_WRITE_2(sc, reg, val)       \
  454         bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val)
  455 #define CSR_WRITE_1(sc, reg, val)       \
  456         bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val)
  457 
  458 #define CSR_READ_4(sc, reg)             \
  459         bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg)
  460 #define CSR_READ_2(sc, reg)             \
  461         bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg)
  462 #define CSR_READ_1(sc, reg)             \
  463         bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg)
  464 
  465 #define STE_TIMEOUT             1000
  466 #define STE_MIN_FRAMELEN        60
  467 #define STE_PACKET_SIZE         1536
  468 #define ETHER_ALIGN             2
  469 #define STE_RX_LIST_CNT         64
  470 #define STE_TX_LIST_CNT         128
  471 #define STE_INC(x, y)           (x) = (x + 1) % y
  472 #define STE_NEXT(x, y)          (x + 1) % y
  473 
  474 struct ste_type {
  475         u_int16_t               ste_vid;
  476         u_int16_t               ste_did;
  477         char                    *ste_name;
  478 };
  479 
  480 struct ste_list_data {
  481         struct ste_desc_onefrag ste_rx_list[STE_RX_LIST_CNT];
  482         struct ste_desc         ste_tx_list[STE_TX_LIST_CNT];
  483 };
  484 
  485 struct ste_chain {
  486         struct ste_desc         *ste_ptr;
  487         struct mbuf             *ste_mbuf;
  488         struct ste_chain        *ste_next;
  489         u_int32_t               ste_phys;
  490 };
  491 
  492 struct ste_chain_onefrag {
  493         struct ste_desc_onefrag *ste_ptr;
  494         struct mbuf             *ste_mbuf;
  495         struct ste_chain_onefrag        *ste_next;
  496 };
  497 
  498 struct ste_chain_data {
  499         struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT];
  500         struct ste_chain         ste_tx_chain[STE_TX_LIST_CNT];
  501         struct ste_chain_onefrag *ste_rx_head;
  502 
  503         int                     ste_tx_prod;
  504         int                     ste_tx_cons;
  505 };
  506 
  507 struct ste_softc {
  508         struct ifnet            *ste_ifp;
  509         bus_space_tag_t         ste_btag;
  510         bus_space_handle_t      ste_bhandle;
  511         struct resource         *ste_res;
  512         struct resource         *ste_irq;
  513         void                    *ste_intrhand;
  514         struct ste_type         *ste_info;
  515         device_t                ste_miibus;
  516         device_t                ste_dev;
  517         int                     ste_tx_thresh;
  518         u_int8_t                ste_link;
  519         int                     ste_if_flags;
  520         struct ste_chain        *ste_tx_prev;
  521         struct ste_list_data    *ste_ldata;
  522         struct ste_chain_data   ste_cdata;
  523         struct callout          ste_stat_callout;
  524         struct mtx              ste_mtx;
  525         u_int8_t                ste_one_phy;
  526 #ifdef DEVICE_POLLING
  527         int                     rxcycles;
  528 #endif
  529 };
  530 
  531 #define STE_LOCK(_sc)           mtx_lock(&(_sc)->ste_mtx)
  532 #define STE_UNLOCK(_sc)         mtx_unlock(&(_sc)->ste_mtx)
  533 #define STE_LOCK_ASSERT(_sc)    mtx_assert(&(_sc)->ste_mtx, MA_OWNED)
  534 
  535 struct ste_mii_frame {
  536         u_int8_t                mii_stdelim;
  537         u_int8_t                mii_opcode;
  538         u_int8_t                mii_phyaddr;
  539         u_int8_t                mii_regaddr;
  540         u_int8_t                mii_turnaround;
  541         u_int16_t               mii_data;
  542 };
  543 
  544 /*
  545  * MII constants
  546  */
  547 #define STE_MII_STARTDELIM      0x01
  548 #define STE_MII_READOP          0x02
  549 #define STE_MII_WRITEOP         0x01
  550 #define STE_MII_TURNAROUND      0x02

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