Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_ti.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81 #include "bpfilter.h" 82 #include "vlan.h" 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/socket.h> 91 #include <sys/queue.h> 92 93 #include <net/if.h> 94 #include <net/if_arp.h> 95 #include <net/ethernet.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 99 #if NBPFILTER > 0 100 #include <net/bpf.h> 101 #endif 102 103 #if NVLAN > 0 104 #include <net/if_types.h> 105 #include <net/if_vlan_var.h> 106 #endif 107 108 #include <netinet/in_systm.h> 109 #include <netinet/in.h> 110 #include <netinet/ip.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/clock.h> /* for DELAY */ 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 118 #include <pci/pcireg.h> 119 #include <pci/pcivar.h> 120 121 #include <pci/if_tireg.h> 122 #include <pci/ti_fw.h> 123 #include <pci/ti_fw2.h> 124 125 #ifdef M_HWCKSUM 126 /*#define TI_CSUM_OFFLOAD*/ 127 #endif 128 129 #if !defined(lint) 130 static const char rcsid[] = 131 "$FreeBSD$"; 132 #endif 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 138 static struct ti_type ti_devs[] = { 139 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 140 "Alteon AceNIC Gigabit Ethernet" }, 141 { TC_VENDORID, TC_DEVICEID_3C985, 142 "3Com 3c985-SX Gigabit Ethernet" }, 143 { NG_VENDORID, NG_DEVICEID_GA620, 144 "Netgear GA620 Gigabit Ethernet" }, 145 { SGI_VENDORID, SGI_DEVICEID_TIGON, 146 "Silicon Graphics Gigabit Ethernet" }, 147 { 0, 0, NULL } 148 }; 149 150 static unsigned long ti_count; 151 152 static const char *ti_probe __P((pcici_t, pcidi_t)); 153 static void ti_attach __P((pcici_t, int)); 154 static void ti_txeof __P((struct ti_softc *)); 155 static void ti_rxeof __P((struct ti_softc *)); 156 157 static void ti_stats_update __P((struct ti_softc *)); 158 static int ti_encap __P((struct ti_softc *, struct mbuf *, 159 u_int32_t *)); 160 161 static void ti_intr __P((void *)); 162 static void ti_start __P((struct ifnet *)); 163 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 164 static void ti_init __P((void *)); 165 static void ti_init2 __P((struct ti_softc *)); 166 static void ti_stop __P((struct ti_softc *)); 167 static void ti_watchdog __P((struct ifnet *)); 168 static void ti_shutdown __P((int, void *)); 169 static int ti_ifmedia_upd __P((struct ifnet *)); 170 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 171 172 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 173 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 174 int, u_int8_t *)); 175 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 176 177 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 178 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 179 static void ti_setmulti __P((struct ti_softc *)); 180 181 static void ti_mem __P((struct ti_softc *, u_int32_t, 182 u_int32_t, caddr_t)); 183 static void ti_loadfw __P((struct ti_softc *)); 184 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 185 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 186 caddr_t, int)); 187 static void ti_handle_events __P((struct ti_softc *)); 188 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 189 static void *ti_jalloc __P((struct ti_softc *)); 190 static void ti_jfree __P((caddr_t, u_int)); 191 static void ti_jref __P((caddr_t, u_int)); 192 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 193 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 194 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 195 static int ti_init_rx_ring_std __P((struct ti_softc *)); 196 static void ti_free_rx_ring_std __P((struct ti_softc *)); 197 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 198 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 199 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 200 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 201 static void ti_free_tx_ring __P((struct ti_softc *)); 202 static int ti_init_tx_ring __P((struct ti_softc *)); 203 204 static int ti_64bitslot_war __P((struct ti_softc *)); 205 static int ti_chipinit __P((struct ti_softc *)); 206 static int ti_gibinit __P((struct ti_softc *)); 207 208 /* 209 * Send an instruction or address to the EEPROM, check for ACK. 210 */ 211 static u_int32_t ti_eeprom_putbyte(sc, byte) 212 struct ti_softc *sc; 213 int byte; 214 { 215 register int i, ack = 0; 216 217 /* 218 * Make sure we're in TX mode. 219 */ 220 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 221 222 /* 223 * Feed in each bit and stobe the clock. 224 */ 225 for (i = 0x80; i; i >>= 1) { 226 if (byte & i) { 227 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 228 } else { 229 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 230 } 231 DELAY(1); 232 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 233 DELAY(1); 234 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 235 } 236 237 /* 238 * Turn off TX mode. 239 */ 240 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 241 242 /* 243 * Check for ack. 244 */ 245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 246 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 248 249 return(ack); 250 } 251 252 /* 253 * Read a byte of data stored in the EEPROM at address 'addr.' 254 * We have to send two address bytes since the EEPROM can hold 255 * more than 256 bytes of data. 256 */ 257 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 258 struct ti_softc *sc; 259 int addr; 260 u_int8_t *dest; 261 { 262 register int i; 263 u_int8_t byte = 0; 264 265 EEPROM_START; 266 267 /* 268 * Send write control code to EEPROM. 269 */ 270 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 271 printf("ti%d: failed to send write command, status: %x\n", 272 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 273 return(1); 274 } 275 276 /* 277 * Send first byte of address of byte we want to read. 278 */ 279 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 280 printf("ti%d: failed to send address, status: %x\n", 281 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 282 return(1); 283 } 284 /* 285 * Send second byte address of byte we want to read. 286 */ 287 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 288 printf("ti%d: failed to send address, status: %x\n", 289 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 290 return(1); 291 } 292 293 EEPROM_STOP; 294 EEPROM_START; 295 /* 296 * Send read control code to EEPROM. 297 */ 298 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 299 printf("ti%d: failed to send read command, status: %x\n", 300 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 301 return(1); 302 } 303 304 /* 305 * Start reading bits from EEPROM. 306 */ 307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 308 for (i = 0x80; i; i >>= 1) { 309 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 DELAY(1); 311 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 312 byte |= i; 313 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 314 DELAY(1); 315 } 316 317 EEPROM_STOP; 318 319 /* 320 * No ACK generated for read, so just return byte. 321 */ 322 323 *dest = byte; 324 325 return(0); 326 } 327 328 /* 329 * Read a sequence of bytes from the EEPROM. 330 */ 331 static int ti_read_eeprom(sc, dest, off, cnt) 332 struct ti_softc *sc; 333 caddr_t dest; 334 int off; 335 int cnt; 336 { 337 int err = 0, i; 338 u_int8_t byte = 0; 339 340 for (i = 0; i < cnt; i++) { 341 err = ti_eeprom_getbyte(sc, off + i, &byte); 342 if (err) 343 break; 344 *(dest + i) = byte; 345 } 346 347 return(err ? 1 : 0); 348 } 349 350 /* 351 * NIC memory access function. Can be used to either clear a section 352 * of NIC local memory or (if buf is non-NULL) copy data into it. 353 */ 354 static void ti_mem(sc, addr, len, buf) 355 struct ti_softc *sc; 356 u_int32_t addr, len; 357 caddr_t buf; 358 { 359 int segptr, segsize, cnt; 360 caddr_t ti_winbase, ptr; 361 362 segptr = addr; 363 cnt = len; 364 #ifdef __i386__ 365 ti_winbase = (caddr_t)(sc->ti_bhandle + TI_WINDOW); 366 #endif 367 #ifdef __alpha__ 368 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 369 #endif 370 ptr = buf; 371 372 while(cnt) { 373 if (cnt < TI_WINLEN) 374 segsize = cnt; 375 else 376 segsize = TI_WINLEN - (segptr % TI_WINLEN); 377 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 378 if (buf == NULL) 379 bzero((char *)ti_winbase + (segptr & 380 (TI_WINLEN - 1)), segsize); 381 else { 382 bcopy((char *)ptr, (char *)ti_winbase + 383 (segptr & (TI_WINLEN - 1)), segsize); 384 ptr += segsize; 385 } 386 segptr += segsize; 387 cnt -= segsize; 388 } 389 390 return; 391 } 392 393 /* 394 * Load firmware image into the NIC. Check that the firmware revision 395 * is acceptable and see if we want the firmware for the Tigon 1 or 396 * Tigon 2. 397 */ 398 static void ti_loadfw(sc) 399 struct ti_softc *sc; 400 { 401 switch(sc->ti_hwrev) { 402 case TI_HWREV_TIGON: 403 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 404 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 405 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 406 printf("ti%d: firmware revision mismatch; want " 407 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 408 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 409 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 410 tigonFwReleaseMinor, tigonFwReleaseFix); 411 return; 412 } 413 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 414 (caddr_t)tigonFwText); 415 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 416 (caddr_t)tigonFwData); 417 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 418 (caddr_t)tigonFwRodata); 419 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 420 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 421 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 422 break; 423 case TI_HWREV_TIGON_II: 424 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 425 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 426 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 427 printf("ti%d: firmware revision mismatch; want " 428 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 429 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 430 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 431 tigon2FwReleaseMinor, tigon2FwReleaseFix); 432 return; 433 } 434 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 435 (caddr_t)tigon2FwText); 436 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 437 (caddr_t)tigon2FwData); 438 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 439 (caddr_t)tigon2FwRodata); 440 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 441 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 442 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 443 break; 444 default: 445 printf("ti%d: can't load firmware: unknown hardware rev\n", 446 sc->ti_unit); 447 break; 448 } 449 450 return; 451 } 452 453 /* 454 * Send the NIC a command via the command ring. 455 */ 456 static void ti_cmd(sc, cmd) 457 struct ti_softc *sc; 458 struct ti_cmd_desc *cmd; 459 { 460 u_int32_t index; 461 462 if (sc->ti_rdata->ti_cmd_ring == NULL) 463 return; 464 465 index = sc->ti_cmd_saved_prodidx; 466 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 467 TI_INC(index, TI_CMD_RING_CNT); 468 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 469 sc->ti_cmd_saved_prodidx = index; 470 471 return; 472 } 473 474 /* 475 * Send the NIC an extended command. The 'len' parameter specifies the 476 * number of command slots to include after the initial command. 477 */ 478 static void ti_cmd_ext(sc, cmd, arg, len) 479 struct ti_softc *sc; 480 struct ti_cmd_desc *cmd; 481 caddr_t arg; 482 int len; 483 { 484 u_int32_t index; 485 register int i; 486 487 if (sc->ti_rdata->ti_cmd_ring == NULL) 488 return; 489 490 index = sc->ti_cmd_saved_prodidx; 491 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 492 TI_INC(index, TI_CMD_RING_CNT); 493 for (i = 0; i < len; i++) { 494 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 495 *(u_int32_t *)(&arg[i * 4])); 496 TI_INC(index, TI_CMD_RING_CNT); 497 } 498 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 499 sc->ti_cmd_saved_prodidx = index; 500 501 return; 502 } 503 504 /* 505 * Handle events that have triggered interrupts. 506 */ 507 static void ti_handle_events(sc) 508 struct ti_softc *sc; 509 { 510 struct ti_event_desc *e; 511 512 if (sc->ti_rdata->ti_event_ring == NULL) 513 return; 514 515 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 516 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 517 switch(e->ti_event) { 518 case TI_EV_LINKSTAT_CHANGED: 519 sc->ti_linkstat = e->ti_code; 520 if (e->ti_code == TI_EV_CODE_LINK_UP) 521 printf("ti%d: 10/100 link up\n", sc->ti_unit); 522 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 523 printf("ti%d: gigabit link up\n", sc->ti_unit); 524 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 525 printf("ti%d: link down\n", sc->ti_unit); 526 break; 527 case TI_EV_ERROR: 528 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 529 printf("ti%d: invalid command\n", sc->ti_unit); 530 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 531 printf("ti%d: unknown command\n", sc->ti_unit); 532 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 533 printf("ti%d: bad config data\n", sc->ti_unit); 534 break; 535 case TI_EV_FIRMWARE_UP: 536 ti_init2(sc); 537 break; 538 case TI_EV_STATS_UPDATED: 539 ti_stats_update(sc); 540 break; 541 case TI_EV_RESET_JUMBO_RING: 542 case TI_EV_MCAST_UPDATED: 543 /* Who cares. */ 544 break; 545 default: 546 printf("ti%d: unknown event: %d\n", 547 sc->ti_unit, e->ti_event); 548 break; 549 } 550 /* Advance the consumer index. */ 551 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 552 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 553 } 554 555 return; 556 } 557 558 /* 559 * Memory management for the jumbo receive ring is a pain in the 560 * butt. We need to allocate at least 9018 bytes of space per frame, 561 * _and_ it has to be contiguous (unless you use the extended 562 * jumbo descriptor format). Using malloc() all the time won't 563 * work: malloc() allocates memory in powers of two, which means we 564 * would end up wasting a considerable amount of space by allocating 565 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 566 * to do our own memory management. 567 * 568 * The driver needs to allocate a contiguous chunk of memory at boot 569 * time. We then chop this up ourselves into 9K pieces and use them 570 * as external mbuf storage. 571 * 572 * One issue here is how much memory to allocate. The jumbo ring has 573 * 256 slots in it, but at 9K per slot than can consume over 2MB of 574 * RAM. This is a bit much, especially considering we also need 575 * RAM for the standard ring and mini ring (on the Tigon 2). To 576 * save space, we only actually allocate enough memory for 64 slots 577 * by default, which works out to between 500 and 600K. This can 578 * be tuned by changing a #define in if_tireg.h. 579 */ 580 581 static int ti_alloc_jumbo_mem(sc) 582 struct ti_softc *sc; 583 { 584 caddr_t ptr; 585 register int i; 586 struct ti_jpool_entry *entry; 587 588 /* Grab a big chunk o' storage. */ 589 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 590 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 591 592 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 593 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 594 return(ENOBUFS); 595 } 596 597 SLIST_INIT(&sc->ti_jfree_listhead); 598 SLIST_INIT(&sc->ti_jinuse_listhead); 599 600 /* 601 * Now divide it up into 9K pieces and save the addresses 602 * in an array. Note that we play an evil trick here by using 603 * the first few bytes in the buffer to hold the the address 604 * of the softc structure for this interface. This is because 605 * ti_jfree() needs it, but it is called by the mbuf management 606 * code which will not pass it to us explicitly. 607 */ 608 ptr = sc->ti_cdata.ti_jumbo_buf; 609 for (i = 0; i < TI_JSLOTS; i++) { 610 u_int64_t **aptr; 611 aptr = (u_int64_t **)ptr; 612 aptr[0] = (u_int64_t *)sc; 613 ptr += sizeof(u_int64_t); 614 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 615 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 616 ptr += (TI_JLEN - sizeof(u_int64_t)); 617 entry = malloc(sizeof(struct ti_jpool_entry), 618 M_DEVBUF, M_NOWAIT); 619 if (entry == NULL) { 620 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 621 sc->ti_cdata.ti_jumbo_buf = NULL; 622 printf("ti%d: no memory for jumbo " 623 "buffer queue!\n", sc->ti_unit); 624 return(ENOBUFS); 625 } 626 entry->slot = i; 627 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 628 } 629 630 return(0); 631 } 632 633 /* 634 * Allocate a jumbo buffer. 635 */ 636 static void *ti_jalloc(sc) 637 struct ti_softc *sc; 638 { 639 struct ti_jpool_entry *entry; 640 641 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 642 643 if (entry == NULL) { 644 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 645 return(NULL); 646 } 647 648 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 649 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 650 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 651 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 652 } 653 654 /* 655 * Adjust usage count on a jumbo buffer. In general this doesn't 656 * get used much because our jumbo buffers don't get passed around 657 * too much, but it's implemented for correctness. 658 */ 659 static void ti_jref(buf, size) 660 caddr_t buf; 661 u_int size; 662 { 663 struct ti_softc *sc; 664 u_int64_t **aptr; 665 register int i; 666 667 /* Extract the softc struct pointer. */ 668 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 669 sc = (struct ti_softc *)(aptr[0]); 670 671 if (sc == NULL) 672 panic("ti_jref: can't find softc pointer!"); 673 674 if (size != TI_JUMBO_FRAMELEN) 675 panic("ti_jref: adjusting refcount of buf of wrong size!"); 676 677 /* calculate the slot this buffer belongs to */ 678 679 i = ((vm_offset_t)aptr 680 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 681 682 if ((i < 0) || (i >= TI_JSLOTS)) 683 panic("ti_jref: asked to reference buffer " 684 "that we don't manage!"); 685 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 686 panic("ti_jref: buffer already free!"); 687 else 688 sc->ti_cdata.ti_jslots[i].ti_inuse++; 689 690 return; 691 } 692 693 /* 694 * Release a jumbo buffer. 695 */ 696 static void ti_jfree(buf, size) 697 caddr_t buf; 698 u_int size; 699 { 700 struct ti_softc *sc; 701 u_int64_t **aptr; 702 int i; 703 struct ti_jpool_entry *entry; 704 705 /* Extract the softc struct pointer. */ 706 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 707 sc = (struct ti_softc *)(aptr[0]); 708 709 if (sc == NULL) 710 panic("ti_jfree: can't find softc pointer!"); 711 712 if (size != TI_JUMBO_FRAMELEN) 713 panic("ti_jfree: freeing buffer of wrong size!"); 714 715 /* calculate the slot this buffer belongs to */ 716 717 i = ((vm_offset_t)aptr 718 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 719 720 if ((i < 0) || (i >= TI_JSLOTS)) 721 panic("ti_jfree: asked to free buffer that we don't manage!"); 722 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 723 panic("ti_jfree: buffer already free!"); 724 else { 725 sc->ti_cdata.ti_jslots[i].ti_inuse--; 726 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 727 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 728 if (entry == NULL) 729 panic("ti_jfree: buffer not in use!"); 730 entry->slot = i; 731 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 732 jpool_entries); 733 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 734 entry, jpool_entries); 735 } 736 } 737 738 return; 739 } 740 741 742 /* 743 * Intialize a standard receive ring descriptor. 744 */ 745 static int ti_newbuf_std(sc, i, m) 746 struct ti_softc *sc; 747 int i; 748 struct mbuf *m; 749 { 750 struct mbuf *m_new = NULL; 751 struct ti_rx_desc *r; 752 753 if (m == NULL) { 754 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 755 if (m_new == NULL) { 756 printf("ti%d: mbuf allocation failed " 757 "-- packet dropped!\n", sc->ti_unit); 758 return(ENOBUFS); 759 } 760 761 MCLGET(m_new, M_DONTWAIT); 762 if (!(m_new->m_flags & M_EXT)) { 763 printf("ti%d: cluster allocation failed " 764 "-- packet dropped!\n", sc->ti_unit); 765 m_freem(m_new); 766 return(ENOBUFS); 767 } 768 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 769 } else { 770 m_new = m; 771 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 772 m_new->m_data = m_new->m_ext.ext_buf; 773 } 774 775 m_adj(m_new, ETHER_ALIGN); 776 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 777 r = &sc->ti_rdata->ti_rx_std_ring[i]; 778 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 779 r->ti_type = TI_BDTYPE_RECV_BD; 780 #ifdef TI_CSUM_OFFLOAD 781 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 782 #else 783 r->ti_flags = 0; 784 #endif 785 r->ti_len = m_new->m_len; 786 r->ti_idx = i; 787 788 return(0); 789 } 790 791 /* 792 * Intialize a mini receive ring descriptor. This only applies to 793 * the Tigon 2. 794 */ 795 static int ti_newbuf_mini(sc, i, m) 796 struct ti_softc *sc; 797 int i; 798 struct mbuf *m; 799 { 800 struct mbuf *m_new = NULL; 801 struct ti_rx_desc *r; 802 803 if (m == NULL) { 804 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 805 if (m_new == NULL) { 806 printf("ti%d: mbuf allocation failed " 807 "-- packet dropped!\n", sc->ti_unit); 808 return(ENOBUFS); 809 } 810 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 811 } else { 812 m_new = m; 813 m_new->m_data = m_new->m_pktdat; 814 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 815 } 816 817 m_adj(m_new, ETHER_ALIGN); 818 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 819 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 820 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 821 r->ti_type = TI_BDTYPE_RECV_BD; 822 r->ti_flags = TI_BDFLAG_MINI_RING; 823 #ifdef TI_CSUM_OFFLOAD 824 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 825 #endif 826 r->ti_len = m_new->m_len; 827 r->ti_idx = i; 828 829 return(0); 830 } 831 832 /* 833 * Initialize a jumbo receive ring descriptor. This allocates 834 * a jumbo buffer from the pool managed internally by the driver. 835 */ 836 static int ti_newbuf_jumbo(sc, i, m) 837 struct ti_softc *sc; 838 int i; 839 struct mbuf *m; 840 { 841 struct mbuf *m_new = NULL; 842 struct ti_rx_desc *r; 843 844 if (m == NULL) { 845 caddr_t *buf = NULL; 846 847 /* Allocate the mbuf. */ 848 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 849 if (m_new == NULL) { 850 printf("ti%d: mbuf allocation failed " 851 "-- packet dropped!\n", sc->ti_unit); 852 return(ENOBUFS); 853 } 854 855 /* Allocate the jumbo buffer */ 856 buf = ti_jalloc(sc); 857 if (buf == NULL) { 858 m_freem(m_new); 859 printf("ti%d: jumbo allocation failed " 860 "-- packet dropped!\n", sc->ti_unit); 861 return(ENOBUFS); 862 } 863 864 /* Attach the buffer to the mbuf. */ 865 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 866 m_new->m_flags |= M_EXT; 867 m_new->m_len = m_new->m_pkthdr.len = 868 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 869 m_new->m_ext.ext_free = ti_jfree; 870 m_new->m_ext.ext_ref = ti_jref; 871 } else { 872 m_new = m; 873 m_new->m_data = m_new->m_ext.ext_buf; 874 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 875 } 876 877 m_adj(m_new, ETHER_ALIGN); 878 /* Set up the descriptor. */ 879 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 880 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 881 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 882 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 883 r->ti_flags = TI_BDFLAG_JUMBO_RING; 884 #ifdef TI_CSUM_OFFLOAD 885 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 886 #endif 887 r->ti_len = m_new->m_len; 888 r->ti_idx = i; 889 890 return(0); 891 } 892 893 /* 894 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 895 * that's 1MB or memory, which is a lot. For now, we fill only the first 896 * 256 ring entries and hope that our CPU is fast enough to keep up with 897 * the NIC. 898 */ 899 static int ti_init_rx_ring_std(sc) 900 struct ti_softc *sc; 901 { 902 register int i; 903 struct ti_cmd_desc cmd; 904 905 for (i = 0; i < TI_SSLOTS; i++) { 906 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 907 return(ENOBUFS); 908 }; 909 910 TI_UPDATE_STDPROD(sc, i - 1); 911 sc->ti_std = i - 1; 912 913 return(0); 914 } 915 916 static void ti_free_rx_ring_std(sc) 917 struct ti_softc *sc; 918 { 919 register int i; 920 921 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 922 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 923 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 924 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 925 } 926 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 927 sizeof(struct ti_rx_desc)); 928 } 929 930 return; 931 } 932 933 static int ti_init_rx_ring_jumbo(sc) 934 struct ti_softc *sc; 935 { 936 register int i; 937 struct ti_cmd_desc cmd; 938 939 for (i = 0; i < (TI_JSLOTS - 20); i++) { 940 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 941 return(ENOBUFS); 942 }; 943 944 TI_UPDATE_JUMBOPROD(sc, i - 1); 945 sc->ti_jumbo = i - 1; 946 947 return(0); 948 } 949 950 static void ti_free_rx_ring_jumbo(sc) 951 struct ti_softc *sc; 952 { 953 register int i; 954 955 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 956 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 957 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 958 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 959 } 960 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 961 sizeof(struct ti_rx_desc)); 962 } 963 964 return; 965 } 966 967 static int ti_init_rx_ring_mini(sc) 968 struct ti_softc *sc; 969 { 970 register int i; 971 972 for (i = 0; i < TI_MSLOTS; i++) { 973 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 974 return(ENOBUFS); 975 }; 976 977 TI_UPDATE_MINIPROD(sc, i - 1); 978 sc->ti_mini = i - 1; 979 980 return(0); 981 } 982 983 static void ti_free_rx_ring_mini(sc) 984 struct ti_softc *sc; 985 { 986 register int i; 987 988 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 989 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 990 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 991 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 992 } 993 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 994 sizeof(struct ti_rx_desc)); 995 } 996 997 return; 998 } 999 1000 static void ti_free_tx_ring(sc) 1001 struct ti_softc *sc; 1002 { 1003 register int i; 1004 1005 if (sc->ti_rdata->ti_tx_ring == NULL) 1006 return; 1007 1008 for (i = 0; i < TI_TX_RING_CNT; i++) { 1009 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1010 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1011 sc->ti_cdata.ti_tx_chain[i] = NULL; 1012 } 1013 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1014 sizeof(struct ti_tx_desc)); 1015 } 1016 1017 return; 1018 } 1019 1020 static int ti_init_tx_ring(sc) 1021 struct ti_softc *sc; 1022 { 1023 sc->ti_txcnt = 0; 1024 sc->ti_tx_saved_considx = 0; 1025 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1026 return(0); 1027 } 1028 1029 /* 1030 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1031 * but we have to support the old way too so that Tigon 1 cards will 1032 * work. 1033 */ 1034 void ti_add_mcast(sc, addr) 1035 struct ti_softc *sc; 1036 struct ether_addr *addr; 1037 { 1038 struct ti_cmd_desc cmd; 1039 u_int16_t *m; 1040 u_int32_t ext[2] = {0, 0}; 1041 1042 m = (u_int16_t *)&addr->octet[0]; 1043 1044 switch(sc->ti_hwrev) { 1045 case TI_HWREV_TIGON: 1046 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1047 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1048 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1049 break; 1050 case TI_HWREV_TIGON_II: 1051 ext[0] = htons(m[0]); 1052 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1053 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1054 break; 1055 default: 1056 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1057 break; 1058 } 1059 1060 return; 1061 } 1062 1063 void ti_del_mcast(sc, addr) 1064 struct ti_softc *sc; 1065 struct ether_addr *addr; 1066 { 1067 struct ti_cmd_desc cmd; 1068 u_int16_t *m; 1069 u_int32_t ext[2] = {0, 0}; 1070 1071 m = (u_int16_t *)&addr->octet[0]; 1072 1073 switch(sc->ti_hwrev) { 1074 case TI_HWREV_TIGON: 1075 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1076 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1077 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1078 break; 1079 case TI_HWREV_TIGON_II: 1080 ext[0] = htons(m[0]); 1081 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1082 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1083 break; 1084 default: 1085 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1086 break; 1087 } 1088 1089 return; 1090 } 1091 1092 /* 1093 * Configure the Tigon's multicast address filter. 1094 * 1095 * The actual multicast table management is a bit of a pain, thanks to 1096 * slight brain damage on the part of both Alteon and us. With our 1097 * multicast code, we are only alerted when the multicast address table 1098 * changes and at that point we only have the current list of addresses: 1099 * we only know the current state, not the previous state, so we don't 1100 * actually know what addresses were removed or added. The firmware has 1101 * state, but we can't get our grubby mits on it, and there is no 'delete 1102 * all multicast addresses' command. Hence, we have to maintain our own 1103 * state so we know what addresses have been programmed into the NIC at 1104 * any given time. 1105 */ 1106 static void ti_setmulti(sc) 1107 struct ti_softc *sc; 1108 { 1109 struct ifnet *ifp; 1110 struct ifmultiaddr *ifma; 1111 struct ti_cmd_desc cmd; 1112 struct ti_mc_entry *mc; 1113 u_int32_t intrs; 1114 1115 ifp = &sc->arpcom.ac_if; 1116 1117 if (ifp->if_flags & IFF_ALLMULTI) { 1118 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1119 return; 1120 } else { 1121 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1122 } 1123 1124 /* Disable interrupts. */ 1125 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1126 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1127 1128 /* First, zot all the existing filters. */ 1129 while (sc->ti_mc_listhead.slh_first != NULL) { 1130 mc = sc->ti_mc_listhead.slh_first; 1131 ti_del_mcast(sc, &mc->mc_addr); 1132 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1133 free(mc, M_DEVBUF); 1134 } 1135 1136 /* Now program new ones. */ 1137 for (ifma = ifp->if_multiaddrs.lh_first; 1138 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1139 if (ifma->ifma_addr->sa_family != AF_LINK) 1140 continue; 1141 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1142 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1143 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1144 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1145 ti_add_mcast(sc, &mc->mc_addr); 1146 } 1147 1148 /* Re-enable interrupts. */ 1149 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1150 1151 return; 1152 } 1153 1154 /* 1155 * Check to see if the BIOS has configured us for a 64 bit slot when 1156 * we aren't actually in one. If we detect this condition, we can work 1157 * around it on the Tigon 2 by setting a bit in the PCI state register, 1158 * but for the Tigon 1 we must give up and abort the interface attach. 1159 */ 1160 static int ti_64bitslot_war(sc) 1161 struct ti_softc *sc; 1162 { 1163 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1164 CSR_WRITE_4(sc, 0x600, 0); 1165 CSR_WRITE_4(sc, 0x604, 0); 1166 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1167 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1168 if (sc->ti_hwrev == TI_HWREV_TIGON) 1169 return(EINVAL); 1170 else { 1171 TI_SETBIT(sc, TI_PCI_STATE, 1172 TI_PCISTATE_32BIT_BUS); 1173 return(0); 1174 } 1175 } 1176 } 1177 1178 return(0); 1179 } 1180 1181 /* 1182 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1183 * self-test results. 1184 */ 1185 static int ti_chipinit(sc) 1186 struct ti_softc *sc; 1187 { 1188 u_int32_t cacheline; 1189 u_int32_t pci_writemax = 0; 1190 1191 /* Initialize link to down state. */ 1192 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1193 1194 /* Set endianness before we access any non-PCI registers. */ 1195 #if BYTE_ORDER == BIG_ENDIAN 1196 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1197 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1198 #else 1199 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1200 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1201 #endif 1202 1203 /* Check the ROM failed bit to see if self-tests passed. */ 1204 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1205 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1206 return(ENODEV); 1207 } 1208 1209 /* Halt the CPU. */ 1210 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1211 1212 /* Figure out the hardware revision. */ 1213 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1214 case TI_REV_TIGON_I: 1215 sc->ti_hwrev = TI_HWREV_TIGON; 1216 break; 1217 case TI_REV_TIGON_II: 1218 sc->ti_hwrev = TI_HWREV_TIGON_II; 1219 break; 1220 default: 1221 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1222 return(ENODEV); 1223 } 1224 1225 /* Do special setup for Tigon 2. */ 1226 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1227 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1228 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1229 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1230 } 1231 1232 /* Set up the PCI state register. */ 1233 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1234 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1235 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1236 } 1237 1238 /* Clear the read/write max DMA parameters. */ 1239 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1240 TI_PCISTATE_READ_MAXDMA)); 1241 1242 /* Get cache line size. */ 1243 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1244 1245 /* 1246 * If the system has set enabled the PCI memory write 1247 * and invalidate command in the command register, set 1248 * the write max parameter accordingly. This is necessary 1249 * to use MWI with the Tigon 2. 1250 */ 1251 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1252 switch(cacheline) { 1253 case 1: 1254 case 4: 1255 case 8: 1256 case 16: 1257 case 32: 1258 case 64: 1259 break; 1260 default: 1261 /* Disable PCI memory write and invalidate. */ 1262 if (bootverbose) 1263 printf("ti%d: cache line size %d not " 1264 "supported; disabling PCI MWI\n", 1265 sc->ti_unit, cacheline); 1266 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1267 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1268 break; 1269 } 1270 } 1271 1272 #ifdef __brokenalpha__ 1273 /* 1274 * From the Alteon sample driver: 1275 * Must insure that we do not cross an 8K (bytes) boundary 1276 * for DMA reads. Our highest limit is 1K bytes. This is a 1277 * restriction on some ALPHA platforms with early revision 1278 * 21174 PCI chipsets, such as the AlphaPC 164lx 1279 */ 1280 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1281 #else 1282 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1283 #endif 1284 1285 /* This sets the min dma param all the way up (0xff). */ 1286 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1287 1288 /* Configure DMA variables. */ 1289 #if BYTE_ORDER == BIG_ENDIAN 1290 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1291 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1292 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1293 TI_OPMODE_DONT_FRAG_JUMBO); 1294 #else 1295 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1296 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1297 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1298 #endif 1299 1300 /* 1301 * Only allow 1 DMA channel to be active at a time. 1302 * I don't think this is a good idea, but without it 1303 * the firmware racks up lots of nicDmaReadRingFull 1304 * errors. 1305 */ 1306 #ifndef TI_CSUM_OFFLOAD 1307 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1308 #endif 1309 1310 /* Recommended settings from Tigon manual. */ 1311 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1312 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1313 1314 if (ti_64bitslot_war(sc)) { 1315 printf("ti%d: bios thinks we're in a 64 bit slot, " 1316 "but we aren't", sc->ti_unit); 1317 return(EINVAL); 1318 } 1319 1320 return(0); 1321 } 1322 1323 /* 1324 * Initialize the general information block and firmware, and 1325 * start the CPU(s) running. 1326 */ 1327 static int ti_gibinit(sc) 1328 struct ti_softc *sc; 1329 { 1330 struct ti_rcb *rcb; 1331 int i; 1332 struct ifnet *ifp; 1333 1334 ifp = &sc->arpcom.ac_if; 1335 1336 /* Disable interrupts for now. */ 1337 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1338 1339 /* Tell the chip where to find the general information block. */ 1340 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1341 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1342 1343 /* Load the firmware into SRAM. */ 1344 ti_loadfw(sc); 1345 1346 /* Set up the contents of the general info and ring control blocks. */ 1347 1348 /* Set up the event ring and producer pointer. */ 1349 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1350 1351 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1352 rcb->ti_flags = 0; 1353 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1354 vtophys(&sc->ti_ev_prodidx); 1355 sc->ti_ev_prodidx.ti_idx = 0; 1356 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1357 sc->ti_ev_saved_considx = 0; 1358 1359 /* Set up the command ring and producer mailbox. */ 1360 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1361 1362 #ifdef __i386__ 1363 sc->ti_rdata->ti_cmd_ring = 1364 (struct ti_cmd_desc *)(sc->ti_bhandle + TI_GCR_CMDRING); 1365 #endif 1366 #ifdef __alpha__ 1367 sc->ti_rdata->ti_cmd_ring = 1368 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1369 #endif 1370 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1371 rcb->ti_flags = 0; 1372 rcb->ti_max_len = 0; 1373 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1374 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1375 } 1376 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1377 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1378 sc->ti_cmd_saved_prodidx = 0; 1379 1380 /* 1381 * Assign the address of the stats refresh buffer. 1382 * We re-use the current stats buffer for this to 1383 * conserve memory. 1384 */ 1385 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1386 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1387 1388 /* Set up the standard receive ring. */ 1389 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1390 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1391 rcb->ti_max_len = TI_FRAMELEN; 1392 rcb->ti_flags = 0; 1393 #ifdef TI_CSUM_OFFLOAD 1394 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1395 #endif 1396 #if NVLAN > 0 1397 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1398 #endif 1399 1400 /* Set up the jumbo receive ring. */ 1401 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1402 TI_HOSTADDR(rcb->ti_hostaddr) = 1403 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1404 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1405 rcb->ti_flags = 0; 1406 #ifdef TI_CSUM_OFFLOAD 1407 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1408 #endif 1409 #if NVLAN > 0 1410 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1411 #endif 1412 1413 /* 1414 * Set up the mini ring. Only activated on the 1415 * Tigon 2 but the slot in the config block is 1416 * still there on the Tigon 1. 1417 */ 1418 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1419 TI_HOSTADDR(rcb->ti_hostaddr) = 1420 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1421 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1422 if (sc->ti_hwrev == TI_HWREV_TIGON) 1423 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1424 else 1425 rcb->ti_flags = 0; 1426 #ifdef TI_CSUM_OFFLOAD 1427 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1428 #endif 1429 #if NVLAN > 0 1430 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1431 #endif 1432 1433 /* 1434 * Set up the receive return ring. 1435 */ 1436 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1437 TI_HOSTADDR(rcb->ti_hostaddr) = 1438 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1439 rcb->ti_flags = 0; 1440 rcb->ti_max_len = TI_RETURN_RING_CNT; 1441 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1442 vtophys(&sc->ti_return_prodidx); 1443 1444 /* 1445 * Set up the tx ring. Note: for the Tigon 2, we have the option 1446 * of putting the transmit ring in the host's address space and 1447 * letting the chip DMA it instead of leaving the ring in the NIC's 1448 * memory and accessing it through the shared memory region. We 1449 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1450 * so we have to revert to the shared memory scheme if we detect 1451 * a Tigon 1 chip. 1452 */ 1453 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1454 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1455 #ifdef __i386__ 1456 sc->ti_rdata->ti_tx_ring_nic = 1457 (struct ti_tx_desc *)(sc->ti_bhandle + TI_WINDOW); 1458 #endif 1459 #ifdef __alpha__ 1460 sc->ti_rdata->ti_tx_ring_nic = 1461 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1462 #endif 1463 } 1464 bzero((char *)sc->ti_rdata->ti_tx_ring, 1465 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1466 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1467 if (sc->ti_hwrev == TI_HWREV_TIGON) 1468 rcb->ti_flags = 0; 1469 else 1470 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1471 #if NVLAN > 0 1472 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1473 #endif 1474 rcb->ti_max_len = TI_TX_RING_CNT; 1475 if (sc->ti_hwrev == TI_HWREV_TIGON) 1476 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1477 else 1478 TI_HOSTADDR(rcb->ti_hostaddr) = 1479 vtophys(&sc->ti_rdata->ti_tx_ring); 1480 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1481 vtophys(&sc->ti_tx_considx); 1482 1483 /* Set up tuneables */ 1484 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1485 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1486 (sc->ti_rx_coal_ticks / 10)); 1487 else 1488 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1489 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1490 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1491 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1492 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1493 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1494 1495 /* Turn interrupts on. */ 1496 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1497 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1498 1499 /* Start CPU. */ 1500 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1501 1502 return(0); 1503 } 1504 1505 /* 1506 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1507 * against our list and return its name if we find a match. 1508 */ 1509 static const char * 1510 ti_probe(config_id, device_id) 1511 pcici_t config_id; 1512 pcidi_t device_id; 1513 { 1514 struct ti_type *t; 1515 1516 t = ti_devs; 1517 1518 while(t->ti_name != NULL) { 1519 if ((device_id & 0xFFFF) == t->ti_vid && 1520 ((device_id >> 16) & 0xFFFF) == t->ti_did) 1521 return(t->ti_name); 1522 t++; 1523 } 1524 1525 return(NULL); 1526 } 1527 1528 1529 static void 1530 ti_attach(config_id, unit) 1531 pcici_t config_id; 1532 int unit; 1533 { 1534 vm_offset_t pbase, vbase; 1535 int s; 1536 u_int32_t command; 1537 struct ifnet *ifp; 1538 struct ti_softc *sc; 1539 1540 s = splimp(); 1541 1542 /* First, allocate memory for the softc struct. */ 1543 sc = malloc(sizeof(struct ti_softc), M_DEVBUF, M_NOWAIT); 1544 if (sc == NULL) { 1545 printf("ti%d: no memory for softc struct!\n", unit); 1546 goto fail; 1547 } 1548 1549 bzero(sc, sizeof(struct ti_softc)); 1550 1551 /* 1552 * Map control/status registers. 1553 */ 1554 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1555 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1556 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1557 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1558 1559 if (!(command & PCIM_CMD_MEMEN)) { 1560 printf("ti%d: failed to enable memory mapping!\n", unit); 1561 free(sc, M_DEVBUF); 1562 goto fail; 1563 } 1564 1565 #ifdef __i386__ 1566 if (!pci_map_mem(config_id, TI_PCI_LOMEM, &vbase, &pbase)) { 1567 printf ("ti%d: couldn't map memory\n", unit); 1568 free(sc, M_DEVBUF); 1569 goto fail; 1570 } 1571 1572 sc->ti_bhandle = vbase; 1573 sc->ti_btag = I386_BUS_SPACE_MEM; 1574 #endif 1575 1576 #ifdef __alpha__ 1577 if (!(pci_map_bwx(config_id, TI_PCI_LOMEM, &vbase, &pbase) || 1578 pci_map_dense(config_id, TI_PCI_LOMEM, &vbase, &pbase))){ 1579 printf ("ti%d: couldn't map memory\n", unit); 1580 free(sc, M_DEVBUF); 1581 goto fail; 1582 } 1583 1584 sc->ti_bhandle = pbase; 1585 sc->ti_vhandle = vbase; 1586 sc->ti_btag = ALPHA_BUS_SPACE_MEM; 1587 #endif 1588 /* Allocate interrupt */ 1589 if (!pci_map_int(config_id, ti_intr, sc, &net_imask)) { 1590 printf("ti%d: couldn't map interrupt\n", unit); 1591 free(sc, M_DEVBUF); 1592 goto fail; 1593 } 1594 1595 sc->ti_unit = unit; 1596 1597 if (ti_chipinit(sc)) { 1598 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1599 free(sc, M_DEVBUF); 1600 goto fail; 1601 } 1602 1603 /* Zero out the NIC's on-board SRAM. */ 1604 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1605 1606 /* Init again -- zeroing memory may have clobbered some registers. */ 1607 if (ti_chipinit(sc)) { 1608 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1609 free(sc, M_DEVBUF); 1610 goto fail; 1611 } 1612 1613 /* 1614 * Get station address from the EEPROM. Note: the manual states 1615 * that the MAC address is at offset 0x8c, however the data is 1616 * stored as two longwords (since that's how it's loaded into 1617 * the NIC). This means the MAC address is actually preceeded 1618 * by two zero bytes. We need to skip over those. 1619 */ 1620 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1621 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1622 printf("ti%d: failed to read station address\n", unit); 1623 free(sc, M_DEVBUF); 1624 goto fail; 1625 } 1626 1627 /* 1628 * A Tigon chip was detected. Inform the world. 1629 */ 1630 printf("ti%d: Ethernet address: %6D\n", unit, 1631 sc->arpcom.ac_enaddr, ":"); 1632 1633 /* Allocate the general information block and ring buffers. */ 1634 sc->ti_rdata_ptr = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1635 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1636 1637 if (sc->ti_rdata_ptr == NULL) { 1638 free(sc, M_DEVBUF); 1639 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1640 goto fail; 1641 } 1642 1643 sc->ti_rdata = (struct ti_ring_data *)sc->ti_rdata_ptr; 1644 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1645 1646 /* Try to allocate memory for jumbo buffers. */ 1647 if (ti_alloc_jumbo_mem(sc)) { 1648 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1649 free(sc->ti_rdata_ptr, M_DEVBUF); 1650 free(sc, M_DEVBUF); 1651 goto fail; 1652 } 1653 1654 /* Set default tuneable values. */ 1655 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1656 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1657 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1658 sc->ti_rx_max_coal_bds = 64; 1659 sc->ti_tx_max_coal_bds = 128; 1660 sc->ti_tx_buf_ratio = 21; 1661 1662 /* Set up ifnet structure */ 1663 ifp = &sc->arpcom.ac_if; 1664 ifp->if_softc = sc; 1665 ifp->if_unit = sc->ti_unit; 1666 ifp->if_name = "ti"; 1667 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1668 ifp->if_ioctl = ti_ioctl; 1669 ifp->if_output = ether_output; 1670 ifp->if_start = ti_start; 1671 ifp->if_watchdog = ti_watchdog; 1672 ifp->if_init = ti_init; 1673 ifp->if_mtu = ETHERMTU; 1674 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1675 1676 /* Set up ifmedia support. */ 1677 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1678 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1679 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1680 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1681 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1682 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1683 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1684 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1685 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1686 1687 /* 1688 * Call MI attach routines. 1689 */ 1690 if_attach(ifp); 1691 ether_ifattach(ifp); 1692 1693 #if NBPFILTER > 0 1694 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1695 #endif 1696 1697 at_shutdown(ti_shutdown, sc, SHUTDOWN_POST_SYNC); 1698 1699 fail: 1700 splx(s); 1701 1702 return; 1703 } 1704 1705 /* 1706 * Frame reception handling. This is called if there's a frame 1707 * on the receive return list. 1708 * 1709 * Note: we have to be able to handle three possibilities here: 1710 * 1) the frame is from the mini receive ring (can only happen) 1711 * on Tigon 2 boards) 1712 * 2) the frame is from the jumbo recieve ring 1713 * 3) the frame is from the standard receive ring 1714 */ 1715 1716 static void ti_rxeof(sc) 1717 struct ti_softc *sc; 1718 { 1719 struct ifnet *ifp; 1720 struct ti_cmd_desc cmd; 1721 1722 ifp = &sc->arpcom.ac_if; 1723 1724 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1725 struct ti_rx_desc *cur_rx; 1726 u_int32_t rxidx; 1727 struct ether_header *eh; 1728 struct mbuf *m = NULL; 1729 #if NVLAN > 0 1730 u_int16_t vlan_tag = 0; 1731 int have_tag = 0; 1732 #endif 1733 #ifdef TI_CSUM_OFFLOAD 1734 struct ip *ip; 1735 #endif 1736 1737 cur_rx = 1738 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1739 rxidx = cur_rx->ti_idx; 1740 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1741 1742 #if NVLAN > 0 1743 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1744 have_tag = 1; 1745 vlan_tag = cur_rx->ti_vlan_tag; 1746 } 1747 #endif 1748 1749 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1750 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1751 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1752 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1753 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1754 ifp->if_ierrors++; 1755 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1756 continue; 1757 } 1758 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1759 ifp->if_ierrors++; 1760 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1761 continue; 1762 } 1763 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1764 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1765 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1766 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1767 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1768 ifp->if_ierrors++; 1769 ti_newbuf_mini(sc, sc->ti_mini, m); 1770 continue; 1771 } 1772 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1773 ifp->if_ierrors++; 1774 ti_newbuf_mini(sc, sc->ti_mini, m); 1775 continue; 1776 } 1777 } else { 1778 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1779 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1780 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1781 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1782 ifp->if_ierrors++; 1783 ti_newbuf_std(sc, sc->ti_std, m); 1784 continue; 1785 } 1786 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1787 ifp->if_ierrors++; 1788 ti_newbuf_std(sc, sc->ti_std, m); 1789 continue; 1790 } 1791 } 1792 1793 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1794 ifp->if_ipackets++; 1795 eh = mtod(m, struct ether_header *); 1796 m->m_pkthdr.rcvif = ifp; 1797 1798 #if NBPFILTER > 0 1799 /* 1800 * Handle BPF listeners. Let the BPF user see the packet, but 1801 * don't pass it up to the ether_input() layer unless it's 1802 * a broadcast packet, multicast packet, matches our ethernet 1803 * address or the interface is in promiscuous mode. 1804 */ 1805 if (ifp->if_bpf) { 1806 bpf_mtap(ifp, m); 1807 if (ifp->if_flags & IFF_PROMISC && 1808 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1809 ETHER_ADDR_LEN) && 1810 (eh->ether_dhost[0] & 1) == 0)) { 1811 m_freem(m); 1812 continue; 1813 } 1814 } 1815 #endif 1816 1817 /* Remove header from mbuf and pass it on. */ 1818 m_adj(m, sizeof(struct ether_header)); 1819 1820 #ifdef TI_CSUM_OFFLOAD 1821 ip = mtod(m, struct ip *); 1822 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) && 1823 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF))) 1824 m->m_flags |= M_HWCKSUM; 1825 #endif 1826 1827 #if NVLAN > 0 1828 /* 1829 * If we received a packet with a vlan tag, pass it 1830 * to vlan_input() instead of ether_input(). 1831 */ 1832 if (have_tag) { 1833 if (vlan_input_tag(eh, m, vlan_tag) < 0) 1834 ifp->if_data.ifi_noproto++; 1835 have_tag = vlan_tag = 0; 1836 continue; 1837 } 1838 #endif 1839 ether_input(ifp, eh, m); 1840 } 1841 1842 /* Only necessary on the Tigon 1. */ 1843 if (sc->ti_hwrev == TI_HWREV_TIGON) 1844 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1845 sc->ti_rx_saved_considx); 1846 1847 TI_UPDATE_STDPROD(sc, sc->ti_std); 1848 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1849 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1850 1851 return; 1852 } 1853 1854 static void ti_txeof(sc) 1855 struct ti_softc *sc; 1856 { 1857 struct ti_tx_desc *cur_tx = NULL; 1858 struct ifnet *ifp; 1859 1860 ifp = &sc->arpcom.ac_if; 1861 1862 /* 1863 * Go through our tx ring and free mbufs for those 1864 * frames that have been sent. 1865 */ 1866 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1867 u_int32_t idx = 0; 1868 1869 idx = sc->ti_tx_saved_considx; 1870 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1871 if (idx > 383) 1872 CSR_WRITE_4(sc, TI_WINBASE, 1873 TI_TX_RING_BASE + 6144); 1874 else if (idx > 255) 1875 CSR_WRITE_4(sc, TI_WINBASE, 1876 TI_TX_RING_BASE + 4096); 1877 else if (idx > 127) 1878 CSR_WRITE_4(sc, TI_WINBASE, 1879 TI_TX_RING_BASE + 2048); 1880 else 1881 CSR_WRITE_4(sc, TI_WINBASE, 1882 TI_TX_RING_BASE); 1883 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1884 } else 1885 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1886 if (cur_tx->ti_flags & TI_BDFLAG_END) 1887 ifp->if_opackets++; 1888 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1889 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1890 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1891 } 1892 sc->ti_txcnt--; 1893 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1894 ifp->if_timer = 0; 1895 } 1896 1897 if (cur_tx != NULL) 1898 ifp->if_flags &= ~IFF_OACTIVE; 1899 1900 return; 1901 } 1902 1903 static void ti_intr(xsc) 1904 void *xsc; 1905 { 1906 struct ti_softc *sc; 1907 struct ifnet *ifp; 1908 1909 sc = xsc; 1910 ifp = &sc->arpcom.ac_if; 1911 1912 #ifdef notdef 1913 /* Avoid this for now -- checking this register is expensive. */ 1914 /* Make sure this is really our interrupt. */ 1915 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1916 return; 1917 #endif 1918 1919 /* Ack interrupt and stop others from occuring. */ 1920 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1921 1922 if (ifp->if_flags & IFF_RUNNING) { 1923 /* Check RX return ring producer/consumer */ 1924 ti_rxeof(sc); 1925 1926 /* Check TX ring producer/consumer */ 1927 ti_txeof(sc); 1928 } 1929 1930 ti_handle_events(sc); 1931 1932 /* Re-enable interrupts. */ 1933 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1934 1935 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1936 ti_start(ifp); 1937 1938 return; 1939 } 1940 1941 static void ti_stats_update(sc) 1942 struct ti_softc *sc; 1943 { 1944 struct ifnet *ifp; 1945 1946 ifp = &sc->arpcom.ac_if; 1947 1948 ifp->if_collisions += 1949 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1950 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1951 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1952 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1953 ifp->if_collisions; 1954 1955 return; 1956 } 1957 1958 /* 1959 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1960 * pointers to descriptors. 1961 */ 1962 static int ti_encap(sc, m_head, txidx) 1963 struct ti_softc *sc; 1964 struct mbuf *m_head; 1965 u_int32_t *txidx; 1966 { 1967 struct ti_tx_desc *f = NULL; 1968 struct mbuf *m; 1969 u_int32_t frag, cur, cnt = 0; 1970 #if NVLAN > 0 1971 struct ifvlan *ifv = NULL; 1972 1973 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1974 m_head->m_pkthdr.rcvif != NULL && 1975 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 1976 ifv = m_head->m_pkthdr.rcvif->if_softc; 1977 #endif 1978 1979 m = m_head; 1980 cur = frag = *txidx; 1981 1982 /* 1983 * Start packing the mbufs in this chain into 1984 * the fragment pointers. Stop when we run out 1985 * of fragments or hit the end of the mbuf chain. 1986 */ 1987 for (m = m_head; m != NULL; m = m->m_next) { 1988 if (m->m_len != 0) { 1989 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1990 if (frag > 383) 1991 CSR_WRITE_4(sc, TI_WINBASE, 1992 TI_TX_RING_BASE + 6144); 1993 else if (frag > 255) 1994 CSR_WRITE_4(sc, TI_WINBASE, 1995 TI_TX_RING_BASE + 4096); 1996 else if (frag > 127) 1997 CSR_WRITE_4(sc, TI_WINBASE, 1998 TI_TX_RING_BASE + 2048); 1999 else 2000 CSR_WRITE_4(sc, TI_WINBASE, 2001 TI_TX_RING_BASE); 2002 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2003 } else 2004 f = &sc->ti_rdata->ti_tx_ring[frag]; 2005 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2006 break; 2007 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2008 f->ti_len = m->m_len; 2009 f->ti_flags = 0; 2010 #if NVLAN > 0 2011 if (ifv != NULL) { 2012 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2013 f->ti_vlan_tag = ifv->ifv_tag; 2014 } else { 2015 f->ti_vlan_tag = 0; 2016 } 2017 #endif 2018 /* 2019 * Sanity check: avoid coming within 16 descriptors 2020 * of the end of the ring. 2021 */ 2022 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2023 return(ENOBUFS); 2024 cur = frag; 2025 TI_INC(frag, TI_TX_RING_CNT); 2026 cnt++; 2027 } 2028 } 2029 2030 if (m != NULL) 2031 return(ENOBUFS); 2032 2033 if (frag == sc->ti_tx_saved_considx) 2034 return(ENOBUFS); 2035 2036 if (sc->ti_hwrev == TI_HWREV_TIGON) 2037 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2038 TI_BDFLAG_END; 2039 else 2040 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2041 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2042 sc->ti_txcnt += cnt; 2043 2044 *txidx = frag; 2045 2046 return(0); 2047 } 2048 2049 /* 2050 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2051 * to the mbuf data regions directly in the transmit descriptors. 2052 */ 2053 static void ti_start(ifp) 2054 struct ifnet *ifp; 2055 { 2056 struct ti_softc *sc; 2057 struct mbuf *m_head = NULL; 2058 u_int32_t prodidx = 0; 2059 2060 sc = ifp->if_softc; 2061 2062 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2063 2064 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2065 IF_DEQUEUE(&ifp->if_snd, m_head); 2066 if (m_head == NULL) 2067 break; 2068 2069 /* 2070 * Pack the data into the transmit ring. If we 2071 * don't have room, set the OACTIVE flag and wait 2072 * for the NIC to drain the ring. 2073 */ 2074 if (ti_encap(sc, m_head, &prodidx)) { 2075 IF_PREPEND(&ifp->if_snd, m_head); 2076 ifp->if_flags |= IFF_OACTIVE; 2077 break; 2078 } 2079 2080 /* 2081 * If there's a BPF listener, bounce a copy of this frame 2082 * to him. 2083 */ 2084 #if NBPFILTER > 0 2085 if (ifp->if_bpf) 2086 bpf_mtap(ifp, m_head); 2087 #endif 2088 } 2089 2090 /* Transmit */ 2091 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2092 2093 /* 2094 * Set a timeout in case the chip goes out to lunch. 2095 */ 2096 ifp->if_timer = 5; 2097 2098 return; 2099 } 2100 2101 static void ti_init(xsc) 2102 void *xsc; 2103 { 2104 struct ti_softc *sc = xsc; 2105 int s; 2106 2107 s = splimp(); 2108 2109 /* Cancel pending I/O and flush buffers. */ 2110 ti_stop(sc); 2111 2112 /* Init the gen info block, ring control blocks and firmware. */ 2113 if (ti_gibinit(sc)) { 2114 printf("ti%d: initialization failure\n", sc->ti_unit); 2115 splx(s); 2116 return; 2117 } 2118 2119 splx(s); 2120 2121 return; 2122 } 2123 2124 static void ti_init2(sc) 2125 struct ti_softc *sc; 2126 { 2127 struct ti_cmd_desc cmd; 2128 struct ifnet *ifp; 2129 u_int16_t *m; 2130 struct ifmedia *ifm; 2131 int tmp; 2132 2133 ifp = &sc->arpcom.ac_if; 2134 2135 /* Specify MTU and interface index. */ 2136 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2137 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2138 ETHER_HDR_LEN + ETHER_CRC_LEN); 2139 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2140 2141 /* Load our MAC address. */ 2142 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2143 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2144 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2145 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2146 2147 /* Enable or disable promiscuous mode as needed. */ 2148 if (ifp->if_flags & IFF_PROMISC) { 2149 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2150 } else { 2151 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2152 } 2153 2154 /* Program multicast filter. */ 2155 ti_setmulti(sc); 2156 2157 /* 2158 * If this is a Tigon 1, we should tell the 2159 * firmware to use software packet filtering. 2160 */ 2161 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2162 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2163 } 2164 2165 /* Init RX ring. */ 2166 ti_init_rx_ring_std(sc); 2167 2168 /* Init jumbo RX ring. */ 2169 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2170 ti_init_rx_ring_jumbo(sc); 2171 2172 /* 2173 * If this is a Tigon 2, we can also configure the 2174 * mini ring. 2175 */ 2176 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2177 ti_init_rx_ring_mini(sc); 2178 2179 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2180 sc->ti_rx_saved_considx = 0; 2181 2182 /* Init TX ring. */ 2183 ti_init_tx_ring(sc); 2184 2185 /* Tell firmware we're alive. */ 2186 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2187 2188 /* Enable host interrupts. */ 2189 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2190 2191 ifp->if_flags |= IFF_RUNNING; 2192 ifp->if_flags &= ~IFF_OACTIVE; 2193 2194 /* 2195 * Make sure to set media properly. We have to do this 2196 * here since we have to issue commands in order to set 2197 * the link negotiation and we can't issue commands until 2198 * the firmware is running. 2199 */ 2200 ifm = &sc->ifmedia; 2201 tmp = ifm->ifm_media; 2202 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2203 ti_ifmedia_upd(ifp); 2204 ifm->ifm_media = tmp; 2205 2206 return; 2207 } 2208 2209 /* 2210 * Set media options. 2211 */ 2212 static int ti_ifmedia_upd(ifp) 2213 struct ifnet *ifp; 2214 { 2215 struct ti_softc *sc; 2216 struct ifmedia *ifm; 2217 struct ti_cmd_desc cmd; 2218 2219 sc = ifp->if_softc; 2220 ifm = &sc->ifmedia; 2221 2222 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2223 return(EINVAL); 2224 2225 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2226 case IFM_AUTO: 2227 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2228 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2229 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2230 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2231 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2232 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2233 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2234 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2235 break; 2236 case IFM_1000_SX: 2237 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2238 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2239 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2240 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2241 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2242 break; 2243 case IFM_100_FX: 2244 case IFM_10_FL: 2245 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2246 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2247 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2248 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2249 } else { 2250 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2251 } 2252 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2253 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2254 } else { 2255 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2256 } 2257 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2258 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2259 break; 2260 } 2261 2262 return(0); 2263 } 2264 2265 /* 2266 * Report current media status. 2267 */ 2268 static void ti_ifmedia_sts(ifp, ifmr) 2269 struct ifnet *ifp; 2270 struct ifmediareq *ifmr; 2271 { 2272 struct ti_softc *sc; 2273 2274 sc = ifp->if_softc; 2275 2276 ifmr->ifm_status = IFM_AVALID; 2277 ifmr->ifm_active = IFM_ETHER; 2278 2279 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2280 return; 2281 2282 ifmr->ifm_status |= IFM_ACTIVE; 2283 2284 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2285 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2286 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2287 u_int32_t media; 2288 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2289 if (media & TI_LNK_100MB) 2290 ifmr->ifm_active |= IFM_100_FX; 2291 if (media & TI_LNK_10MB) 2292 ifmr->ifm_active |= IFM_10_FL; 2293 if (media & TI_LNK_FULL_DUPLEX) 2294 ifmr->ifm_active |= IFM_FDX; 2295 if (media & TI_LNK_HALF_DUPLEX) 2296 ifmr->ifm_active |= IFM_HDX; 2297 } 2298 2299 return; 2300 } 2301 2302 static int ti_ioctl(ifp, command, data) 2303 struct ifnet *ifp; 2304 u_long command; 2305 caddr_t data; 2306 { 2307 struct ti_softc *sc = ifp->if_softc; 2308 struct ifreq *ifr = (struct ifreq *) data; 2309 int s, error = 0; 2310 struct ti_cmd_desc cmd; 2311 2312 s = splimp(); 2313 2314 switch(command) { 2315 case SIOCSIFADDR: 2316 case SIOCGIFADDR: 2317 error = ether_ioctl(ifp, command, data); 2318 break; 2319 case SIOCSIFMTU: 2320 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2321 error = EINVAL; 2322 else { 2323 ifp->if_mtu = ifr->ifr_mtu; 2324 ti_init(sc); 2325 } 2326 break; 2327 case SIOCSIFFLAGS: 2328 if (ifp->if_flags & IFF_UP) { 2329 /* 2330 * If only the state of the PROMISC flag changed, 2331 * then just use the 'set promisc mode' command 2332 * instead of reinitializing the entire NIC. Doing 2333 * a full re-init means reloading the firmware and 2334 * waiting for it to start up, which may take a 2335 * second or two. 2336 */ 2337 if (ifp->if_flags & IFF_RUNNING && 2338 ifp->if_flags & IFF_PROMISC && 2339 !(sc->ti_if_flags & IFF_PROMISC)) { 2340 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2341 TI_CMD_CODE_PROMISC_ENB, 0); 2342 } else if (ifp->if_flags & IFF_RUNNING && 2343 !(ifp->if_flags & IFF_PROMISC) && 2344 sc->ti_if_flags & IFF_PROMISC) { 2345 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2346 TI_CMD_CODE_PROMISC_DIS, 0); 2347 } else 2348 ti_init(sc); 2349 } else { 2350 if (ifp->if_flags & IFF_RUNNING) { 2351 ti_stop(sc); 2352 } 2353 } 2354 sc->ti_if_flags = ifp->if_flags; 2355 error = 0; 2356 break; 2357 case SIOCADDMULTI: 2358 case SIOCDELMULTI: 2359 if (ifp->if_flags & IFF_RUNNING) { 2360 ti_setmulti(sc); 2361 error = 0; 2362 } 2363 break; 2364 case SIOCSIFMEDIA: 2365 case SIOCGIFMEDIA: 2366 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2367 break; 2368 default: 2369 error = EINVAL; 2370 break; 2371 } 2372 2373 (void)splx(s); 2374 2375 return(error); 2376 } 2377 2378 static void ti_watchdog(ifp) 2379 struct ifnet *ifp; 2380 { 2381 struct ti_softc *sc; 2382 2383 sc = ifp->if_softc; 2384 2385 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2386 ti_stop(sc); 2387 ti_init(sc); 2388 2389 ifp->if_oerrors++; 2390 2391 return; 2392 } 2393 2394 /* 2395 * Stop the adapter and free any mbufs allocated to the 2396 * RX and TX lists. 2397 */ 2398 static void ti_stop(sc) 2399 struct ti_softc *sc; 2400 { 2401 struct ifnet *ifp; 2402 struct ti_cmd_desc cmd; 2403 2404 ifp = &sc->arpcom.ac_if; 2405 2406 /* Disable host interrupts. */ 2407 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2408 /* 2409 * Tell firmware we're shutting down. 2410 */ 2411 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2412 2413 /* Halt and reinitialize. */ 2414 ti_chipinit(sc); 2415 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2416 ti_chipinit(sc); 2417 2418 /* Free the RX lists. */ 2419 ti_free_rx_ring_std(sc); 2420 2421 /* Free jumbo RX list. */ 2422 ti_free_rx_ring_jumbo(sc); 2423 2424 /* Free mini RX list. */ 2425 ti_free_rx_ring_mini(sc); 2426 2427 /* Free TX buffers. */ 2428 ti_free_tx_ring(sc); 2429 2430 sc->ti_ev_prodidx.ti_idx = 0; 2431 sc->ti_return_prodidx.ti_idx = 0; 2432 sc->ti_tx_considx.ti_idx = 0; 2433 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2434 2435 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2436 2437 return; 2438 } 2439 2440 /* 2441 * Stop all chip I/O so that the kernel's probe routines don't 2442 * get confused by errant DMAs when rebooting. 2443 */ 2444 static void ti_shutdown(howto, xsc) 2445 int howto; 2446 void *xsc; 2447 { 2448 struct ti_softc *sc; 2449 2450 sc = xsc; 2451 2452 ti_chipinit(sc); 2453 2454 return; 2455 } 2456 2457 static struct pci_device ti_device = { 2458 "ti", 2459 ti_probe, 2460 ti_attach, 2461 &ti_count, 2462 NULL 2463 }; 2464 DATA_SET(pcidevice_set, ti_device);
Cache object: 10bbd8ca9e22cadc7804e60aa7379e60
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