FreeBSD/Linux Kernel Cross Reference
sys/pci/if_ti.c
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD$
33 */
34
35 /*
36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
37 * Manuals, sample driver and firmware source kits are available
38 * from http://www.alteon.com/support/openkits.
39 *
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Electrical Engineering Department
42 * Columbia University, New York City
43 */
44
45 /*
46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
50 * filtering and jumbo (9014 byte) frames. The hardware is largely
51 * controlled by firmware, which must be loaded into the NIC during
52 * initialization.
53 *
54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
55 * revision, which supports new features such as extended commands,
56 * extended jumbo receive ring desciptors and a mini receive ring.
57 *
58 * Alteon Networks is to be commended for releasing such a vast amount
59 * of development material for the Tigon NIC without requiring an NDA
60 * (although they really should have done it a long time ago). With
61 * any luck, the other vendors will finally wise up and follow Alteon's
62 * stellar example.
63 *
64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
65 * this driver by #including it as a C header file. This bloats the
66 * driver somewhat, but it's the easiest method considering that the
67 * driver code and firmware code need to be kept in sync. The source
68 * for the firmware is not provided with the FreeBSD distribution since
69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
70 *
71 * The following people deserve special thanks:
72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
73 * for testing
74 * - Raymond Lee of Netgear, for providing a pair of Netgear
75 * GA620 Tigon 2 boards for testing
76 * - Ulf Zimmermann, for bringing the GA260 to my attention and
77 * convincing me to write this driver.
78 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 */
80
81 #include <sys/param.h>
82 #include <sys/systm.h>
83 #include <sys/sockio.h>
84 #include <sys/mbuf.h>
85 #include <sys/malloc.h>
86 #include <sys/kernel.h>
87 #include <sys/socket.h>
88 #include <sys/queue.h>
89
90 #include <net/if.h>
91 #include <net/if_arp.h>
92 #include <net/ethernet.h>
93 #include <net/if_dl.h>
94 #include <net/if_media.h>
95 #include <net/if_types.h>
96 #include <net/if_vlan_var.h>
97
98 #include <net/bpf.h>
99
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103
104 #include <vm/vm.h> /* for vtophys */
105 #include <vm/pmap.h> /* for vtophys */
106 #include <machine/clock.h> /* for DELAY */
107 #include <machine/bus_memio.h>
108 #include <machine/bus.h>
109 #include <machine/resource.h>
110 #include <sys/bus.h>
111 #include <sys/rman.h>
112
113 #include <pci/pcireg.h>
114 #include <pci/pcivar.h>
115
116 #include <pci/if_tireg.h>
117 #include <pci/ti_fw.h>
118 #include <pci/ti_fw2.h>
119
120 /*
121 * Temporarily disable the checksum offload support for now.
122 * Tests with ftp.freesoftware.com show that after about 12 hours,
123 * the firmware will begin calculating completely bogus TX checksums
124 * and refuse to stop until the interface is reset. Unfortunately,
125 * there isn't enough time to fully debug this before the 4.1
126 * release, so this will need to stay off for now.
127 */
128 #ifdef notdef
129 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
130 #else
131 #define TI_CSUM_FEATURES 0
132 #endif
133
134 #if !defined(lint)
135 static const char rcsid[] =
136 "$FreeBSD$";
137 #endif
138
139 /*
140 * Various supported device vendors/types and their names.
141 */
142
143 static struct ti_type ti_devs[] = {
144 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
145 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
146 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
147 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
148 { TC_VENDORID, TC_DEVICEID_3C985,
149 "3Com 3c985-SX Gigabit Ethernet" },
150 { NG_VENDORID, NG_DEVICEID_GA620,
151 "Netgear GA620 1000baseSX Gigabit Ethernet" },
152 { NG_VENDORID, NG_DEVICEID_GA620T,
153 "Netgear GA620 1000baseT Gigabit Ethernet" },
154 { SGI_VENDORID, SGI_DEVICEID_TIGON,
155 "Silicon Graphics Gigabit Ethernet" },
156 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
157 "Farallon PN9000SX Gigabit Ethernet" },
158 { 0, 0, NULL }
159 };
160
161 static int ti_probe __P((device_t));
162 static int ti_attach __P((device_t));
163 static int ti_detach __P((device_t));
164 static void ti_txeof __P((struct ti_softc *));
165 static void ti_rxeof __P((struct ti_softc *));
166
167 static void ti_stats_update __P((struct ti_softc *));
168 static int ti_encap __P((struct ti_softc *, struct mbuf *,
169 u_int32_t *));
170
171 static void ti_intr __P((void *));
172 static void ti_start __P((struct ifnet *));
173 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t));
174 static void ti_init __P((void *));
175 static void ti_init2 __P((struct ti_softc *));
176 static void ti_stop __P((struct ti_softc *));
177 static void ti_watchdog __P((struct ifnet *));
178 static void ti_shutdown __P((device_t));
179 static int ti_ifmedia_upd __P((struct ifnet *));
180 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
181
182 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int));
183 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *,
184 int, u_int8_t *));
185 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int));
186
187 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *));
188 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *));
189 static void ti_setmulti __P((struct ti_softc *));
190
191 static void ti_mem __P((struct ti_softc *, u_int32_t,
192 u_int32_t, caddr_t));
193 static void ti_loadfw __P((struct ti_softc *));
194 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *));
195 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *,
196 caddr_t, int));
197 static void ti_handle_events __P((struct ti_softc *));
198 static int ti_alloc_jumbo_mem __P((struct ti_softc *));
199 static void *ti_jalloc __P((struct ti_softc *));
200 static void ti_jfree __P((caddr_t, u_int));
201 static void ti_jref __P((caddr_t, u_int));
202 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *));
203 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *));
204 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *));
205 static int ti_init_rx_ring_std __P((struct ti_softc *));
206 static void ti_free_rx_ring_std __P((struct ti_softc *));
207 static int ti_init_rx_ring_jumbo __P((struct ti_softc *));
208 static void ti_free_rx_ring_jumbo __P((struct ti_softc *));
209 static int ti_init_rx_ring_mini __P((struct ti_softc *));
210 static void ti_free_rx_ring_mini __P((struct ti_softc *));
211 static void ti_free_tx_ring __P((struct ti_softc *));
212 static int ti_init_tx_ring __P((struct ti_softc *));
213
214 static int ti_64bitslot_war __P((struct ti_softc *));
215 static int ti_chipinit __P((struct ti_softc *));
216 static int ti_gibinit __P((struct ti_softc *));
217
218 static device_method_t ti_methods[] = {
219 /* Device interface */
220 DEVMETHOD(device_probe, ti_probe),
221 DEVMETHOD(device_attach, ti_attach),
222 DEVMETHOD(device_detach, ti_detach),
223 DEVMETHOD(device_shutdown, ti_shutdown),
224 { 0, 0 }
225 };
226
227 static driver_t ti_driver = {
228 "ti",
229 ti_methods,
230 sizeof(struct ti_softc)
231 };
232
233 static devclass_t ti_devclass;
234
235 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
236
237 /*
238 * Send an instruction or address to the EEPROM, check for ACK.
239 */
240 static u_int32_t ti_eeprom_putbyte(sc, byte)
241 struct ti_softc *sc;
242 int byte;
243 {
244 register int i, ack = 0;
245
246 /*
247 * Make sure we're in TX mode.
248 */
249 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
250
251 /*
252 * Feed in each bit and stobe the clock.
253 */
254 for (i = 0x80; i; i >>= 1) {
255 if (byte & i) {
256 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
257 } else {
258 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
259 }
260 DELAY(1);
261 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
262 DELAY(1);
263 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
264 }
265
266 /*
267 * Turn off TX mode.
268 */
269 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
270
271 /*
272 * Check for ack.
273 */
274 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
275 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
276 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
277
278 return(ack);
279 }
280
281 /*
282 * Read a byte of data stored in the EEPROM at address 'addr.'
283 * We have to send two address bytes since the EEPROM can hold
284 * more than 256 bytes of data.
285 */
286 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
287 struct ti_softc *sc;
288 int addr;
289 u_int8_t *dest;
290 {
291 register int i;
292 u_int8_t byte = 0;
293
294 EEPROM_START;
295
296 /*
297 * Send write control code to EEPROM.
298 */
299 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
300 printf("ti%d: failed to send write command, status: %x\n",
301 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
302 return(1);
303 }
304
305 /*
306 * Send first byte of address of byte we want to read.
307 */
308 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
309 printf("ti%d: failed to send address, status: %x\n",
310 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
311 return(1);
312 }
313 /*
314 * Send second byte address of byte we want to read.
315 */
316 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
317 printf("ti%d: failed to send address, status: %x\n",
318 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
319 return(1);
320 }
321
322 EEPROM_STOP;
323 EEPROM_START;
324 /*
325 * Send read control code to EEPROM.
326 */
327 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
328 printf("ti%d: failed to send read command, status: %x\n",
329 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
330 return(1);
331 }
332
333 /*
334 * Start reading bits from EEPROM.
335 */
336 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
337 for (i = 0x80; i; i >>= 1) {
338 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
339 DELAY(1);
340 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
341 byte |= i;
342 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
343 DELAY(1);
344 }
345
346 EEPROM_STOP;
347
348 /*
349 * No ACK generated for read, so just return byte.
350 */
351
352 *dest = byte;
353
354 return(0);
355 }
356
357 /*
358 * Read a sequence of bytes from the EEPROM.
359 */
360 static int ti_read_eeprom(sc, dest, off, cnt)
361 struct ti_softc *sc;
362 caddr_t dest;
363 int off;
364 int cnt;
365 {
366 int err = 0, i;
367 u_int8_t byte = 0;
368
369 for (i = 0; i < cnt; i++) {
370 err = ti_eeprom_getbyte(sc, off + i, &byte);
371 if (err)
372 break;
373 *(dest + i) = byte;
374 }
375
376 return(err ? 1 : 0);
377 }
378
379 /*
380 * NIC memory access function. Can be used to either clear a section
381 * of NIC local memory or (if buf is non-NULL) copy data into it.
382 */
383 static void ti_mem(sc, addr, len, buf)
384 struct ti_softc *sc;
385 u_int32_t addr, len;
386 caddr_t buf;
387 {
388 int segptr, segsize, cnt;
389 caddr_t ti_winbase, ptr;
390
391 segptr = addr;
392 cnt = len;
393 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
394 ptr = buf;
395
396 while(cnt) {
397 if (cnt < TI_WINLEN)
398 segsize = cnt;
399 else
400 segsize = TI_WINLEN - (segptr % TI_WINLEN);
401 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
402 if (buf == NULL)
403 bzero((char *)ti_winbase + (segptr &
404 (TI_WINLEN - 1)), segsize);
405 else {
406 bcopy((char *)ptr, (char *)ti_winbase +
407 (segptr & (TI_WINLEN - 1)), segsize);
408 ptr += segsize;
409 }
410 segptr += segsize;
411 cnt -= segsize;
412 }
413
414 return;
415 }
416
417 /*
418 * Load firmware image into the NIC. Check that the firmware revision
419 * is acceptable and see if we want the firmware for the Tigon 1 or
420 * Tigon 2.
421 */
422 static void ti_loadfw(sc)
423 struct ti_softc *sc;
424 {
425 switch(sc->ti_hwrev) {
426 case TI_HWREV_TIGON:
427 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
428 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
429 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
430 printf("ti%d: firmware revision mismatch; want "
431 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
432 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
433 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
434 tigonFwReleaseMinor, tigonFwReleaseFix);
435 return;
436 }
437 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
438 (caddr_t)tigonFwText);
439 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
440 (caddr_t)tigonFwData);
441 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
442 (caddr_t)tigonFwRodata);
443 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
444 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
445 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
446 break;
447 case TI_HWREV_TIGON_II:
448 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
449 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
450 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
451 printf("ti%d: firmware revision mismatch; want "
452 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
453 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
454 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
455 tigon2FwReleaseMinor, tigon2FwReleaseFix);
456 return;
457 }
458 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
459 (caddr_t)tigon2FwText);
460 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
461 (caddr_t)tigon2FwData);
462 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
463 (caddr_t)tigon2FwRodata);
464 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
465 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
466 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
467 break;
468 default:
469 printf("ti%d: can't load firmware: unknown hardware rev\n",
470 sc->ti_unit);
471 break;
472 }
473
474 return;
475 }
476
477 /*
478 * Send the NIC a command via the command ring.
479 */
480 static void ti_cmd(sc, cmd)
481 struct ti_softc *sc;
482 struct ti_cmd_desc *cmd;
483 {
484 u_int32_t index;
485
486 if (sc->ti_rdata->ti_cmd_ring == NULL)
487 return;
488
489 index = sc->ti_cmd_saved_prodidx;
490 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
491 TI_INC(index, TI_CMD_RING_CNT);
492 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
493 sc->ti_cmd_saved_prodidx = index;
494
495 return;
496 }
497
498 /*
499 * Send the NIC an extended command. The 'len' parameter specifies the
500 * number of command slots to include after the initial command.
501 */
502 static void ti_cmd_ext(sc, cmd, arg, len)
503 struct ti_softc *sc;
504 struct ti_cmd_desc *cmd;
505 caddr_t arg;
506 int len;
507 {
508 u_int32_t index;
509 register int i;
510
511 if (sc->ti_rdata->ti_cmd_ring == NULL)
512 return;
513
514 index = sc->ti_cmd_saved_prodidx;
515 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
516 TI_INC(index, TI_CMD_RING_CNT);
517 for (i = 0; i < len; i++) {
518 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
519 *(u_int32_t *)(&arg[i * 4]));
520 TI_INC(index, TI_CMD_RING_CNT);
521 }
522 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
523 sc->ti_cmd_saved_prodidx = index;
524
525 return;
526 }
527
528 /*
529 * Handle events that have triggered interrupts.
530 */
531 static void ti_handle_events(sc)
532 struct ti_softc *sc;
533 {
534 struct ti_event_desc *e;
535
536 if (sc->ti_rdata->ti_event_ring == NULL)
537 return;
538
539 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
540 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
541 switch(e->ti_event) {
542 case TI_EV_LINKSTAT_CHANGED:
543 sc->ti_linkstat = e->ti_code;
544 if (e->ti_code == TI_EV_CODE_LINK_UP)
545 printf("ti%d: 10/100 link up\n", sc->ti_unit);
546 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
547 printf("ti%d: gigabit link up\n", sc->ti_unit);
548 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
549 printf("ti%d: link down\n", sc->ti_unit);
550 break;
551 case TI_EV_ERROR:
552 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
553 printf("ti%d: invalid command\n", sc->ti_unit);
554 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
555 printf("ti%d: unknown command\n", sc->ti_unit);
556 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
557 printf("ti%d: bad config data\n", sc->ti_unit);
558 break;
559 case TI_EV_FIRMWARE_UP:
560 ti_init2(sc);
561 break;
562 case TI_EV_STATS_UPDATED:
563 ti_stats_update(sc);
564 break;
565 case TI_EV_RESET_JUMBO_RING:
566 case TI_EV_MCAST_UPDATED:
567 /* Who cares. */
568 break;
569 default:
570 printf("ti%d: unknown event: %d\n",
571 sc->ti_unit, e->ti_event);
572 break;
573 }
574 /* Advance the consumer index. */
575 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
576 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
577 }
578
579 return;
580 }
581
582 /*
583 * Memory management for the jumbo receive ring is a pain in the
584 * butt. We need to allocate at least 9018 bytes of space per frame,
585 * _and_ it has to be contiguous (unless you use the extended
586 * jumbo descriptor format). Using malloc() all the time won't
587 * work: malloc() allocates memory in powers of two, which means we
588 * would end up wasting a considerable amount of space by allocating
589 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
590 * to do our own memory management.
591 *
592 * The driver needs to allocate a contiguous chunk of memory at boot
593 * time. We then chop this up ourselves into 9K pieces and use them
594 * as external mbuf storage.
595 *
596 * One issue here is how much memory to allocate. The jumbo ring has
597 * 256 slots in it, but at 9K per slot than can consume over 2MB of
598 * RAM. This is a bit much, especially considering we also need
599 * RAM for the standard ring and mini ring (on the Tigon 2). To
600 * save space, we only actually allocate enough memory for 64 slots
601 * by default, which works out to between 500 and 600K. This can
602 * be tuned by changing a #define in if_tireg.h.
603 */
604
605 static int ti_alloc_jumbo_mem(sc)
606 struct ti_softc *sc;
607 {
608 caddr_t ptr;
609 register int i;
610 struct ti_jpool_entry *entry;
611
612 /* Grab a big chunk o' storage. */
613 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
614 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
615
616 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
617 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
618 return(ENOBUFS);
619 }
620
621 SLIST_INIT(&sc->ti_jfree_listhead);
622 SLIST_INIT(&sc->ti_jinuse_listhead);
623
624 /*
625 * Now divide it up into 9K pieces and save the addresses
626 * in an array. Note that we play an evil trick here by using
627 * the first few bytes in the buffer to hold the the address
628 * of the softc structure for this interface. This is because
629 * ti_jfree() needs it, but it is called by the mbuf management
630 * code which will not pass it to us explicitly.
631 */
632 ptr = sc->ti_cdata.ti_jumbo_buf;
633 for (i = 0; i < TI_JSLOTS; i++) {
634 u_int64_t **aptr;
635 aptr = (u_int64_t **)ptr;
636 aptr[0] = (u_int64_t *)sc;
637 ptr += sizeof(u_int64_t);
638 sc->ti_cdata.ti_jslots[i].ti_buf = ptr;
639 sc->ti_cdata.ti_jslots[i].ti_inuse = 0;
640 ptr += (TI_JLEN - sizeof(u_int64_t));
641 entry = malloc(sizeof(struct ti_jpool_entry),
642 M_DEVBUF, M_NOWAIT);
643 if (entry == NULL) {
644 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
645 M_DEVBUF);
646 sc->ti_cdata.ti_jumbo_buf = NULL;
647 printf("ti%d: no memory for jumbo "
648 "buffer queue!\n", sc->ti_unit);
649 return(ENOBUFS);
650 }
651 entry->slot = i;
652 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
653 }
654
655 return(0);
656 }
657
658 /*
659 * Allocate a jumbo buffer.
660 */
661 static void *ti_jalloc(sc)
662 struct ti_softc *sc;
663 {
664 struct ti_jpool_entry *entry;
665
666 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
667
668 if (entry == NULL) {
669 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
670 return(NULL);
671 }
672
673 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
674 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
675 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1;
676 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf);
677 }
678
679 /*
680 * Adjust usage count on a jumbo buffer. In general this doesn't
681 * get used much because our jumbo buffers don't get passed around
682 * too much, but it's implemented for correctness.
683 */
684 static void ti_jref(buf, size)
685 caddr_t buf;
686 u_int size;
687 {
688 struct ti_softc *sc;
689 u_int64_t **aptr;
690 register int i;
691
692 /* Extract the softc struct pointer. */
693 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
694 sc = (struct ti_softc *)(aptr[0]);
695
696 if (sc == NULL)
697 panic("ti_jref: can't find softc pointer!");
698
699 if (size != TI_JUMBO_FRAMELEN)
700 panic("ti_jref: adjusting refcount of buf of wrong size!");
701
702 /* calculate the slot this buffer belongs to */
703
704 i = ((vm_offset_t)aptr
705 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
706
707 if ((i < 0) || (i >= TI_JSLOTS))
708 panic("ti_jref: asked to reference buffer "
709 "that we don't manage!");
710 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
711 panic("ti_jref: buffer already free!");
712 else
713 sc->ti_cdata.ti_jslots[i].ti_inuse++;
714
715 return;
716 }
717
718 /*
719 * Release a jumbo buffer.
720 */
721 static void ti_jfree(buf, size)
722 caddr_t buf;
723 u_int size;
724 {
725 struct ti_softc *sc;
726 u_int64_t **aptr;
727 int i;
728 struct ti_jpool_entry *entry;
729
730 /* Extract the softc struct pointer. */
731 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
732 sc = (struct ti_softc *)(aptr[0]);
733
734 if (sc == NULL)
735 panic("ti_jfree: can't find softc pointer!");
736
737 if (size != TI_JUMBO_FRAMELEN)
738 panic("ti_jfree: freeing buffer of wrong size!");
739
740 /* calculate the slot this buffer belongs to */
741
742 i = ((vm_offset_t)aptr
743 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
744
745 if ((i < 0) || (i >= TI_JSLOTS))
746 panic("ti_jfree: asked to free buffer that we don't manage!");
747 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
748 panic("ti_jfree: buffer already free!");
749 else {
750 sc->ti_cdata.ti_jslots[i].ti_inuse--;
751 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) {
752 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
753 if (entry == NULL)
754 panic("ti_jfree: buffer not in use!");
755 entry->slot = i;
756 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead,
757 jpool_entries);
758 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead,
759 entry, jpool_entries);
760 }
761 }
762
763 return;
764 }
765
766
767 /*
768 * Intialize a standard receive ring descriptor.
769 */
770 static int ti_newbuf_std(sc, i, m)
771 struct ti_softc *sc;
772 int i;
773 struct mbuf *m;
774 {
775 struct mbuf *m_new = NULL;
776 struct ti_rx_desc *r;
777
778 if (m == NULL) {
779 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
780 if (m_new == NULL)
781 return(ENOBUFS);
782
783 MCLGET(m_new, M_DONTWAIT);
784 if (!(m_new->m_flags & M_EXT)) {
785 m_freem(m_new);
786 return(ENOBUFS);
787 }
788 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
789 } else {
790 m_new = m;
791 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
792 m_new->m_data = m_new->m_ext.ext_buf;
793 }
794
795 m_adj(m_new, ETHER_ALIGN);
796 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
797 r = &sc->ti_rdata->ti_rx_std_ring[i];
798 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
799 r->ti_type = TI_BDTYPE_RECV_BD;
800 r->ti_flags = 0;
801 if (sc->arpcom.ac_if.if_hwassist)
802 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
803 r->ti_len = m_new->m_len;
804 r->ti_idx = i;
805
806 return(0);
807 }
808
809 /*
810 * Intialize a mini receive ring descriptor. This only applies to
811 * the Tigon 2.
812 */
813 static int ti_newbuf_mini(sc, i, m)
814 struct ti_softc *sc;
815 int i;
816 struct mbuf *m;
817 {
818 struct mbuf *m_new = NULL;
819 struct ti_rx_desc *r;
820
821 if (m == NULL) {
822 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
823 if (m_new == NULL) {
824 return(ENOBUFS);
825 }
826 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
827 } else {
828 m_new = m;
829 m_new->m_data = m_new->m_pktdat;
830 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
831 }
832
833 m_adj(m_new, ETHER_ALIGN);
834 r = &sc->ti_rdata->ti_rx_mini_ring[i];
835 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
836 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
837 r->ti_type = TI_BDTYPE_RECV_BD;
838 r->ti_flags = TI_BDFLAG_MINI_RING;
839 if (sc->arpcom.ac_if.if_hwassist)
840 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
841 r->ti_len = m_new->m_len;
842 r->ti_idx = i;
843
844 return(0);
845 }
846
847 /*
848 * Initialize a jumbo receive ring descriptor. This allocates
849 * a jumbo buffer from the pool managed internally by the driver.
850 */
851 static int ti_newbuf_jumbo(sc, i, m)
852 struct ti_softc *sc;
853 int i;
854 struct mbuf *m;
855 {
856 struct mbuf *m_new = NULL;
857 struct ti_rx_desc *r;
858
859 if (m == NULL) {
860 caddr_t *buf = NULL;
861
862 /* Allocate the mbuf. */
863 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
864 if (m_new == NULL) {
865 return(ENOBUFS);
866 }
867
868 /* Allocate the jumbo buffer */
869 buf = ti_jalloc(sc);
870 if (buf == NULL) {
871 m_freem(m_new);
872 printf("ti%d: jumbo allocation failed "
873 "-- packet dropped!\n", sc->ti_unit);
874 return(ENOBUFS);
875 }
876
877 /* Attach the buffer to the mbuf. */
878 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
879 m_new->m_flags |= M_EXT;
880 m_new->m_len = m_new->m_pkthdr.len =
881 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
882 m_new->m_ext.ext_free = ti_jfree;
883 m_new->m_ext.ext_ref = ti_jref;
884 } else {
885 m_new = m;
886 m_new->m_data = m_new->m_ext.ext_buf;
887 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
888 }
889
890 m_adj(m_new, ETHER_ALIGN);
891 /* Set up the descriptor. */
892 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
893 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
894 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
895 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
896 r->ti_flags = TI_BDFLAG_JUMBO_RING;
897 if (sc->arpcom.ac_if.if_hwassist)
898 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
899 r->ti_len = m_new->m_len;
900 r->ti_idx = i;
901
902 return(0);
903 }
904
905 /*
906 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
907 * that's 1MB or memory, which is a lot. For now, we fill only the first
908 * 256 ring entries and hope that our CPU is fast enough to keep up with
909 * the NIC.
910 */
911 static int ti_init_rx_ring_std(sc)
912 struct ti_softc *sc;
913 {
914 register int i;
915 struct ti_cmd_desc cmd;
916
917 for (i = 0; i < TI_SSLOTS; i++) {
918 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
919 return(ENOBUFS);
920 };
921
922 TI_UPDATE_STDPROD(sc, i - 1);
923 sc->ti_std = i - 1;
924
925 return(0);
926 }
927
928 static void ti_free_rx_ring_std(sc)
929 struct ti_softc *sc;
930 {
931 register int i;
932
933 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
934 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
935 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
936 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
937 }
938 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
939 sizeof(struct ti_rx_desc));
940 }
941
942 return;
943 }
944
945 static int ti_init_rx_ring_jumbo(sc)
946 struct ti_softc *sc;
947 {
948 register int i;
949 struct ti_cmd_desc cmd;
950
951 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
952 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
953 return(ENOBUFS);
954 };
955
956 TI_UPDATE_JUMBOPROD(sc, i - 1);
957 sc->ti_jumbo = i - 1;
958
959 return(0);
960 }
961
962 static void ti_free_rx_ring_jumbo(sc)
963 struct ti_softc *sc;
964 {
965 register int i;
966
967 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
968 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
969 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
970 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
971 }
972 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
973 sizeof(struct ti_rx_desc));
974 }
975
976 return;
977 }
978
979 static int ti_init_rx_ring_mini(sc)
980 struct ti_softc *sc;
981 {
982 register int i;
983
984 for (i = 0; i < TI_MSLOTS; i++) {
985 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
986 return(ENOBUFS);
987 };
988
989 TI_UPDATE_MINIPROD(sc, i - 1);
990 sc->ti_mini = i - 1;
991
992 return(0);
993 }
994
995 static void ti_free_rx_ring_mini(sc)
996 struct ti_softc *sc;
997 {
998 register int i;
999
1000 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1001 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1002 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1003 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1004 }
1005 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1006 sizeof(struct ti_rx_desc));
1007 }
1008
1009 return;
1010 }
1011
1012 static void ti_free_tx_ring(sc)
1013 struct ti_softc *sc;
1014 {
1015 register int i;
1016
1017 if (sc->ti_rdata->ti_tx_ring == NULL)
1018 return;
1019
1020 for (i = 0; i < TI_TX_RING_CNT; i++) {
1021 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1022 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1023 sc->ti_cdata.ti_tx_chain[i] = NULL;
1024 }
1025 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1026 sizeof(struct ti_tx_desc));
1027 }
1028
1029 return;
1030 }
1031
1032 static int ti_init_tx_ring(sc)
1033 struct ti_softc *sc;
1034 {
1035 sc->ti_txcnt = 0;
1036 sc->ti_tx_saved_considx = 0;
1037 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1038 return(0);
1039 }
1040
1041 /*
1042 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1043 * but we have to support the old way too so that Tigon 1 cards will
1044 * work.
1045 */
1046 void ti_add_mcast(sc, addr)
1047 struct ti_softc *sc;
1048 struct ether_addr *addr;
1049 {
1050 struct ti_cmd_desc cmd;
1051 u_int16_t *m;
1052 u_int32_t ext[2] = {0, 0};
1053
1054 m = (u_int16_t *)&addr->octet[0];
1055
1056 switch(sc->ti_hwrev) {
1057 case TI_HWREV_TIGON:
1058 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1059 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1060 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1061 break;
1062 case TI_HWREV_TIGON_II:
1063 ext[0] = htons(m[0]);
1064 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1065 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1066 break;
1067 default:
1068 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1069 break;
1070 }
1071
1072 return;
1073 }
1074
1075 void ti_del_mcast(sc, addr)
1076 struct ti_softc *sc;
1077 struct ether_addr *addr;
1078 {
1079 struct ti_cmd_desc cmd;
1080 u_int16_t *m;
1081 u_int32_t ext[2] = {0, 0};
1082
1083 m = (u_int16_t *)&addr->octet[0];
1084
1085 switch(sc->ti_hwrev) {
1086 case TI_HWREV_TIGON:
1087 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1088 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1089 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1090 break;
1091 case TI_HWREV_TIGON_II:
1092 ext[0] = htons(m[0]);
1093 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1094 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1095 break;
1096 default:
1097 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1098 break;
1099 }
1100
1101 return;
1102 }
1103
1104 /*
1105 * Configure the Tigon's multicast address filter.
1106 *
1107 * The actual multicast table management is a bit of a pain, thanks to
1108 * slight brain damage on the part of both Alteon and us. With our
1109 * multicast code, we are only alerted when the multicast address table
1110 * changes and at that point we only have the current list of addresses:
1111 * we only know the current state, not the previous state, so we don't
1112 * actually know what addresses were removed or added. The firmware has
1113 * state, but we can't get our grubby mits on it, and there is no 'delete
1114 * all multicast addresses' command. Hence, we have to maintain our own
1115 * state so we know what addresses have been programmed into the NIC at
1116 * any given time.
1117 */
1118 static void ti_setmulti(sc)
1119 struct ti_softc *sc;
1120 {
1121 struct ifnet *ifp;
1122 struct ifmultiaddr *ifma;
1123 struct ti_cmd_desc cmd;
1124 struct ti_mc_entry *mc;
1125 u_int32_t intrs;
1126
1127 ifp = &sc->arpcom.ac_if;
1128
1129 if (ifp->if_flags & IFF_ALLMULTI) {
1130 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1131 return;
1132 } else {
1133 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1134 }
1135
1136 /* Disable interrupts. */
1137 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1138 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1139
1140 /* First, zot all the existing filters. */
1141 while (sc->ti_mc_listhead.slh_first != NULL) {
1142 mc = sc->ti_mc_listhead.slh_first;
1143 ti_del_mcast(sc, &mc->mc_addr);
1144 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1145 free(mc, M_DEVBUF);
1146 }
1147
1148 /* Now program new ones. */
1149 for (ifma = ifp->if_multiaddrs.lh_first;
1150 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1151 if (ifma->ifma_addr->sa_family != AF_LINK)
1152 continue;
1153 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1154 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1155 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1156 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1157 ti_add_mcast(sc, &mc->mc_addr);
1158 }
1159
1160 /* Re-enable interrupts. */
1161 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1162
1163 return;
1164 }
1165
1166 /*
1167 * Check to see if the BIOS has configured us for a 64 bit slot when
1168 * we aren't actually in one. If we detect this condition, we can work
1169 * around it on the Tigon 2 by setting a bit in the PCI state register,
1170 * but for the Tigon 1 we must give up and abort the interface attach.
1171 */
1172 static int ti_64bitslot_war(sc)
1173 struct ti_softc *sc;
1174 {
1175 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1176 CSR_WRITE_4(sc, 0x600, 0);
1177 CSR_WRITE_4(sc, 0x604, 0);
1178 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1179 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1180 if (sc->ti_hwrev == TI_HWREV_TIGON)
1181 return(EINVAL);
1182 else {
1183 TI_SETBIT(sc, TI_PCI_STATE,
1184 TI_PCISTATE_32BIT_BUS);
1185 return(0);
1186 }
1187 }
1188 }
1189
1190 return(0);
1191 }
1192
1193 /*
1194 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1195 * self-test results.
1196 */
1197 static int ti_chipinit(sc)
1198 struct ti_softc *sc;
1199 {
1200 u_int32_t cacheline;
1201 u_int32_t pci_writemax = 0;
1202
1203 /* Initialize link to down state. */
1204 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1205
1206 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
1207 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1208 else
1209 sc->arpcom.ac_if.if_hwassist = 0;
1210
1211 /* Set endianness before we access any non-PCI registers. */
1212 #if BYTE_ORDER == BIG_ENDIAN
1213 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1214 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1215 #else
1216 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1217 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1218 #endif
1219
1220 /* Check the ROM failed bit to see if self-tests passed. */
1221 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1222 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1223 return(ENODEV);
1224 }
1225
1226 /* Halt the CPU. */
1227 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1228
1229 /* Figure out the hardware revision. */
1230 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1231 case TI_REV_TIGON_I:
1232 sc->ti_hwrev = TI_HWREV_TIGON;
1233 break;
1234 case TI_REV_TIGON_II:
1235 sc->ti_hwrev = TI_HWREV_TIGON_II;
1236 break;
1237 default:
1238 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1239 return(ENODEV);
1240 }
1241
1242 /* Do special setup for Tigon 2. */
1243 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1244 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1246 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1247 }
1248
1249 /* Set up the PCI state register. */
1250 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1251 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1252 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1253 }
1254
1255 /* Clear the read/write max DMA parameters. */
1256 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1257 TI_PCISTATE_READ_MAXDMA));
1258
1259 /* Get cache line size. */
1260 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1261
1262 /*
1263 * If the system has set enabled the PCI memory write
1264 * and invalidate command in the command register, set
1265 * the write max parameter accordingly. This is necessary
1266 * to use MWI with the Tigon 2.
1267 */
1268 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1269 switch(cacheline) {
1270 case 1:
1271 case 4:
1272 case 8:
1273 case 16:
1274 case 32:
1275 case 64:
1276 break;
1277 default:
1278 /* Disable PCI memory write and invalidate. */
1279 if (bootverbose)
1280 printf("ti%d: cache line size %d not "
1281 "supported; disabling PCI MWI\n",
1282 sc->ti_unit, cacheline);
1283 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1284 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1285 break;
1286 }
1287 }
1288
1289 #ifdef __brokenalpha__
1290 /*
1291 * From the Alteon sample driver:
1292 * Must insure that we do not cross an 8K (bytes) boundary
1293 * for DMA reads. Our highest limit is 1K bytes. This is a
1294 * restriction on some ALPHA platforms with early revision
1295 * 21174 PCI chipsets, such as the AlphaPC 164lx
1296 */
1297 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1298 #else
1299 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1300 #endif
1301
1302 /* This sets the min dma param all the way up (0xff). */
1303 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1304
1305 /* Configure DMA variables. */
1306 #if BYTE_ORDER == BIG_ENDIAN
1307 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1308 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1309 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1310 TI_OPMODE_DONT_FRAG_JUMBO);
1311 #else
1312 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1313 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1314 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1315 #endif
1316
1317 /*
1318 * Only allow 1 DMA channel to be active at a time.
1319 * I don't think this is a good idea, but without it
1320 * the firmware racks up lots of nicDmaReadRingFull
1321 * errors. This is not compatible with hardware checksums.
1322 */
1323 if (sc->arpcom.ac_if.if_hwassist == 0)
1324 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1325
1326 /* Recommended settings from Tigon manual. */
1327 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1328 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1329
1330 if (ti_64bitslot_war(sc)) {
1331 printf("ti%d: bios thinks we're in a 64 bit slot, "
1332 "but we aren't", sc->ti_unit);
1333 return(EINVAL);
1334 }
1335
1336 return(0);
1337 }
1338
1339 /*
1340 * Initialize the general information block and firmware, and
1341 * start the CPU(s) running.
1342 */
1343 static int ti_gibinit(sc)
1344 struct ti_softc *sc;
1345 {
1346 struct ti_rcb *rcb;
1347 int i;
1348 struct ifnet *ifp;
1349
1350 ifp = &sc->arpcom.ac_if;
1351
1352 /* Disable interrupts for now. */
1353 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1354
1355 /* Tell the chip where to find the general information block. */
1356 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1357 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1358
1359 /* Load the firmware into SRAM. */
1360 ti_loadfw(sc);
1361
1362 /* Set up the contents of the general info and ring control blocks. */
1363
1364 /* Set up the event ring and producer pointer. */
1365 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1366
1367 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1368 rcb->ti_flags = 0;
1369 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1370 vtophys(&sc->ti_ev_prodidx);
1371 sc->ti_ev_prodidx.ti_idx = 0;
1372 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1373 sc->ti_ev_saved_considx = 0;
1374
1375 /* Set up the command ring and producer mailbox. */
1376 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1377
1378 sc->ti_rdata->ti_cmd_ring =
1379 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1380 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1381 rcb->ti_flags = 0;
1382 rcb->ti_max_len = 0;
1383 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1384 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1385 }
1386 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1387 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1388 sc->ti_cmd_saved_prodidx = 0;
1389
1390 /*
1391 * Assign the address of the stats refresh buffer.
1392 * We re-use the current stats buffer for this to
1393 * conserve memory.
1394 */
1395 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1396 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1397
1398 /* Set up the standard receive ring. */
1399 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1400 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1401 rcb->ti_max_len = TI_FRAMELEN;
1402 rcb->ti_flags = 0;
1403 if (sc->arpcom.ac_if.if_hwassist)
1404 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1405 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1406 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1407
1408 /* Set up the jumbo receive ring. */
1409 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1410 TI_HOSTADDR(rcb->ti_hostaddr) =
1411 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1412 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1413 rcb->ti_flags = 0;
1414 if (sc->arpcom.ac_if.if_hwassist)
1415 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1416 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1417 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1418
1419 /*
1420 * Set up the mini ring. Only activated on the
1421 * Tigon 2 but the slot in the config block is
1422 * still there on the Tigon 1.
1423 */
1424 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1425 TI_HOSTADDR(rcb->ti_hostaddr) =
1426 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1427 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1428 if (sc->ti_hwrev == TI_HWREV_TIGON)
1429 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1430 else
1431 rcb->ti_flags = 0;
1432 if (sc->arpcom.ac_if.if_hwassist)
1433 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1434 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1435 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1436
1437 /*
1438 * Set up the receive return ring.
1439 */
1440 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1441 TI_HOSTADDR(rcb->ti_hostaddr) =
1442 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1443 rcb->ti_flags = 0;
1444 rcb->ti_max_len = TI_RETURN_RING_CNT;
1445 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1446 vtophys(&sc->ti_return_prodidx);
1447
1448 /*
1449 * Set up the tx ring. Note: for the Tigon 2, we have the option
1450 * of putting the transmit ring in the host's address space and
1451 * letting the chip DMA it instead of leaving the ring in the NIC's
1452 * memory and accessing it through the shared memory region. We
1453 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1454 * so we have to revert to the shared memory scheme if we detect
1455 * a Tigon 1 chip.
1456 */
1457 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1458 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1459 sc->ti_rdata->ti_tx_ring_nic =
1460 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1461 }
1462 bzero((char *)sc->ti_rdata->ti_tx_ring,
1463 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1464 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1465 if (sc->ti_hwrev == TI_HWREV_TIGON)
1466 rcb->ti_flags = 0;
1467 else
1468 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1469 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1470 if (sc->arpcom.ac_if.if_hwassist)
1471 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1472 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1473 rcb->ti_max_len = TI_TX_RING_CNT;
1474 if (sc->ti_hwrev == TI_HWREV_TIGON)
1475 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1476 else
1477 TI_HOSTADDR(rcb->ti_hostaddr) =
1478 vtophys(&sc->ti_rdata->ti_tx_ring);
1479 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1480 vtophys(&sc->ti_tx_considx);
1481
1482 /* Set up tuneables */
1483 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1484 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1485 (sc->ti_rx_coal_ticks / 10));
1486 else
1487 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1488 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1489 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1490 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1491 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1492 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1493
1494 /* Turn interrupts on. */
1495 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1496 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1497
1498 /* Start CPU. */
1499 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1500
1501 return(0);
1502 }
1503
1504 /*
1505 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1506 * against our list and return its name if we find a match.
1507 */
1508 static int ti_probe(dev)
1509 device_t dev;
1510 {
1511 struct ti_type *t;
1512
1513 t = ti_devs;
1514
1515 while(t->ti_name != NULL) {
1516 if ((pci_get_vendor(dev) == t->ti_vid) &&
1517 (pci_get_device(dev) == t->ti_did)) {
1518 device_set_desc(dev, t->ti_name);
1519 return(0);
1520 }
1521 t++;
1522 }
1523
1524 return(ENXIO);
1525 }
1526
1527 static int ti_attach(dev)
1528 device_t dev;
1529 {
1530 int s;
1531 u_int32_t command;
1532 struct ifnet *ifp;
1533 struct ti_softc *sc;
1534 int unit, error = 0, rid;
1535
1536 s = splimp();
1537
1538 sc = device_get_softc(dev);
1539 unit = device_get_unit(dev);
1540 bzero(sc, sizeof(struct ti_softc));
1541 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM;
1542 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities;
1543
1544 /*
1545 * Map control/status registers.
1546 */
1547 command = pci_read_config(dev, PCIR_COMMAND, 4);
1548 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1549 pci_write_config(dev, PCIR_COMMAND, command, 4);
1550 command = pci_read_config(dev, PCIR_COMMAND, 4);
1551
1552 if (!(command & PCIM_CMD_MEMEN)) {
1553 printf("ti%d: failed to enable memory mapping!\n", unit);
1554 error = ENXIO;
1555 goto fail;
1556 }
1557
1558 rid = TI_PCI_LOMEM;
1559 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1560 0, ~0, 1, RF_ACTIVE);
1561
1562 if (sc->ti_res == NULL) {
1563 printf ("ti%d: couldn't map memory\n", unit);
1564 error = ENXIO;
1565 goto fail;
1566 }
1567
1568 sc->ti_btag = rman_get_bustag(sc->ti_res);
1569 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1570 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1571
1572 /*
1573 * XXX FIXME: rman_get_virtual() on the alpha is currently
1574 * broken and returns a physical address instead of a kernel
1575 * virtual address. Consequently, we need to do a little
1576 * extra mangling of the vhandle on the alpha. This should
1577 * eventually be fixed! The whole idea here is to get rid
1578 * of platform dependencies.
1579 */
1580 #ifdef __alpha__
1581 if (pci_cvt_to_bwx(sc->ti_vhandle))
1582 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle);
1583 else
1584 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle);
1585 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle);
1586 #endif
1587
1588 /* Allocate interrupt */
1589 rid = 0;
1590
1591 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1592 RF_SHAREABLE | RF_ACTIVE);
1593
1594 if (sc->ti_irq == NULL) {
1595 printf("ti%d: couldn't map interrupt\n", unit);
1596 error = ENXIO;
1597 goto fail;
1598 }
1599
1600 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1601 ti_intr, sc, &sc->ti_intrhand);
1602
1603 if (error) {
1604 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1605 bus_release_resource(dev, SYS_RES_MEMORY,
1606 TI_PCI_LOMEM, sc->ti_res);
1607 printf("ti%d: couldn't set up irq\n", unit);
1608 goto fail;
1609 }
1610
1611 sc->ti_unit = unit;
1612
1613 if (ti_chipinit(sc)) {
1614 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1615 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1616 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1617 bus_release_resource(dev, SYS_RES_MEMORY,
1618 TI_PCI_LOMEM, sc->ti_res);
1619 error = ENXIO;
1620 goto fail;
1621 }
1622
1623 /* Zero out the NIC's on-board SRAM. */
1624 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1625
1626 /* Init again -- zeroing memory may have clobbered some registers. */
1627 if (ti_chipinit(sc)) {
1628 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1629 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1630 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1631 bus_release_resource(dev, SYS_RES_MEMORY,
1632 TI_PCI_LOMEM, sc->ti_res);
1633 error = ENXIO;
1634 goto fail;
1635 }
1636
1637 /*
1638 * Get station address from the EEPROM. Note: the manual states
1639 * that the MAC address is at offset 0x8c, however the data is
1640 * stored as two longwords (since that's how it's loaded into
1641 * the NIC). This means the MAC address is actually preceeded
1642 * by two zero bytes. We need to skip over those.
1643 */
1644 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1645 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1646 printf("ti%d: failed to read station address\n", unit);
1647 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1648 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1649 bus_release_resource(dev, SYS_RES_MEMORY,
1650 TI_PCI_LOMEM, sc->ti_res);
1651 error = ENXIO;
1652 goto fail;
1653 }
1654
1655 /*
1656 * A Tigon chip was detected. Inform the world.
1657 */
1658 printf("ti%d: Ethernet address: %6D\n", unit,
1659 sc->arpcom.ac_enaddr, ":");
1660
1661 /* Allocate the general information block and ring buffers. */
1662 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1663 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1664
1665 if (sc->ti_rdata == NULL) {
1666 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1667 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1668 bus_release_resource(dev, SYS_RES_MEMORY,
1669 TI_PCI_LOMEM, sc->ti_res);
1670 error = ENXIO;
1671 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1672 goto fail;
1673 }
1674
1675 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1676
1677 /* Try to allocate memory for jumbo buffers. */
1678 if (ti_alloc_jumbo_mem(sc)) {
1679 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1680 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1681 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1682 bus_release_resource(dev, SYS_RES_MEMORY,
1683 TI_PCI_LOMEM, sc->ti_res);
1684 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data),
1685 M_DEVBUF);
1686 error = ENXIO;
1687 goto fail;
1688 }
1689
1690 /*
1691 * We really need a better way to tell a 1000baseTX card
1692 * from a 1000baseSX one, since in theory there could be
1693 * OEMed 1000baseTX cards from lame vendors who aren't
1694 * clever enough to change the PCI ID. For the moment
1695 * though, the AceNIC is the only copper card available.
1696 */
1697 if (pci_get_vendor(dev) == ALT_VENDORID &&
1698 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1699 sc->ti_copper = 1;
1700 /* Ok, it's not the only copper card available. */
1701 if (pci_get_vendor(dev) == NG_VENDORID &&
1702 pci_get_device(dev) == NG_DEVICEID_GA620T)
1703 sc->ti_copper = 1;
1704
1705 /* Set default tuneable values. */
1706 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1707 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1708 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1709 sc->ti_rx_max_coal_bds = 64;
1710 sc->ti_tx_max_coal_bds = 128;
1711 sc->ti_tx_buf_ratio = 21;
1712
1713 /* Set up ifnet structure */
1714 ifp = &sc->arpcom.ac_if;
1715 ifp->if_softc = sc;
1716 ifp->if_unit = sc->ti_unit;
1717 ifp->if_name = "ti";
1718 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1719 ifp->if_ioctl = ti_ioctl;
1720 ifp->if_output = ether_output;
1721 ifp->if_start = ti_start;
1722 ifp->if_watchdog = ti_watchdog;
1723 ifp->if_init = ti_init;
1724 ifp->if_mtu = ETHERMTU;
1725 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
1726
1727 /* Set up ifmedia support. */
1728 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1729 if (sc->ti_copper) {
1730 /*
1731 * Copper cards allow manual 10/100 mode selection,
1732 * but not manual 1000baseTX mode selection. Why?
1733 * Becuase currently there's no way to specify the
1734 * master/slave setting through the firmware interface,
1735 * so Alteon decided to just bag it and handle it
1736 * via autonegotiation.
1737 */
1738 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1739 ifmedia_add(&sc->ifmedia,
1740 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1741 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1742 ifmedia_add(&sc->ifmedia,
1743 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1744 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL);
1745 ifmedia_add(&sc->ifmedia,
1746 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL);
1747 } else {
1748 /* Fiber cards don't support 10/100 modes. */
1749 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1750 ifmedia_add(&sc->ifmedia,
1751 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1752 }
1753 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1754 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1755
1756 /*
1757 * Call MI attach routine.
1758 */
1759 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1760
1761 fail:
1762 splx(s);
1763
1764 return(error);
1765 }
1766
1767 static int ti_detach(dev)
1768 device_t dev;
1769 {
1770 struct ti_softc *sc;
1771 struct ifnet *ifp;
1772 int s;
1773
1774 s = splimp();
1775
1776 sc = device_get_softc(dev);
1777 ifp = &sc->arpcom.ac_if;
1778
1779 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1780 ti_stop(sc);
1781
1782 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1783 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1784 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1785
1786 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1787 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1788 ifmedia_removeall(&sc->ifmedia);
1789
1790 splx(s);
1791
1792 return(0);
1793 }
1794
1795 /*
1796 * Frame reception handling. This is called if there's a frame
1797 * on the receive return list.
1798 *
1799 * Note: we have to be able to handle three possibilities here:
1800 * 1) the frame is from the mini receive ring (can only happen)
1801 * on Tigon 2 boards)
1802 * 2) the frame is from the jumbo recieve ring
1803 * 3) the frame is from the standard receive ring
1804 */
1805
1806 static void ti_rxeof(sc)
1807 struct ti_softc *sc;
1808 {
1809 struct ifnet *ifp;
1810 struct ti_cmd_desc cmd;
1811
1812 ifp = &sc->arpcom.ac_if;
1813
1814 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1815 struct ti_rx_desc *cur_rx;
1816 u_int32_t rxidx;
1817 struct ether_header *eh;
1818 struct mbuf *m = NULL;
1819 u_int16_t vlan_tag = 0;
1820 int have_tag = 0;
1821
1822 cur_rx =
1823 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1824 rxidx = cur_rx->ti_idx;
1825 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1826
1827 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1828 have_tag = 1;
1829 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1830 }
1831
1832 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1833 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1834 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1835 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1836 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1837 ifp->if_ierrors++;
1838 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1839 continue;
1840 }
1841 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1842 ifp->if_ierrors++;
1843 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1844 continue;
1845 }
1846 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1847 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1848 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1849 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1850 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1851 ifp->if_ierrors++;
1852 ti_newbuf_mini(sc, sc->ti_mini, m);
1853 continue;
1854 }
1855 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1856 ifp->if_ierrors++;
1857 ti_newbuf_mini(sc, sc->ti_mini, m);
1858 continue;
1859 }
1860 } else {
1861 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1862 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1863 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1864 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1865 ifp->if_ierrors++;
1866 ti_newbuf_std(sc, sc->ti_std, m);
1867 continue;
1868 }
1869 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1870 ifp->if_ierrors++;
1871 ti_newbuf_std(sc, sc->ti_std, m);
1872 continue;
1873 }
1874 }
1875
1876 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1877 ifp->if_ipackets++;
1878 eh = mtod(m, struct ether_header *);
1879 m->m_pkthdr.rcvif = ifp;
1880
1881 /* Remove header from mbuf and pass it on. */
1882 m_adj(m, sizeof(struct ether_header));
1883
1884 if (ifp->if_hwassist) {
1885 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1886 CSUM_DATA_VALID;
1887 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1888 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1889 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1890 }
1891
1892 /*
1893 * If we received a packet with a vlan tag, pass it
1894 * to vlan_input() instead of ether_input().
1895 */
1896 if (have_tag) {
1897 VLAN_INPUT_TAG(eh, m, vlan_tag);
1898 have_tag = vlan_tag = 0;
1899 continue;
1900 }
1901 ether_input(ifp, eh, m);
1902 }
1903
1904 /* Only necessary on the Tigon 1. */
1905 if (sc->ti_hwrev == TI_HWREV_TIGON)
1906 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1907 sc->ti_rx_saved_considx);
1908
1909 TI_UPDATE_STDPROD(sc, sc->ti_std);
1910 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1911 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1912
1913 return;
1914 }
1915
1916 static void ti_txeof(sc)
1917 struct ti_softc *sc;
1918 {
1919 struct ti_tx_desc *cur_tx = NULL;
1920 struct ifnet *ifp;
1921
1922 ifp = &sc->arpcom.ac_if;
1923
1924 /*
1925 * Go through our tx ring and free mbufs for those
1926 * frames that have been sent.
1927 */
1928 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1929 u_int32_t idx = 0;
1930
1931 idx = sc->ti_tx_saved_considx;
1932 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1933 if (idx > 383)
1934 CSR_WRITE_4(sc, TI_WINBASE,
1935 TI_TX_RING_BASE + 6144);
1936 else if (idx > 255)
1937 CSR_WRITE_4(sc, TI_WINBASE,
1938 TI_TX_RING_BASE + 4096);
1939 else if (idx > 127)
1940 CSR_WRITE_4(sc, TI_WINBASE,
1941 TI_TX_RING_BASE + 2048);
1942 else
1943 CSR_WRITE_4(sc, TI_WINBASE,
1944 TI_TX_RING_BASE);
1945 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1946 } else
1947 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1948 if (cur_tx->ti_flags & TI_BDFLAG_END)
1949 ifp->if_opackets++;
1950 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1951 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1952 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1953 }
1954 sc->ti_txcnt--;
1955 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1956 ifp->if_timer = 0;
1957 }
1958
1959 if (cur_tx != NULL)
1960 ifp->if_flags &= ~IFF_OACTIVE;
1961
1962 return;
1963 }
1964
1965 static void ti_intr(xsc)
1966 void *xsc;
1967 {
1968 struct ti_softc *sc;
1969 struct ifnet *ifp;
1970
1971 sc = xsc;
1972 ifp = &sc->arpcom.ac_if;
1973
1974 #ifdef notdef
1975 /* Avoid this for now -- checking this register is expensive. */
1976 /* Make sure this is really our interrupt. */
1977 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
1978 return;
1979 #endif
1980
1981 /* Ack interrupt and stop others from occuring. */
1982 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1983
1984 if (ifp->if_flags & IFF_RUNNING) {
1985 /* Check RX return ring producer/consumer */
1986 ti_rxeof(sc);
1987
1988 /* Check TX ring producer/consumer */
1989 ti_txeof(sc);
1990 }
1991
1992 ti_handle_events(sc);
1993
1994 /* Re-enable interrupts. */
1995 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1996
1997 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1998 ti_start(ifp);
1999
2000 return;
2001 }
2002
2003 static void ti_stats_update(sc)
2004 struct ti_softc *sc;
2005 {
2006 struct ifnet *ifp;
2007
2008 ifp = &sc->arpcom.ac_if;
2009
2010 ifp->if_collisions +=
2011 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2012 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2013 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2014 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2015 ifp->if_collisions;
2016
2017 return;
2018 }
2019
2020 /*
2021 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2022 * pointers to descriptors.
2023 */
2024 static int ti_encap(sc, m_head, txidx)
2025 struct ti_softc *sc;
2026 struct mbuf *m_head;
2027 u_int32_t *txidx;
2028 {
2029 struct ti_tx_desc *f = NULL;
2030 struct mbuf *m;
2031 u_int32_t frag, cur, cnt = 0;
2032 u_int16_t csum_flags = 0;
2033 struct ifvlan *ifv = NULL;
2034
2035 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2036 m_head->m_pkthdr.rcvif != NULL &&
2037 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2038 ifv = m_head->m_pkthdr.rcvif->if_softc;
2039
2040 m = m_head;
2041 cur = frag = *txidx;
2042
2043 if (m_head->m_pkthdr.csum_flags) {
2044 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2045 csum_flags |= TI_BDFLAG_IP_CKSUM;
2046 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2047 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2048 if (m_head->m_flags & M_LASTFRAG)
2049 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2050 else if (m_head->m_flags & M_FRAG)
2051 csum_flags |= TI_BDFLAG_IP_FRAG;
2052 }
2053 /*
2054 * Start packing the mbufs in this chain into
2055 * the fragment pointers. Stop when we run out
2056 * of fragments or hit the end of the mbuf chain.
2057 */
2058 for (m = m_head; m != NULL; m = m->m_next) {
2059 if (m->m_len != 0) {
2060 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2061 if (frag > 383)
2062 CSR_WRITE_4(sc, TI_WINBASE,
2063 TI_TX_RING_BASE + 6144);
2064 else if (frag > 255)
2065 CSR_WRITE_4(sc, TI_WINBASE,
2066 TI_TX_RING_BASE + 4096);
2067 else if (frag > 127)
2068 CSR_WRITE_4(sc, TI_WINBASE,
2069 TI_TX_RING_BASE + 2048);
2070 else
2071 CSR_WRITE_4(sc, TI_WINBASE,
2072 TI_TX_RING_BASE);
2073 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2074 } else
2075 f = &sc->ti_rdata->ti_tx_ring[frag];
2076 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2077 break;
2078 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2079 f->ti_len = m->m_len;
2080 f->ti_flags = csum_flags;
2081
2082 if (ifv != NULL) {
2083 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2084 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
2085 } else {
2086 f->ti_vlan_tag = 0;
2087 }
2088
2089 /*
2090 * Sanity check: avoid coming within 16 descriptors
2091 * of the end of the ring.
2092 */
2093 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2094 return(ENOBUFS);
2095 cur = frag;
2096 TI_INC(frag, TI_TX_RING_CNT);
2097 cnt++;
2098 }
2099 }
2100
2101 if (m != NULL)
2102 return(ENOBUFS);
2103
2104 if (frag == sc->ti_tx_saved_considx)
2105 return(ENOBUFS);
2106
2107 if (sc->ti_hwrev == TI_HWREV_TIGON)
2108 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2109 TI_BDFLAG_END;
2110 else
2111 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2112 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2113 sc->ti_txcnt += cnt;
2114
2115 *txidx = frag;
2116
2117 return(0);
2118 }
2119
2120 /*
2121 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2122 * to the mbuf data regions directly in the transmit descriptors.
2123 */
2124 static void ti_start(ifp)
2125 struct ifnet *ifp;
2126 {
2127 struct ti_softc *sc;
2128 struct mbuf *m_head = NULL;
2129 u_int32_t prodidx = 0;
2130
2131 sc = ifp->if_softc;
2132
2133 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2134
2135 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2136 IF_DEQUEUE(&ifp->if_snd, m_head);
2137 if (m_head == NULL)
2138 break;
2139
2140 /*
2141 * XXX
2142 * safety overkill. If this is a fragmented packet chain
2143 * with delayed TCP/UDP checksums, then only encapsulate
2144 * it if we have enough descriptors to handle the entire
2145 * chain at once.
2146 * (paranoia -- may not actually be needed)
2147 */
2148 if (m_head->m_flags & M_FIRSTFRAG &&
2149 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2150 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2151 m_head->m_pkthdr.csum_data + 16) {
2152 IF_PREPEND(&ifp->if_snd, m_head);
2153 ifp->if_flags |= IFF_OACTIVE;
2154 break;
2155 }
2156 }
2157
2158 /*
2159 * Pack the data into the transmit ring. If we
2160 * don't have room, set the OACTIVE flag and wait
2161 * for the NIC to drain the ring.
2162 */
2163 if (ti_encap(sc, m_head, &prodidx)) {
2164 IF_PREPEND(&ifp->if_snd, m_head);
2165 ifp->if_flags |= IFF_OACTIVE;
2166 break;
2167 }
2168
2169 /*
2170 * If there's a BPF listener, bounce a copy of this frame
2171 * to him.
2172 */
2173 if (ifp->if_bpf)
2174 bpf_mtap(ifp, m_head);
2175 }
2176
2177 /* Transmit */
2178 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2179
2180 /*
2181 * Set a timeout in case the chip goes out to lunch.
2182 */
2183 ifp->if_timer = 5;
2184
2185 return;
2186 }
2187
2188 static void ti_init(xsc)
2189 void *xsc;
2190 {
2191 struct ti_softc *sc = xsc;
2192 int s;
2193
2194 s = splimp();
2195
2196 /* Cancel pending I/O and flush buffers. */
2197 ti_stop(sc);
2198
2199 /* Init the gen info block, ring control blocks and firmware. */
2200 if (ti_gibinit(sc)) {
2201 printf("ti%d: initialization failure\n", sc->ti_unit);
2202 splx(s);
2203 return;
2204 }
2205
2206 splx(s);
2207
2208 return;
2209 }
2210
2211 static void ti_init2(sc)
2212 struct ti_softc *sc;
2213 {
2214 struct ti_cmd_desc cmd;
2215 struct ifnet *ifp;
2216 u_int16_t *m;
2217 struct ifmedia *ifm;
2218 int tmp;
2219
2220 ifp = &sc->arpcom.ac_if;
2221
2222 /* Specify MTU and interface index. */
2223 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit);
2224 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2225 ETHER_HDR_LEN + ETHER_CRC_LEN);
2226 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2227
2228 /* Load our MAC address. */
2229 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2230 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2231 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2232 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2233
2234 /* Enable or disable promiscuous mode as needed. */
2235 if (ifp->if_flags & IFF_PROMISC) {
2236 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2237 } else {
2238 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2239 }
2240
2241 /* Program multicast filter. */
2242 ti_setmulti(sc);
2243
2244 /*
2245 * If this is a Tigon 1, we should tell the
2246 * firmware to use software packet filtering.
2247 */
2248 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2249 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2250 }
2251
2252 /* Init RX ring. */
2253 ti_init_rx_ring_std(sc);
2254
2255 /* Init jumbo RX ring. */
2256 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2257 ti_init_rx_ring_jumbo(sc);
2258
2259 /*
2260 * If this is a Tigon 2, we can also configure the
2261 * mini ring.
2262 */
2263 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2264 ti_init_rx_ring_mini(sc);
2265
2266 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2267 sc->ti_rx_saved_considx = 0;
2268
2269 /* Init TX ring. */
2270 ti_init_tx_ring(sc);
2271
2272 /* Tell firmware we're alive. */
2273 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2274
2275 /* Enable host interrupts. */
2276 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2277
2278 ifp->if_flags |= IFF_RUNNING;
2279 ifp->if_flags &= ~IFF_OACTIVE;
2280
2281 /*
2282 * Make sure to set media properly. We have to do this
2283 * here since we have to issue commands in order to set
2284 * the link negotiation and we can't issue commands until
2285 * the firmware is running.
2286 */
2287 ifm = &sc->ifmedia;
2288 tmp = ifm->ifm_media;
2289 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2290 ti_ifmedia_upd(ifp);
2291 ifm->ifm_media = tmp;
2292
2293 return;
2294 }
2295
2296 /*
2297 * Set media options.
2298 */
2299 static int ti_ifmedia_upd(ifp)
2300 struct ifnet *ifp;
2301 {
2302 struct ti_softc *sc;
2303 struct ifmedia *ifm;
2304 struct ti_cmd_desc cmd;
2305
2306 sc = ifp->if_softc;
2307 ifm = &sc->ifmedia;
2308
2309 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2310 return(EINVAL);
2311
2312 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2313 case IFM_AUTO:
2314 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2315 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2316 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2317 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2318 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2319 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2320 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2321 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2322 break;
2323 case IFM_1000_SX:
2324 case IFM_1000_TX:
2325 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2326 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2327 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2328 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2329 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2330 }
2331 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2332 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2333 break;
2334 case IFM_100_FX:
2335 case IFM_10_FL:
2336 case IFM_100_TX:
2337 case IFM_10_T:
2338 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2339 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2340 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2341 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2342 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2343 } else {
2344 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2345 }
2346 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2347 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2348 } else {
2349 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2350 }
2351 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2352 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2353 break;
2354 }
2355
2356 return(0);
2357 }
2358
2359 /*
2360 * Report current media status.
2361 */
2362 static void ti_ifmedia_sts(ifp, ifmr)
2363 struct ifnet *ifp;
2364 struct ifmediareq *ifmr;
2365 {
2366 struct ti_softc *sc;
2367 u_int32_t media = 0;
2368
2369 sc = ifp->if_softc;
2370
2371 ifmr->ifm_status = IFM_AVALID;
2372 ifmr->ifm_active = IFM_ETHER;
2373
2374 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2375 return;
2376
2377 ifmr->ifm_status |= IFM_ACTIVE;
2378
2379 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2380 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2381 if (sc->ti_copper)
2382 ifmr->ifm_active |= IFM_1000_TX;
2383 else
2384 ifmr->ifm_active |= IFM_1000_SX;
2385 if (media & TI_GLNK_FULL_DUPLEX)
2386 ifmr->ifm_active |= IFM_FDX;
2387 else
2388 ifmr->ifm_active |= IFM_HDX;
2389 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2390 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2391 if (sc->ti_copper) {
2392 if (media & TI_LNK_100MB)
2393 ifmr->ifm_active |= IFM_100_TX;
2394 if (media & TI_LNK_10MB)
2395 ifmr->ifm_active |= IFM_10_T;
2396 } else {
2397 if (media & TI_LNK_100MB)
2398 ifmr->ifm_active |= IFM_100_FX;
2399 if (media & TI_LNK_10MB)
2400 ifmr->ifm_active |= IFM_10_FL;
2401 }
2402 if (media & TI_LNK_FULL_DUPLEX)
2403 ifmr->ifm_active |= IFM_FDX;
2404 if (media & TI_LNK_HALF_DUPLEX)
2405 ifmr->ifm_active |= IFM_HDX;
2406 }
2407
2408 return;
2409 }
2410
2411 static int ti_ioctl(ifp, command, data)
2412 struct ifnet *ifp;
2413 u_long command;
2414 caddr_t data;
2415 {
2416 struct ti_softc *sc = ifp->if_softc;
2417 struct ifreq *ifr = (struct ifreq *) data;
2418 int s, mask, error = 0;
2419 struct ti_cmd_desc cmd;
2420
2421 s = splimp();
2422
2423 switch(command) {
2424 case SIOCSIFADDR:
2425 case SIOCGIFADDR:
2426 error = ether_ioctl(ifp, command, data);
2427 break;
2428 case SIOCSIFMTU:
2429 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2430 error = EINVAL;
2431 else {
2432 ifp->if_mtu = ifr->ifr_mtu;
2433 ti_init(sc);
2434 }
2435 break;
2436 case SIOCSIFFLAGS:
2437 if (ifp->if_flags & IFF_UP) {
2438 /*
2439 * If only the state of the PROMISC flag changed,
2440 * then just use the 'set promisc mode' command
2441 * instead of reinitializing the entire NIC. Doing
2442 * a full re-init means reloading the firmware and
2443 * waiting for it to start up, which may take a
2444 * second or two.
2445 */
2446 if (ifp->if_flags & IFF_RUNNING &&
2447 ifp->if_flags & IFF_PROMISC &&
2448 !(sc->ti_if_flags & IFF_PROMISC)) {
2449 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2450 TI_CMD_CODE_PROMISC_ENB, 0);
2451 } else if (ifp->if_flags & IFF_RUNNING &&
2452 !(ifp->if_flags & IFF_PROMISC) &&
2453 sc->ti_if_flags & IFF_PROMISC) {
2454 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2455 TI_CMD_CODE_PROMISC_DIS, 0);
2456 } else
2457 ti_init(sc);
2458 } else {
2459 if (ifp->if_flags & IFF_RUNNING) {
2460 ti_stop(sc);
2461 }
2462 }
2463 sc->ti_if_flags = ifp->if_flags;
2464 error = 0;
2465 break;
2466 case SIOCADDMULTI:
2467 case SIOCDELMULTI:
2468 if (ifp->if_flags & IFF_RUNNING) {
2469 ti_setmulti(sc);
2470 error = 0;
2471 }
2472 break;
2473 case SIOCSIFMEDIA:
2474 case SIOCGIFMEDIA:
2475 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2476 break;
2477 case SIOCSIFCAP:
2478 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2479 if (mask & IFCAP_HWCSUM) {
2480 if (IFCAP_HWCSUM & ifp->if_capenable)
2481 ifp->if_capenable &= ~IFCAP_HWCSUM;
2482 else
2483 ifp->if_capenable |= IFCAP_HWCSUM;
2484 if (ifp->if_flags & IFF_RUNNING)
2485 ti_init(sc);
2486 }
2487 error = 0;
2488 break;
2489 default:
2490 error = EINVAL;
2491 break;
2492 }
2493
2494 (void)splx(s);
2495
2496 return(error);
2497 }
2498
2499 static void ti_watchdog(ifp)
2500 struct ifnet *ifp;
2501 {
2502 struct ti_softc *sc;
2503
2504 sc = ifp->if_softc;
2505
2506 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2507 ti_stop(sc);
2508 ti_init(sc);
2509
2510 ifp->if_oerrors++;
2511
2512 return;
2513 }
2514
2515 /*
2516 * Stop the adapter and free any mbufs allocated to the
2517 * RX and TX lists.
2518 */
2519 static void ti_stop(sc)
2520 struct ti_softc *sc;
2521 {
2522 struct ifnet *ifp;
2523 struct ti_cmd_desc cmd;
2524
2525 ifp = &sc->arpcom.ac_if;
2526
2527 /* Disable host interrupts. */
2528 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2529 /*
2530 * Tell firmware we're shutting down.
2531 */
2532 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2533
2534 /* Halt and reinitialize. */
2535 ti_chipinit(sc);
2536 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2537 ti_chipinit(sc);
2538
2539 /* Free the RX lists. */
2540 ti_free_rx_ring_std(sc);
2541
2542 /* Free jumbo RX list. */
2543 ti_free_rx_ring_jumbo(sc);
2544
2545 /* Free mini RX list. */
2546 ti_free_rx_ring_mini(sc);
2547
2548 /* Free TX buffers. */
2549 ti_free_tx_ring(sc);
2550
2551 sc->ti_ev_prodidx.ti_idx = 0;
2552 sc->ti_return_prodidx.ti_idx = 0;
2553 sc->ti_tx_considx.ti_idx = 0;
2554 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2555
2556 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2557
2558 return;
2559 }
2560
2561 /*
2562 * Stop all chip I/O so that the kernel's probe routines don't
2563 * get confused by errant DMAs when rebooting.
2564 */
2565 static void ti_shutdown(dev)
2566 device_t dev;
2567 {
2568 struct ti_softc *sc;
2569
2570 sc = device_get_softc(dev);
2571
2572 ti_chipinit(sc);
2573
2574 return;
2575 }
Cache object: 40e5184d963ec9d989f6a18ebea7cca7
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