FreeBSD/Linux Kernel Cross Reference
sys/pci/if_ti.c
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
37 *
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
41 */
42
43 /*
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
50 * initialization.
51 *
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
55 *
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
60 * stellar example.
61 *
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
68 *
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
71 * for testing
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
77 */
78
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD: releng/5.1/sys/pci/if_ti.c 113812 2003-04-21 18:34:04Z imp $");
81
82 #include "opt_ti.h"
83
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
87 #include <sys/mbuf.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/socket.h>
91 #include <sys/queue.h>
92 #include <sys/conf.h>
93
94 #include <net/if.h>
95 #include <net/if_arp.h>
96 #include <net/ethernet.h>
97 #include <net/if_dl.h>
98 #include <net/if_media.h>
99 #include <net/if_types.h>
100 #include <net/if_vlan_var.h>
101
102 #include <net/bpf.h>
103
104 #include <netinet/in_systm.h>
105 #include <netinet/in.h>
106 #include <netinet/ip.h>
107
108 #include <vm/vm.h> /* for vtophys */
109 #include <vm/pmap.h> /* for vtophys */
110 #include <machine/bus_memio.h>
111 #include <machine/bus.h>
112 #include <machine/resource.h>
113 #include <sys/bus.h>
114 #include <sys/rman.h>
115
116 /* #define TI_PRIVATE_JUMBOS */
117
118 #if !defined(TI_PRIVATE_JUMBOS)
119 #include <sys/sockio.h>
120 #include <sys/uio.h>
121 #include <sys/lock.h>
122 #include <vm/vm_extern.h>
123 #include <vm/pmap.h>
124 #include <vm/vm_map.h>
125 #include <vm/vm_map.h>
126 #include <vm/vm_param.h>
127 #include <vm/vm_pageout.h>
128 #include <sys/vmmeter.h>
129 #include <vm/vm_page.h>
130 #include <vm/vm_object.h>
131 #include <vm/vm_kern.h>
132 #include <sys/proc.h>
133 #include <sys/jumbo.h>
134 #endif /* !TI_PRIVATE_JUMBOS */
135 #include <sys/vnode.h> /* for vfindev, vgone */
136
137 #include <pci/pcireg.h>
138 #include <pci/pcivar.h>
139
140 #include <sys/tiio.h>
141 #include <pci/if_tireg.h>
142 #include <pci/ti_fw.h>
143 #include <pci/ti_fw2.h>
144
145 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
146 /*
147 * We can only turn on header splitting if we're using extended receive
148 * BDs.
149 */
150 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
151 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
152 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
153
154 struct ti_softc *tis[8];
155
156 typedef enum {
157 TI_SWAP_HTON,
158 TI_SWAP_NTOH
159 } ti_swap_type;
160
161
162 /*
163 * Various supported device vendors/types and their names.
164 */
165
166 static struct ti_type ti_devs[] = {
167 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
168 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
169 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
170 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
171 { TC_VENDORID, TC_DEVICEID_3C985,
172 "3Com 3c985-SX Gigabit Ethernet" },
173 { NG_VENDORID, NG_DEVICEID_GA620,
174 "Netgear GA620 1000baseSX Gigabit Ethernet" },
175 { NG_VENDORID, NG_DEVICEID_GA620T,
176 "Netgear GA620 1000baseT Gigabit Ethernet" },
177 { SGI_VENDORID, SGI_DEVICEID_TIGON,
178 "Silicon Graphics Gigabit Ethernet" },
179 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
180 "Farallon PN9000SX Gigabit Ethernet" },
181 { 0, 0, NULL }
182 };
183
184 #define TI_CDEV_MAJOR 153
185
186 static d_open_t ti_open;
187 static d_close_t ti_close;
188 static d_ioctl_t ti_ioctl2;
189
190 static struct cdevsw ti_cdevsw = {
191 .d_open = ti_open,
192 .d_close = ti_close,
193 .d_ioctl = ti_ioctl2,
194 .d_name = "ti",
195 .d_maj = TI_CDEV_MAJOR,
196 };
197
198 static int ti_probe (device_t);
199 static int ti_attach (device_t);
200 static int ti_detach (device_t);
201 static void ti_txeof (struct ti_softc *);
202 static void ti_rxeof (struct ti_softc *);
203
204 static void ti_stats_update (struct ti_softc *);
205 static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *);
206
207 static void ti_intr (void *);
208 static void ti_start (struct ifnet *);
209 static int ti_ioctl (struct ifnet *, u_long, caddr_t);
210 static void ti_init (void *);
211 static void ti_init2 (struct ti_softc *);
212 static void ti_stop (struct ti_softc *);
213 static void ti_watchdog (struct ifnet *);
214 static void ti_shutdown (device_t);
215 static int ti_ifmedia_upd (struct ifnet *);
216 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *);
217
218 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int);
219 static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *);
220 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int);
221
222 static void ti_add_mcast (struct ti_softc *, struct ether_addr *);
223 static void ti_del_mcast (struct ti_softc *, struct ether_addr *);
224 static void ti_setmulti (struct ti_softc *);
225
226 static void ti_mem (struct ti_softc *, u_int32_t,
227 u_int32_t, caddr_t);
228 static int ti_copy_mem (struct ti_softc *, u_int32_t,
229 u_int32_t, caddr_t, int, int);
230 static int ti_copy_scratch (struct ti_softc *, u_int32_t,
231 u_int32_t, caddr_t, int, int, int);
232 static int ti_bcopy_swap (const void *, void *, size_t,
233 ti_swap_type);
234 static void ti_loadfw (struct ti_softc *);
235 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *);
236 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *,
237 caddr_t, int);
238 static void ti_handle_events (struct ti_softc *);
239 #ifdef TI_PRIVATE_JUMBOS
240 static int ti_alloc_jumbo_mem (struct ti_softc *);
241 static void *ti_jalloc (struct ti_softc *);
242 static void ti_jfree (void *, void *);
243 #endif /* TI_PRIVATE_JUMBOS */
244 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *);
245 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *);
246 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *);
247 static int ti_init_rx_ring_std (struct ti_softc *);
248 static void ti_free_rx_ring_std (struct ti_softc *);
249 static int ti_init_rx_ring_jumbo (struct ti_softc *);
250 static void ti_free_rx_ring_jumbo (struct ti_softc *);
251 static int ti_init_rx_ring_mini (struct ti_softc *);
252 static void ti_free_rx_ring_mini (struct ti_softc *);
253 static void ti_free_tx_ring (struct ti_softc *);
254 static int ti_init_tx_ring (struct ti_softc *);
255
256 static int ti_64bitslot_war (struct ti_softc *);
257 static int ti_chipinit (struct ti_softc *);
258 static int ti_gibinit (struct ti_softc *);
259
260 #ifdef TI_JUMBO_HDRSPLIT
261 static __inline void ti_hdr_split (struct mbuf *top, int hdr_len,
262 int pkt_len, int idx);
263 #endif /* TI_JUMBO_HDRSPLIT */
264
265 static device_method_t ti_methods[] = {
266 /* Device interface */
267 DEVMETHOD(device_probe, ti_probe),
268 DEVMETHOD(device_attach, ti_attach),
269 DEVMETHOD(device_detach, ti_detach),
270 DEVMETHOD(device_shutdown, ti_shutdown),
271 { 0, 0 }
272 };
273
274 static driver_t ti_driver = {
275 "ti",
276 ti_methods,
277 sizeof(struct ti_softc)
278 };
279
280 static devclass_t ti_devclass;
281
282 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
283 MODULE_DEPEND(ti, pci, 1, 1, 1);
284 MODULE_DEPEND(ti, ether, 1, 1, 1);
285
286 /* List of Tigon softcs */
287 static STAILQ_HEAD(ti_softc_list, ti_softc) ti_sc_list;
288
289 static struct ti_softc *
290 ti_lookup_softc(int unit)
291 {
292 struct ti_softc *sc;
293 for (sc = STAILQ_FIRST(&ti_sc_list); sc != NULL;
294 sc = STAILQ_NEXT(sc, ti_links))
295 if (sc->ti_unit == unit)
296 return(sc);
297 return(NULL);
298 }
299
300 /*
301 * Send an instruction or address to the EEPROM, check for ACK.
302 */
303 static u_int32_t ti_eeprom_putbyte(sc, byte)
304 struct ti_softc *sc;
305 int byte;
306 {
307 register int i, ack = 0;
308
309 /*
310 * Make sure we're in TX mode.
311 */
312 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
313
314 /*
315 * Feed in each bit and stobe the clock.
316 */
317 for (i = 0x80; i; i >>= 1) {
318 if (byte & i) {
319 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
320 } else {
321 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
322 }
323 DELAY(1);
324 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
325 DELAY(1);
326 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
327 }
328
329 /*
330 * Turn off TX mode.
331 */
332 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
333
334 /*
335 * Check for ack.
336 */
337 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
338 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
339 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
340
341 return(ack);
342 }
343
344 /*
345 * Read a byte of data stored in the EEPROM at address 'addr.'
346 * We have to send two address bytes since the EEPROM can hold
347 * more than 256 bytes of data.
348 */
349 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
350 struct ti_softc *sc;
351 int addr;
352 u_int8_t *dest;
353 {
354 register int i;
355 u_int8_t byte = 0;
356
357 EEPROM_START;
358
359 /*
360 * Send write control code to EEPROM.
361 */
362 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
363 printf("ti%d: failed to send write command, status: %x\n",
364 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
365 return(1);
366 }
367
368 /*
369 * Send first byte of address of byte we want to read.
370 */
371 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
372 printf("ti%d: failed to send address, status: %x\n",
373 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
374 return(1);
375 }
376 /*
377 * Send second byte address of byte we want to read.
378 */
379 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
380 printf("ti%d: failed to send address, status: %x\n",
381 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
382 return(1);
383 }
384
385 EEPROM_STOP;
386 EEPROM_START;
387 /*
388 * Send read control code to EEPROM.
389 */
390 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
391 printf("ti%d: failed to send read command, status: %x\n",
392 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
393 return(1);
394 }
395
396 /*
397 * Start reading bits from EEPROM.
398 */
399 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
400 for (i = 0x80; i; i >>= 1) {
401 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
402 DELAY(1);
403 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
404 byte |= i;
405 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
406 DELAY(1);
407 }
408
409 EEPROM_STOP;
410
411 /*
412 * No ACK generated for read, so just return byte.
413 */
414
415 *dest = byte;
416
417 return(0);
418 }
419
420 /*
421 * Read a sequence of bytes from the EEPROM.
422 */
423 static int
424 ti_read_eeprom(sc, dest, off, cnt)
425 struct ti_softc *sc;
426 caddr_t dest;
427 int off;
428 int cnt;
429 {
430 int err = 0, i;
431 u_int8_t byte = 0;
432
433 for (i = 0; i < cnt; i++) {
434 err = ti_eeprom_getbyte(sc, off + i, &byte);
435 if (err)
436 break;
437 *(dest + i) = byte;
438 }
439
440 return(err ? 1 : 0);
441 }
442
443 /*
444 * NIC memory access function. Can be used to either clear a section
445 * of NIC local memory or (if buf is non-NULL) copy data into it.
446 */
447 static void
448 ti_mem(sc, addr, len, buf)
449 struct ti_softc *sc;
450 u_int32_t addr, len;
451 caddr_t buf;
452 {
453 int segptr, segsize, cnt;
454 caddr_t ti_winbase, ptr;
455
456 segptr = addr;
457 cnt = len;
458 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
459 ptr = buf;
460
461 while(cnt) {
462 if (cnt < TI_WINLEN)
463 segsize = cnt;
464 else
465 segsize = TI_WINLEN - (segptr % TI_WINLEN);
466 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
467 if (buf == NULL)
468 bzero((char *)ti_winbase + (segptr &
469 (TI_WINLEN - 1)), segsize);
470 else {
471 bcopy((char *)ptr, (char *)ti_winbase +
472 (segptr & (TI_WINLEN - 1)), segsize);
473 ptr += segsize;
474 }
475 segptr += segsize;
476 cnt -= segsize;
477 }
478
479 return;
480 }
481
482 static int
483 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata)
484 struct ti_softc *sc;
485 u_int32_t tigon_addr, len;
486 caddr_t buf;
487 int useraddr, readdata;
488 {
489 int segptr, segsize, cnt;
490 caddr_t ptr;
491 u_int32_t origwin;
492 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
493 int resid, segresid;
494 int first_pass;
495
496 /*
497 * At the moment, we don't handle non-aligned cases, we just bail.
498 * If this proves to be a problem, it will be fixed.
499 */
500 if ((readdata == 0)
501 && (tigon_addr & 0x3)) {
502 printf("ti%d: ti_copy_mem: tigon address %#x isn't "
503 "word-aligned\n", sc->ti_unit, tigon_addr);
504 printf("ti%d: ti_copy_mem: unaligned writes aren't yet "
505 "supported\n", sc->ti_unit);
506 return(EINVAL);
507 }
508
509 segptr = tigon_addr & ~0x3;
510 segresid = tigon_addr - segptr;
511
512 /*
513 * This is the non-aligned amount left over that we'll need to
514 * copy.
515 */
516 resid = len & 0x3;
517
518 /* Add in the left over amount at the front of the buffer */
519 resid += segresid;
520
521 cnt = len & ~0x3;
522 /*
523 * If resid + segresid is >= 4, add multiples of 4 to the count and
524 * decrease the residual by that much.
525 */
526 cnt += resid & ~0x3;
527 resid -= resid & ~0x3;
528
529 ptr = buf;
530
531 first_pass = 1;
532
533 /*
534 * Make sure we aren't interrupted while we're changing the window
535 * pointer.
536 */
537 TI_LOCK(sc);
538
539 /*
540 * Save the old window base value.
541 */
542 origwin = CSR_READ_4(sc, TI_WINBASE);
543
544 while(cnt) {
545 bus_size_t ti_offset;
546
547 if (cnt < TI_WINLEN)
548 segsize = cnt;
549 else
550 segsize = TI_WINLEN - (segptr % TI_WINLEN);
551 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
552
553 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
554
555 if (readdata) {
556
557 bus_space_read_region_4(sc->ti_btag,
558 sc->ti_bhandle, ti_offset,
559 (u_int32_t *)tmparray,
560 segsize >> 2);
561 if (useraddr) {
562 /*
563 * Yeah, this is a little on the kludgy
564 * side, but at least this code is only
565 * used for debugging.
566 */
567 ti_bcopy_swap(tmparray, tmparray2, segsize,
568 TI_SWAP_NTOH);
569
570 if (first_pass) {
571 copyout(&tmparray2[segresid], ptr,
572 segsize - segresid);
573 first_pass = 0;
574 } else
575 copyout(tmparray2, ptr, segsize);
576 } else {
577 if (first_pass) {
578
579 ti_bcopy_swap(tmparray, tmparray2,
580 segsize, TI_SWAP_NTOH);
581 bcopy(&tmparray2[segresid], ptr,
582 segsize - segresid);
583 first_pass = 0;
584 } else
585 ti_bcopy_swap(tmparray, ptr, segsize,
586 TI_SWAP_NTOH);
587 }
588
589 } else {
590 if (useraddr) {
591 copyin(ptr, tmparray2, segsize);
592 ti_bcopy_swap(tmparray2, tmparray, segsize,
593 TI_SWAP_HTON);
594 } else
595 ti_bcopy_swap(ptr, tmparray, segsize,
596 TI_SWAP_HTON);
597
598 bus_space_write_region_4(sc->ti_btag,
599 sc->ti_bhandle, ti_offset,
600 (u_int32_t *)tmparray,
601 segsize >> 2);
602 }
603 segptr += segsize;
604 ptr += segsize;
605 cnt -= segsize;
606 }
607
608 /*
609 * Handle leftover, non-word-aligned bytes.
610 */
611 if (resid != 0) {
612 u_int32_t tmpval, tmpval2;
613 bus_size_t ti_offset;
614
615 /*
616 * Set the segment pointer.
617 */
618 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
619
620 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
621
622 /*
623 * First, grab whatever is in our source/destination.
624 * We'll obviously need this for reads, but also for
625 * writes, since we'll be doing read/modify/write.
626 */
627 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
628 ti_offset, &tmpval, 1);
629
630 /*
631 * Next, translate this from little-endian to big-endian
632 * (at least on i386 boxes).
633 */
634 tmpval2 = ntohl(tmpval);
635
636 if (readdata) {
637 /*
638 * If we're reading, just copy the leftover number
639 * of bytes from the host byte order buffer to
640 * the user's buffer.
641 */
642 if (useraddr)
643 copyout(&tmpval2, ptr, resid);
644 else
645 bcopy(&tmpval2, ptr, resid);
646 } else {
647 /*
648 * If we're writing, first copy the bytes to be
649 * written into the network byte order buffer,
650 * leaving the rest of the buffer with whatever was
651 * originally in there. Then, swap the bytes
652 * around into host order and write them out.
653 *
654 * XXX KDM the read side of this has been verified
655 * to work, but the write side of it has not been
656 * verified. So user beware.
657 */
658 if (useraddr)
659 copyin(ptr, &tmpval2, resid);
660 else
661 bcopy(ptr, &tmpval2, resid);
662
663 tmpval = htonl(tmpval2);
664
665 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
666 ti_offset, &tmpval, 1);
667 }
668 }
669
670 CSR_WRITE_4(sc, TI_WINBASE, origwin);
671
672 TI_UNLOCK(sc);
673
674 return(0);
675 }
676
677 static int
678 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu)
679 struct ti_softc *sc;
680 u_int32_t tigon_addr, len;
681 caddr_t buf;
682 int useraddr, readdata;
683 int cpu;
684 {
685 u_int32_t segptr;
686 int cnt;
687 u_int32_t tmpval, tmpval2;
688 caddr_t ptr;
689
690 /*
691 * At the moment, we don't handle non-aligned cases, we just bail.
692 * If this proves to be a problem, it will be fixed.
693 */
694 if (tigon_addr & 0x3) {
695 printf("ti%d: ti_copy_scratch: tigon address %#x isn't "
696 "word-aligned\n", sc->ti_unit, tigon_addr);
697 return(EINVAL);
698 }
699
700 if (len & 0x3) {
701 printf("ti%d: ti_copy_scratch: transfer length %d isn't "
702 "word-aligned\n", sc->ti_unit, len);
703 return(EINVAL);
704 }
705
706 segptr = tigon_addr;
707 cnt = len;
708 ptr = buf;
709
710 TI_LOCK(sc);
711
712 while (cnt) {
713 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
714
715 if (readdata) {
716 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
717
718 tmpval = ntohl(tmpval2);
719
720 /*
721 * Note: I've used this debugging interface
722 * extensively with Alteon's 12.3.15 firmware,
723 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
724 *
725 * When you compile the firmware without
726 * optimization, which is necessary sometimes in
727 * order to properly step through it, you sometimes
728 * read out a bogus value of 0xc0017c instead of
729 * whatever was supposed to be in that scratchpad
730 * location. That value is on the stack somewhere,
731 * but I've never been able to figure out what was
732 * causing the problem.
733 *
734 * The address seems to pop up in random places,
735 * often not in the same place on two subsequent
736 * reads.
737 *
738 * In any case, the underlying data doesn't seem
739 * to be affected, just the value read out.
740 *
741 * KDM, 3/7/2000
742 */
743
744 if (tmpval2 == 0xc0017c)
745 printf("ti%d: found 0xc0017c at %#x "
746 "(tmpval2)\n", sc->ti_unit, segptr);
747
748 if (tmpval == 0xc0017c)
749 printf("ti%d: found 0xc0017c at %#x "
750 "(tmpval)\n", sc->ti_unit, segptr);
751
752 if (useraddr)
753 copyout(&tmpval, ptr, 4);
754 else
755 bcopy(&tmpval, ptr, 4);
756 } else {
757 if (useraddr)
758 copyin(ptr, &tmpval2, 4);
759 else
760 bcopy(ptr, &tmpval2, 4);
761
762 tmpval = htonl(tmpval2);
763
764 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
765 }
766
767 cnt -= 4;
768 segptr += 4;
769 ptr += 4;
770 }
771
772 TI_UNLOCK(sc);
773
774 return(0);
775 }
776
777 static int
778 ti_bcopy_swap(src, dst, len, swap_type)
779 const void *src;
780 void *dst;
781 size_t len;
782 ti_swap_type swap_type;
783 {
784 const u_int8_t *tmpsrc;
785 u_int8_t *tmpdst;
786 size_t tmplen;
787
788 if (len & 0x3) {
789 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
790 len);
791 return(-1);
792 }
793
794 tmpsrc = src;
795 tmpdst = dst;
796 tmplen = len;
797
798 while (tmplen) {
799 if (swap_type == TI_SWAP_NTOH)
800 *(u_int32_t *)tmpdst =
801 ntohl(*(const u_int32_t *)tmpsrc);
802 else
803 *(u_int32_t *)tmpdst =
804 htonl(*(const u_int32_t *)tmpsrc);
805
806 tmpsrc += 4;
807 tmpdst += 4;
808 tmplen -= 4;
809 }
810
811 return(0);
812 }
813
814 /*
815 * Load firmware image into the NIC. Check that the firmware revision
816 * is acceptable and see if we want the firmware for the Tigon 1 or
817 * Tigon 2.
818 */
819 static void
820 ti_loadfw(sc)
821 struct ti_softc *sc;
822 {
823 switch(sc->ti_hwrev) {
824 case TI_HWREV_TIGON:
825 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
826 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
827 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
828 printf("ti%d: firmware revision mismatch; want "
829 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
830 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
831 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
832 tigonFwReleaseMinor, tigonFwReleaseFix);
833 return;
834 }
835 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
836 (caddr_t)tigonFwText);
837 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
838 (caddr_t)tigonFwData);
839 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
840 (caddr_t)tigonFwRodata);
841 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
842 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
843 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
844 break;
845 case TI_HWREV_TIGON_II:
846 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
847 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
848 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
849 printf("ti%d: firmware revision mismatch; want "
850 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
851 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
852 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
853 tigon2FwReleaseMinor, tigon2FwReleaseFix);
854 return;
855 }
856 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
857 (caddr_t)tigon2FwText);
858 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
859 (caddr_t)tigon2FwData);
860 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
861 (caddr_t)tigon2FwRodata);
862 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
863 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
864 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
865 break;
866 default:
867 printf("ti%d: can't load firmware: unknown hardware rev\n",
868 sc->ti_unit);
869 break;
870 }
871
872 return;
873 }
874
875 /*
876 * Send the NIC a command via the command ring.
877 */
878 static void
879 ti_cmd(sc, cmd)
880 struct ti_softc *sc;
881 struct ti_cmd_desc *cmd;
882 {
883 u_int32_t index;
884
885 if (sc->ti_rdata->ti_cmd_ring == NULL)
886 return;
887
888 index = sc->ti_cmd_saved_prodidx;
889 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
890 TI_INC(index, TI_CMD_RING_CNT);
891 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
892 sc->ti_cmd_saved_prodidx = index;
893
894 return;
895 }
896
897 /*
898 * Send the NIC an extended command. The 'len' parameter specifies the
899 * number of command slots to include after the initial command.
900 */
901 static void
902 ti_cmd_ext(sc, cmd, arg, len)
903 struct ti_softc *sc;
904 struct ti_cmd_desc *cmd;
905 caddr_t arg;
906 int len;
907 {
908 u_int32_t index;
909 register int i;
910
911 if (sc->ti_rdata->ti_cmd_ring == NULL)
912 return;
913
914 index = sc->ti_cmd_saved_prodidx;
915 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
916 TI_INC(index, TI_CMD_RING_CNT);
917 for (i = 0; i < len; i++) {
918 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
919 *(u_int32_t *)(&arg[i * 4]));
920 TI_INC(index, TI_CMD_RING_CNT);
921 }
922 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
923 sc->ti_cmd_saved_prodidx = index;
924
925 return;
926 }
927
928 /*
929 * Handle events that have triggered interrupts.
930 */
931 static void
932 ti_handle_events(sc)
933 struct ti_softc *sc;
934 {
935 struct ti_event_desc *e;
936
937 if (sc->ti_rdata->ti_event_ring == NULL)
938 return;
939
940 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
941 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
942 switch(e->ti_event) {
943 case TI_EV_LINKSTAT_CHANGED:
944 sc->ti_linkstat = e->ti_code;
945 if (e->ti_code == TI_EV_CODE_LINK_UP)
946 printf("ti%d: 10/100 link up\n", sc->ti_unit);
947 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
948 printf("ti%d: gigabit link up\n", sc->ti_unit);
949 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
950 printf("ti%d: link down\n", sc->ti_unit);
951 break;
952 case TI_EV_ERROR:
953 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
954 printf("ti%d: invalid command\n", sc->ti_unit);
955 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
956 printf("ti%d: unknown command\n", sc->ti_unit);
957 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
958 printf("ti%d: bad config data\n", sc->ti_unit);
959 break;
960 case TI_EV_FIRMWARE_UP:
961 ti_init2(sc);
962 break;
963 case TI_EV_STATS_UPDATED:
964 ti_stats_update(sc);
965 break;
966 case TI_EV_RESET_JUMBO_RING:
967 case TI_EV_MCAST_UPDATED:
968 /* Who cares. */
969 break;
970 default:
971 printf("ti%d: unknown event: %d\n",
972 sc->ti_unit, e->ti_event);
973 break;
974 }
975 /* Advance the consumer index. */
976 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
977 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
978 }
979
980 return;
981 }
982
983 #ifdef TI_PRIVATE_JUMBOS
984
985 /*
986 * Memory management for the jumbo receive ring is a pain in the
987 * butt. We need to allocate at least 9018 bytes of space per frame,
988 * _and_ it has to be contiguous (unless you use the extended
989 * jumbo descriptor format). Using malloc() all the time won't
990 * work: malloc() allocates memory in powers of two, which means we
991 * would end up wasting a considerable amount of space by allocating
992 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
993 * to do our own memory management.
994 *
995 * The driver needs to allocate a contiguous chunk of memory at boot
996 * time. We then chop this up ourselves into 9K pieces and use them
997 * as external mbuf storage.
998 *
999 * One issue here is how much memory to allocate. The jumbo ring has
1000 * 256 slots in it, but at 9K per slot than can consume over 2MB of
1001 * RAM. This is a bit much, especially considering we also need
1002 * RAM for the standard ring and mini ring (on the Tigon 2). To
1003 * save space, we only actually allocate enough memory for 64 slots
1004 * by default, which works out to between 500 and 600K. This can
1005 * be tuned by changing a #define in if_tireg.h.
1006 */
1007
1008 static int
1009 ti_alloc_jumbo_mem(sc)
1010 struct ti_softc *sc;
1011 {
1012 caddr_t ptr;
1013 register int i;
1014 struct ti_jpool_entry *entry;
1015
1016 /* Grab a big chunk o' storage. */
1017 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
1018 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1019
1020 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
1021 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
1022 return(ENOBUFS);
1023 }
1024
1025 SLIST_INIT(&sc->ti_jfree_listhead);
1026 SLIST_INIT(&sc->ti_jinuse_listhead);
1027
1028 /*
1029 * Now divide it up into 9K pieces and save the addresses
1030 * in an array.
1031 */
1032 ptr = sc->ti_cdata.ti_jumbo_buf;
1033 for (i = 0; i < TI_JSLOTS; i++) {
1034 sc->ti_cdata.ti_jslots[i] = ptr;
1035 ptr += TI_JLEN;
1036 entry = malloc(sizeof(struct ti_jpool_entry),
1037 M_DEVBUF, M_NOWAIT);
1038 if (entry == NULL) {
1039 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
1040 M_DEVBUF);
1041 sc->ti_cdata.ti_jumbo_buf = NULL;
1042 printf("ti%d: no memory for jumbo "
1043 "buffer queue!\n", sc->ti_unit);
1044 return(ENOBUFS);
1045 }
1046 entry->slot = i;
1047 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1048 }
1049
1050 return(0);
1051 }
1052
1053 /*
1054 * Allocate a jumbo buffer.
1055 */
1056 static void *ti_jalloc(sc)
1057 struct ti_softc *sc;
1058 {
1059 struct ti_jpool_entry *entry;
1060
1061 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1062
1063 if (entry == NULL) {
1064 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
1065 return(NULL);
1066 }
1067
1068 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1069 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1070 return(sc->ti_cdata.ti_jslots[entry->slot]);
1071 }
1072
1073 /*
1074 * Release a jumbo buffer.
1075 */
1076 static void
1077 ti_jfree(buf, args)
1078 void *buf;
1079 void *args;
1080 {
1081 struct ti_softc *sc;
1082 int i;
1083 struct ti_jpool_entry *entry;
1084
1085 /* Extract the softc struct pointer. */
1086 sc = (struct ti_softc *)args;
1087
1088 if (sc == NULL)
1089 panic("ti_jfree: didn't get softc pointer!");
1090
1091 /* calculate the slot this buffer belongs to */
1092 i = ((vm_offset_t)buf
1093 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1094
1095 if ((i < 0) || (i >= TI_JSLOTS))
1096 panic("ti_jfree: asked to free buffer that we don't manage!");
1097
1098 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1099 if (entry == NULL)
1100 panic("ti_jfree: buffer not in use!");
1101 entry->slot = i;
1102 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1103 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1104
1105 return;
1106 }
1107
1108 #endif /* TI_PRIVATE_JUMBOS */
1109
1110 /*
1111 * Intialize a standard receive ring descriptor.
1112 */
1113 static int
1114 ti_newbuf_std(sc, i, m)
1115 struct ti_softc *sc;
1116 int i;
1117 struct mbuf *m;
1118 {
1119 struct mbuf *m_new = NULL;
1120 struct ti_rx_desc *r;
1121
1122 if (m == NULL) {
1123 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1124 if (m_new == NULL)
1125 return(ENOBUFS);
1126
1127 MCLGET(m_new, M_DONTWAIT);
1128 if (!(m_new->m_flags & M_EXT)) {
1129 m_freem(m_new);
1130 return(ENOBUFS);
1131 }
1132 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1133 } else {
1134 m_new = m;
1135 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1136 m_new->m_data = m_new->m_ext.ext_buf;
1137 }
1138
1139 m_adj(m_new, ETHER_ALIGN);
1140 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1141 r = &sc->ti_rdata->ti_rx_std_ring[i];
1142 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1143 r->ti_type = TI_BDTYPE_RECV_BD;
1144 r->ti_flags = 0;
1145 if (sc->arpcom.ac_if.if_hwassist)
1146 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1147 r->ti_len = m_new->m_len;
1148 r->ti_idx = i;
1149
1150 return(0);
1151 }
1152
1153 /*
1154 * Intialize a mini receive ring descriptor. This only applies to
1155 * the Tigon 2.
1156 */
1157 static int
1158 ti_newbuf_mini(sc, i, m)
1159 struct ti_softc *sc;
1160 int i;
1161 struct mbuf *m;
1162 {
1163 struct mbuf *m_new = NULL;
1164 struct ti_rx_desc *r;
1165
1166 if (m == NULL) {
1167 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1168 if (m_new == NULL) {
1169 return(ENOBUFS);
1170 }
1171 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1172 } else {
1173 m_new = m;
1174 m_new->m_data = m_new->m_pktdat;
1175 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1176 }
1177
1178 m_adj(m_new, ETHER_ALIGN);
1179 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1180 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1181 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1182 r->ti_type = TI_BDTYPE_RECV_BD;
1183 r->ti_flags = TI_BDFLAG_MINI_RING;
1184 if (sc->arpcom.ac_if.if_hwassist)
1185 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1186 r->ti_len = m_new->m_len;
1187 r->ti_idx = i;
1188
1189 return(0);
1190 }
1191
1192 #ifdef TI_PRIVATE_JUMBOS
1193
1194 /*
1195 * Initialize a jumbo receive ring descriptor. This allocates
1196 * a jumbo buffer from the pool managed internally by the driver.
1197 */
1198 static int
1199 ti_newbuf_jumbo(sc, i, m)
1200 struct ti_softc *sc;
1201 int i;
1202 struct mbuf *m;
1203 {
1204 struct mbuf *m_new = NULL;
1205 struct ti_rx_desc *r;
1206
1207 if (m == NULL) {
1208 caddr_t *buf = NULL;
1209
1210 /* Allocate the mbuf. */
1211 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1212 if (m_new == NULL) {
1213 return(ENOBUFS);
1214 }
1215
1216 /* Allocate the jumbo buffer */
1217 buf = ti_jalloc(sc);
1218 if (buf == NULL) {
1219 m_freem(m_new);
1220 printf("ti%d: jumbo allocation failed "
1221 "-- packet dropped!\n", sc->ti_unit);
1222 return(ENOBUFS);
1223 }
1224
1225 /* Attach the buffer to the mbuf. */
1226 m_new->m_data = (void *) buf;
1227 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1228 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
1229 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1230 } else {
1231 m_new = m;
1232 m_new->m_data = m_new->m_ext.ext_buf;
1233 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1234 }
1235
1236 m_adj(m_new, ETHER_ALIGN);
1237 /* Set up the descriptor. */
1238 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1239 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1240 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1241 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1242 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1243 if (sc->arpcom.ac_if.if_hwassist)
1244 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1245 r->ti_len = m_new->m_len;
1246 r->ti_idx = i;
1247
1248 return(0);
1249 }
1250
1251 #else
1252 #include <vm/vm_page.h>
1253
1254 #if (PAGE_SIZE == 4096)
1255 #define NPAYLOAD 2
1256 #else
1257 #define NPAYLOAD 1
1258 #endif
1259
1260 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1261 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1262 #define NFS_HDR_LEN (UDP_HDR_LEN)
1263 static int HDR_LEN = TCP_HDR_LEN;
1264
1265
1266 /*
1267 * Initialize a jumbo receive ring descriptor. This allocates
1268 * a jumbo buffer from the pool managed internally by the driver.
1269 */
1270 static int
1271 ti_newbuf_jumbo(sc, idx, m_old)
1272 struct ti_softc *sc;
1273 int idx;
1274 struct mbuf *m_old;
1275 {
1276 struct mbuf *cur, *m_new = NULL;
1277 struct mbuf *m[3] = {NULL, NULL, NULL};
1278 struct ti_rx_desc_ext *r;
1279 vm_page_t frame;
1280 /* 1 extra buf to make nobufs easy*/
1281 caddr_t buf[3] = {NULL, NULL, NULL};
1282 int i;
1283
1284 if (m_old != NULL) {
1285 m_new = m_old;
1286 cur = m_old->m_next;
1287 for (i = 0; i <= NPAYLOAD; i++){
1288 m[i] = cur;
1289 cur = cur->m_next;
1290 }
1291 } else {
1292 /* Allocate the mbufs. */
1293 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1294 if (m_new == NULL) {
1295 printf("ti%d: mbuf allocation failed "
1296 "-- packet dropped!\n", sc->ti_unit);
1297 goto nobufs;
1298 }
1299 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1300 if (m[NPAYLOAD] == NULL) {
1301 printf("ti%d: cluster mbuf allocation failed "
1302 "-- packet dropped!\n", sc->ti_unit);
1303 goto nobufs;
1304 }
1305 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1306 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1307 printf("ti%d: mbuf allocation failed "
1308 "-- packet dropped!\n", sc->ti_unit);
1309 goto nobufs;
1310 }
1311 m[NPAYLOAD]->m_len = MCLBYTES;
1312
1313 for (i = 0; i < NPAYLOAD; i++){
1314 MGET(m[i], M_DONTWAIT, MT_DATA);
1315 if (m[i] == NULL) {
1316 printf("ti%d: mbuf allocation failed "
1317 "-- packet dropped!\n", sc->ti_unit);
1318 goto nobufs;
1319 }
1320 if (!(frame = jumbo_pg_alloc())){
1321 printf("ti%d: buffer allocation failed "
1322 "-- packet dropped!\n", sc->ti_unit);
1323 printf(" index %d page %d\n", idx, i);
1324 goto nobufs;
1325 }
1326 buf[i] = jumbo_phys_to_kva(VM_PAGE_TO_PHYS(frame));
1327 }
1328 for (i = 0; i < NPAYLOAD; i++){
1329 /* Attach the buffer to the mbuf. */
1330 m[i]->m_data = (void *)buf[i];
1331 m[i]->m_len = PAGE_SIZE;
1332 MEXTADD(m[i], (void *)buf[i], PAGE_SIZE,
1333 jumbo_freem, NULL, 0, EXT_DISPOSABLE);
1334 m[i]->m_next = m[i+1];
1335 }
1336 /* link the buffers to the header */
1337 m_new->m_next = m[0];
1338 m_new->m_data += ETHER_ALIGN;
1339 if (sc->ti_hdrsplit)
1340 m_new->m_len = MHLEN - ETHER_ALIGN;
1341 else
1342 m_new->m_len = HDR_LEN;
1343 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1344 }
1345
1346 /* Set up the descriptor. */
1347 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1348 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1349 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t));
1350 r->ti_len0 = m_new->m_len;
1351
1352 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t));
1353 r->ti_len1 = PAGE_SIZE;
1354
1355 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t));
1356 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1357
1358 if (PAGE_SIZE == 4096) {
1359 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t));
1360 r->ti_len3 = MCLBYTES;
1361 } else {
1362 r->ti_len3 = 0;
1363 }
1364 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1365
1366 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1367
1368 if (sc->arpcom.ac_if.if_hwassist)
1369 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1370
1371 r->ti_idx = idx;
1372
1373 return(0);
1374
1375 nobufs:
1376
1377 /*
1378 * Warning! :
1379 * This can only be called before the mbufs are strung together.
1380 * If the mbufs are strung together, m_freem() will free the chain,
1381 * so that the later mbufs will be freed multiple times.
1382 */
1383 if (m_new)
1384 m_freem(m_new);
1385
1386 for(i = 0; i < 3; i++){
1387 if (m[i])
1388 m_freem(m[i]);
1389 if (buf[i])
1390 jumbo_pg_free((vm_offset_t)buf[i]);
1391 }
1392 return ENOBUFS;
1393 }
1394 #endif
1395
1396
1397
1398 /*
1399 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1400 * that's 1MB or memory, which is a lot. For now, we fill only the first
1401 * 256 ring entries and hope that our CPU is fast enough to keep up with
1402 * the NIC.
1403 */
1404 static int
1405 ti_init_rx_ring_std(sc)
1406 struct ti_softc *sc;
1407 {
1408 register int i;
1409 struct ti_cmd_desc cmd;
1410
1411 for (i = 0; i < TI_SSLOTS; i++) {
1412 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1413 return(ENOBUFS);
1414 };
1415
1416 TI_UPDATE_STDPROD(sc, i - 1);
1417 sc->ti_std = i - 1;
1418
1419 return(0);
1420 }
1421
1422 static void
1423 ti_free_rx_ring_std(sc)
1424 struct ti_softc *sc;
1425 {
1426 register int i;
1427
1428 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1429 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1430 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1431 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1432 }
1433 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1434 sizeof(struct ti_rx_desc));
1435 }
1436
1437 return;
1438 }
1439
1440 static int
1441 ti_init_rx_ring_jumbo(sc)
1442 struct ti_softc *sc;
1443 {
1444 register int i;
1445 struct ti_cmd_desc cmd;
1446
1447 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1448 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1449 return(ENOBUFS);
1450 };
1451
1452 TI_UPDATE_JUMBOPROD(sc, i - 1);
1453 sc->ti_jumbo = i - 1;
1454
1455 return(0);
1456 }
1457
1458 static void
1459 ti_free_rx_ring_jumbo(sc)
1460 struct ti_softc *sc;
1461 {
1462 register int i;
1463
1464 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1465 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1466 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1467 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1468 }
1469 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1470 sizeof(struct ti_rx_desc));
1471 }
1472
1473 return;
1474 }
1475
1476 static int
1477 ti_init_rx_ring_mini(sc)
1478 struct ti_softc *sc;
1479 {
1480 register int i;
1481
1482 for (i = 0; i < TI_MSLOTS; i++) {
1483 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1484 return(ENOBUFS);
1485 };
1486
1487 TI_UPDATE_MINIPROD(sc, i - 1);
1488 sc->ti_mini = i - 1;
1489
1490 return(0);
1491 }
1492
1493 static void
1494 ti_free_rx_ring_mini(sc)
1495 struct ti_softc *sc;
1496 {
1497 register int i;
1498
1499 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1500 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1501 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1502 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1503 }
1504 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1505 sizeof(struct ti_rx_desc));
1506 }
1507
1508 return;
1509 }
1510
1511 static void
1512 ti_free_tx_ring(sc)
1513 struct ti_softc *sc;
1514 {
1515 register int i;
1516
1517 if (sc->ti_rdata->ti_tx_ring == NULL)
1518 return;
1519
1520 for (i = 0; i < TI_TX_RING_CNT; i++) {
1521 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1522 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1523 sc->ti_cdata.ti_tx_chain[i] = NULL;
1524 }
1525 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1526 sizeof(struct ti_tx_desc));
1527 }
1528
1529 return;
1530 }
1531
1532 static int
1533 ti_init_tx_ring(sc)
1534 struct ti_softc *sc;
1535 {
1536 sc->ti_txcnt = 0;
1537 sc->ti_tx_saved_considx = 0;
1538 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1539 return(0);
1540 }
1541
1542 /*
1543 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1544 * but we have to support the old way too so that Tigon 1 cards will
1545 * work.
1546 */
1547 static void
1548 ti_add_mcast(sc, addr)
1549 struct ti_softc *sc;
1550 struct ether_addr *addr;
1551 {
1552 struct ti_cmd_desc cmd;
1553 u_int16_t *m;
1554 u_int32_t ext[2] = {0, 0};
1555
1556 m = (u_int16_t *)&addr->octet[0];
1557
1558 switch(sc->ti_hwrev) {
1559 case TI_HWREV_TIGON:
1560 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1561 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1562 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1563 break;
1564 case TI_HWREV_TIGON_II:
1565 ext[0] = htons(m[0]);
1566 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1567 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1568 break;
1569 default:
1570 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1571 break;
1572 }
1573
1574 return;
1575 }
1576
1577 static void
1578 ti_del_mcast(sc, addr)
1579 struct ti_softc *sc;
1580 struct ether_addr *addr;
1581 {
1582 struct ti_cmd_desc cmd;
1583 u_int16_t *m;
1584 u_int32_t ext[2] = {0, 0};
1585
1586 m = (u_int16_t *)&addr->octet[0];
1587
1588 switch(sc->ti_hwrev) {
1589 case TI_HWREV_TIGON:
1590 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1591 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1592 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1593 break;
1594 case TI_HWREV_TIGON_II:
1595 ext[0] = htons(m[0]);
1596 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1597 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1598 break;
1599 default:
1600 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1601 break;
1602 }
1603
1604 return;
1605 }
1606
1607 /*
1608 * Configure the Tigon's multicast address filter.
1609 *
1610 * The actual multicast table management is a bit of a pain, thanks to
1611 * slight brain damage on the part of both Alteon and us. With our
1612 * multicast code, we are only alerted when the multicast address table
1613 * changes and at that point we only have the current list of addresses:
1614 * we only know the current state, not the previous state, so we don't
1615 * actually know what addresses were removed or added. The firmware has
1616 * state, but we can't get our grubby mits on it, and there is no 'delete
1617 * all multicast addresses' command. Hence, we have to maintain our own
1618 * state so we know what addresses have been programmed into the NIC at
1619 * any given time.
1620 */
1621 static void
1622 ti_setmulti(sc)
1623 struct ti_softc *sc;
1624 {
1625 struct ifnet *ifp;
1626 struct ifmultiaddr *ifma;
1627 struct ti_cmd_desc cmd;
1628 struct ti_mc_entry *mc;
1629 u_int32_t intrs;
1630
1631 ifp = &sc->arpcom.ac_if;
1632
1633 if (ifp->if_flags & IFF_ALLMULTI) {
1634 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1635 return;
1636 } else {
1637 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1638 }
1639
1640 /* Disable interrupts. */
1641 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1642 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1643
1644 /* First, zot all the existing filters. */
1645 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1646 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1647 ti_del_mcast(sc, &mc->mc_addr);
1648 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1649 free(mc, M_DEVBUF);
1650 }
1651
1652 /* Now program new ones. */
1653 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1654 if (ifma->ifma_addr->sa_family != AF_LINK)
1655 continue;
1656 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1657 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1658 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1659 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1660 ti_add_mcast(sc, &mc->mc_addr);
1661 }
1662
1663 /* Re-enable interrupts. */
1664 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1665
1666 return;
1667 }
1668
1669 /*
1670 * Check to see if the BIOS has configured us for a 64 bit slot when
1671 * we aren't actually in one. If we detect this condition, we can work
1672 * around it on the Tigon 2 by setting a bit in the PCI state register,
1673 * but for the Tigon 1 we must give up and abort the interface attach.
1674 */
1675 static int ti_64bitslot_war(sc)
1676 struct ti_softc *sc;
1677 {
1678 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1679 CSR_WRITE_4(sc, 0x600, 0);
1680 CSR_WRITE_4(sc, 0x604, 0);
1681 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1682 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1683 if (sc->ti_hwrev == TI_HWREV_TIGON)
1684 return(EINVAL);
1685 else {
1686 TI_SETBIT(sc, TI_PCI_STATE,
1687 TI_PCISTATE_32BIT_BUS);
1688 return(0);
1689 }
1690 }
1691 }
1692
1693 return(0);
1694 }
1695
1696 /*
1697 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1698 * self-test results.
1699 */
1700 static int
1701 ti_chipinit(sc)
1702 struct ti_softc *sc;
1703 {
1704 u_int32_t cacheline;
1705 u_int32_t pci_writemax = 0;
1706 u_int32_t hdrsplit;
1707
1708 /* Initialize link to down state. */
1709 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1710
1711 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
1712 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1713 else
1714 sc->arpcom.ac_if.if_hwassist = 0;
1715
1716 /* Set endianness before we access any non-PCI registers. */
1717 #if BYTE_ORDER == BIG_ENDIAN
1718 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1719 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1720 #else
1721 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1722 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1723 #endif
1724
1725 /* Check the ROM failed bit to see if self-tests passed. */
1726 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1727 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1728 return(ENODEV);
1729 }
1730
1731 /* Halt the CPU. */
1732 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1733
1734 /* Figure out the hardware revision. */
1735 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1736 case TI_REV_TIGON_I:
1737 sc->ti_hwrev = TI_HWREV_TIGON;
1738 break;
1739 case TI_REV_TIGON_II:
1740 sc->ti_hwrev = TI_HWREV_TIGON_II;
1741 break;
1742 default:
1743 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1744 return(ENODEV);
1745 }
1746
1747 /* Do special setup for Tigon 2. */
1748 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1749 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1750 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1751 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1752 }
1753
1754 /*
1755 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1756 * can't do header splitting.
1757 */
1758 #ifdef TI_JUMBO_HDRSPLIT
1759 if (sc->ti_hwrev != TI_HWREV_TIGON)
1760 sc->ti_hdrsplit = 1;
1761 else
1762 printf("ti%d: can't do header splitting on a Tigon I board\n",
1763 sc->ti_unit);
1764 #endif /* TI_JUMBO_HDRSPLIT */
1765
1766 /* Set up the PCI state register. */
1767 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1768 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1769 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1770 }
1771
1772 /* Clear the read/write max DMA parameters. */
1773 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1774 TI_PCISTATE_READ_MAXDMA));
1775
1776 /* Get cache line size. */
1777 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1778
1779 /*
1780 * If the system has set enabled the PCI memory write
1781 * and invalidate command in the command register, set
1782 * the write max parameter accordingly. This is necessary
1783 * to use MWI with the Tigon 2.
1784 */
1785 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1786 switch(cacheline) {
1787 case 1:
1788 case 4:
1789 case 8:
1790 case 16:
1791 case 32:
1792 case 64:
1793 break;
1794 default:
1795 /* Disable PCI memory write and invalidate. */
1796 if (bootverbose)
1797 printf("ti%d: cache line size %d not "
1798 "supported; disabling PCI MWI\n",
1799 sc->ti_unit, cacheline);
1800 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1801 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1802 break;
1803 }
1804 }
1805
1806 #ifdef __brokenalpha__
1807 /*
1808 * From the Alteon sample driver:
1809 * Must insure that we do not cross an 8K (bytes) boundary
1810 * for DMA reads. Our highest limit is 1K bytes. This is a
1811 * restriction on some ALPHA platforms with early revision
1812 * 21174 PCI chipsets, such as the AlphaPC 164lx
1813 */
1814 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1815 #else
1816 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1817 #endif
1818
1819 /* This sets the min dma param all the way up (0xff). */
1820 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1821
1822 if (sc->ti_hdrsplit)
1823 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1824 else
1825 hdrsplit = 0;
1826
1827 /* Configure DMA variables. */
1828 #if BYTE_ORDER == BIG_ENDIAN
1829 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1830 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1831 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1832 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1833 #else /* BYTE_ORDER */
1834 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1835 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1836 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1837 #endif /* BYTE_ORDER */
1838
1839 /*
1840 * Only allow 1 DMA channel to be active at a time.
1841 * I don't think this is a good idea, but without it
1842 * the firmware racks up lots of nicDmaReadRingFull
1843 * errors. This is not compatible with hardware checksums.
1844 */
1845 if (sc->arpcom.ac_if.if_hwassist == 0)
1846 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1847
1848 /* Recommended settings from Tigon manual. */
1849 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1850 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1851
1852 if (ti_64bitslot_war(sc)) {
1853 printf("ti%d: bios thinks we're in a 64 bit slot, "
1854 "but we aren't", sc->ti_unit);
1855 return(EINVAL);
1856 }
1857
1858 return(0);
1859 }
1860
1861 /*
1862 * Initialize the general information block and firmware, and
1863 * start the CPU(s) running.
1864 */
1865 static int
1866 ti_gibinit(sc)
1867 struct ti_softc *sc;
1868 {
1869 struct ti_rcb *rcb;
1870 int i;
1871 struct ifnet *ifp;
1872
1873 ifp = &sc->arpcom.ac_if;
1874
1875 /* Disable interrupts for now. */
1876 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1877
1878 /* Tell the chip where to find the general information block. */
1879 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1880 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1881
1882 /* Load the firmware into SRAM. */
1883 ti_loadfw(sc);
1884
1885 /* Set up the contents of the general info and ring control blocks. */
1886
1887 /* Set up the event ring and producer pointer. */
1888 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1889
1890 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1891 rcb->ti_flags = 0;
1892 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1893 vtophys(&sc->ti_ev_prodidx);
1894 sc->ti_ev_prodidx.ti_idx = 0;
1895 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1896 sc->ti_ev_saved_considx = 0;
1897
1898 /* Set up the command ring and producer mailbox. */
1899 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1900
1901 sc->ti_rdata->ti_cmd_ring =
1902 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1903 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1904 rcb->ti_flags = 0;
1905 rcb->ti_max_len = 0;
1906 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1907 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1908 }
1909 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1910 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1911 sc->ti_cmd_saved_prodidx = 0;
1912
1913 /*
1914 * Assign the address of the stats refresh buffer.
1915 * We re-use the current stats buffer for this to
1916 * conserve memory.
1917 */
1918 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1919 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1920
1921 /* Set up the standard receive ring. */
1922 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1923 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1924 rcb->ti_max_len = TI_FRAMELEN;
1925 rcb->ti_flags = 0;
1926 if (sc->arpcom.ac_if.if_hwassist)
1927 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1928 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1929 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1930
1931 /* Set up the jumbo receive ring. */
1932 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1933 TI_HOSTADDR(rcb->ti_hostaddr) =
1934 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1935
1936 #ifdef TI_PRIVATE_JUMBOS
1937 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1938 rcb->ti_flags = 0;
1939 #else
1940 rcb->ti_max_len = PAGE_SIZE;
1941 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
1942 #endif
1943 if (sc->arpcom.ac_if.if_hwassist)
1944 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1945 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1946 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1947
1948 /*
1949 * Set up the mini ring. Only activated on the
1950 * Tigon 2 but the slot in the config block is
1951 * still there on the Tigon 1.
1952 */
1953 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1954 TI_HOSTADDR(rcb->ti_hostaddr) =
1955 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1956 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1957 if (sc->ti_hwrev == TI_HWREV_TIGON)
1958 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1959 else
1960 rcb->ti_flags = 0;
1961 if (sc->arpcom.ac_if.if_hwassist)
1962 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1963 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1964 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1965
1966 /*
1967 * Set up the receive return ring.
1968 */
1969 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1970 TI_HOSTADDR(rcb->ti_hostaddr) =
1971 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1972 rcb->ti_flags = 0;
1973 rcb->ti_max_len = TI_RETURN_RING_CNT;
1974 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1975 vtophys(&sc->ti_return_prodidx);
1976
1977 /*
1978 * Set up the tx ring. Note: for the Tigon 2, we have the option
1979 * of putting the transmit ring in the host's address space and
1980 * letting the chip DMA it instead of leaving the ring in the NIC's
1981 * memory and accessing it through the shared memory region. We
1982 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1983 * so we have to revert to the shared memory scheme if we detect
1984 * a Tigon 1 chip.
1985 */
1986 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1987 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1988 sc->ti_rdata->ti_tx_ring_nic =
1989 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1990 }
1991 bzero((char *)sc->ti_rdata->ti_tx_ring,
1992 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1993 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1994 if (sc->ti_hwrev == TI_HWREV_TIGON)
1995 rcb->ti_flags = 0;
1996 else
1997 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1998 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1999 if (sc->arpcom.ac_if.if_hwassist)
2000 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2001 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2002 rcb->ti_max_len = TI_TX_RING_CNT;
2003 if (sc->ti_hwrev == TI_HWREV_TIGON)
2004 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
2005 else
2006 TI_HOSTADDR(rcb->ti_hostaddr) =
2007 vtophys(&sc->ti_rdata->ti_tx_ring);
2008 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
2009 vtophys(&sc->ti_tx_considx);
2010
2011 /* Set up tuneables */
2012 #if 0
2013 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2014 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2015 (sc->ti_rx_coal_ticks / 10));
2016 else
2017 #endif
2018 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2019 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2020 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2021 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2022 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2023 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2024
2025 /* Turn interrupts on. */
2026 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2027 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2028
2029 /* Start CPU. */
2030 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2031
2032 return(0);
2033 }
2034
2035 /*
2036 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2037 * against our list and return its name if we find a match.
2038 */
2039 static int
2040 ti_probe(dev)
2041 device_t dev;
2042 {
2043 struct ti_type *t;
2044
2045 t = ti_devs;
2046
2047 while(t->ti_name != NULL) {
2048 if ((pci_get_vendor(dev) == t->ti_vid) &&
2049 (pci_get_device(dev) == t->ti_did)) {
2050 device_set_desc(dev, t->ti_name);
2051 return(0);
2052 }
2053 t++;
2054 }
2055
2056 return(ENXIO);
2057 }
2058
2059 #ifdef KLD_MODULE
2060 static int
2061 log2rndup(int len)
2062 {
2063 int log2size = 0, t = len;
2064 while (t > 1) {
2065 log2size++;
2066 t >>= 1;
2067 }
2068 if (len != (1 << log2size))
2069 log2size++;
2070 return log2size;
2071 }
2072
2073 static int
2074 ti_mbuf_sanity(device_t dev)
2075 {
2076 if ((mbstat.m_msize != MSIZE) || mbstat.m_mclbytes != MCLBYTES){
2077 device_printf(dev, "\n");
2078 device_printf(dev, "This module was compiled with "
2079 "-DMCLSHIFT=%d -DMSIZE=%d\n", MCLSHIFT,
2080 MSIZE);
2081 device_printf(dev, "The kernel was compiled with MCLSHIFT=%d,"
2082 " MSIZE=%d\n", log2rndup(mbstat.m_mclbytes),
2083 (int)mbstat.m_msize);
2084 return(EINVAL);
2085 }
2086 return(0);
2087 }
2088 #endif
2089
2090
2091 static int
2092 ti_attach(dev)
2093 device_t dev;
2094 {
2095 struct ifnet *ifp;
2096 struct ti_softc *sc;
2097 int unit, error = 0, rid;
2098
2099 sc = NULL;
2100
2101 #ifdef KLD_MODULE
2102 if (ti_mbuf_sanity(dev)){
2103 device_printf(dev, "Module mbuf constants do not match "
2104 "kernel constants!\n");
2105 device_printf(dev, "Rebuild the module or the kernel so "
2106 "they match\n");
2107 device_printf(dev, "\n");
2108 error = EINVAL;
2109 goto fail;
2110 }
2111 #endif
2112
2113 sc = device_get_softc(dev);
2114 unit = device_get_unit(dev);
2115
2116 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2117 MTX_DEF | MTX_RECURSE);
2118 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2119 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
2120 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities;
2121
2122 /*
2123 * Map control/status registers.
2124 */
2125 pci_enable_busmaster(dev);
2126
2127 rid = TI_PCI_LOMEM;
2128 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
2129 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE);
2130
2131 if (sc->ti_res == NULL) {
2132 printf ("ti%d: couldn't map memory\n", unit);
2133 error = ENXIO;
2134 goto fail;
2135 }
2136
2137 sc->ti_btag = rman_get_bustag(sc->ti_res);
2138 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2139 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
2140
2141 /* Allocate interrupt */
2142 rid = 0;
2143
2144 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2145 RF_SHAREABLE | RF_ACTIVE);
2146
2147 if (sc->ti_irq == NULL) {
2148 printf("ti%d: couldn't map interrupt\n", unit);
2149 error = ENXIO;
2150 goto fail;
2151 }
2152
2153 sc->ti_unit = unit;
2154
2155 if (ti_chipinit(sc)) {
2156 printf("ti%d: chip initialization failed\n", sc->ti_unit);
2157 error = ENXIO;
2158 goto fail;
2159 }
2160
2161 /* Zero out the NIC's on-board SRAM. */
2162 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2163
2164 /* Init again -- zeroing memory may have clobbered some registers. */
2165 if (ti_chipinit(sc)) {
2166 printf("ti%d: chip initialization failed\n", sc->ti_unit);
2167 error = ENXIO;
2168 goto fail;
2169 }
2170
2171 /*
2172 * Get station address from the EEPROM. Note: the manual states
2173 * that the MAC address is at offset 0x8c, however the data is
2174 * stored as two longwords (since that's how it's loaded into
2175 * the NIC). This means the MAC address is actually preceded
2176 * by two zero bytes. We need to skip over those.
2177 */
2178 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
2179 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2180 printf("ti%d: failed to read station address\n", unit);
2181 error = ENXIO;
2182 goto fail;
2183 }
2184
2185 /*
2186 * A Tigon chip was detected. Inform the world.
2187 */
2188 printf("ti%d: Ethernet address: %6D\n", unit,
2189 sc->arpcom.ac_enaddr, ":");
2190
2191 /* Allocate the general information block and ring buffers. */
2192 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
2193 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
2194
2195 if (sc->ti_rdata == NULL) {
2196 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
2197 error = ENXIO;
2198 goto fail;
2199 }
2200
2201 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2202
2203 /* Try to allocate memory for jumbo buffers. */
2204 #ifdef TI_PRIVATE_JUMBOS
2205 if (ti_alloc_jumbo_mem(sc)) {
2206 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
2207 error = ENXIO;
2208 goto fail;
2209 }
2210 #else
2211 if (!jumbo_vm_init()) {
2212 printf("ti%d: VM initialization failed!\n", sc->ti_unit);
2213 error = ENOMEM;
2214 goto fail;
2215 }
2216 #endif
2217
2218 /*
2219 * We really need a better way to tell a 1000baseTX card
2220 * from a 1000baseSX one, since in theory there could be
2221 * OEMed 1000baseTX cards from lame vendors who aren't
2222 * clever enough to change the PCI ID. For the moment
2223 * though, the AceNIC is the only copper card available.
2224 */
2225 if (pci_get_vendor(dev) == ALT_VENDORID &&
2226 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2227 sc->ti_copper = 1;
2228 /* Ok, it's not the only copper card available. */
2229 if (pci_get_vendor(dev) == NG_VENDORID &&
2230 pci_get_device(dev) == NG_DEVICEID_GA620T)
2231 sc->ti_copper = 1;
2232
2233 /* Set default tuneable values. */
2234 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
2235 #if 0
2236 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
2237 #endif
2238 sc->ti_rx_coal_ticks = 170;
2239 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
2240 sc->ti_rx_max_coal_bds = 64;
2241 #if 0
2242 sc->ti_tx_max_coal_bds = 128;
2243 #endif
2244 sc->ti_tx_max_coal_bds = 32;
2245 sc->ti_tx_buf_ratio = 21;
2246
2247 /* Set up ifnet structure */
2248 ifp = &sc->arpcom.ac_if;
2249 ifp->if_softc = sc;
2250 ifp->if_unit = sc->ti_unit;
2251 ifp->if_name = "ti";
2252 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2253 tis[unit] = sc;
2254 ifp->if_ioctl = ti_ioctl;
2255 ifp->if_output = ether_output;
2256 ifp->if_start = ti_start;
2257 ifp->if_watchdog = ti_watchdog;
2258 ifp->if_init = ti_init;
2259 ifp->if_mtu = ETHERMTU;
2260 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
2261
2262 /* Set up ifmedia support. */
2263 if (sc->ti_copper) {
2264 /*
2265 * Copper cards allow manual 10/100 mode selection,
2266 * but not manual 1000baseTX mode selection. Why?
2267 * Becuase currently there's no way to specify the
2268 * master/slave setting through the firmware interface,
2269 * so Alteon decided to just bag it and handle it
2270 * via autonegotiation.
2271 */
2272 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2273 ifmedia_add(&sc->ifmedia,
2274 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2275 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2276 ifmedia_add(&sc->ifmedia,
2277 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2278 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2279 ifmedia_add(&sc->ifmedia,
2280 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2281 } else {
2282 /* Fiber cards don't support 10/100 modes. */
2283 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2284 ifmedia_add(&sc->ifmedia,
2285 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2286 }
2287 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2288 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2289
2290 /*
2291 * We're assuming here that card initialization is a sequential
2292 * thing. If it isn't, multiple cards probing at the same time
2293 * could stomp on the list of softcs here.
2294 */
2295 /*
2296 * If this is the first card to be initialized, initialize the
2297 * softc queue.
2298 */
2299 if (unit == 0)
2300 STAILQ_INIT(&ti_sc_list);
2301
2302 STAILQ_INSERT_TAIL(&ti_sc_list, sc, ti_links);
2303
2304 /* Register the device */
2305 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
2306 0600, "ti%d", sc->ti_unit);
2307
2308 /*
2309 * Call MI attach routine.
2310 */
2311 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
2312
2313 /* Hook interrupt last to avoid having to lock softc */
2314 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
2315 ti_intr, sc, &sc->ti_intrhand);
2316
2317 if (error) {
2318 printf("ti%d: couldn't set up irq\n", unit);
2319 ether_ifdetach(ifp);
2320 goto fail;
2321 }
2322
2323 fail:
2324 if (sc && error)
2325 ti_detach(dev);
2326
2327 return(error);
2328 }
2329
2330 /*
2331 * Verify that our character special device is not currently
2332 * open. Also track down any cached vnodes & kill them before
2333 * the module is unloaded
2334 */
2335 static int
2336 ti_unref_special(device_t dev)
2337 {
2338 struct vnode *ti_vn;
2339 int count;
2340 struct ti_softc *sc = sc = device_get_softc(dev);
2341
2342 if (!vfinddev(sc->dev, VCHR, &ti_vn)) {
2343 return 0;
2344 }
2345
2346 if ((count = vcount(ti_vn))) {
2347 device_printf(dev, "%d refs to special device, "
2348 "denying unload\n", count);
2349 return count;
2350 }
2351 /* now we know that there's a vnode in the cache. We hunt it
2352 down and kill it now, before unloading */
2353 vgone(ti_vn);
2354 return(0);
2355 }
2356
2357 /*
2358 * Shutdown hardware and free up resources. This can be called any
2359 * time after the mutex has been initialized. It is called in both
2360 * the error case in attach and the normal detach case so it needs
2361 * to be careful about only freeing resources that have actually been
2362 * allocated.
2363 */
2364 static int
2365 ti_detach(dev)
2366 device_t dev;
2367 {
2368 struct ti_softc *sc;
2369 struct ifnet *ifp;
2370
2371 if (ti_unref_special(dev))
2372 return EBUSY;
2373
2374 sc = device_get_softc(dev);
2375 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2376 TI_LOCK(sc);
2377 ifp = &sc->arpcom.ac_if;
2378
2379 /* These should only be active if attach succeeded */
2380 if (device_is_attached(dev)) {
2381 ti_stop(sc);
2382 ether_ifdetach(ifp);
2383 bus_generic_detach(dev);
2384 }
2385 ifmedia_removeall(&sc->ifmedia);
2386
2387 if (sc->ti_intrhand)
2388 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2389 if (sc->ti_irq)
2390 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2391 if (sc->ti_res) {
2392 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2393 sc->ti_res);
2394 }
2395
2396 #ifdef TI_PRIVATE_JUMBOS
2397 if (sc->ti_cdata.ti_jumbo_buf)
2398 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
2399 #endif
2400 if (sc->ti_rdata)
2401 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
2402
2403 TI_UNLOCK(sc);
2404 mtx_destroy(&sc->ti_mtx);
2405
2406 return(0);
2407 }
2408
2409 #ifdef TI_JUMBO_HDRSPLIT
2410 /*
2411 * If hdr_len is 0, that means that header splitting wasn't done on
2412 * this packet for some reason. The two most likely reasons are that
2413 * the protocol isn't a supported protocol for splitting, or this
2414 * packet had a fragment offset that wasn't 0.
2415 *
2416 * The header length, if it is non-zero, will always be the length of
2417 * the headers on the packet, but that length could be longer than the
2418 * first mbuf. So we take the minimum of the two as the actual
2419 * length.
2420 */
2421 static __inline void
2422 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2423 {
2424 int i = 0;
2425 int lengths[4] = {0, 0, 0, 0};
2426 struct mbuf *m, *mp;
2427
2428 if (hdr_len != 0)
2429 top->m_len = min(hdr_len, top->m_len);
2430 pkt_len -= top->m_len;
2431 lengths[i++] = top->m_len;
2432
2433 mp = top;
2434 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2435 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2436 pkt_len -= m->m_len;
2437 lengths[i++] = m->m_len;
2438 mp = m;
2439 }
2440
2441 #if 0
2442 if (hdr_len != 0)
2443 printf("got split packet: ");
2444 else
2445 printf("got non-split packet: ");
2446
2447 printf("%d,%d,%d,%d = %d\n", lengths[0],
2448 lengths[1], lengths[2], lengths[3],
2449 lengths[0] + lengths[1] + lengths[2] +
2450 lengths[3]);
2451 #endif
2452
2453 if (pkt_len)
2454 panic("header splitting didn't");
2455
2456 if (m) {
2457 m_freem(m);
2458 mp->m_next = NULL;
2459
2460 }
2461 if (mp->m_next != NULL)
2462 panic("ti_hdr_split: last mbuf in chain should be null");
2463 }
2464 #endif /* TI_JUMBO_HDRSPLIT */
2465
2466 /*
2467 * Frame reception handling. This is called if there's a frame
2468 * on the receive return list.
2469 *
2470 * Note: we have to be able to handle three possibilities here:
2471 * 1) the frame is from the mini receive ring (can only happen)
2472 * on Tigon 2 boards)
2473 * 2) the frame is from the jumbo recieve ring
2474 * 3) the frame is from the standard receive ring
2475 */
2476
2477 static void
2478 ti_rxeof(sc)
2479 struct ti_softc *sc;
2480 {
2481 struct ifnet *ifp;
2482 struct ti_cmd_desc cmd;
2483
2484 ifp = &sc->arpcom.ac_if;
2485
2486 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2487 struct ti_rx_desc *cur_rx;
2488 u_int32_t rxidx;
2489 struct ether_header *eh;
2490 struct mbuf *m = NULL;
2491 u_int16_t vlan_tag = 0;
2492 int have_tag = 0;
2493
2494 cur_rx =
2495 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2496 rxidx = cur_rx->ti_idx;
2497 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2498
2499 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2500 have_tag = 1;
2501 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
2502 }
2503
2504 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2505
2506 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2507 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2508 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2509 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2510 ifp->if_ierrors++;
2511 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2512 continue;
2513 }
2514 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2515 ifp->if_ierrors++;
2516 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2517 continue;
2518 }
2519 #ifdef TI_PRIVATE_JUMBOS
2520 m->m_len = cur_rx->ti_len;
2521 #else /* TI_PRIVATE_JUMBOS */
2522 #ifdef TI_JUMBO_HDRSPLIT
2523 if (sc->ti_hdrsplit)
2524 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2525 cur_rx->ti_len, rxidx);
2526 else
2527 #endif /* TI_JUMBO_HDRSPLIT */
2528 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2529 #endif /* TI_PRIVATE_JUMBOS */
2530 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2531 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2532 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2533 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2534 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2535 ifp->if_ierrors++;
2536 ti_newbuf_mini(sc, sc->ti_mini, m);
2537 continue;
2538 }
2539 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2540 ifp->if_ierrors++;
2541 ti_newbuf_mini(sc, sc->ti_mini, m);
2542 continue;
2543 }
2544 m->m_len = cur_rx->ti_len;
2545 } else {
2546 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2547 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2548 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2549 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2550 ifp->if_ierrors++;
2551 ti_newbuf_std(sc, sc->ti_std, m);
2552 continue;
2553 }
2554 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2555 ifp->if_ierrors++;
2556 ti_newbuf_std(sc, sc->ti_std, m);
2557 continue;
2558 }
2559 m->m_len = cur_rx->ti_len;
2560 }
2561
2562 m->m_pkthdr.len = cur_rx->ti_len;
2563 ifp->if_ipackets++;
2564 eh = mtod(m, struct ether_header *);
2565 m->m_pkthdr.rcvif = ifp;
2566
2567 if (ifp->if_hwassist) {
2568 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
2569 CSUM_DATA_VALID;
2570 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2571 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2572 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
2573 }
2574
2575 /*
2576 * If we received a packet with a vlan tag,
2577 * tag it before passing the packet upward.
2578 */
2579 if (have_tag)
2580 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue);
2581 (*ifp->if_input)(ifp, m);
2582 }
2583
2584 /* Only necessary on the Tigon 1. */
2585 if (sc->ti_hwrev == TI_HWREV_TIGON)
2586 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2587 sc->ti_rx_saved_considx);
2588
2589 TI_UPDATE_STDPROD(sc, sc->ti_std);
2590 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2591 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2592
2593 return;
2594 }
2595
2596 static void
2597 ti_txeof(sc)
2598 struct ti_softc *sc;
2599 {
2600 struct ti_tx_desc *cur_tx = NULL;
2601 struct ifnet *ifp;
2602
2603 ifp = &sc->arpcom.ac_if;
2604
2605 /*
2606 * Go through our tx ring and free mbufs for those
2607 * frames that have been sent.
2608 */
2609 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
2610 u_int32_t idx = 0;
2611
2612 idx = sc->ti_tx_saved_considx;
2613 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2614 if (idx > 383)
2615 CSR_WRITE_4(sc, TI_WINBASE,
2616 TI_TX_RING_BASE + 6144);
2617 else if (idx > 255)
2618 CSR_WRITE_4(sc, TI_WINBASE,
2619 TI_TX_RING_BASE + 4096);
2620 else if (idx > 127)
2621 CSR_WRITE_4(sc, TI_WINBASE,
2622 TI_TX_RING_BASE + 2048);
2623 else
2624 CSR_WRITE_4(sc, TI_WINBASE,
2625 TI_TX_RING_BASE);
2626 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
2627 } else
2628 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2629 if (cur_tx->ti_flags & TI_BDFLAG_END)
2630 ifp->if_opackets++;
2631 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
2632 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
2633 sc->ti_cdata.ti_tx_chain[idx] = NULL;
2634 }
2635 sc->ti_txcnt--;
2636 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
2637 ifp->if_timer = 0;
2638 }
2639
2640 if (cur_tx != NULL)
2641 ifp->if_flags &= ~IFF_OACTIVE;
2642
2643 return;
2644 }
2645
2646 static void
2647 ti_intr(xsc)
2648 void *xsc;
2649 {
2650 struct ti_softc *sc;
2651 struct ifnet *ifp;
2652
2653 sc = xsc;
2654 TI_LOCK(sc);
2655 ifp = &sc->arpcom.ac_if;
2656
2657 /*#ifdef notdef*/
2658 /* Avoid this for now -- checking this register is expensive. */
2659 /* Make sure this is really our interrupt. */
2660 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2661 TI_UNLOCK(sc);
2662 return;
2663 }
2664 /*#endif*/
2665
2666 /* Ack interrupt and stop others from occuring. */
2667 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2668
2669 if (ifp->if_flags & IFF_RUNNING) {
2670 /* Check RX return ring producer/consumer */
2671 ti_rxeof(sc);
2672
2673 /* Check TX ring producer/consumer */
2674 ti_txeof(sc);
2675 }
2676
2677 ti_handle_events(sc);
2678
2679 /* Re-enable interrupts. */
2680 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2681
2682 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2683 ti_start(ifp);
2684
2685 TI_UNLOCK(sc);
2686
2687 return;
2688 }
2689
2690 static void
2691 ti_stats_update(sc)
2692 struct ti_softc *sc;
2693 {
2694 struct ifnet *ifp;
2695
2696 ifp = &sc->arpcom.ac_if;
2697
2698 ifp->if_collisions +=
2699 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2700 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2701 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2702 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2703 ifp->if_collisions;
2704
2705 return;
2706 }
2707
2708 /*
2709 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2710 * pointers to descriptors.
2711 */
2712 static int
2713 ti_encap(sc, m_head, txidx)
2714 struct ti_softc *sc;
2715 struct mbuf *m_head;
2716 u_int32_t *txidx;
2717 {
2718 struct ti_tx_desc *f = NULL;
2719 struct mbuf *m;
2720 u_int32_t frag, cur, cnt = 0;
2721 u_int16_t csum_flags = 0;
2722 struct m_tag *mtag;
2723
2724 m = m_head;
2725 cur = frag = *txidx;
2726
2727 if (m_head->m_pkthdr.csum_flags) {
2728 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2729 csum_flags |= TI_BDFLAG_IP_CKSUM;
2730 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2731 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2732 if (m_head->m_flags & M_LASTFRAG)
2733 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2734 else if (m_head->m_flags & M_FRAG)
2735 csum_flags |= TI_BDFLAG_IP_FRAG;
2736 }
2737
2738 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m);
2739
2740 /*
2741 * Start packing the mbufs in this chain into
2742 * the fragment pointers. Stop when we run out
2743 * of fragments or hit the end of the mbuf chain.
2744 */
2745 for (m = m_head; m != NULL; m = m->m_next) {
2746 if (m->m_len != 0) {
2747 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2748 if (frag > 383)
2749 CSR_WRITE_4(sc, TI_WINBASE,
2750 TI_TX_RING_BASE + 6144);
2751 else if (frag > 255)
2752 CSR_WRITE_4(sc, TI_WINBASE,
2753 TI_TX_RING_BASE + 4096);
2754 else if (frag > 127)
2755 CSR_WRITE_4(sc, TI_WINBASE,
2756 TI_TX_RING_BASE + 2048);
2757 else
2758 CSR_WRITE_4(sc, TI_WINBASE,
2759 TI_TX_RING_BASE);
2760 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2761 } else
2762 f = &sc->ti_rdata->ti_tx_ring[frag];
2763 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2764 break;
2765 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2766 f->ti_len = m->m_len;
2767 f->ti_flags = csum_flags;
2768
2769 if (mtag != NULL) {
2770 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2771 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff;
2772 } else {
2773 f->ti_vlan_tag = 0;
2774 }
2775
2776 /*
2777 * Sanity check: avoid coming within 16 descriptors
2778 * of the end of the ring.
2779 */
2780 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2781 return(ENOBUFS);
2782 cur = frag;
2783 TI_INC(frag, TI_TX_RING_CNT);
2784 cnt++;
2785 }
2786 }
2787
2788 if (m != NULL)
2789 return(ENOBUFS);
2790
2791 if (frag == sc->ti_tx_saved_considx)
2792 return(ENOBUFS);
2793
2794 if (sc->ti_hwrev == TI_HWREV_TIGON)
2795 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2796 TI_BDFLAG_END;
2797 else
2798 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2799 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2800 sc->ti_txcnt += cnt;
2801
2802 *txidx = frag;
2803
2804 return(0);
2805 }
2806
2807 /*
2808 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2809 * to the mbuf data regions directly in the transmit descriptors.
2810 */
2811 static void
2812 ti_start(ifp)
2813 struct ifnet *ifp;
2814 {
2815 struct ti_softc *sc;
2816 struct mbuf *m_head = NULL;
2817 u_int32_t prodidx = 0;
2818
2819 sc = ifp->if_softc;
2820 TI_LOCK(sc);
2821
2822 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2823
2824 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2825 IF_DEQUEUE(&ifp->if_snd, m_head);
2826 if (m_head == NULL)
2827 break;
2828
2829 /*
2830 * XXX
2831 * safety overkill. If this is a fragmented packet chain
2832 * with delayed TCP/UDP checksums, then only encapsulate
2833 * it if we have enough descriptors to handle the entire
2834 * chain at once.
2835 * (paranoia -- may not actually be needed)
2836 */
2837 if (m_head->m_flags & M_FIRSTFRAG &&
2838 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2839 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2840 m_head->m_pkthdr.csum_data + 16) {
2841 IF_PREPEND(&ifp->if_snd, m_head);
2842 ifp->if_flags |= IFF_OACTIVE;
2843 break;
2844 }
2845 }
2846
2847 /*
2848 * Pack the data into the transmit ring. If we
2849 * don't have room, set the OACTIVE flag and wait
2850 * for the NIC to drain the ring.
2851 */
2852 if (ti_encap(sc, m_head, &prodidx)) {
2853 IF_PREPEND(&ifp->if_snd, m_head);
2854 ifp->if_flags |= IFF_OACTIVE;
2855 break;
2856 }
2857
2858 /*
2859 * If there's a BPF listener, bounce a copy of this frame
2860 * to him.
2861 */
2862 BPF_MTAP(ifp, m_head);
2863 }
2864
2865 /* Transmit */
2866 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2867
2868 /*
2869 * Set a timeout in case the chip goes out to lunch.
2870 */
2871 ifp->if_timer = 5;
2872 TI_UNLOCK(sc);
2873
2874 return;
2875 }
2876
2877 static void
2878 ti_init(xsc)
2879 void *xsc;
2880 {
2881 struct ti_softc *sc = xsc;
2882
2883 /* Cancel pending I/O and flush buffers. */
2884 ti_stop(sc);
2885
2886 TI_LOCK(sc);
2887 /* Init the gen info block, ring control blocks and firmware. */
2888 if (ti_gibinit(sc)) {
2889 printf("ti%d: initialization failure\n", sc->ti_unit);
2890 TI_UNLOCK(sc);
2891 return;
2892 }
2893
2894 TI_UNLOCK(sc);
2895
2896 return;
2897 }
2898
2899 static void ti_init2(sc)
2900 struct ti_softc *sc;
2901 {
2902 struct ti_cmd_desc cmd;
2903 struct ifnet *ifp;
2904 u_int16_t *m;
2905 struct ifmedia *ifm;
2906 int tmp;
2907
2908 ifp = &sc->arpcom.ac_if;
2909
2910 /* Specify MTU and interface index. */
2911 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit);
2912 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2913 ETHER_HDR_LEN + ETHER_CRC_LEN);
2914 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2915
2916 /* Load our MAC address. */
2917 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2918 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2919 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2920 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2921
2922 /* Enable or disable promiscuous mode as needed. */
2923 if (ifp->if_flags & IFF_PROMISC) {
2924 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2925 } else {
2926 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2927 }
2928
2929 /* Program multicast filter. */
2930 ti_setmulti(sc);
2931
2932 /*
2933 * If this is a Tigon 1, we should tell the
2934 * firmware to use software packet filtering.
2935 */
2936 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2937 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2938 }
2939
2940 /* Init RX ring. */
2941 ti_init_rx_ring_std(sc);
2942
2943 /* Init jumbo RX ring. */
2944 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2945 ti_init_rx_ring_jumbo(sc);
2946
2947 /*
2948 * If this is a Tigon 2, we can also configure the
2949 * mini ring.
2950 */
2951 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2952 ti_init_rx_ring_mini(sc);
2953
2954 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2955 sc->ti_rx_saved_considx = 0;
2956
2957 /* Init TX ring. */
2958 ti_init_tx_ring(sc);
2959
2960 /* Tell firmware we're alive. */
2961 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2962
2963 /* Enable host interrupts. */
2964 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2965
2966 ifp->if_flags |= IFF_RUNNING;
2967 ifp->if_flags &= ~IFF_OACTIVE;
2968
2969 /*
2970 * Make sure to set media properly. We have to do this
2971 * here since we have to issue commands in order to set
2972 * the link negotiation and we can't issue commands until
2973 * the firmware is running.
2974 */
2975 ifm = &sc->ifmedia;
2976 tmp = ifm->ifm_media;
2977 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2978 ti_ifmedia_upd(ifp);
2979 ifm->ifm_media = tmp;
2980
2981 return;
2982 }
2983
2984 /*
2985 * Set media options.
2986 */
2987 static int
2988 ti_ifmedia_upd(ifp)
2989 struct ifnet *ifp;
2990 {
2991 struct ti_softc *sc;
2992 struct ifmedia *ifm;
2993 struct ti_cmd_desc cmd;
2994 u_int32_t flowctl;
2995
2996 sc = ifp->if_softc;
2997 ifm = &sc->ifmedia;
2998
2999 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3000 return(EINVAL);
3001
3002 flowctl = 0;
3003
3004 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3005 case IFM_AUTO:
3006 /*
3007 * Transmit flow control doesn't work on the Tigon 1.
3008 */
3009 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3010
3011 /*
3012 * Transmit flow control can also cause problems on the
3013 * Tigon 2, apparantly with both the copper and fiber
3014 * boards. The symptom is that the interface will just
3015 * hang. This was reproduced with Alteon 180 switches.
3016 */
3017 #if 0
3018 if (sc->ti_hwrev != TI_HWREV_TIGON)
3019 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3020 #endif
3021
3022 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3023 TI_GLNK_FULL_DUPLEX| flowctl |
3024 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3025
3026 flowctl = TI_LNK_RX_FLOWCTL_Y;
3027 #if 0
3028 if (sc->ti_hwrev != TI_HWREV_TIGON)
3029 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3030 #endif
3031
3032 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3033 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3034 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3035 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3036 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3037 break;
3038 case IFM_1000_SX:
3039 case IFM_1000_T:
3040 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3041 #if 0
3042 if (sc->ti_hwrev != TI_HWREV_TIGON)
3043 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3044 #endif
3045
3046 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3047 flowctl |TI_GLNK_ENB);
3048 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3049 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3050 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3051 }
3052 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3053 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3054 break;
3055 case IFM_100_FX:
3056 case IFM_10_FL:
3057 case IFM_100_TX:
3058 case IFM_10_T:
3059 flowctl = TI_LNK_RX_FLOWCTL_Y;
3060 #if 0
3061 if (sc->ti_hwrev != TI_HWREV_TIGON)
3062 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3063 #endif
3064
3065 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3066 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3067 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3068 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3069 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3070 } else {
3071 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3072 }
3073 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3074 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3075 } else {
3076 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3077 }
3078 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3079 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3080 break;
3081 }
3082
3083 return(0);
3084 }
3085
3086 /*
3087 * Report current media status.
3088 */
3089 static void
3090 ti_ifmedia_sts(ifp, ifmr)
3091 struct ifnet *ifp;
3092 struct ifmediareq *ifmr;
3093 {
3094 struct ti_softc *sc;
3095 u_int32_t media = 0;
3096
3097 sc = ifp->if_softc;
3098
3099 ifmr->ifm_status = IFM_AVALID;
3100 ifmr->ifm_active = IFM_ETHER;
3101
3102 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
3103 return;
3104
3105 ifmr->ifm_status |= IFM_ACTIVE;
3106
3107 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3108 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3109 if (sc->ti_copper)
3110 ifmr->ifm_active |= IFM_1000_T;
3111 else
3112 ifmr->ifm_active |= IFM_1000_SX;
3113 if (media & TI_GLNK_FULL_DUPLEX)
3114 ifmr->ifm_active |= IFM_FDX;
3115 else
3116 ifmr->ifm_active |= IFM_HDX;
3117 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3118 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3119 if (sc->ti_copper) {
3120 if (media & TI_LNK_100MB)
3121 ifmr->ifm_active |= IFM_100_TX;
3122 if (media & TI_LNK_10MB)
3123 ifmr->ifm_active |= IFM_10_T;
3124 } else {
3125 if (media & TI_LNK_100MB)
3126 ifmr->ifm_active |= IFM_100_FX;
3127 if (media & TI_LNK_10MB)
3128 ifmr->ifm_active |= IFM_10_FL;
3129 }
3130 if (media & TI_LNK_FULL_DUPLEX)
3131 ifmr->ifm_active |= IFM_FDX;
3132 if (media & TI_LNK_HALF_DUPLEX)
3133 ifmr->ifm_active |= IFM_HDX;
3134 }
3135
3136 return;
3137 }
3138
3139 static int
3140 ti_ioctl(ifp, command, data)
3141 struct ifnet *ifp;
3142 u_long command;
3143 caddr_t data;
3144 {
3145 struct ti_softc *sc = ifp->if_softc;
3146 struct ifreq *ifr = (struct ifreq *) data;
3147 int mask, error = 0;
3148 struct ti_cmd_desc cmd;
3149
3150 TI_LOCK(sc);
3151
3152 switch(command) {
3153 case SIOCSIFMTU:
3154 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3155 error = EINVAL;
3156 else {
3157 ifp->if_mtu = ifr->ifr_mtu;
3158 ti_init(sc);
3159 }
3160 break;
3161 case SIOCSIFFLAGS:
3162 if (ifp->if_flags & IFF_UP) {
3163 /*
3164 * If only the state of the PROMISC flag changed,
3165 * then just use the 'set promisc mode' command
3166 * instead of reinitializing the entire NIC. Doing
3167 * a full re-init means reloading the firmware and
3168 * waiting for it to start up, which may take a
3169 * second or two.
3170 */
3171 if (ifp->if_flags & IFF_RUNNING &&
3172 ifp->if_flags & IFF_PROMISC &&
3173 !(sc->ti_if_flags & IFF_PROMISC)) {
3174 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3175 TI_CMD_CODE_PROMISC_ENB, 0);
3176 } else if (ifp->if_flags & IFF_RUNNING &&
3177 !(ifp->if_flags & IFF_PROMISC) &&
3178 sc->ti_if_flags & IFF_PROMISC) {
3179 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3180 TI_CMD_CODE_PROMISC_DIS, 0);
3181 } else
3182 ti_init(sc);
3183 } else {
3184 if (ifp->if_flags & IFF_RUNNING) {
3185 ti_stop(sc);
3186 }
3187 }
3188 sc->ti_if_flags = ifp->if_flags;
3189 error = 0;
3190 break;
3191 case SIOCADDMULTI:
3192 case SIOCDELMULTI:
3193 if (ifp->if_flags & IFF_RUNNING) {
3194 ti_setmulti(sc);
3195 error = 0;
3196 }
3197 break;
3198 case SIOCSIFMEDIA:
3199 case SIOCGIFMEDIA:
3200 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3201 break;
3202 case SIOCSIFCAP:
3203 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3204 if (mask & IFCAP_HWCSUM) {
3205 if (IFCAP_HWCSUM & ifp->if_capenable)
3206 ifp->if_capenable &= ~IFCAP_HWCSUM;
3207 else
3208 ifp->if_capenable |= IFCAP_HWCSUM;
3209 if (ifp->if_flags & IFF_RUNNING)
3210 ti_init(sc);
3211 }
3212 error = 0;
3213 break;
3214 default:
3215 error = ether_ioctl(ifp, command, data);
3216 break;
3217 }
3218
3219 TI_UNLOCK(sc);
3220
3221 return(error);
3222 }
3223
3224 static int
3225 ti_open(dev_t dev, int flags, int fmt, struct thread *td)
3226 {
3227 int unit;
3228 struct ti_softc *sc;
3229
3230 unit = minor(dev) & 0xff;
3231
3232 sc = ti_lookup_softc(unit);
3233
3234 if (sc == NULL)
3235 return(ENODEV);
3236
3237 TI_LOCK(sc);
3238 sc->ti_flags |= TI_FLAG_DEBUGING;
3239 TI_UNLOCK(sc);
3240
3241 return(0);
3242 }
3243
3244 static int
3245 ti_close(dev_t dev, int flag, int fmt, struct thread *td)
3246 {
3247 int unit;
3248 struct ti_softc *sc;
3249
3250 unit = minor(dev) & 0xff;
3251
3252 sc = ti_lookup_softc(unit);
3253
3254 if (sc == NULL)
3255 return(ENODEV);
3256
3257 TI_LOCK(sc);
3258 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3259 TI_UNLOCK(sc);
3260
3261 return(0);
3262 }
3263
3264 /*
3265 * This ioctl routine goes along with the Tigon character device.
3266 */
3267 static int
3268 ti_ioctl2(dev_t dev, u_long cmd, caddr_t addr, int flag, struct thread *td)
3269 {
3270 int unit, error;
3271 struct ti_softc *sc;
3272
3273 unit = minor(dev) & 0xff;
3274
3275 sc = ti_lookup_softc(unit);
3276
3277 if (sc == NULL)
3278 return(ENODEV);
3279
3280 error = 0;
3281
3282 switch(cmd) {
3283 case TIIOCGETSTATS:
3284 {
3285 struct ti_stats *outstats;
3286
3287 outstats = (struct ti_stats *)addr;
3288
3289 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3290 sizeof(struct ti_stats));
3291 break;
3292 }
3293 case TIIOCGETPARAMS:
3294 {
3295 struct ti_params *params;
3296
3297 params = (struct ti_params *)addr;
3298
3299 params->ti_stat_ticks = sc->ti_stat_ticks;
3300 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3301 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3302 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3303 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3304 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3305 params->param_mask = TI_PARAM_ALL;
3306
3307 error = 0;
3308
3309 break;
3310 }
3311 case TIIOCSETPARAMS:
3312 {
3313 struct ti_params *params;
3314
3315 params = (struct ti_params *)addr;
3316
3317 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3318 sc->ti_stat_ticks = params->ti_stat_ticks;
3319 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3320 }
3321
3322 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3323 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3324 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3325 sc->ti_rx_coal_ticks);
3326 }
3327
3328 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3329 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3330 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3331 sc->ti_tx_coal_ticks);
3332 }
3333
3334 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3335 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3336 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3337 sc->ti_rx_max_coal_bds);
3338 }
3339
3340 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3341 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3342 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3343 sc->ti_tx_max_coal_bds);
3344 }
3345
3346 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3347 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3348 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3349 sc->ti_tx_buf_ratio);
3350 }
3351
3352 error = 0;
3353
3354 break;
3355 }
3356 case TIIOCSETTRACE: {
3357 ti_trace_type trace_type;
3358
3359 trace_type = *(ti_trace_type *)addr;
3360
3361 /*
3362 * Set tracing to whatever the user asked for. Setting
3363 * this register to 0 should have the effect of disabling
3364 * tracing.
3365 */
3366 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3367
3368 error = 0;
3369
3370 break;
3371 }
3372 case TIIOCGETTRACE: {
3373 struct ti_trace_buf *trace_buf;
3374 u_int32_t trace_start, cur_trace_ptr, trace_len;
3375
3376 trace_buf = (struct ti_trace_buf *)addr;
3377
3378 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3379 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3380 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3381
3382 #if 0
3383 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, "
3384 "trace_len = %d\n", sc->ti_unit, trace_start,
3385 cur_trace_ptr, trace_len);
3386 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit,
3387 trace_buf->buf_len);
3388 #endif
3389
3390 error = ti_copy_mem(sc, trace_start, min(trace_len,
3391 trace_buf->buf_len),
3392 (caddr_t)trace_buf->buf, 1, 1);
3393
3394 if (error == 0) {
3395 trace_buf->fill_len = min(trace_len,
3396 trace_buf->buf_len);
3397 if (cur_trace_ptr < trace_start)
3398 trace_buf->cur_trace_ptr =
3399 trace_start - cur_trace_ptr;
3400 else
3401 trace_buf->cur_trace_ptr =
3402 cur_trace_ptr - trace_start;
3403 } else
3404 trace_buf->fill_len = 0;
3405
3406
3407 break;
3408 }
3409
3410 /*
3411 * For debugging, five ioctls are needed:
3412 * ALT_ATTACH
3413 * ALT_READ_TG_REG
3414 * ALT_WRITE_TG_REG
3415 * ALT_READ_TG_MEM
3416 * ALT_WRITE_TG_MEM
3417 */
3418 case ALT_ATTACH:
3419 /*
3420 * From what I can tell, Alteon's Solaris Tigon driver
3421 * only has one character device, so you have to attach
3422 * to the Tigon board you're interested in. This seems
3423 * like a not-so-good way to do things, since unless you
3424 * subsequently specify the unit number of the device
3425 * you're interested in in every ioctl, you'll only be
3426 * able to debug one board at a time.
3427 */
3428 error = 0;
3429 break;
3430 case ALT_READ_TG_MEM:
3431 case ALT_WRITE_TG_MEM:
3432 {
3433 struct tg_mem *mem_param;
3434 u_int32_t sram_end, scratch_end;
3435
3436 mem_param = (struct tg_mem *)addr;
3437
3438 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3439 sram_end = TI_END_SRAM_I;
3440 scratch_end = TI_END_SCRATCH_I;
3441 } else {
3442 sram_end = TI_END_SRAM_II;
3443 scratch_end = TI_END_SCRATCH_II;
3444 }
3445
3446 /*
3447 * For now, we'll only handle accessing regular SRAM,
3448 * nothing else.
3449 */
3450 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3451 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3452 /*
3453 * In this instance, we always copy to/from user
3454 * space, so the user space argument is set to 1.
3455 */
3456 error = ti_copy_mem(sc, mem_param->tgAddr,
3457 mem_param->len,
3458 mem_param->userAddr, 1,
3459 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3460 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3461 && (mem_param->tgAddr <= scratch_end)) {
3462 error = ti_copy_scratch(sc, mem_param->tgAddr,
3463 mem_param->len,
3464 mem_param->userAddr, 1,
3465 (cmd == ALT_READ_TG_MEM) ?
3466 1 : 0, TI_PROCESSOR_A);
3467 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3468 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3469 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3470 printf("ti%d: invalid memory range for "
3471 "Tigon I\n", sc->ti_unit);
3472 error = EINVAL;
3473 break;
3474 }
3475 error = ti_copy_scratch(sc, mem_param->tgAddr -
3476 TI_SCRATCH_DEBUG_OFF,
3477 mem_param->len,
3478 mem_param->userAddr, 1,
3479 (cmd == ALT_READ_TG_MEM) ?
3480 1 : 0, TI_PROCESSOR_B);
3481 } else {
3482 printf("ti%d: memory address %#x len %d is out of "
3483 "supported range\n", sc->ti_unit,
3484 mem_param->tgAddr, mem_param->len);
3485 error = EINVAL;
3486 }
3487
3488 break;
3489 }
3490 case ALT_READ_TG_REG:
3491 case ALT_WRITE_TG_REG:
3492 {
3493 struct tg_reg *regs;
3494 u_int32_t tmpval;
3495
3496 regs = (struct tg_reg *)addr;
3497
3498 /*
3499 * Make sure the address in question isn't out of range.
3500 */
3501 if (regs->addr > TI_REG_MAX) {
3502 error = EINVAL;
3503 break;
3504 }
3505 if (cmd == ALT_READ_TG_REG) {
3506 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3507 regs->addr, &tmpval, 1);
3508 regs->data = ntohl(tmpval);
3509 #if 0
3510 if ((regs->addr == TI_CPU_STATE)
3511 || (regs->addr == TI_CPU_CTL_B)) {
3512 printf("ti%d: register %#x = %#x\n",
3513 sc->ti_unit, regs->addr, tmpval);
3514 }
3515 #endif
3516 } else {
3517 tmpval = htonl(regs->data);
3518 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3519 regs->addr, &tmpval, 1);
3520 }
3521
3522 break;
3523 }
3524 default:
3525 error = ENOTTY;
3526 break;
3527 }
3528 return(error);
3529 }
3530
3531 static void
3532 ti_watchdog(ifp)
3533 struct ifnet *ifp;
3534 {
3535 struct ti_softc *sc;
3536
3537 sc = ifp->if_softc;
3538 TI_LOCK(sc);
3539
3540 /*
3541 * When we're debugging, the chip is often stopped for long periods
3542 * of time, and that would normally cause the watchdog timer to fire.
3543 * Since that impedes debugging, we don't want to do that.
3544 */
3545 if (sc->ti_flags & TI_FLAG_DEBUGING) {
3546 TI_UNLOCK(sc);
3547 return;
3548 }
3549
3550 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
3551 ti_stop(sc);
3552 ti_init(sc);
3553
3554 ifp->if_oerrors++;
3555 TI_UNLOCK(sc);
3556
3557 return;
3558 }
3559
3560 /*
3561 * Stop the adapter and free any mbufs allocated to the
3562 * RX and TX lists.
3563 */
3564 static void
3565 ti_stop(sc)
3566 struct ti_softc *sc;
3567 {
3568 struct ifnet *ifp;
3569 struct ti_cmd_desc cmd;
3570
3571 TI_LOCK(sc);
3572
3573 ifp = &sc->arpcom.ac_if;
3574
3575 /* Disable host interrupts. */
3576 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3577 /*
3578 * Tell firmware we're shutting down.
3579 */
3580 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3581
3582 /* Halt and reinitialize. */
3583 ti_chipinit(sc);
3584 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
3585 ti_chipinit(sc);
3586
3587 /* Free the RX lists. */
3588 ti_free_rx_ring_std(sc);
3589
3590 /* Free jumbo RX list. */
3591 ti_free_rx_ring_jumbo(sc);
3592
3593 /* Free mini RX list. */
3594 ti_free_rx_ring_mini(sc);
3595
3596 /* Free TX buffers. */
3597 ti_free_tx_ring(sc);
3598
3599 sc->ti_ev_prodidx.ti_idx = 0;
3600 sc->ti_return_prodidx.ti_idx = 0;
3601 sc->ti_tx_considx.ti_idx = 0;
3602 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3603
3604 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3605 TI_UNLOCK(sc);
3606
3607 return;
3608 }
3609
3610 /*
3611 * Stop all chip I/O so that the kernel's probe routines don't
3612 * get confused by errant DMAs when rebooting.
3613 */
3614 static void
3615 ti_shutdown(dev)
3616 device_t dev;
3617 {
3618 struct ti_softc *sc;
3619
3620 sc = device_get_softc(dev);
3621 TI_LOCK(sc);
3622 ti_chipinit(sc);
3623 TI_UNLOCK(sc);
3624
3625 return;
3626 }
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