The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_ti.c

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    1 /*-
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 /*
   34  * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
   35  * Manuals, sample driver and firmware source kits are available
   36  * from http://www.alteon.com/support/openkits.
   37  *
   38  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   39  * Electrical Engineering Department
   40  * Columbia University, New York City
   41  */
   42 
   43 /*
   44  * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
   45  * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
   46  * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
   47  * Tigon supports hardware IP, TCP and UCP checksumming, multicast
   48  * filtering and jumbo (9014 byte) frames. The hardware is largely
   49  * controlled by firmware, which must be loaded into the NIC during
   50  * initialization.
   51  *
   52  * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
   53  * revision, which supports new features such as extended commands,
   54  * extended jumbo receive ring desciptors and a mini receive ring.
   55  *
   56  * Alteon Networks is to be commended for releasing such a vast amount
   57  * of development material for the Tigon NIC without requiring an NDA
   58  * (although they really should have done it a long time ago). With
   59  * any luck, the other vendors will finally wise up and follow Alteon's
   60  * stellar example.
   61  *
   62  * The firmware for the Tigon 1 and 2 NICs is compiled directly into
   63  * this driver by #including it as a C header file. This bloats the
   64  * driver somewhat, but it's the easiest method considering that the
   65  * driver code and firmware code need to be kept in sync. The source
   66  * for the firmware is not provided with the FreeBSD distribution since
   67  * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
   68  *
   69  * The following people deserve special thanks:
   70  * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
   71  *   for testing
   72  * - Raymond Lee of Netgear, for providing a pair of Netgear
   73  *   GA620 Tigon 2 boards for testing
   74  * - Ulf Zimmermann, for bringing the GA260 to my attention and
   75  *   convincing me to write this driver.
   76  * - Andrew Gallatin for providing FreeBSD/Alpha support.
   77  */
   78 
   79 #include <sys/cdefs.h>
   80 __FBSDID("$FreeBSD$");
   81 
   82 #include "opt_ti.h"
   83 
   84 #include <sys/param.h>
   85 #include <sys/systm.h>
   86 #include <sys/sockio.h>
   87 #include <sys/mbuf.h>
   88 #include <sys/malloc.h>
   89 #include <sys/kernel.h>
   90 #include <sys/module.h>
   91 #include <sys/socket.h>
   92 #include <sys/queue.h>
   93 #include <sys/conf.h>
   94 
   95 #include <net/if.h>
   96 #include <net/if_arp.h>
   97 #include <net/ethernet.h>
   98 #include <net/if_dl.h>
   99 #include <net/if_media.h>
  100 #include <net/if_types.h>
  101 #include <net/if_vlan_var.h>
  102 
  103 #include <net/bpf.h>
  104 
  105 #include <netinet/in_systm.h>
  106 #include <netinet/in.h>
  107 #include <netinet/ip.h>
  108 
  109 #include <vm/vm.h>              /* for vtophys */
  110 #include <vm/pmap.h>            /* for vtophys */
  111 #include <machine/bus_memio.h>
  112 #include <machine/bus.h>
  113 #include <machine/resource.h>
  114 #include <sys/bus.h>
  115 #include <sys/rman.h>
  116 
  117 /* #define TI_PRIVATE_JUMBOS */
  118 
  119 #if !defined(TI_PRIVATE_JUMBOS)
  120 #include <sys/sockio.h>
  121 #include <sys/uio.h>
  122 #include <sys/lock.h>
  123 #include <vm/vm_extern.h>
  124 #include <vm/pmap.h>
  125 #include <vm/vm_map.h>
  126 #include <vm/vm_map.h>
  127 #include <vm/vm_param.h>
  128 #include <vm/vm_pageout.h>
  129 #include <sys/vmmeter.h>
  130 #include <vm/vm_page.h>
  131 #include <vm/vm_object.h>
  132 #include <vm/vm_kern.h>
  133 #include <sys/proc.h>
  134 #include <sys/jumbo.h>
  135 #endif /* !TI_PRIVATE_JUMBOS */
  136 
  137 #include <dev/pci/pcireg.h>
  138 #include <dev/pci/pcivar.h>
  139 
  140 #include <sys/tiio.h>
  141 #include <pci/if_tireg.h>
  142 #include <pci/ti_fw.h>
  143 #include <pci/ti_fw2.h>
  144 
  145 #define TI_CSUM_FEATURES        (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
  146 /*
  147  * We can only turn on header splitting if we're using extended receive
  148  * BDs.
  149  */
  150 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
  151 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
  152 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
  153 
  154 struct ti_softc *tis[8];
  155 
  156 typedef enum {
  157         TI_SWAP_HTON,
  158         TI_SWAP_NTOH
  159 } ti_swap_type;
  160 
  161 
  162 /*
  163  * Various supported device vendors/types and their names.
  164  */
  165 
  166 static struct ti_type ti_devs[] = {
  167         { ALT_VENDORID, ALT_DEVICEID_ACENIC,
  168                 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
  169         { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
  170                 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
  171         { TC_VENDORID,  TC_DEVICEID_3C985,
  172                 "3Com 3c985-SX Gigabit Ethernet" },
  173         { NG_VENDORID, NG_DEVICEID_GA620,
  174                 "Netgear GA620 1000baseSX Gigabit Ethernet" },
  175         { NG_VENDORID, NG_DEVICEID_GA620T,
  176                 "Netgear GA620 1000baseT Gigabit Ethernet" },
  177         { SGI_VENDORID, SGI_DEVICEID_TIGON,
  178                 "Silicon Graphics Gigabit Ethernet" },
  179         { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
  180                 "Farallon PN9000SX Gigabit Ethernet" },
  181         { 0, 0, NULL }
  182 };
  183 
  184 
  185 static  d_open_t        ti_open;
  186 static  d_close_t       ti_close;
  187 static  d_ioctl_t       ti_ioctl2;
  188 
  189 static struct cdevsw ti_cdevsw = {
  190         .d_version =    D_VERSION,
  191         .d_flags =      D_NEEDGIANT,
  192         .d_open =       ti_open,
  193         .d_close =      ti_close,
  194         .d_ioctl =      ti_ioctl2,
  195         .d_name =       "ti",
  196 };
  197 
  198 static int ti_probe(device_t);
  199 static int ti_attach(device_t);
  200 static int ti_detach(device_t);
  201 static void ti_txeof(struct ti_softc *);
  202 static void ti_rxeof(struct ti_softc *);
  203 
  204 static void ti_stats_update(struct ti_softc *);
  205 static int ti_encap(struct ti_softc *, struct mbuf *, u_int32_t *);
  206 
  207 static void ti_intr(void *);
  208 static void ti_start(struct ifnet *);
  209 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
  210 static void ti_init(void *);
  211 static void ti_init2(struct ti_softc *);
  212 static void ti_stop(struct ti_softc *);
  213 static void ti_watchdog(struct ifnet *);
  214 static void ti_shutdown(device_t);
  215 static int ti_ifmedia_upd(struct ifnet *);
  216 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  217 
  218 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int);
  219 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *);
  220 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
  221 
  222 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
  223 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
  224 static void ti_setmulti(struct ti_softc *);
  225 
  226 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t);
  227 static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int);
  228 static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t,
  229                 int, int, int);
  230 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
  231 static void ti_loadfw(struct ti_softc *);
  232 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
  233 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
  234 static void ti_handle_events(struct ti_softc *);
  235 #ifdef TI_PRIVATE_JUMBOS
  236 static int ti_alloc_jumbo_mem(struct ti_softc *);
  237 static void *ti_jalloc(struct ti_softc *);
  238 static void ti_jfree(void *, void *);
  239 #endif /* TI_PRIVATE_JUMBOS */
  240 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
  241 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
  242 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
  243 static int ti_init_rx_ring_std(struct ti_softc *);
  244 static void ti_free_rx_ring_std(struct ti_softc *);
  245 static int ti_init_rx_ring_jumbo(struct ti_softc *);
  246 static void ti_free_rx_ring_jumbo(struct ti_softc *);
  247 static int ti_init_rx_ring_mini(struct ti_softc *);
  248 static void ti_free_rx_ring_mini(struct ti_softc *);
  249 static void ti_free_tx_ring(struct ti_softc *);
  250 static int ti_init_tx_ring(struct ti_softc *);
  251 
  252 static int ti_64bitslot_war(struct ti_softc *);
  253 static int ti_chipinit(struct ti_softc *);
  254 static int ti_gibinit(struct ti_softc *);
  255 
  256 #ifdef TI_JUMBO_HDRSPLIT
  257 static __inline void ti_hdr_split       (struct mbuf *top, int hdr_len,
  258                                              int pkt_len, int idx);
  259 #endif /* TI_JUMBO_HDRSPLIT */
  260 
  261 static device_method_t ti_methods[] = {
  262         /* Device interface */
  263         DEVMETHOD(device_probe,         ti_probe),
  264         DEVMETHOD(device_attach,        ti_attach),
  265         DEVMETHOD(device_detach,        ti_detach),
  266         DEVMETHOD(device_shutdown,      ti_shutdown),
  267         { 0, 0 }
  268 };
  269 
  270 static driver_t ti_driver = {
  271         "ti",
  272         ti_methods,
  273         sizeof(struct ti_softc)
  274 };
  275 
  276 static devclass_t ti_devclass;
  277 
  278 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
  279 MODULE_DEPEND(ti, pci, 1, 1, 1);
  280 MODULE_DEPEND(ti, ether, 1, 1, 1);
  281 
  282 /*
  283  * Send an instruction or address to the EEPROM, check for ACK.
  284  */
  285 static u_int32_t ti_eeprom_putbyte(sc, byte)
  286         struct ti_softc         *sc;
  287         int                     byte;
  288 {
  289         register int            i, ack = 0;
  290 
  291         /*
  292          * Make sure we're in TX mode.
  293          */
  294         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
  295 
  296         /*
  297          * Feed in each bit and stobe the clock.
  298          */
  299         for (i = 0x80; i; i >>= 1) {
  300                 if (byte & i) {
  301                         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
  302                 } else {
  303                         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
  304                 }
  305                 DELAY(1);
  306                 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  307                 DELAY(1);
  308                 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  309         }
  310 
  311         /*
  312          * Turn off TX mode.
  313          */
  314         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
  315 
  316         /*
  317          * Check for ack.
  318          */
  319         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  320         ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
  321         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  322 
  323         return (ack);
  324 }
  325 
  326 /*
  327  * Read a byte of data stored in the EEPROM at address 'addr.'
  328  * We have to send two address bytes since the EEPROM can hold
  329  * more than 256 bytes of data.
  330  */
  331 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
  332         struct ti_softc         *sc;
  333         int                     addr;
  334         u_int8_t                *dest;
  335 {
  336         register int            i;
  337         u_int8_t                byte = 0;
  338 
  339         EEPROM_START;
  340 
  341         /*
  342          * Send write control code to EEPROM.
  343          */
  344         if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
  345                 printf("ti%d: failed to send write command, status: %x\n",
  346                     sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  347                 return (1);
  348         }
  349 
  350         /*
  351          * Send first byte of address of byte we want to read.
  352          */
  353         if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
  354                 printf("ti%d: failed to send address, status: %x\n",
  355                     sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  356                 return (1);
  357         }
  358         /*
  359          * Send second byte address of byte we want to read.
  360          */
  361         if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
  362                 printf("ti%d: failed to send address, status: %x\n",
  363                     sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  364                 return (1);
  365         }
  366 
  367         EEPROM_STOP;
  368         EEPROM_START;
  369         /*
  370          * Send read control code to EEPROM.
  371          */
  372         if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
  373                 printf("ti%d: failed to send read command, status: %x\n",
  374                     sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  375                 return (1);
  376         }
  377 
  378         /*
  379          * Start reading bits from EEPROM.
  380          */
  381         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
  382         for (i = 0x80; i; i >>= 1) {
  383                 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  384                 DELAY(1);
  385                 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
  386                         byte |= i;
  387                 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  388                 DELAY(1);
  389         }
  390 
  391         EEPROM_STOP;
  392 
  393         /*
  394          * No ACK generated for read, so just return byte.
  395          */
  396 
  397         *dest = byte;
  398 
  399         return (0);
  400 }
  401 
  402 /*
  403  * Read a sequence of bytes from the EEPROM.
  404  */
  405 static int
  406 ti_read_eeprom(sc, dest, off, cnt)
  407         struct ti_softc         *sc;
  408         caddr_t                 dest;
  409         int                     off;
  410         int                     cnt;
  411 {
  412         int                     err = 0, i;
  413         u_int8_t                byte = 0;
  414 
  415         for (i = 0; i < cnt; i++) {
  416                 err = ti_eeprom_getbyte(sc, off + i, &byte);
  417                 if (err)
  418                         break;
  419                 *(dest + i) = byte;
  420         }
  421 
  422         return (err ? 1 : 0);
  423 }
  424 
  425 /*
  426  * NIC memory access function. Can be used to either clear a section
  427  * of NIC local memory or (if buf is non-NULL) copy data into it.
  428  */
  429 static void
  430 ti_mem(sc, addr, len, buf)
  431         struct ti_softc         *sc;
  432         u_int32_t               addr, len;
  433         caddr_t                 buf;
  434 {
  435         int                     segptr, segsize, cnt;
  436         caddr_t                 ti_winbase, ptr;
  437 
  438         segptr = addr;
  439         cnt = len;
  440         ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
  441         ptr = buf;
  442 
  443         while (cnt) {
  444                 if (cnt < TI_WINLEN)
  445                         segsize = cnt;
  446                 else
  447                         segsize = TI_WINLEN - (segptr % TI_WINLEN);
  448                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
  449                 if (buf == NULL)
  450                         bzero((char *)ti_winbase + (segptr &
  451                             (TI_WINLEN - 1)), segsize);
  452                 else {
  453                         bcopy((char *)ptr, (char *)ti_winbase +
  454                             (segptr & (TI_WINLEN - 1)), segsize);
  455                         ptr += segsize;
  456                 }
  457                 segptr += segsize;
  458                 cnt -= segsize;
  459         }
  460 }
  461 
  462 static int
  463 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata)
  464         struct ti_softc         *sc;
  465         u_int32_t               tigon_addr, len;
  466         caddr_t                 buf;
  467         int                     useraddr, readdata;
  468 {
  469         int             segptr, segsize, cnt;
  470         caddr_t         ptr;
  471         u_int32_t       origwin;
  472         u_int8_t        tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
  473         int             resid, segresid;
  474         int             first_pass;
  475 
  476         /*
  477          * At the moment, we don't handle non-aligned cases, we just bail.
  478          * If this proves to be a problem, it will be fixed.
  479          */
  480         if ((readdata == 0)
  481          && (tigon_addr & 0x3)) {
  482                 printf("ti%d: ti_copy_mem: tigon address %#x isn't "
  483                        "word-aligned\n", sc->ti_unit, tigon_addr);
  484                 printf("ti%d: ti_copy_mem: unaligned writes aren't yet "
  485                        "supported\n", sc->ti_unit);
  486                 return (EINVAL);
  487         }
  488 
  489         segptr = tigon_addr & ~0x3;
  490         segresid = tigon_addr - segptr;
  491 
  492         /*
  493          * This is the non-aligned amount left over that we'll need to
  494          * copy.
  495          */
  496         resid = len & 0x3;
  497 
  498         /* Add in the left over amount at the front of the buffer */
  499         resid += segresid;
  500 
  501         cnt = len & ~0x3;
  502         /*
  503          * If resid + segresid is >= 4, add multiples of 4 to the count and
  504          * decrease the residual by that much.
  505          */
  506         cnt += resid & ~0x3;
  507         resid -= resid & ~0x3;
  508 
  509         ptr = buf;
  510 
  511         first_pass = 1;
  512 
  513         /*
  514          * Make sure we aren't interrupted while we're changing the window
  515          * pointer.
  516          */
  517         TI_LOCK(sc);
  518 
  519         /*
  520          * Save the old window base value.
  521          */
  522         origwin = CSR_READ_4(sc, TI_WINBASE);
  523 
  524         while (cnt) {
  525                 bus_size_t ti_offset;
  526 
  527                 if (cnt < TI_WINLEN)
  528                         segsize = cnt;
  529                 else
  530                         segsize = TI_WINLEN - (segptr % TI_WINLEN);
  531                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
  532 
  533                 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
  534 
  535                 if (readdata) {
  536 
  537                         bus_space_read_region_4(sc->ti_btag,
  538                                                 sc->ti_bhandle, ti_offset,
  539                                                 (u_int32_t *)tmparray,
  540                                                 segsize >> 2);
  541                         if (useraddr) {
  542                                 /*
  543                                  * Yeah, this is a little on the kludgy
  544                                  * side, but at least this code is only
  545                                  * used for debugging.
  546                                  */
  547                                 ti_bcopy_swap(tmparray, tmparray2, segsize,
  548                                               TI_SWAP_NTOH);
  549 
  550                                 if (first_pass) {
  551                                         copyout(&tmparray2[segresid], ptr,
  552                                                 segsize - segresid);
  553                                         first_pass = 0;
  554                                 } else
  555                                         copyout(tmparray2, ptr, segsize);
  556                         } else {
  557                                 if (first_pass) {
  558 
  559                                         ti_bcopy_swap(tmparray, tmparray2,
  560                                                       segsize, TI_SWAP_NTOH);
  561                                         bcopy(&tmparray2[segresid], ptr,
  562                                               segsize - segresid);
  563                                         first_pass = 0;
  564                                 } else
  565                                         ti_bcopy_swap(tmparray, ptr, segsize,
  566                                                       TI_SWAP_NTOH);
  567                         }
  568 
  569                 } else {
  570                         if (useraddr) {
  571                                 copyin(ptr, tmparray2, segsize);
  572                                 ti_bcopy_swap(tmparray2, tmparray, segsize,
  573                                               TI_SWAP_HTON);
  574                         } else
  575                                 ti_bcopy_swap(ptr, tmparray, segsize,
  576                                               TI_SWAP_HTON);
  577 
  578                         bus_space_write_region_4(sc->ti_btag,
  579                                                  sc->ti_bhandle, ti_offset,
  580                                                  (u_int32_t *)tmparray,
  581                                                  segsize >> 2);
  582                 }
  583                 segptr += segsize;
  584                 ptr += segsize;
  585                 cnt -= segsize;
  586         }
  587 
  588         /*
  589          * Handle leftover, non-word-aligned bytes.
  590          */
  591         if (resid != 0) {
  592                 u_int32_t       tmpval, tmpval2;
  593                 bus_size_t      ti_offset;
  594 
  595                 /*
  596                  * Set the segment pointer.
  597                  */
  598                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
  599 
  600                 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
  601 
  602                 /*
  603                  * First, grab whatever is in our source/destination.
  604                  * We'll obviously need this for reads, but also for
  605                  * writes, since we'll be doing read/modify/write.
  606                  */
  607                 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
  608                                         ti_offset, &tmpval, 1);
  609 
  610                 /*
  611                  * Next, translate this from little-endian to big-endian
  612                  * (at least on i386 boxes).
  613                  */
  614                 tmpval2 = ntohl(tmpval);
  615 
  616                 if (readdata) {
  617                         /*
  618                          * If we're reading, just copy the leftover number
  619                          * of bytes from the host byte order buffer to
  620                          * the user's buffer.
  621                          */
  622                         if (useraddr)
  623                                 copyout(&tmpval2, ptr, resid);
  624                         else
  625                                 bcopy(&tmpval2, ptr, resid);
  626                 } else {
  627                         /*
  628                          * If we're writing, first copy the bytes to be
  629                          * written into the network byte order buffer,
  630                          * leaving the rest of the buffer with whatever was
  631                          * originally in there.  Then, swap the bytes
  632                          * around into host order and write them out.
  633                          *
  634                          * XXX KDM the read side of this has been verified
  635                          * to work, but the write side of it has not been
  636                          * verified.  So user beware.
  637                          */
  638                         if (useraddr)
  639                                 copyin(ptr, &tmpval2, resid);
  640                         else
  641                                 bcopy(ptr, &tmpval2, resid);
  642 
  643                         tmpval = htonl(tmpval2);
  644 
  645                         bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
  646                                                  ti_offset, &tmpval, 1);
  647                 }
  648         }
  649 
  650         CSR_WRITE_4(sc, TI_WINBASE, origwin);
  651 
  652         TI_UNLOCK(sc);
  653 
  654         return (0);
  655 }
  656 
  657 static int
  658 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu)
  659         struct ti_softc         *sc;
  660         u_int32_t               tigon_addr, len;
  661         caddr_t                 buf;
  662         int                     useraddr, readdata;
  663         int                     cpu;
  664 {
  665         u_int32_t       segptr;
  666         int             cnt;
  667         u_int32_t       tmpval, tmpval2;
  668         caddr_t         ptr;
  669 
  670         /*
  671          * At the moment, we don't handle non-aligned cases, we just bail.
  672          * If this proves to be a problem, it will be fixed.
  673          */
  674         if (tigon_addr & 0x3) {
  675                 printf("ti%d: ti_copy_scratch: tigon address %#x isn't "
  676                        "word-aligned\n", sc->ti_unit, tigon_addr);
  677                 return (EINVAL);
  678         }
  679 
  680         if (len & 0x3) {
  681                 printf("ti%d: ti_copy_scratch: transfer length %d isn't "
  682                        "word-aligned\n", sc->ti_unit, len);
  683                 return (EINVAL);
  684         }
  685 
  686         segptr = tigon_addr;
  687         cnt = len;
  688         ptr = buf;
  689 
  690         TI_LOCK(sc);
  691 
  692         while (cnt) {
  693                 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
  694 
  695                 if (readdata) {
  696                         tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
  697 
  698                         tmpval = ntohl(tmpval2);
  699 
  700                         /*
  701                          * Note:  I've used this debugging interface
  702                          * extensively with Alteon's 12.3.15 firmware,
  703                          * compiled with GCC 2.7.2.1 and binutils 2.9.1.
  704                          *
  705                          * When you compile the firmware without
  706                          * optimization, which is necessary sometimes in
  707                          * order to properly step through it, you sometimes
  708                          * read out a bogus value of 0xc0017c instead of
  709                          * whatever was supposed to be in that scratchpad
  710                          * location.  That value is on the stack somewhere,
  711                          * but I've never been able to figure out what was
  712                          * causing the problem.
  713                          *
  714                          * The address seems to pop up in random places,
  715                          * often not in the same place on two subsequent
  716                          * reads.
  717                          *
  718                          * In any case, the underlying data doesn't seem
  719                          * to be affected, just the value read out.
  720                          *
  721                          * KDM, 3/7/2000
  722                          */
  723 
  724                         if (tmpval2 == 0xc0017c)
  725                                 printf("ti%d: found 0xc0017c at %#x "
  726                                        "(tmpval2)\n", sc->ti_unit, segptr);
  727 
  728                         if (tmpval == 0xc0017c)
  729                                 printf("ti%d: found 0xc0017c at %#x "
  730                                        "(tmpval)\n", sc->ti_unit, segptr);
  731 
  732                         if (useraddr)
  733                                 copyout(&tmpval, ptr, 4);
  734                         else
  735                                 bcopy(&tmpval, ptr, 4);
  736                 } else {
  737                         if (useraddr)
  738                                 copyin(ptr, &tmpval2, 4);
  739                         else
  740                                 bcopy(ptr, &tmpval2, 4);
  741 
  742                         tmpval = htonl(tmpval2);
  743 
  744                         CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
  745                 }
  746 
  747                 cnt -= 4;
  748                 segptr += 4;
  749                 ptr += 4;
  750         }
  751 
  752         TI_UNLOCK(sc);
  753 
  754         return (0);
  755 }
  756 
  757 static int
  758 ti_bcopy_swap(src, dst, len, swap_type)
  759         const void      *src;
  760         void            *dst;
  761         size_t          len;
  762         ti_swap_type    swap_type;
  763 {
  764         const u_int8_t *tmpsrc;
  765         u_int8_t *tmpdst;
  766         size_t tmplen;
  767 
  768         if (len & 0x3) {
  769                 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
  770                        len);
  771                 return (-1);
  772         }
  773 
  774         tmpsrc = src;
  775         tmpdst = dst;
  776         tmplen = len;
  777 
  778         while (tmplen) {
  779                 if (swap_type == TI_SWAP_NTOH)
  780                         *(u_int32_t *)tmpdst =
  781                                 ntohl(*(const u_int32_t *)tmpsrc);
  782                 else
  783                         *(u_int32_t *)tmpdst =
  784                                 htonl(*(const u_int32_t *)tmpsrc);
  785 
  786                 tmpsrc += 4;
  787                 tmpdst += 4;
  788                 tmplen -= 4;
  789         }
  790 
  791         return (0);
  792 }
  793 
  794 /*
  795  * Load firmware image into the NIC. Check that the firmware revision
  796  * is acceptable and see if we want the firmware for the Tigon 1 or
  797  * Tigon 2.
  798  */
  799 static void
  800 ti_loadfw(sc)
  801         struct ti_softc         *sc;
  802 {
  803         switch (sc->ti_hwrev) {
  804         case TI_HWREV_TIGON:
  805                 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
  806                     tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
  807                     tigonFwReleaseFix != TI_FIRMWARE_FIX) {
  808                         printf("ti%d: firmware revision mismatch; want "
  809                             "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
  810                             TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
  811                             TI_FIRMWARE_FIX, tigonFwReleaseMajor,
  812                             tigonFwReleaseMinor, tigonFwReleaseFix);
  813                         return;
  814                 }
  815                 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
  816                     (caddr_t)tigonFwText);
  817                 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
  818                     (caddr_t)tigonFwData);
  819                 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
  820                     (caddr_t)tigonFwRodata);
  821                 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
  822                 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
  823                 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
  824                 break;
  825         case TI_HWREV_TIGON_II:
  826                 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
  827                     tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
  828                     tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
  829                         printf("ti%d: firmware revision mismatch; want "
  830                             "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
  831                             TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
  832                             TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
  833                             tigon2FwReleaseMinor, tigon2FwReleaseFix);
  834                         return;
  835                 }
  836                 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
  837                     (caddr_t)tigon2FwText);
  838                 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
  839                     (caddr_t)tigon2FwData);
  840                 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
  841                     (caddr_t)tigon2FwRodata);
  842                 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
  843                 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
  844                 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
  845                 break;
  846         default:
  847                 printf("ti%d: can't load firmware: unknown hardware rev\n",
  848                     sc->ti_unit);
  849                 break;
  850         }
  851 }
  852 
  853 /*
  854  * Send the NIC a command via the command ring.
  855  */
  856 static void
  857 ti_cmd(sc, cmd)
  858         struct ti_softc         *sc;
  859         struct ti_cmd_desc      *cmd;
  860 {
  861         u_int32_t               index;
  862 
  863         if (sc->ti_rdata->ti_cmd_ring == NULL)
  864                 return;
  865 
  866         index = sc->ti_cmd_saved_prodidx;
  867         CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
  868         TI_INC(index, TI_CMD_RING_CNT);
  869         CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
  870         sc->ti_cmd_saved_prodidx = index;
  871 }
  872 
  873 /*
  874  * Send the NIC an extended command. The 'len' parameter specifies the
  875  * number of command slots to include after the initial command.
  876  */
  877 static void
  878 ti_cmd_ext(sc, cmd, arg, len)
  879         struct ti_softc         *sc;
  880         struct ti_cmd_desc      *cmd;
  881         caddr_t                 arg;
  882         int                     len;
  883 {
  884         u_int32_t               index;
  885         register int            i;
  886 
  887         if (sc->ti_rdata->ti_cmd_ring == NULL)
  888                 return;
  889 
  890         index = sc->ti_cmd_saved_prodidx;
  891         CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
  892         TI_INC(index, TI_CMD_RING_CNT);
  893         for (i = 0; i < len; i++) {
  894                 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
  895                     *(u_int32_t *)(&arg[i * 4]));
  896                 TI_INC(index, TI_CMD_RING_CNT);
  897         }
  898         CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
  899         sc->ti_cmd_saved_prodidx = index;
  900 }
  901 
  902 /*
  903  * Handle events that have triggered interrupts.
  904  */
  905 static void
  906 ti_handle_events(sc)
  907         struct ti_softc         *sc;
  908 {
  909         struct ti_event_desc    *e;
  910 
  911         if (sc->ti_rdata->ti_event_ring == NULL)
  912                 return;
  913 
  914         while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
  915                 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
  916                 switch (e->ti_event) {
  917                 case TI_EV_LINKSTAT_CHANGED:
  918                         sc->ti_linkstat = e->ti_code;
  919                         if (e->ti_code == TI_EV_CODE_LINK_UP)
  920                                 printf("ti%d: 10/100 link up\n", sc->ti_unit);
  921                         else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
  922                                 printf("ti%d: gigabit link up\n", sc->ti_unit);
  923                         else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
  924                                 printf("ti%d: link down\n", sc->ti_unit);
  925                         break;
  926                 case TI_EV_ERROR:
  927                         if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
  928                                 printf("ti%d: invalid command\n", sc->ti_unit);
  929                         else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
  930                                 printf("ti%d: unknown command\n", sc->ti_unit);
  931                         else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
  932                                 printf("ti%d: bad config data\n", sc->ti_unit);
  933                         break;
  934                 case TI_EV_FIRMWARE_UP:
  935                         ti_init2(sc);
  936                         break;
  937                 case TI_EV_STATS_UPDATED:
  938                         ti_stats_update(sc);
  939                         break;
  940                 case TI_EV_RESET_JUMBO_RING:
  941                 case TI_EV_MCAST_UPDATED:
  942                         /* Who cares. */
  943                         break;
  944                 default:
  945                         printf("ti%d: unknown event: %d\n",
  946                             sc->ti_unit, e->ti_event);
  947                         break;
  948                 }
  949                 /* Advance the consumer index. */
  950                 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
  951                 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
  952         }
  953 }
  954 
  955 #ifdef TI_PRIVATE_JUMBOS
  956 
  957 /*
  958  * Memory management for the jumbo receive ring is a pain in the
  959  * butt. We need to allocate at least 9018 bytes of space per frame,
  960  * _and_ it has to be contiguous (unless you use the extended
  961  * jumbo descriptor format). Using malloc() all the time won't
  962  * work: malloc() allocates memory in powers of two, which means we
  963  * would end up wasting a considerable amount of space by allocating
  964  * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
  965  * to do our own memory management.
  966  *
  967  * The driver needs to allocate a contiguous chunk of memory at boot
  968  * time. We then chop this up ourselves into 9K pieces and use them
  969  * as external mbuf storage.
  970  *
  971  * One issue here is how much memory to allocate. The jumbo ring has
  972  * 256 slots in it, but at 9K per slot than can consume over 2MB of
  973  * RAM. This is a bit much, especially considering we also need
  974  * RAM for the standard ring and mini ring (on the Tigon 2). To
  975  * save space, we only actually allocate enough memory for 64 slots
  976  * by default, which works out to between 500 and 600K. This can
  977  * be tuned by changing a #define in if_tireg.h.
  978  */
  979 
  980 static int
  981 ti_alloc_jumbo_mem(sc)
  982         struct ti_softc         *sc;
  983 {
  984         caddr_t                 ptr;
  985         register int            i;
  986         struct ti_jpool_entry   *entry;
  987 
  988         /* Grab a big chunk o' storage. */
  989         sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
  990                 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
  991 
  992         if (sc->ti_cdata.ti_jumbo_buf == NULL) {
  993                 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
  994                 return (ENOBUFS);
  995         }
  996 
  997         SLIST_INIT(&sc->ti_jfree_listhead);
  998         SLIST_INIT(&sc->ti_jinuse_listhead);
  999 
 1000         /*
 1001          * Now divide it up into 9K pieces and save the addresses
 1002          * in an array.
 1003          */
 1004         ptr = sc->ti_cdata.ti_jumbo_buf;
 1005         for (i = 0; i < TI_JSLOTS; i++) {
 1006                 sc->ti_cdata.ti_jslots[i] = ptr;
 1007                 ptr += TI_JLEN;
 1008                 entry = malloc(sizeof(struct ti_jpool_entry),
 1009                                M_DEVBUF, M_NOWAIT);
 1010                 if (entry == NULL) {
 1011                         contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
 1012                                    M_DEVBUF);
 1013                         sc->ti_cdata.ti_jumbo_buf = NULL;
 1014                         printf("ti%d: no memory for jumbo "
 1015                             "buffer queue!\n", sc->ti_unit);
 1016                         return (ENOBUFS);
 1017                 }
 1018                 entry->slot = i;
 1019                 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
 1020         }
 1021 
 1022         return (0);
 1023 }
 1024 
 1025 /*
 1026  * Allocate a jumbo buffer.
 1027  */
 1028 static void *ti_jalloc(sc)
 1029         struct ti_softc         *sc;
 1030 {
 1031         struct ti_jpool_entry   *entry;
 1032 
 1033         entry = SLIST_FIRST(&sc->ti_jfree_listhead);
 1034 
 1035         if (entry == NULL) {
 1036                 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
 1037                 return (NULL);
 1038         }
 1039 
 1040         SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
 1041         SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
 1042         return (sc->ti_cdata.ti_jslots[entry->slot]);
 1043 }
 1044 
 1045 /*
 1046  * Release a jumbo buffer.
 1047  */
 1048 static void
 1049 ti_jfree(buf, args)
 1050         void                    *buf;
 1051         void                    *args;
 1052 {
 1053         struct ti_softc         *sc;
 1054         int                     i;
 1055         struct ti_jpool_entry   *entry;
 1056 
 1057         /* Extract the softc struct pointer. */
 1058         sc = (struct ti_softc *)args;
 1059 
 1060         if (sc == NULL)
 1061                 panic("ti_jfree: didn't get softc pointer!");
 1062 
 1063         /* calculate the slot this buffer belongs to */
 1064         i = ((vm_offset_t)buf
 1065              - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
 1066 
 1067         if ((i < 0) || (i >= TI_JSLOTS))
 1068                 panic("ti_jfree: asked to free buffer that we don't manage!");
 1069 
 1070         entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
 1071         if (entry == NULL)
 1072                 panic("ti_jfree: buffer not in use!");
 1073         entry->slot = i;
 1074         SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
 1075         SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
 1076 }
 1077 
 1078 #endif /* TI_PRIVATE_JUMBOS */
 1079 
 1080 /*
 1081  * Intialize a standard receive ring descriptor.
 1082  */
 1083 static int
 1084 ti_newbuf_std(sc, i, m)
 1085         struct ti_softc         *sc;
 1086         int                     i;
 1087         struct mbuf             *m;
 1088 {
 1089         struct mbuf             *m_new = NULL;
 1090         struct ti_rx_desc       *r;
 1091 
 1092         if (m == NULL) {
 1093                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1094                 if (m_new == NULL)
 1095                         return (ENOBUFS);
 1096 
 1097                 MCLGET(m_new, M_DONTWAIT);
 1098                 if (!(m_new->m_flags & M_EXT)) {
 1099                         m_freem(m_new);
 1100                         return (ENOBUFS);
 1101                 }
 1102                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 1103         } else {
 1104                 m_new = m;
 1105                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 1106                 m_new->m_data = m_new->m_ext.ext_buf;
 1107         }
 1108 
 1109         m_adj(m_new, ETHER_ALIGN);
 1110         sc->ti_cdata.ti_rx_std_chain[i] = m_new;
 1111         r = &sc->ti_rdata->ti_rx_std_ring[i];
 1112         TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
 1113         r->ti_type = TI_BDTYPE_RECV_BD;
 1114         r->ti_flags = 0;
 1115         if (sc->arpcom.ac_if.if_hwassist)
 1116                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
 1117         r->ti_len = m_new->m_len;
 1118         r->ti_idx = i;
 1119 
 1120         return (0);
 1121 }
 1122 
 1123 /*
 1124  * Intialize a mini receive ring descriptor. This only applies to
 1125  * the Tigon 2.
 1126  */
 1127 static int
 1128 ti_newbuf_mini(sc, i, m)
 1129         struct ti_softc         *sc;
 1130         int                     i;
 1131         struct mbuf             *m;
 1132 {
 1133         struct mbuf             *m_new = NULL;
 1134         struct ti_rx_desc       *r;
 1135 
 1136         if (m == NULL) {
 1137                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1138                 if (m_new == NULL) {
 1139                         return (ENOBUFS);
 1140                 }
 1141                 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
 1142         } else {
 1143                 m_new = m;
 1144                 m_new->m_data = m_new->m_pktdat;
 1145                 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
 1146         }
 1147 
 1148         m_adj(m_new, ETHER_ALIGN);
 1149         r = &sc->ti_rdata->ti_rx_mini_ring[i];
 1150         sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
 1151         TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
 1152         r->ti_type = TI_BDTYPE_RECV_BD;
 1153         r->ti_flags = TI_BDFLAG_MINI_RING;
 1154         if (sc->arpcom.ac_if.if_hwassist)
 1155                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
 1156         r->ti_len = m_new->m_len;
 1157         r->ti_idx = i;
 1158 
 1159         return (0);
 1160 }
 1161 
 1162 #ifdef TI_PRIVATE_JUMBOS
 1163 
 1164 /*
 1165  * Initialize a jumbo receive ring descriptor. This allocates
 1166  * a jumbo buffer from the pool managed internally by the driver.
 1167  */
 1168 static int
 1169 ti_newbuf_jumbo(sc, i, m)
 1170         struct ti_softc         *sc;
 1171         int                     i;
 1172         struct mbuf             *m;
 1173 {
 1174         struct mbuf             *m_new = NULL;
 1175         struct ti_rx_desc       *r;
 1176 
 1177         if (m == NULL) {
 1178                 caddr_t                 *buf = NULL;
 1179 
 1180                 /* Allocate the mbuf. */
 1181                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1182                 if (m_new == NULL) {
 1183                         return (ENOBUFS);
 1184                 }
 1185 
 1186                 /* Allocate the jumbo buffer */
 1187                 buf = ti_jalloc(sc);
 1188                 if (buf == NULL) {
 1189                         m_freem(m_new);
 1190                         printf("ti%d: jumbo allocation failed "
 1191                             "-- packet dropped!\n", sc->ti_unit);
 1192                         return (ENOBUFS);
 1193                 }
 1194 
 1195                 /* Attach the buffer to the mbuf. */
 1196                 m_new->m_data = (void *) buf;
 1197                 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
 1198                 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
 1199                     (struct ti_softc *)sc, 0, EXT_NET_DRV);
 1200         } else {
 1201                 m_new = m;
 1202                 m_new->m_data = m_new->m_ext.ext_buf;
 1203                 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
 1204         }
 1205 
 1206         m_adj(m_new, ETHER_ALIGN);
 1207         /* Set up the descriptor. */
 1208         r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
 1209         sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
 1210         TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
 1211         r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
 1212         r->ti_flags = TI_BDFLAG_JUMBO_RING;
 1213         if (sc->arpcom.ac_if.if_hwassist)
 1214                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
 1215         r->ti_len = m_new->m_len;
 1216         r->ti_idx = i;
 1217 
 1218         return (0);
 1219 }
 1220 
 1221 #else
 1222 #include <vm/vm_page.h>
 1223 
 1224 #if (PAGE_SIZE == 4096)
 1225 #define NPAYLOAD 2
 1226 #else
 1227 #define NPAYLOAD 1
 1228 #endif
 1229 
 1230 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
 1231 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
 1232 #define NFS_HDR_LEN (UDP_HDR_LEN)
 1233 static int HDR_LEN =  TCP_HDR_LEN;
 1234 
 1235 
 1236 /*
 1237  * Initialize a jumbo receive ring descriptor. This allocates
 1238  * a jumbo buffer from the pool managed internally by the driver.
 1239  */
 1240 static int
 1241 ti_newbuf_jumbo(sc, idx, m_old)
 1242         struct ti_softc         *sc;
 1243         int                     idx;
 1244         struct mbuf             *m_old;
 1245 {
 1246         struct mbuf             *cur, *m_new = NULL;
 1247         struct mbuf             *m[3] = {NULL, NULL, NULL};
 1248         struct ti_rx_desc_ext   *r;
 1249         vm_page_t               frame;
 1250                                 /* 1 extra buf to make nobufs easy*/
 1251         caddr_t                 buf[3] = {NULL, NULL, NULL};
 1252         int                     i;
 1253 
 1254         if (m_old != NULL) {
 1255                 m_new = m_old;
 1256                 cur = m_old->m_next;
 1257                 for (i = 0; i <= NPAYLOAD; i++){
 1258                         m[i] = cur;
 1259                         cur = cur->m_next;
 1260                 }
 1261         } else {
 1262                 /* Allocate the mbufs. */
 1263                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1264                 if (m_new == NULL) {
 1265                         printf("ti%d: mbuf allocation failed "
 1266                                "-- packet dropped!\n", sc->ti_unit);
 1267                         goto nobufs;
 1268                 }
 1269                 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
 1270                 if (m[NPAYLOAD] == NULL) {
 1271                         printf("ti%d: cluster mbuf allocation failed "
 1272                                "-- packet dropped!\n", sc->ti_unit);
 1273                         goto nobufs;
 1274                 }
 1275                 MCLGET(m[NPAYLOAD], M_DONTWAIT);
 1276                 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
 1277                         printf("ti%d: mbuf allocation failed "
 1278                                "-- packet dropped!\n", sc->ti_unit);
 1279                         goto nobufs;
 1280                 }
 1281                 m[NPAYLOAD]->m_len = MCLBYTES;
 1282 
 1283                 for (i = 0; i < NPAYLOAD; i++){
 1284                         MGET(m[i], M_DONTWAIT, MT_DATA);
 1285                         if (m[i] == NULL) {
 1286                                 printf("ti%d: mbuf allocation failed "
 1287                                        "-- packet dropped!\n", sc->ti_unit);
 1288                                 goto nobufs;
 1289                         }
 1290                         if (!(frame = jumbo_pg_alloc())){
 1291                                 printf("ti%d: buffer allocation failed "
 1292                                        "-- packet dropped!\n", sc->ti_unit);
 1293                                 printf("      index %d page %d\n", idx, i);
 1294                                 goto nobufs;
 1295                         }
 1296                         buf[i] = jumbo_phys_to_kva(VM_PAGE_TO_PHYS(frame));
 1297                 }
 1298                 for (i = 0; i < NPAYLOAD; i++){
 1299                 /* Attach the buffer to the mbuf. */
 1300                         m[i]->m_data = (void *)buf[i];
 1301                         m[i]->m_len = PAGE_SIZE;
 1302                         MEXTADD(m[i], (void *)buf[i], PAGE_SIZE,
 1303                                 jumbo_freem, NULL, 0, EXT_DISPOSABLE);
 1304                         m[i]->m_next = m[i+1];
 1305                 }
 1306                 /* link the buffers to the header */
 1307                 m_new->m_next = m[0];
 1308                 m_new->m_data += ETHER_ALIGN;
 1309                 if (sc->ti_hdrsplit)
 1310                         m_new->m_len = MHLEN - ETHER_ALIGN;
 1311                 else
 1312                         m_new->m_len = HDR_LEN;
 1313                 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
 1314         }
 1315 
 1316         /* Set up the descriptor. */
 1317         r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
 1318         sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
 1319         TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t));
 1320         r->ti_len0 = m_new->m_len;
 1321 
 1322         TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t));
 1323         r->ti_len1 = PAGE_SIZE;
 1324 
 1325         TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t));
 1326         r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
 1327 
 1328         if (PAGE_SIZE == 4096) {
 1329                 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t));
 1330                 r->ti_len3 = MCLBYTES;
 1331         } else {
 1332                 r->ti_len3 = 0;
 1333         }
 1334         r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
 1335 
 1336         r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
 1337 
 1338         if (sc->arpcom.ac_if.if_hwassist)
 1339                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
 1340 
 1341         r->ti_idx = idx;
 1342 
 1343         return (0);
 1344 
 1345 nobufs:
 1346 
 1347         /*
 1348          * Warning! :
 1349          * This can only be called before the mbufs are strung together.
 1350          * If the mbufs are strung together, m_freem() will free the chain,
 1351          * so that the later mbufs will be freed multiple times.
 1352          */
 1353         if (m_new)
 1354                 m_freem(m_new);
 1355 
 1356         for (i = 0; i < 3; i++) {
 1357                 if (m[i])
 1358                         m_freem(m[i]);
 1359                 if (buf[i])
 1360                         jumbo_pg_free((vm_offset_t)buf[i]);
 1361         }
 1362         return (ENOBUFS);
 1363 }
 1364 #endif
 1365 
 1366 
 1367 
 1368 /*
 1369  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 1370  * that's 1MB or memory, which is a lot. For now, we fill only the first
 1371  * 256 ring entries and hope that our CPU is fast enough to keep up with
 1372  * the NIC.
 1373  */
 1374 static int
 1375 ti_init_rx_ring_std(sc)
 1376         struct ti_softc         *sc;
 1377 {
 1378         register int            i;
 1379         struct ti_cmd_desc      cmd;
 1380 
 1381         for (i = 0; i < TI_SSLOTS; i++) {
 1382                 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
 1383                         return (ENOBUFS);
 1384         };
 1385 
 1386         TI_UPDATE_STDPROD(sc, i - 1);
 1387         sc->ti_std = i - 1;
 1388 
 1389         return (0);
 1390 }
 1391 
 1392 static void
 1393 ti_free_rx_ring_std(sc)
 1394         struct ti_softc         *sc;
 1395 {
 1396         register int            i;
 1397 
 1398         for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
 1399                 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
 1400                         m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
 1401                         sc->ti_cdata.ti_rx_std_chain[i] = NULL;
 1402                 }
 1403                 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
 1404                     sizeof(struct ti_rx_desc));
 1405         }
 1406 }
 1407 
 1408 static int
 1409 ti_init_rx_ring_jumbo(sc)
 1410         struct ti_softc         *sc;
 1411 {
 1412         register int            i;
 1413         struct ti_cmd_desc      cmd;
 1414 
 1415         for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
 1416                 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 1417                         return (ENOBUFS);
 1418         };
 1419 
 1420         TI_UPDATE_JUMBOPROD(sc, i - 1);
 1421         sc->ti_jumbo = i - 1;
 1422 
 1423         return (0);
 1424 }
 1425 
 1426 static void
 1427 ti_free_rx_ring_jumbo(sc)
 1428         struct ti_softc         *sc;
 1429 {
 1430         register int            i;
 1431 
 1432         for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
 1433                 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
 1434                         m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
 1435                         sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
 1436                 }
 1437                 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
 1438                     sizeof(struct ti_rx_desc));
 1439         }
 1440 }
 1441 
 1442 static int
 1443 ti_init_rx_ring_mini(sc)
 1444         struct ti_softc         *sc;
 1445 {
 1446         register int            i;
 1447 
 1448         for (i = 0; i < TI_MSLOTS; i++) {
 1449                 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
 1450                         return (ENOBUFS);
 1451         };
 1452 
 1453         TI_UPDATE_MINIPROD(sc, i - 1);
 1454         sc->ti_mini = i - 1;
 1455 
 1456         return (0);
 1457 }
 1458 
 1459 static void
 1460 ti_free_rx_ring_mini(sc)
 1461         struct ti_softc         *sc;
 1462 {
 1463         register int            i;
 1464 
 1465         for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
 1466                 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
 1467                         m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
 1468                         sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
 1469                 }
 1470                 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
 1471                     sizeof(struct ti_rx_desc));
 1472         }
 1473 }
 1474 
 1475 static void
 1476 ti_free_tx_ring(sc)
 1477         struct ti_softc         *sc;
 1478 {
 1479         register int            i;
 1480 
 1481         if (sc->ti_rdata->ti_tx_ring == NULL)
 1482                 return;
 1483 
 1484         for (i = 0; i < TI_TX_RING_CNT; i++) {
 1485                 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
 1486                         m_freem(sc->ti_cdata.ti_tx_chain[i]);
 1487                         sc->ti_cdata.ti_tx_chain[i] = NULL;
 1488                 }
 1489                 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
 1490                     sizeof(struct ti_tx_desc));
 1491         }
 1492 }
 1493 
 1494 static int
 1495 ti_init_tx_ring(sc)
 1496         struct ti_softc         *sc;
 1497 {
 1498         sc->ti_txcnt = 0;
 1499         sc->ti_tx_saved_considx = 0;
 1500         CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
 1501         return (0);
 1502 }
 1503 
 1504 /*
 1505  * The Tigon 2 firmware has a new way to add/delete multicast addresses,
 1506  * but we have to support the old way too so that Tigon 1 cards will
 1507  * work.
 1508  */
 1509 static void
 1510 ti_add_mcast(sc, addr)
 1511         struct ti_softc         *sc;
 1512         struct ether_addr       *addr;
 1513 {
 1514         struct ti_cmd_desc      cmd;
 1515         u_int16_t               *m;
 1516         u_int32_t               ext[2] = {0, 0};
 1517 
 1518         m = (u_int16_t *)&addr->octet[0];
 1519 
 1520         switch (sc->ti_hwrev) {
 1521         case TI_HWREV_TIGON:
 1522                 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
 1523                 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
 1524                 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
 1525                 break;
 1526         case TI_HWREV_TIGON_II:
 1527                 ext[0] = htons(m[0]);
 1528                 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
 1529                 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
 1530                 break;
 1531         default:
 1532                 printf("ti%d: unknown hwrev\n", sc->ti_unit);
 1533                 break;
 1534         }
 1535 }
 1536 
 1537 static void
 1538 ti_del_mcast(sc, addr)
 1539         struct ti_softc         *sc;
 1540         struct ether_addr       *addr;
 1541 {
 1542         struct ti_cmd_desc      cmd;
 1543         u_int16_t               *m;
 1544         u_int32_t               ext[2] = {0, 0};
 1545 
 1546         m = (u_int16_t *)&addr->octet[0];
 1547 
 1548         switch (sc->ti_hwrev) {
 1549         case TI_HWREV_TIGON:
 1550                 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
 1551                 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
 1552                 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
 1553                 break;
 1554         case TI_HWREV_TIGON_II:
 1555                 ext[0] = htons(m[0]);
 1556                 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
 1557                 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
 1558                 break;
 1559         default:
 1560                 printf("ti%d: unknown hwrev\n", sc->ti_unit);
 1561                 break;
 1562         }
 1563 }
 1564 
 1565 /*
 1566  * Configure the Tigon's multicast address filter.
 1567  *
 1568  * The actual multicast table management is a bit of a pain, thanks to
 1569  * slight brain damage on the part of both Alteon and us. With our
 1570  * multicast code, we are only alerted when the multicast address table
 1571  * changes and at that point we only have the current list of addresses:
 1572  * we only know the current state, not the previous state, so we don't
 1573  * actually know what addresses were removed or added. The firmware has
 1574  * state, but we can't get our grubby mits on it, and there is no 'delete
 1575  * all multicast addresses' command. Hence, we have to maintain our own
 1576  * state so we know what addresses have been programmed into the NIC at
 1577  * any given time.
 1578  */
 1579 static void
 1580 ti_setmulti(sc)
 1581         struct ti_softc         *sc;
 1582 {
 1583         struct ifnet            *ifp;
 1584         struct ifmultiaddr      *ifma;
 1585         struct ti_cmd_desc      cmd;
 1586         struct ti_mc_entry      *mc;
 1587         u_int32_t               intrs;
 1588 
 1589         ifp = &sc->arpcom.ac_if;
 1590 
 1591         if (ifp->if_flags & IFF_ALLMULTI) {
 1592                 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
 1593                 return;
 1594         } else {
 1595                 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
 1596         }
 1597 
 1598         /* Disable interrupts. */
 1599         intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
 1600         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 1601 
 1602         /* First, zot all the existing filters. */
 1603         while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
 1604                 mc = SLIST_FIRST(&sc->ti_mc_listhead);
 1605                 ti_del_mcast(sc, &mc->mc_addr);
 1606                 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
 1607                 free(mc, M_DEVBUF);
 1608         }
 1609 
 1610         /* Now program new ones. */
 1611         IF_ADDR_LOCK(ifp);
 1612         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 1613                 if (ifma->ifma_addr->sa_family != AF_LINK)
 1614                         continue;
 1615                 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
 1616                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 1617                     (char *)&mc->mc_addr, ETHER_ADDR_LEN);
 1618                 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
 1619                 ti_add_mcast(sc, &mc->mc_addr);
 1620         }
 1621         IF_ADDR_UNLOCK(ifp);
 1622 
 1623         /* Re-enable interrupts. */
 1624         CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
 1625 }
 1626 
 1627 /*
 1628  * Check to see if the BIOS has configured us for a 64 bit slot when
 1629  * we aren't actually in one. If we detect this condition, we can work
 1630  * around it on the Tigon 2 by setting a bit in the PCI state register,
 1631  * but for the Tigon 1 we must give up and abort the interface attach.
 1632  */
 1633 static int ti_64bitslot_war(sc)
 1634         struct ti_softc         *sc;
 1635 {
 1636         if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
 1637                 CSR_WRITE_4(sc, 0x600, 0);
 1638                 CSR_WRITE_4(sc, 0x604, 0);
 1639                 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
 1640                 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
 1641                         if (sc->ti_hwrev == TI_HWREV_TIGON)
 1642                                 return (EINVAL);
 1643                         else {
 1644                                 TI_SETBIT(sc, TI_PCI_STATE,
 1645                                     TI_PCISTATE_32BIT_BUS);
 1646                                 return (0);
 1647                         }
 1648                 }
 1649         }
 1650 
 1651         return (0);
 1652 }
 1653 
 1654 /*
 1655  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 1656  * self-test results.
 1657  */
 1658 static int
 1659 ti_chipinit(sc)
 1660         struct ti_softc         *sc;
 1661 {
 1662         u_int32_t               cacheline;
 1663         u_int32_t               pci_writemax = 0;
 1664         u_int32_t               hdrsplit;
 1665 
 1666         /* Initialize link to down state. */
 1667         sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
 1668 
 1669         if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
 1670                 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
 1671         else
 1672                 sc->arpcom.ac_if.if_hwassist = 0;
 1673 
 1674         /* Set endianness before we access any non-PCI registers. */
 1675 #if BYTE_ORDER == BIG_ENDIAN
 1676         CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
 1677             TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
 1678 #else
 1679         CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
 1680             TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
 1681 #endif
 1682 
 1683         /* Check the ROM failed bit to see if self-tests passed. */
 1684         if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
 1685                 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
 1686                 return (ENODEV);
 1687         }
 1688 
 1689         /* Halt the CPU. */
 1690         TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
 1691 
 1692         /* Figure out the hardware revision. */
 1693         switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
 1694         case TI_REV_TIGON_I:
 1695                 sc->ti_hwrev = TI_HWREV_TIGON;
 1696                 break;
 1697         case TI_REV_TIGON_II:
 1698                 sc->ti_hwrev = TI_HWREV_TIGON_II;
 1699                 break;
 1700         default:
 1701                 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
 1702                 return (ENODEV);
 1703         }
 1704 
 1705         /* Do special setup for Tigon 2. */
 1706         if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
 1707                 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
 1708                 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
 1709                 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
 1710         }
 1711 
 1712         /*
 1713          * We don't have firmware source for the Tigon 1, so Tigon 1 boards
 1714          * can't do header splitting.
 1715          */
 1716 #ifdef TI_JUMBO_HDRSPLIT
 1717         if (sc->ti_hwrev != TI_HWREV_TIGON)
 1718                 sc->ti_hdrsplit = 1;
 1719         else
 1720                 printf("ti%d: can't do header splitting on a Tigon I board\n",
 1721                        sc->ti_unit);
 1722 #endif /* TI_JUMBO_HDRSPLIT */
 1723 
 1724         /* Set up the PCI state register. */
 1725         CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
 1726         if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
 1727                 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
 1728         }
 1729 
 1730         /* Clear the read/write max DMA parameters. */
 1731         TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
 1732             TI_PCISTATE_READ_MAXDMA));
 1733 
 1734         /* Get cache line size. */
 1735         cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
 1736 
 1737         /*
 1738          * If the system has set enabled the PCI memory write
 1739          * and invalidate command in the command register, set
 1740          * the write max parameter accordingly. This is necessary
 1741          * to use MWI with the Tigon 2.
 1742          */
 1743         if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
 1744                 switch (cacheline) {
 1745                 case 1:
 1746                 case 4:
 1747                 case 8:
 1748                 case 16:
 1749                 case 32:
 1750                 case 64:
 1751                         break;
 1752                 default:
 1753                 /* Disable PCI memory write and invalidate. */
 1754                         if (bootverbose)
 1755                                 printf("ti%d: cache line size %d not "
 1756                                     "supported; disabling PCI MWI\n",
 1757                                     sc->ti_unit, cacheline);
 1758                         CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
 1759                             TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
 1760                         break;
 1761                 }
 1762         }
 1763 
 1764 #ifdef __brokenalpha__
 1765         /*
 1766          * From the Alteon sample driver:
 1767          * Must insure that we do not cross an 8K (bytes) boundary
 1768          * for DMA reads.  Our highest limit is 1K bytes.  This is a
 1769          * restriction on some ALPHA platforms with early revision
 1770          * 21174 PCI chipsets, such as the AlphaPC 164lx
 1771          */
 1772         TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
 1773 #else
 1774         TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
 1775 #endif
 1776 
 1777         /* This sets the min dma param all the way up (0xff). */
 1778         TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
 1779 
 1780         if (sc->ti_hdrsplit)
 1781                 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
 1782         else
 1783                 hdrsplit = 0;
 1784 
 1785         /* Configure DMA variables. */
 1786 #if BYTE_ORDER == BIG_ENDIAN
 1787         CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
 1788             TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
 1789             TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
 1790             TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
 1791 #else /* BYTE_ORDER */
 1792         CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
 1793             TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
 1794             TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
 1795 #endif /* BYTE_ORDER */
 1796 
 1797         /*
 1798          * Only allow 1 DMA channel to be active at a time.
 1799          * I don't think this is a good idea, but without it
 1800          * the firmware racks up lots of nicDmaReadRingFull
 1801          * errors.  This is not compatible with hardware checksums.
 1802          */
 1803         if (sc->arpcom.ac_if.if_hwassist == 0)
 1804                 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
 1805 
 1806         /* Recommended settings from Tigon manual. */
 1807         CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
 1808         CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
 1809 
 1810         if (ti_64bitslot_war(sc)) {
 1811                 printf("ti%d: bios thinks we're in a 64 bit slot, "
 1812                     "but we aren't", sc->ti_unit);
 1813                 return (EINVAL);
 1814         }
 1815 
 1816         return (0);
 1817 }
 1818 
 1819 /*
 1820  * Initialize the general information block and firmware, and
 1821  * start the CPU(s) running.
 1822  */
 1823 static int
 1824 ti_gibinit(sc)
 1825         struct ti_softc         *sc;
 1826 {
 1827         struct ti_rcb           *rcb;
 1828         int                     i;
 1829         struct ifnet            *ifp;
 1830 
 1831         ifp = &sc->arpcom.ac_if;
 1832 
 1833         /* Disable interrupts for now. */
 1834         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 1835 
 1836         /* Tell the chip where to find the general information block. */
 1837         CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
 1838         CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
 1839 
 1840         /* Load the firmware into SRAM. */
 1841         ti_loadfw(sc);
 1842 
 1843         /* Set up the contents of the general info and ring control blocks. */
 1844 
 1845         /* Set up the event ring and producer pointer. */
 1846         rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
 1847 
 1848         TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
 1849         rcb->ti_flags = 0;
 1850         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
 1851             vtophys(&sc->ti_ev_prodidx);
 1852         sc->ti_ev_prodidx.ti_idx = 0;
 1853         CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
 1854         sc->ti_ev_saved_considx = 0;
 1855 
 1856         /* Set up the command ring and producer mailbox. */
 1857         rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
 1858 
 1859         sc->ti_rdata->ti_cmd_ring =
 1860             (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
 1861         TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
 1862         rcb->ti_flags = 0;
 1863         rcb->ti_max_len = 0;
 1864         for (i = 0; i < TI_CMD_RING_CNT; i++) {
 1865                 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
 1866         }
 1867         CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
 1868         CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
 1869         sc->ti_cmd_saved_prodidx = 0;
 1870 
 1871         /*
 1872          * Assign the address of the stats refresh buffer.
 1873          * We re-use the current stats buffer for this to
 1874          * conserve memory.
 1875          */
 1876         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
 1877             vtophys(&sc->ti_rdata->ti_info.ti_stats);
 1878 
 1879         /* Set up the standard receive ring. */
 1880         rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
 1881         TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
 1882         rcb->ti_max_len = TI_FRAMELEN;
 1883         rcb->ti_flags = 0;
 1884         if (sc->arpcom.ac_if.if_hwassist)
 1885                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
 1886                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1887         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 1888 
 1889         /* Set up the jumbo receive ring. */
 1890         rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
 1891         TI_HOSTADDR(rcb->ti_hostaddr) =
 1892             vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
 1893 
 1894 #ifdef TI_PRIVATE_JUMBOS
 1895         rcb->ti_max_len = TI_JUMBO_FRAMELEN;
 1896         rcb->ti_flags = 0;
 1897 #else
 1898         rcb->ti_max_len = PAGE_SIZE;
 1899         rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
 1900 #endif
 1901         if (sc->arpcom.ac_if.if_hwassist)
 1902                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
 1903                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1904         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 1905 
 1906         /*
 1907          * Set up the mini ring. Only activated on the
 1908          * Tigon 2 but the slot in the config block is
 1909          * still there on the Tigon 1.
 1910          */
 1911         rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
 1912         TI_HOSTADDR(rcb->ti_hostaddr) =
 1913             vtophys(&sc->ti_rdata->ti_rx_mini_ring);
 1914         rcb->ti_max_len = MHLEN - ETHER_ALIGN;
 1915         if (sc->ti_hwrev == TI_HWREV_TIGON)
 1916                 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
 1917         else
 1918                 rcb->ti_flags = 0;
 1919         if (sc->arpcom.ac_if.if_hwassist)
 1920                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
 1921                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1922         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 1923 
 1924         /*
 1925          * Set up the receive return ring.
 1926          */
 1927         rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
 1928         TI_HOSTADDR(rcb->ti_hostaddr) =
 1929             vtophys(&sc->ti_rdata->ti_rx_return_ring);
 1930         rcb->ti_flags = 0;
 1931         rcb->ti_max_len = TI_RETURN_RING_CNT;
 1932         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
 1933             vtophys(&sc->ti_return_prodidx);
 1934 
 1935         /*
 1936          * Set up the tx ring. Note: for the Tigon 2, we have the option
 1937          * of putting the transmit ring in the host's address space and
 1938          * letting the chip DMA it instead of leaving the ring in the NIC's
 1939          * memory and accessing it through the shared memory region. We
 1940          * do this for the Tigon 2, but it doesn't work on the Tigon 1,
 1941          * so we have to revert to the shared memory scheme if we detect
 1942          * a Tigon 1 chip.
 1943          */
 1944         CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
 1945         if (sc->ti_hwrev == TI_HWREV_TIGON) {
 1946                 sc->ti_rdata->ti_tx_ring_nic =
 1947                     (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
 1948         }
 1949         bzero((char *)sc->ti_rdata->ti_tx_ring,
 1950             TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
 1951         rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
 1952         if (sc->ti_hwrev == TI_HWREV_TIGON)
 1953                 rcb->ti_flags = 0;
 1954         else
 1955                 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
 1956         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 1957         if (sc->arpcom.ac_if.if_hwassist)
 1958                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
 1959                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1960         rcb->ti_max_len = TI_TX_RING_CNT;
 1961         if (sc->ti_hwrev == TI_HWREV_TIGON)
 1962                 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
 1963         else
 1964                 TI_HOSTADDR(rcb->ti_hostaddr) =
 1965                     vtophys(&sc->ti_rdata->ti_tx_ring);
 1966         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
 1967             vtophys(&sc->ti_tx_considx);
 1968 
 1969         /* Set up tuneables */
 1970 #if 0
 1971         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
 1972                 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
 1973                     (sc->ti_rx_coal_ticks / 10));
 1974         else
 1975 #endif
 1976                 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
 1977         CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
 1978         CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
 1979         CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
 1980         CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
 1981         CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
 1982 
 1983         /* Turn interrupts on. */
 1984         CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
 1985         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
 1986 
 1987         /* Start CPU. */
 1988         TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
 1989 
 1990         return (0);
 1991 }
 1992 
 1993 /*
 1994  * Probe for a Tigon chip. Check the PCI vendor and device IDs
 1995  * against our list and return its name if we find a match.
 1996  */
 1997 static int
 1998 ti_probe(dev)
 1999         device_t                dev;
 2000 {
 2001         struct ti_type          *t;
 2002 
 2003         t = ti_devs;
 2004 
 2005         while (t->ti_name != NULL) {
 2006                 if ((pci_get_vendor(dev) == t->ti_vid) &&
 2007                     (pci_get_device(dev) == t->ti_did)) {
 2008                         device_set_desc(dev, t->ti_name);
 2009                         return (BUS_PROBE_DEFAULT);
 2010                 }
 2011                 t++;
 2012         }
 2013 
 2014         return (ENXIO);
 2015 }
 2016 
 2017 static int
 2018 ti_attach(dev)
 2019         device_t                dev;
 2020 {
 2021         struct ifnet            *ifp;
 2022         struct ti_softc         *sc;
 2023         int                     unit, error = 0, rid;
 2024 
 2025         sc = device_get_softc(dev);
 2026         unit = device_get_unit(dev);
 2027 
 2028         mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 2029             MTX_DEF | MTX_RECURSE);
 2030         ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
 2031         sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM |
 2032             IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
 2033         sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities;
 2034 
 2035         /*
 2036          * Map control/status registers.
 2037          */
 2038         pci_enable_busmaster(dev);
 2039 
 2040         rid = TI_PCI_LOMEM;
 2041         sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 2042             RF_ACTIVE|PCI_RF_DENSE);
 2043 
 2044         if (sc->ti_res == NULL) {
 2045                 printf ("ti%d: couldn't map memory\n", unit);
 2046                 error = ENXIO;
 2047                 goto fail;
 2048         }
 2049 
 2050         sc->ti_btag = rman_get_bustag(sc->ti_res);
 2051         sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
 2052         sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
 2053 
 2054         /* Allocate interrupt */
 2055         rid = 0;
 2056 
 2057         sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 2058             RF_SHAREABLE | RF_ACTIVE);
 2059 
 2060         if (sc->ti_irq == NULL) {
 2061                 printf("ti%d: couldn't map interrupt\n", unit);
 2062                 error = ENXIO;
 2063                 goto fail;
 2064         }
 2065 
 2066         sc->ti_unit = unit;
 2067 
 2068         if (ti_chipinit(sc)) {
 2069                 printf("ti%d: chip initialization failed\n", sc->ti_unit);
 2070                 error = ENXIO;
 2071                 goto fail;
 2072         }
 2073 
 2074         /* Zero out the NIC's on-board SRAM. */
 2075         ti_mem(sc, 0x2000, 0x100000 - 0x2000,  NULL);
 2076 
 2077         /* Init again -- zeroing memory may have clobbered some registers. */
 2078         if (ti_chipinit(sc)) {
 2079                 printf("ti%d: chip initialization failed\n", sc->ti_unit);
 2080                 error = ENXIO;
 2081                 goto fail;
 2082         }
 2083 
 2084         /*
 2085          * Get station address from the EEPROM. Note: the manual states
 2086          * that the MAC address is at offset 0x8c, however the data is
 2087          * stored as two longwords (since that's how it's loaded into
 2088          * the NIC). This means the MAC address is actually preceded
 2089          * by two zero bytes. We need to skip over those.
 2090          */
 2091         if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
 2092                                 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
 2093                 printf("ti%d: failed to read station address\n", unit);
 2094                 error = ENXIO;
 2095                 goto fail;
 2096         }
 2097 
 2098         /* Allocate the general information block and ring buffers. */
 2099         sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
 2100             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 2101 
 2102         if (sc->ti_rdata == NULL) {
 2103                 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
 2104                 error = ENXIO;
 2105                 goto fail;
 2106         }
 2107 
 2108         bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
 2109 
 2110         /* Try to allocate memory for jumbo buffers. */
 2111 #ifdef TI_PRIVATE_JUMBOS
 2112         if (ti_alloc_jumbo_mem(sc)) {
 2113                 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
 2114                 error = ENXIO;
 2115                 goto fail;
 2116         }
 2117 #else
 2118         if (!jumbo_vm_init()) {
 2119                 printf("ti%d: VM initialization failed!\n", sc->ti_unit);
 2120                 error = ENOMEM;
 2121                 goto fail;
 2122         }
 2123 #endif
 2124 
 2125         /*
 2126          * We really need a better way to tell a 1000baseTX card
 2127          * from a 1000baseSX one, since in theory there could be
 2128          * OEMed 1000baseTX cards from lame vendors who aren't
 2129          * clever enough to change the PCI ID. For the moment
 2130          * though, the AceNIC is the only copper card available.
 2131          */
 2132         if (pci_get_vendor(dev) == ALT_VENDORID &&
 2133             pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
 2134                 sc->ti_copper = 1;
 2135         /* Ok, it's not the only copper card available. */
 2136         if (pci_get_vendor(dev) == NG_VENDORID &&
 2137             pci_get_device(dev) == NG_DEVICEID_GA620T)
 2138                 sc->ti_copper = 1;
 2139 
 2140         /* Set default tuneable values. */
 2141         sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
 2142 #if 0
 2143         sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
 2144 #endif
 2145         sc->ti_rx_coal_ticks = 170;
 2146         sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
 2147         sc->ti_rx_max_coal_bds = 64;
 2148 #if 0
 2149         sc->ti_tx_max_coal_bds = 128;
 2150 #endif
 2151         sc->ti_tx_max_coal_bds = 32;
 2152         sc->ti_tx_buf_ratio = 21;
 2153 
 2154         /* Set up ifnet structure */
 2155         ifp = &sc->arpcom.ac_if;
 2156         ifp->if_softc = sc;
 2157         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 2158         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
 2159             IFF_NEEDSGIANT;
 2160         tis[unit] = sc;
 2161         ifp->if_ioctl = ti_ioctl;
 2162         ifp->if_start = ti_start;
 2163         ifp->if_watchdog = ti_watchdog;
 2164         ifp->if_init = ti_init;
 2165         ifp->if_mtu = ETHERMTU;
 2166         ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
 2167 
 2168         /* Set up ifmedia support. */
 2169         if (sc->ti_copper) {
 2170                 /*
 2171                  * Copper cards allow manual 10/100 mode selection,
 2172                  * but not manual 1000baseTX mode selection. Why?
 2173                  * Becuase currently there's no way to specify the
 2174                  * master/slave setting through the firmware interface,
 2175                  * so Alteon decided to just bag it and handle it
 2176                  * via autonegotiation.
 2177                  */
 2178                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 2179                 ifmedia_add(&sc->ifmedia,
 2180                     IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
 2181                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
 2182                 ifmedia_add(&sc->ifmedia,
 2183                     IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
 2184                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
 2185                 ifmedia_add(&sc->ifmedia,
 2186                     IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
 2187         } else {
 2188                 /* Fiber cards don't support 10/100 modes. */
 2189                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
 2190                 ifmedia_add(&sc->ifmedia,
 2191                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 2192         }
 2193         ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 2194         ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
 2195 
 2196         /*
 2197          * We're assuming here that card initialization is a sequential
 2198          * thing.  If it isn't, multiple cards probing at the same time
 2199          * could stomp on the list of softcs here.
 2200          */
 2201 
 2202         /* Register the device */
 2203         sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
 2204                            0600, "ti%d", sc->ti_unit);
 2205         sc->dev->si_drv1 = sc;
 2206 
 2207         /*
 2208          * Call MI attach routine.
 2209          */
 2210         ether_ifattach(ifp, sc->arpcom.ac_enaddr);
 2211 
 2212         /* Hook interrupt last to avoid having to lock softc */
 2213         error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
 2214            ti_intr, sc, &sc->ti_intrhand);
 2215 
 2216         if (error) {
 2217                 printf("ti%d: couldn't set up irq\n", unit);
 2218                 ether_ifdetach(ifp);
 2219                 goto fail;
 2220         }
 2221 
 2222 fail:
 2223         if (sc && error)
 2224                 ti_detach(dev);
 2225 
 2226         return (error);
 2227 }
 2228 
 2229 /*
 2230  * Shutdown hardware and free up resources. This can be called any
 2231  * time after the mutex has been initialized. It is called in both
 2232  * the error case in attach and the normal detach case so it needs
 2233  * to be careful about only freeing resources that have actually been
 2234  * allocated.
 2235  */
 2236 static int
 2237 ti_detach(dev)
 2238         device_t                dev;
 2239 {
 2240         struct ti_softc         *sc;
 2241         struct ifnet            *ifp;
 2242 
 2243         sc = device_get_softc(dev);
 2244         destroy_dev(sc->dev);
 2245         KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
 2246         TI_LOCK(sc);
 2247         ifp = &sc->arpcom.ac_if;
 2248 
 2249         /* These should only be active if attach succeeded */
 2250         if (device_is_attached(dev)) {
 2251                 ti_stop(sc);
 2252                 ether_ifdetach(ifp);
 2253                 bus_generic_detach(dev);
 2254         }
 2255         ifmedia_removeall(&sc->ifmedia);
 2256 
 2257         if (sc->ti_intrhand)
 2258                 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
 2259         if (sc->ti_irq)
 2260                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
 2261         if (sc->ti_res) {
 2262                 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
 2263                     sc->ti_res);
 2264         }
 2265 
 2266 #ifdef TI_PRIVATE_JUMBOS
 2267         if (sc->ti_cdata.ti_jumbo_buf)
 2268                 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
 2269 #endif
 2270         if (sc->ti_rdata)
 2271                 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
 2272 
 2273         TI_UNLOCK(sc);
 2274         mtx_destroy(&sc->ti_mtx);
 2275 
 2276         return (0);
 2277 }
 2278 
 2279 #ifdef TI_JUMBO_HDRSPLIT
 2280 /*
 2281  * If hdr_len is 0, that means that header splitting wasn't done on
 2282  * this packet for some reason.  The two most likely reasons are that
 2283  * the protocol isn't a supported protocol for splitting, or this
 2284  * packet had a fragment offset that wasn't 0.
 2285  *
 2286  * The header length, if it is non-zero, will always be the length of
 2287  * the headers on the packet, but that length could be longer than the
 2288  * first mbuf.  So we take the minimum of the two as the actual
 2289  * length.
 2290  */
 2291 static __inline void
 2292 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
 2293 {
 2294         int i = 0;
 2295         int lengths[4] = {0, 0, 0, 0};
 2296         struct mbuf *m, *mp;
 2297 
 2298         if (hdr_len != 0)
 2299                 top->m_len = min(hdr_len, top->m_len);
 2300         pkt_len -= top->m_len;
 2301         lengths[i++] = top->m_len;
 2302 
 2303         mp = top;
 2304         for (m = top->m_next; m && pkt_len; m = m->m_next) {
 2305                 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
 2306                 pkt_len -= m->m_len;
 2307                 lengths[i++] = m->m_len;
 2308                 mp = m;
 2309         }
 2310 
 2311 #if 0
 2312         if (hdr_len != 0)
 2313                 printf("got split packet: ");
 2314         else
 2315                 printf("got non-split packet: ");
 2316 
 2317         printf("%d,%d,%d,%d = %d\n", lengths[0],
 2318             lengths[1], lengths[2], lengths[3],
 2319             lengths[0] + lengths[1] + lengths[2] +
 2320             lengths[3]);
 2321 #endif
 2322 
 2323         if (pkt_len)
 2324                 panic("header splitting didn't");
 2325 
 2326         if (m) {
 2327                 m_freem(m);
 2328                 mp->m_next = NULL;
 2329 
 2330         }
 2331         if (mp->m_next != NULL)
 2332                 panic("ti_hdr_split: last mbuf in chain should be null");
 2333 }
 2334 #endif /* TI_JUMBO_HDRSPLIT */
 2335 
 2336 /*
 2337  * Frame reception handling. This is called if there's a frame
 2338  * on the receive return list.
 2339  *
 2340  * Note: we have to be able to handle three possibilities here:
 2341  * 1) the frame is from the mini receive ring (can only happen)
 2342  *    on Tigon 2 boards)
 2343  * 2) the frame is from the jumbo recieve ring
 2344  * 3) the frame is from the standard receive ring
 2345  */
 2346 
 2347 static void
 2348 ti_rxeof(sc)
 2349         struct ti_softc         *sc;
 2350 {
 2351         struct ifnet            *ifp;
 2352         struct ti_cmd_desc      cmd;
 2353 
 2354         TI_LOCK_ASSERT(sc);
 2355 
 2356         ifp = &sc->arpcom.ac_if;
 2357 
 2358         while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
 2359                 struct ti_rx_desc       *cur_rx;
 2360                 u_int32_t               rxidx;
 2361                 struct mbuf             *m = NULL;
 2362                 u_int16_t               vlan_tag = 0;
 2363                 int                     have_tag = 0;
 2364 
 2365                 cur_rx =
 2366                     &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
 2367                 rxidx = cur_rx->ti_idx;
 2368                 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
 2369 
 2370                 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
 2371                         have_tag = 1;
 2372                         vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
 2373                 }
 2374 
 2375                 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
 2376 
 2377                         TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
 2378                         m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
 2379                         sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
 2380                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
 2381                                 ifp->if_ierrors++;
 2382                                 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
 2383                                 continue;
 2384                         }
 2385                         if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
 2386                                 ifp->if_ierrors++;
 2387                                 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
 2388                                 continue;
 2389                         }
 2390 #ifdef TI_PRIVATE_JUMBOS
 2391                         m->m_len = cur_rx->ti_len;
 2392 #else /* TI_PRIVATE_JUMBOS */
 2393 #ifdef TI_JUMBO_HDRSPLIT
 2394                         if (sc->ti_hdrsplit)
 2395                                 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
 2396                                              cur_rx->ti_len, rxidx);
 2397                         else
 2398 #endif /* TI_JUMBO_HDRSPLIT */
 2399                         m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
 2400 #endif /* TI_PRIVATE_JUMBOS */
 2401                 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
 2402                         TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
 2403                         m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
 2404                         sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
 2405                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
 2406                                 ifp->if_ierrors++;
 2407                                 ti_newbuf_mini(sc, sc->ti_mini, m);
 2408                                 continue;
 2409                         }
 2410                         if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
 2411                                 ifp->if_ierrors++;
 2412                                 ti_newbuf_mini(sc, sc->ti_mini, m);
 2413                                 continue;
 2414                         }
 2415                         m->m_len = cur_rx->ti_len;
 2416                 } else {
 2417                         TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
 2418                         m = sc->ti_cdata.ti_rx_std_chain[rxidx];
 2419                         sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
 2420                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
 2421                                 ifp->if_ierrors++;
 2422                                 ti_newbuf_std(sc, sc->ti_std, m);
 2423                                 continue;
 2424                         }
 2425                         if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
 2426                                 ifp->if_ierrors++;
 2427                                 ti_newbuf_std(sc, sc->ti_std, m);
 2428                                 continue;
 2429                         }
 2430                         m->m_len = cur_rx->ti_len;
 2431                 }
 2432 
 2433                 m->m_pkthdr.len = cur_rx->ti_len;
 2434                 ifp->if_ipackets++;
 2435                 m->m_pkthdr.rcvif = ifp;
 2436 
 2437                 if (ifp->if_hwassist) {
 2438                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
 2439                             CSUM_DATA_VALID;
 2440                         if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
 2441                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
 2442                         m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
 2443                 }
 2444 
 2445                 /*
 2446                  * If we received a packet with a vlan tag,
 2447                  * tag it before passing the packet upward.
 2448                  */
 2449                 if (have_tag)
 2450                         VLAN_INPUT_TAG(ifp, m, vlan_tag, continue);
 2451                 TI_UNLOCK(sc);
 2452                 (*ifp->if_input)(ifp, m);
 2453                 TI_LOCK(sc);
 2454         }
 2455 
 2456         /* Only necessary on the Tigon 1. */
 2457         if (sc->ti_hwrev == TI_HWREV_TIGON)
 2458                 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
 2459                     sc->ti_rx_saved_considx);
 2460 
 2461         TI_UPDATE_STDPROD(sc, sc->ti_std);
 2462         TI_UPDATE_MINIPROD(sc, sc->ti_mini);
 2463         TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
 2464 }
 2465 
 2466 static void
 2467 ti_txeof(sc)
 2468         struct ti_softc         *sc;
 2469 {
 2470         struct ti_tx_desc       *cur_tx = NULL;
 2471         struct ifnet            *ifp;
 2472 
 2473         ifp = &sc->arpcom.ac_if;
 2474 
 2475         /*
 2476          * Go through our tx ring and free mbufs for those
 2477          * frames that have been sent.
 2478          */
 2479         while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
 2480                 u_int32_t               idx = 0;
 2481 
 2482                 idx = sc->ti_tx_saved_considx;
 2483                 if (sc->ti_hwrev == TI_HWREV_TIGON) {
 2484                         if (idx > 383)
 2485                                 CSR_WRITE_4(sc, TI_WINBASE,
 2486                                     TI_TX_RING_BASE + 6144);
 2487                         else if (idx > 255)
 2488                                 CSR_WRITE_4(sc, TI_WINBASE,
 2489                                     TI_TX_RING_BASE + 4096);
 2490                         else if (idx > 127)
 2491                                 CSR_WRITE_4(sc, TI_WINBASE,
 2492                                     TI_TX_RING_BASE + 2048);
 2493                         else
 2494                                 CSR_WRITE_4(sc, TI_WINBASE,
 2495                                     TI_TX_RING_BASE);
 2496                         cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
 2497                 } else
 2498                         cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
 2499                 if (cur_tx->ti_flags & TI_BDFLAG_END)
 2500                         ifp->if_opackets++;
 2501                 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
 2502                         m_freem(sc->ti_cdata.ti_tx_chain[idx]);
 2503                         sc->ti_cdata.ti_tx_chain[idx] = NULL;
 2504                 }
 2505                 sc->ti_txcnt--;
 2506                 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
 2507                 ifp->if_timer = 0;
 2508         }
 2509 
 2510         if (cur_tx != NULL)
 2511                 ifp->if_flags &= ~IFF_OACTIVE;
 2512 }
 2513 
 2514 static void
 2515 ti_intr(xsc)
 2516         void                    *xsc;
 2517 {
 2518         struct ti_softc         *sc;
 2519         struct ifnet            *ifp;
 2520 
 2521         sc = xsc;
 2522         TI_LOCK(sc);
 2523         ifp = &sc->arpcom.ac_if;
 2524 
 2525 /*#ifdef notdef*/
 2526         /* Avoid this for now -- checking this register is expensive. */
 2527         /* Make sure this is really our interrupt. */
 2528         if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
 2529                 TI_UNLOCK(sc);
 2530                 return;
 2531         }
 2532 /*#endif*/
 2533 
 2534         /* Ack interrupt and stop others from occuring. */
 2535         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 2536 
 2537         if (ifp->if_flags & IFF_RUNNING) {
 2538                 /* Check RX return ring producer/consumer */
 2539                 ti_rxeof(sc);
 2540 
 2541                 /* Check TX ring producer/consumer */
 2542                 ti_txeof(sc);
 2543         }
 2544 
 2545         ti_handle_events(sc);
 2546 
 2547         /* Re-enable interrupts. */
 2548         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
 2549 
 2550         if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
 2551                 ti_start(ifp);
 2552 
 2553         TI_UNLOCK(sc);
 2554 }
 2555 
 2556 static void
 2557 ti_stats_update(sc)
 2558         struct ti_softc         *sc;
 2559 {
 2560         struct ifnet            *ifp;
 2561 
 2562         ifp = &sc->arpcom.ac_if;
 2563 
 2564         ifp->if_collisions +=
 2565            (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
 2566            sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
 2567            sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
 2568            sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
 2569            ifp->if_collisions;
 2570 }
 2571 
 2572 /*
 2573  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
 2574  * pointers to descriptors.
 2575  */
 2576 static int
 2577 ti_encap(sc, m_head, txidx)
 2578         struct ti_softc         *sc;
 2579         struct mbuf             *m_head;
 2580         u_int32_t               *txidx;
 2581 {
 2582         struct ti_tx_desc       *f = NULL;
 2583         struct mbuf             *m;
 2584         u_int32_t               frag, cur, cnt = 0;
 2585         u_int16_t               csum_flags = 0;
 2586         struct m_tag            *mtag;
 2587 
 2588         m = m_head;
 2589         cur = frag = *txidx;
 2590 
 2591         if (m_head->m_pkthdr.csum_flags) {
 2592                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
 2593                         csum_flags |= TI_BDFLAG_IP_CKSUM;
 2594                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
 2595                         csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
 2596                 if (m_head->m_flags & M_LASTFRAG)
 2597                         csum_flags |= TI_BDFLAG_IP_FRAG_END;
 2598                 else if (m_head->m_flags & M_FRAG)
 2599                         csum_flags |= TI_BDFLAG_IP_FRAG;
 2600         }
 2601 
 2602         mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m);
 2603 
 2604         /*
 2605          * Start packing the mbufs in this chain into
 2606          * the fragment pointers. Stop when we run out
 2607          * of fragments or hit the end of the mbuf chain.
 2608          */
 2609         for (m = m_head; m != NULL; m = m->m_next) {
 2610                 if (m->m_len != 0) {
 2611                         if (sc->ti_hwrev == TI_HWREV_TIGON) {
 2612                                 if (frag > 383)
 2613                                         CSR_WRITE_4(sc, TI_WINBASE,
 2614                                             TI_TX_RING_BASE + 6144);
 2615                                 else if (frag > 255)
 2616                                         CSR_WRITE_4(sc, TI_WINBASE,
 2617                                             TI_TX_RING_BASE + 4096);
 2618                                 else if (frag > 127)
 2619                                         CSR_WRITE_4(sc, TI_WINBASE,
 2620                                             TI_TX_RING_BASE + 2048);
 2621                                 else
 2622                                         CSR_WRITE_4(sc, TI_WINBASE,
 2623                                             TI_TX_RING_BASE);
 2624                                 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
 2625                         } else
 2626                                 f = &sc->ti_rdata->ti_tx_ring[frag];
 2627                         if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
 2628                                 break;
 2629                         TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
 2630                         f->ti_len = m->m_len;
 2631                         f->ti_flags = csum_flags;
 2632 
 2633                         if (mtag != NULL) {
 2634                                 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
 2635                                 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff;
 2636                         } else {
 2637                                 f->ti_vlan_tag = 0;
 2638                         }
 2639 
 2640                         /*
 2641                          * Sanity check: avoid coming within 16 descriptors
 2642                          * of the end of the ring.
 2643                          */
 2644                         if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
 2645                                 return (ENOBUFS);
 2646                         cur = frag;
 2647                         TI_INC(frag, TI_TX_RING_CNT);
 2648                         cnt++;
 2649                 }
 2650         }
 2651 
 2652         if (m != NULL)
 2653                 return (ENOBUFS);
 2654 
 2655         if (frag == sc->ti_tx_saved_considx)
 2656                 return (ENOBUFS);
 2657 
 2658         if (sc->ti_hwrev == TI_HWREV_TIGON)
 2659                 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
 2660                     TI_BDFLAG_END;
 2661         else
 2662                 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
 2663         sc->ti_cdata.ti_tx_chain[cur] = m_head;
 2664         sc->ti_txcnt += cnt;
 2665 
 2666         *txidx = frag;
 2667 
 2668         return (0);
 2669 }
 2670 
 2671 /*
 2672  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 2673  * to the mbuf data regions directly in the transmit descriptors.
 2674  */
 2675 static void
 2676 ti_start(ifp)
 2677         struct ifnet            *ifp;
 2678 {
 2679         struct ti_softc         *sc;
 2680         struct mbuf             *m_head = NULL;
 2681         u_int32_t               prodidx = 0;
 2682 
 2683         sc = ifp->if_softc;
 2684         TI_LOCK(sc);
 2685 
 2686         prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
 2687 
 2688         while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
 2689                 IF_DEQUEUE(&ifp->if_snd, m_head);
 2690                 if (m_head == NULL)
 2691                         break;
 2692 
 2693                 /*
 2694                  * XXX
 2695                  * safety overkill.  If this is a fragmented packet chain
 2696                  * with delayed TCP/UDP checksums, then only encapsulate
 2697                  * it if we have enough descriptors to handle the entire
 2698                  * chain at once.
 2699                  * (paranoia -- may not actually be needed)
 2700                  */
 2701                 if (m_head->m_flags & M_FIRSTFRAG &&
 2702                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
 2703                         if ((TI_TX_RING_CNT - sc->ti_txcnt) <
 2704                             m_head->m_pkthdr.csum_data + 16) {
 2705                                 IF_PREPEND(&ifp->if_snd, m_head);
 2706                                 ifp->if_flags |= IFF_OACTIVE;
 2707                                 break;
 2708                         }
 2709                 }
 2710 
 2711                 /*
 2712                  * Pack the data into the transmit ring. If we
 2713                  * don't have room, set the OACTIVE flag and wait
 2714                  * for the NIC to drain the ring.
 2715                  */
 2716                 if (ti_encap(sc, m_head, &prodidx)) {
 2717                         IF_PREPEND(&ifp->if_snd, m_head);
 2718                         ifp->if_flags |= IFF_OACTIVE;
 2719                         break;
 2720                 }
 2721 
 2722                 /*
 2723                  * If there's a BPF listener, bounce a copy of this frame
 2724                  * to him.
 2725                  */
 2726                 BPF_MTAP(ifp, m_head);
 2727         }
 2728 
 2729         /* Transmit */
 2730         CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
 2731 
 2732         /*
 2733          * Set a timeout in case the chip goes out to lunch.
 2734          */
 2735         ifp->if_timer = 5;
 2736         TI_UNLOCK(sc);
 2737 }
 2738 
 2739 static void
 2740 ti_init(xsc)
 2741         void                    *xsc;
 2742 {
 2743         struct ti_softc         *sc = xsc;
 2744 
 2745         /* Cancel pending I/O and flush buffers. */
 2746         ti_stop(sc);
 2747 
 2748         TI_LOCK(sc);
 2749         /* Init the gen info block, ring control blocks and firmware. */
 2750         if (ti_gibinit(sc)) {
 2751                 printf("ti%d: initialization failure\n", sc->ti_unit);
 2752                 TI_UNLOCK(sc);
 2753                 return;
 2754         }
 2755 
 2756         TI_UNLOCK(sc);
 2757 }
 2758 
 2759 static void ti_init2(sc)
 2760         struct ti_softc         *sc;
 2761 {
 2762         struct ti_cmd_desc      cmd;
 2763         struct ifnet            *ifp;
 2764         u_int16_t               *m;
 2765         struct ifmedia          *ifm;
 2766         int                     tmp;
 2767 
 2768         ifp = &sc->arpcom.ac_if;
 2769 
 2770         /* Specify MTU and interface index. */
 2771         CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
 2772         CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
 2773             ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
 2774         TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
 2775 
 2776         /* Load our MAC address. */
 2777         m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
 2778         CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
 2779         CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
 2780         TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
 2781 
 2782         /* Enable or disable promiscuous mode as needed. */
 2783         if (ifp->if_flags & IFF_PROMISC) {
 2784                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
 2785         } else {
 2786                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
 2787         }
 2788 
 2789         /* Program multicast filter. */
 2790         ti_setmulti(sc);
 2791 
 2792         /*
 2793          * If this is a Tigon 1, we should tell the
 2794          * firmware to use software packet filtering.
 2795          */
 2796         if (sc->ti_hwrev == TI_HWREV_TIGON) {
 2797                 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
 2798         }
 2799 
 2800         /* Init RX ring. */
 2801         ti_init_rx_ring_std(sc);
 2802 
 2803         /* Init jumbo RX ring. */
 2804         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
 2805                 ti_init_rx_ring_jumbo(sc);
 2806 
 2807         /*
 2808          * If this is a Tigon 2, we can also configure the
 2809          * mini ring.
 2810          */
 2811         if (sc->ti_hwrev == TI_HWREV_TIGON_II)
 2812                 ti_init_rx_ring_mini(sc);
 2813 
 2814         CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
 2815         sc->ti_rx_saved_considx = 0;
 2816 
 2817         /* Init TX ring. */
 2818         ti_init_tx_ring(sc);
 2819 
 2820         /* Tell firmware we're alive. */
 2821         TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
 2822 
 2823         /* Enable host interrupts. */
 2824         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
 2825 
 2826         ifp->if_flags |= IFF_RUNNING;
 2827         ifp->if_flags &= ~IFF_OACTIVE;
 2828 
 2829         /*
 2830          * Make sure to set media properly. We have to do this
 2831          * here since we have to issue commands in order to set
 2832          * the link negotiation and we can't issue commands until
 2833          * the firmware is running.
 2834          */
 2835         ifm = &sc->ifmedia;
 2836         tmp = ifm->ifm_media;
 2837         ifm->ifm_media = ifm->ifm_cur->ifm_media;
 2838         ti_ifmedia_upd(ifp);
 2839         ifm->ifm_media = tmp;
 2840 }
 2841 
 2842 /*
 2843  * Set media options.
 2844  */
 2845 static int
 2846 ti_ifmedia_upd(ifp)
 2847         struct ifnet            *ifp;
 2848 {
 2849         struct ti_softc         *sc;
 2850         struct ifmedia          *ifm;
 2851         struct ti_cmd_desc      cmd;
 2852         u_int32_t               flowctl;
 2853 
 2854         sc = ifp->if_softc;
 2855         ifm = &sc->ifmedia;
 2856 
 2857         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 2858                 return (EINVAL);
 2859 
 2860         flowctl = 0;
 2861 
 2862         switch (IFM_SUBTYPE(ifm->ifm_media)) {
 2863         case IFM_AUTO:
 2864                 /*
 2865                  * Transmit flow control doesn't work on the Tigon 1.
 2866                  */
 2867                 flowctl = TI_GLNK_RX_FLOWCTL_Y;
 2868 
 2869                 /*
 2870                  * Transmit flow control can also cause problems on the
 2871                  * Tigon 2, apparantly with both the copper and fiber
 2872                  * boards.  The symptom is that the interface will just
 2873                  * hang.  This was reproduced with Alteon 180 switches.
 2874                  */
 2875 #if 0
 2876                 if (sc->ti_hwrev != TI_HWREV_TIGON)
 2877                         flowctl |= TI_GLNK_TX_FLOWCTL_Y;
 2878 #endif
 2879 
 2880                 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
 2881                     TI_GLNK_FULL_DUPLEX| flowctl |
 2882                     TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
 2883 
 2884                 flowctl = TI_LNK_RX_FLOWCTL_Y;
 2885 #if 0
 2886                 if (sc->ti_hwrev != TI_HWREV_TIGON)
 2887                         flowctl |= TI_LNK_TX_FLOWCTL_Y;
 2888 #endif
 2889 
 2890                 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
 2891                     TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
 2892                     TI_LNK_AUTONEGENB|TI_LNK_ENB);
 2893                 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
 2894                     TI_CMD_CODE_NEGOTIATE_BOTH, 0);
 2895                 break;
 2896         case IFM_1000_SX:
 2897         case IFM_1000_T:
 2898                 flowctl = TI_GLNK_RX_FLOWCTL_Y;
 2899 #if 0
 2900                 if (sc->ti_hwrev != TI_HWREV_TIGON)
 2901                         flowctl |= TI_GLNK_TX_FLOWCTL_Y;
 2902 #endif
 2903 
 2904                 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
 2905                     flowctl |TI_GLNK_ENB);
 2906                 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
 2907                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
 2908                         TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
 2909                 }
 2910                 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
 2911                     TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
 2912                 break;
 2913         case IFM_100_FX:
 2914         case IFM_10_FL:
 2915         case IFM_100_TX:
 2916         case IFM_10_T:
 2917                 flowctl = TI_LNK_RX_FLOWCTL_Y;
 2918 #if 0
 2919                 if (sc->ti_hwrev != TI_HWREV_TIGON)
 2920                         flowctl |= TI_LNK_TX_FLOWCTL_Y;
 2921 #endif
 2922 
 2923                 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
 2924                 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
 2925                 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
 2926                     IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
 2927                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
 2928                 } else {
 2929                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
 2930                 }
 2931                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
 2932                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
 2933                 } else {
 2934                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
 2935                 }
 2936                 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
 2937                     TI_CMD_CODE_NEGOTIATE_10_100, 0);
 2938                 break;
 2939         }
 2940 
 2941         return (0);
 2942 }
 2943 
 2944 /*
 2945  * Report current media status.
 2946  */
 2947 static void
 2948 ti_ifmedia_sts(ifp, ifmr)
 2949         struct ifnet            *ifp;
 2950         struct ifmediareq       *ifmr;
 2951 {
 2952         struct ti_softc         *sc;
 2953         u_int32_t               media = 0;
 2954 
 2955         sc = ifp->if_softc;
 2956 
 2957         ifmr->ifm_status = IFM_AVALID;
 2958         ifmr->ifm_active = IFM_ETHER;
 2959 
 2960         if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
 2961                 return;
 2962 
 2963         ifmr->ifm_status |= IFM_ACTIVE;
 2964 
 2965         if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
 2966                 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
 2967                 if (sc->ti_copper)
 2968                         ifmr->ifm_active |= IFM_1000_T;
 2969                 else
 2970                         ifmr->ifm_active |= IFM_1000_SX;
 2971                 if (media & TI_GLNK_FULL_DUPLEX)
 2972                         ifmr->ifm_active |= IFM_FDX;
 2973                 else
 2974                         ifmr->ifm_active |= IFM_HDX;
 2975         } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
 2976                 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
 2977                 if (sc->ti_copper) {
 2978                         if (media & TI_LNK_100MB)
 2979                                 ifmr->ifm_active |= IFM_100_TX;
 2980                         if (media & TI_LNK_10MB)
 2981                                 ifmr->ifm_active |= IFM_10_T;
 2982                 } else {
 2983                         if (media & TI_LNK_100MB)
 2984                                 ifmr->ifm_active |= IFM_100_FX;
 2985                         if (media & TI_LNK_10MB)
 2986                                 ifmr->ifm_active |= IFM_10_FL;
 2987                 }
 2988                 if (media & TI_LNK_FULL_DUPLEX)
 2989                         ifmr->ifm_active |= IFM_FDX;
 2990                 if (media & TI_LNK_HALF_DUPLEX)
 2991                         ifmr->ifm_active |= IFM_HDX;
 2992         }
 2993 }
 2994 
 2995 static int
 2996 ti_ioctl(ifp, command, data)
 2997         struct ifnet            *ifp;
 2998         u_long                  command;
 2999         caddr_t                 data;
 3000 {
 3001         struct ti_softc         *sc = ifp->if_softc;
 3002         struct ifreq            *ifr = (struct ifreq *) data;
 3003         int                     mask, error = 0;
 3004         struct ti_cmd_desc      cmd;
 3005 
 3006         TI_LOCK(sc);
 3007 
 3008         switch (command) {
 3009         case SIOCSIFMTU:
 3010                 if (ifr->ifr_mtu > TI_JUMBO_MTU)
 3011                         error = EINVAL;
 3012                 else {
 3013                         ifp->if_mtu = ifr->ifr_mtu;
 3014                         ti_init(sc);
 3015                 }
 3016                 break;
 3017         case SIOCSIFFLAGS:
 3018                 if (ifp->if_flags & IFF_UP) {
 3019                         /*
 3020                          * If only the state of the PROMISC flag changed,
 3021                          * then just use the 'set promisc mode' command
 3022                          * instead of reinitializing the entire NIC. Doing
 3023                          * a full re-init means reloading the firmware and
 3024                          * waiting for it to start up, which may take a
 3025                          * second or two.
 3026                          */
 3027                         if (ifp->if_flags & IFF_RUNNING &&
 3028                             ifp->if_flags & IFF_PROMISC &&
 3029                             !(sc->ti_if_flags & IFF_PROMISC)) {
 3030                                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
 3031                                     TI_CMD_CODE_PROMISC_ENB, 0);
 3032                         } else if (ifp->if_flags & IFF_RUNNING &&
 3033                             !(ifp->if_flags & IFF_PROMISC) &&
 3034                             sc->ti_if_flags & IFF_PROMISC) {
 3035                                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
 3036                                     TI_CMD_CODE_PROMISC_DIS, 0);
 3037                         } else
 3038                                 ti_init(sc);
 3039                 } else {
 3040                         if (ifp->if_flags & IFF_RUNNING) {
 3041                                 ti_stop(sc);
 3042                         }
 3043                 }
 3044                 sc->ti_if_flags = ifp->if_flags;
 3045                 error = 0;
 3046                 break;
 3047         case SIOCADDMULTI:
 3048         case SIOCDELMULTI:
 3049                 if (ifp->if_flags & IFF_RUNNING) {
 3050                         ti_setmulti(sc);
 3051                         error = 0;
 3052                 }
 3053                 break;
 3054         case SIOCSIFMEDIA:
 3055         case SIOCGIFMEDIA:
 3056                 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
 3057                 break;
 3058         case SIOCSIFCAP:
 3059                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 3060                 if (mask & IFCAP_HWCSUM) {
 3061                         if (IFCAP_HWCSUM & ifp->if_capenable)
 3062                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
 3063                         else
 3064                                 ifp->if_capenable |= IFCAP_HWCSUM;
 3065                         if (ifp->if_flags & IFF_RUNNING)
 3066                                 ti_init(sc);
 3067                 }
 3068                 error = 0;
 3069                 break;
 3070         default:
 3071                 error = ether_ioctl(ifp, command, data);
 3072                 break;
 3073         }
 3074 
 3075         TI_UNLOCK(sc);
 3076 
 3077         return (error);
 3078 }
 3079 
 3080 static int
 3081 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
 3082 {
 3083         struct ti_softc *sc;
 3084 
 3085         sc = dev->si_drv1;
 3086         if (sc == NULL)
 3087                 return (ENODEV);
 3088 
 3089         TI_LOCK(sc);
 3090         sc->ti_flags |= TI_FLAG_DEBUGING;
 3091         TI_UNLOCK(sc);
 3092 
 3093         return (0);
 3094 }
 3095 
 3096 static int
 3097 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
 3098 {
 3099         struct ti_softc *sc;
 3100 
 3101         sc = dev->si_drv1;
 3102         if (sc == NULL)
 3103                 return (ENODEV);
 3104 
 3105         TI_LOCK(sc);
 3106         sc->ti_flags &= ~TI_FLAG_DEBUGING;
 3107         TI_UNLOCK(sc);
 3108 
 3109         return (0);
 3110 }
 3111 
 3112 /*
 3113  * This ioctl routine goes along with the Tigon character device.
 3114  */
 3115 static int
 3116 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, struct thread *td)
 3117 {
 3118         int error;
 3119         struct ti_softc *sc;
 3120 
 3121         sc = dev->si_drv1;
 3122         if (sc == NULL)
 3123                 return (ENODEV);
 3124 
 3125         error = 0;
 3126 
 3127         switch (cmd) {
 3128         case TIIOCGETSTATS:
 3129         {
 3130                 struct ti_stats *outstats;
 3131 
 3132                 outstats = (struct ti_stats *)addr;
 3133 
 3134                 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
 3135                       sizeof(struct ti_stats));
 3136                 break;
 3137         }
 3138         case TIIOCGETPARAMS:
 3139         {
 3140                 struct ti_params        *params;
 3141 
 3142                 params = (struct ti_params *)addr;
 3143 
 3144                 params->ti_stat_ticks = sc->ti_stat_ticks;
 3145                 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
 3146                 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
 3147                 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
 3148                 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
 3149                 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
 3150                 params->param_mask = TI_PARAM_ALL;
 3151 
 3152                 error = 0;
 3153 
 3154                 break;
 3155         }
 3156         case TIIOCSETPARAMS:
 3157         {
 3158                 struct ti_params *params;
 3159 
 3160                 params = (struct ti_params *)addr;
 3161 
 3162                 if (params->param_mask & TI_PARAM_STAT_TICKS) {
 3163                         sc->ti_stat_ticks = params->ti_stat_ticks;
 3164                         CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
 3165                 }
 3166 
 3167                 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
 3168                         sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
 3169                         CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
 3170                                     sc->ti_rx_coal_ticks);
 3171                 }
 3172 
 3173                 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
 3174                         sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
 3175                         CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
 3176                                     sc->ti_tx_coal_ticks);
 3177                 }
 3178 
 3179                 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
 3180                         sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
 3181                         CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
 3182                                     sc->ti_rx_max_coal_bds);
 3183                 }
 3184 
 3185                 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
 3186                         sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
 3187                         CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
 3188                                     sc->ti_tx_max_coal_bds);
 3189                 }
 3190 
 3191                 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
 3192                         sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
 3193                         CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
 3194                                     sc->ti_tx_buf_ratio);
 3195                 }
 3196 
 3197                 error = 0;
 3198 
 3199                 break;
 3200         }
 3201         case TIIOCSETTRACE: {
 3202                 ti_trace_type   trace_type;
 3203 
 3204                 trace_type = *(ti_trace_type *)addr;
 3205 
 3206                 /*
 3207                  * Set tracing to whatever the user asked for.  Setting
 3208                  * this register to 0 should have the effect of disabling
 3209                  * tracing.
 3210                  */
 3211                 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
 3212 
 3213                 error = 0;
 3214 
 3215                 break;
 3216         }
 3217         case TIIOCGETTRACE: {
 3218                 struct ti_trace_buf     *trace_buf;
 3219                 u_int32_t               trace_start, cur_trace_ptr, trace_len;
 3220 
 3221                 trace_buf = (struct ti_trace_buf *)addr;
 3222 
 3223                 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
 3224                 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
 3225                 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
 3226 
 3227 #if 0
 3228                 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, "
 3229                        "trace_len = %d\n", sc->ti_unit, trace_start,
 3230                        cur_trace_ptr, trace_len);
 3231                 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit,
 3232                        trace_buf->buf_len);
 3233 #endif
 3234 
 3235                 error = ti_copy_mem(sc, trace_start, min(trace_len,
 3236                                     trace_buf->buf_len),
 3237                                     (caddr_t)trace_buf->buf, 1, 1);
 3238 
 3239                 if (error == 0) {
 3240                         trace_buf->fill_len = min(trace_len,
 3241                                                   trace_buf->buf_len);
 3242                         if (cur_trace_ptr < trace_start)
 3243                                 trace_buf->cur_trace_ptr =
 3244                                         trace_start - cur_trace_ptr;
 3245                         else
 3246                                 trace_buf->cur_trace_ptr =
 3247                                         cur_trace_ptr - trace_start;
 3248                 } else
 3249                         trace_buf->fill_len = 0;
 3250 
 3251                 break;
 3252         }
 3253 
 3254         /*
 3255          * For debugging, five ioctls are needed:
 3256          * ALT_ATTACH
 3257          * ALT_READ_TG_REG
 3258          * ALT_WRITE_TG_REG
 3259          * ALT_READ_TG_MEM
 3260          * ALT_WRITE_TG_MEM
 3261          */
 3262         case ALT_ATTACH:
 3263                 /*
 3264                  * From what I can tell, Alteon's Solaris Tigon driver
 3265                  * only has one character device, so you have to attach
 3266                  * to the Tigon board you're interested in.  This seems
 3267                  * like a not-so-good way to do things, since unless you
 3268                  * subsequently specify the unit number of the device
 3269                  * you're interested in in every ioctl, you'll only be
 3270                  * able to debug one board at a time.
 3271                  */
 3272                 error = 0;
 3273                 break;
 3274         case ALT_READ_TG_MEM:
 3275         case ALT_WRITE_TG_MEM:
 3276         {
 3277                 struct tg_mem *mem_param;
 3278                 u_int32_t sram_end, scratch_end;
 3279 
 3280                 mem_param = (struct tg_mem *)addr;
 3281 
 3282                 if (sc->ti_hwrev == TI_HWREV_TIGON) {
 3283                         sram_end = TI_END_SRAM_I;
 3284                         scratch_end = TI_END_SCRATCH_I;
 3285                 } else {
 3286                         sram_end = TI_END_SRAM_II;
 3287                         scratch_end = TI_END_SCRATCH_II;
 3288                 }
 3289 
 3290                 /*
 3291                  * For now, we'll only handle accessing regular SRAM,
 3292                  * nothing else.
 3293                  */
 3294                 if ((mem_param->tgAddr >= TI_BEG_SRAM)
 3295                  && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
 3296                         /*
 3297                          * In this instance, we always copy to/from user
 3298                          * space, so the user space argument is set to 1.
 3299                          */
 3300                         error = ti_copy_mem(sc, mem_param->tgAddr,
 3301                                             mem_param->len,
 3302                                             mem_param->userAddr, 1,
 3303                                             (cmd == ALT_READ_TG_MEM) ? 1 : 0);
 3304                 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
 3305                         && (mem_param->tgAddr <= scratch_end)) {
 3306                         error = ti_copy_scratch(sc, mem_param->tgAddr,
 3307                                                 mem_param->len,
 3308                                                 mem_param->userAddr, 1,
 3309                                                 (cmd == ALT_READ_TG_MEM) ?
 3310                                                 1 : 0, TI_PROCESSOR_A);
 3311                 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
 3312                         && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
 3313                         if (sc->ti_hwrev == TI_HWREV_TIGON) {
 3314                                 printf("ti%d:  invalid memory range for "
 3315                                        "Tigon I\n", sc->ti_unit);
 3316                                 error = EINVAL;
 3317                                 break;
 3318                         }
 3319                         error = ti_copy_scratch(sc, mem_param->tgAddr -
 3320                                                 TI_SCRATCH_DEBUG_OFF,
 3321                                                 mem_param->len,
 3322                                                 mem_param->userAddr, 1,
 3323                                                 (cmd == ALT_READ_TG_MEM) ?
 3324                                                 1 : 0, TI_PROCESSOR_B);
 3325                 } else {
 3326                         printf("ti%d: memory address %#x len %d is out of "
 3327                                "supported range\n", sc->ti_unit,
 3328                                 mem_param->tgAddr, mem_param->len);
 3329                         error = EINVAL;
 3330                 }
 3331 
 3332                 break;
 3333         }
 3334         case ALT_READ_TG_REG:
 3335         case ALT_WRITE_TG_REG:
 3336         {
 3337                 struct tg_reg   *regs;
 3338                 u_int32_t       tmpval;
 3339 
 3340                 regs = (struct tg_reg *)addr;
 3341 
 3342                 /*
 3343                  * Make sure the address in question isn't out of range.
 3344                  */
 3345                 if (regs->addr > TI_REG_MAX) {
 3346                         error = EINVAL;
 3347                         break;
 3348                 }
 3349                 if (cmd == ALT_READ_TG_REG) {
 3350                         bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
 3351                                                 regs->addr, &tmpval, 1);
 3352                         regs->data = ntohl(tmpval);
 3353 #if 0
 3354                         if ((regs->addr == TI_CPU_STATE)
 3355                          || (regs->addr == TI_CPU_CTL_B)) {
 3356                                 printf("ti%d: register %#x = %#x\n",
 3357                                        sc->ti_unit, regs->addr, tmpval);
 3358                         }
 3359 #endif
 3360                 } else {
 3361                         tmpval = htonl(regs->data);
 3362                         bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
 3363                                                  regs->addr, &tmpval, 1);
 3364                 }
 3365 
 3366                 break;
 3367         }
 3368         default:
 3369                 error = ENOTTY;
 3370                 break;
 3371         }
 3372         return (error);
 3373 }
 3374 
 3375 static void
 3376 ti_watchdog(ifp)
 3377         struct ifnet            *ifp;
 3378 {
 3379         struct ti_softc         *sc;
 3380 
 3381         sc = ifp->if_softc;
 3382         TI_LOCK(sc);
 3383 
 3384         /*
 3385          * When we're debugging, the chip is often stopped for long periods
 3386          * of time, and that would normally cause the watchdog timer to fire.
 3387          * Since that impedes debugging, we don't want to do that.
 3388          */
 3389         if (sc->ti_flags & TI_FLAG_DEBUGING) {
 3390                 TI_UNLOCK(sc);
 3391                 return;
 3392         }
 3393 
 3394         printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
 3395         ti_stop(sc);
 3396         ti_init(sc);
 3397 
 3398         ifp->if_oerrors++;
 3399         TI_UNLOCK(sc);
 3400 }
 3401 
 3402 /*
 3403  * Stop the adapter and free any mbufs allocated to the
 3404  * RX and TX lists.
 3405  */
 3406 static void
 3407 ti_stop(sc)
 3408         struct ti_softc         *sc;
 3409 {
 3410         struct ifnet            *ifp;
 3411         struct ti_cmd_desc      cmd;
 3412 
 3413         TI_LOCK(sc);
 3414 
 3415         ifp = &sc->arpcom.ac_if;
 3416 
 3417         /* Disable host interrupts. */
 3418         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 3419         /*
 3420          * Tell firmware we're shutting down.
 3421          */
 3422         TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
 3423 
 3424         /* Halt and reinitialize. */
 3425         ti_chipinit(sc);
 3426         ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
 3427         ti_chipinit(sc);
 3428 
 3429         /* Free the RX lists. */
 3430         ti_free_rx_ring_std(sc);
 3431 
 3432         /* Free jumbo RX list. */
 3433         ti_free_rx_ring_jumbo(sc);
 3434 
 3435         /* Free mini RX list. */
 3436         ti_free_rx_ring_mini(sc);
 3437 
 3438         /* Free TX buffers. */
 3439         ti_free_tx_ring(sc);
 3440 
 3441         sc->ti_ev_prodidx.ti_idx = 0;
 3442         sc->ti_return_prodidx.ti_idx = 0;
 3443         sc->ti_tx_considx.ti_idx = 0;
 3444         sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
 3445 
 3446         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 3447         TI_UNLOCK(sc);
 3448 }
 3449 
 3450 /*
 3451  * Stop all chip I/O so that the kernel's probe routines don't
 3452  * get confused by errant DMAs when rebooting.
 3453  */
 3454 static void
 3455 ti_shutdown(dev)
 3456         device_t                dev;
 3457 {
 3458         struct ti_softc         *sc;
 3459 
 3460         sc = device_get_softc(dev);
 3461         TI_LOCK(sc);
 3462         ti_chipinit(sc);
 3463         TI_UNLOCK(sc);
 3464 }

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