The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_ti.c

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    1 /*-
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 /*
   34  * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
   35  * Manuals, sample driver and firmware source kits are available
   36  * from http://www.alteon.com/support/openkits.
   37  *
   38  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   39  * Electrical Engineering Department
   40  * Columbia University, New York City
   41  */
   42 
   43 /*
   44  * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
   45  * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
   46  * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
   47  * Tigon supports hardware IP, TCP and UCP checksumming, multicast
   48  * filtering and jumbo (9014 byte) frames. The hardware is largely
   49  * controlled by firmware, which must be loaded into the NIC during
   50  * initialization.
   51  *
   52  * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
   53  * revision, which supports new features such as extended commands,
   54  * extended jumbo receive ring desciptors and a mini receive ring.
   55  *
   56  * Alteon Networks is to be commended for releasing such a vast amount
   57  * of development material for the Tigon NIC without requiring an NDA
   58  * (although they really should have done it a long time ago). With
   59  * any luck, the other vendors will finally wise up and follow Alteon's
   60  * stellar example.
   61  *
   62  * The firmware for the Tigon 1 and 2 NICs is compiled directly into
   63  * this driver by #including it as a C header file. This bloats the
   64  * driver somewhat, but it's the easiest method considering that the
   65  * driver code and firmware code need to be kept in sync. The source
   66  * for the firmware is not provided with the FreeBSD distribution since
   67  * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
   68  *
   69  * The following people deserve special thanks:
   70  * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
   71  *   for testing
   72  * - Raymond Lee of Netgear, for providing a pair of Netgear
   73  *   GA620 Tigon 2 boards for testing
   74  * - Ulf Zimmermann, for bringing the GA260 to my attention and
   75  *   convincing me to write this driver.
   76  * - Andrew Gallatin for providing FreeBSD/Alpha support.
   77  */
   78 
   79 #include <sys/cdefs.h>
   80 __FBSDID("$FreeBSD: releng/6.2/sys/pci/if_ti.c 154345 2006-01-14 10:05:07Z glebius $");
   81 
   82 #include "opt_ti.h"
   83 
   84 #include <sys/param.h>
   85 #include <sys/systm.h>
   86 #include <sys/sockio.h>
   87 #include <sys/mbuf.h>
   88 #include <sys/malloc.h>
   89 #include <sys/kernel.h>
   90 #include <sys/module.h>
   91 #include <sys/socket.h>
   92 #include <sys/queue.h>
   93 #include <sys/conf.h>
   94 
   95 #include <net/if.h>
   96 #include <net/if_arp.h>
   97 #include <net/ethernet.h>
   98 #include <net/if_dl.h>
   99 #include <net/if_media.h>
  100 #include <net/if_types.h>
  101 #include <net/if_vlan_var.h>
  102 
  103 #include <net/bpf.h>
  104 
  105 #include <netinet/in_systm.h>
  106 #include <netinet/in.h>
  107 #include <netinet/ip.h>
  108 
  109 #include <vm/vm.h>              /* for vtophys */
  110 #include <vm/pmap.h>            /* for vtophys */
  111 #include <machine/bus.h>
  112 #include <machine/resource.h>
  113 #include <sys/bus.h>
  114 #include <sys/rman.h>
  115 
  116 /* #define TI_PRIVATE_JUMBOS */
  117 
  118 #if !defined(TI_PRIVATE_JUMBOS)
  119 #include <sys/sockio.h>
  120 #include <sys/uio.h>
  121 #include <sys/lock.h>
  122 #include <sys/sf_buf.h>
  123 #include <vm/vm_extern.h>
  124 #include <vm/pmap.h>
  125 #include <vm/vm_map.h>
  126 #include <vm/vm_map.h>
  127 #include <vm/vm_param.h>
  128 #include <vm/vm_pageout.h>
  129 #include <sys/vmmeter.h>
  130 #include <vm/vm_page.h>
  131 #include <vm/vm_object.h>
  132 #include <vm/vm_kern.h>
  133 #include <sys/proc.h>
  134 #endif /* !TI_PRIVATE_JUMBOS */
  135 
  136 #include <dev/pci/pcireg.h>
  137 #include <dev/pci/pcivar.h>
  138 
  139 #include <sys/tiio.h>
  140 #include <pci/if_tireg.h>
  141 #include <pci/ti_fw.h>
  142 #include <pci/ti_fw2.h>
  143 
  144 #define TI_CSUM_FEATURES        (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
  145 /*
  146  * We can only turn on header splitting if we're using extended receive
  147  * BDs.
  148  */
  149 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
  150 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
  151 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
  152 
  153 struct ti_softc *tis[8];
  154 
  155 typedef enum {
  156         TI_SWAP_HTON,
  157         TI_SWAP_NTOH
  158 } ti_swap_type;
  159 
  160 
  161 /*
  162  * Various supported device vendors/types and their names.
  163  */
  164 
  165 static struct ti_type ti_devs[] = {
  166         { ALT_VENDORID, ALT_DEVICEID_ACENIC,
  167                 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
  168         { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
  169                 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
  170         { TC_VENDORID,  TC_DEVICEID_3C985,
  171                 "3Com 3c985-SX Gigabit Ethernet" },
  172         { NG_VENDORID, NG_DEVICEID_GA620,
  173                 "Netgear GA620 1000baseSX Gigabit Ethernet" },
  174         { NG_VENDORID, NG_DEVICEID_GA620T,
  175                 "Netgear GA620 1000baseT Gigabit Ethernet" },
  176         { SGI_VENDORID, SGI_DEVICEID_TIGON,
  177                 "Silicon Graphics Gigabit Ethernet" },
  178         { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
  179                 "Farallon PN9000SX Gigabit Ethernet" },
  180         { 0, 0, NULL }
  181 };
  182 
  183 
  184 static  d_open_t        ti_open;
  185 static  d_close_t       ti_close;
  186 static  d_ioctl_t       ti_ioctl2;
  187 
  188 static struct cdevsw ti_cdevsw = {
  189         .d_version =    D_VERSION,
  190         .d_flags =      D_NEEDGIANT,
  191         .d_open =       ti_open,
  192         .d_close =      ti_close,
  193         .d_ioctl =      ti_ioctl2,
  194         .d_name =       "ti",
  195 };
  196 
  197 static int ti_probe(device_t);
  198 static int ti_attach(device_t);
  199 static int ti_detach(device_t);
  200 static void ti_txeof(struct ti_softc *);
  201 static void ti_rxeof(struct ti_softc *);
  202 
  203 static void ti_stats_update(struct ti_softc *);
  204 static int ti_encap(struct ti_softc *, struct mbuf *, u_int32_t *);
  205 
  206 static void ti_intr(void *);
  207 static void ti_start(struct ifnet *);
  208 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
  209 static void ti_init(void *);
  210 static void ti_init2(struct ti_softc *);
  211 static void ti_stop(struct ti_softc *);
  212 static void ti_watchdog(struct ifnet *);
  213 static void ti_shutdown(device_t);
  214 static int ti_ifmedia_upd(struct ifnet *);
  215 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  216 
  217 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int);
  218 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *);
  219 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
  220 
  221 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
  222 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
  223 static void ti_setmulti(struct ti_softc *);
  224 
  225 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t);
  226 static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int);
  227 static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t,
  228                 int, int, int);
  229 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
  230 static void ti_loadfw(struct ti_softc *);
  231 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
  232 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
  233 static void ti_handle_events(struct ti_softc *);
  234 #ifdef TI_PRIVATE_JUMBOS
  235 static int ti_alloc_jumbo_mem(struct ti_softc *);
  236 static void *ti_jalloc(struct ti_softc *);
  237 static void ti_jfree(void *, void *);
  238 #endif /* TI_PRIVATE_JUMBOS */
  239 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
  240 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
  241 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
  242 static int ti_init_rx_ring_std(struct ti_softc *);
  243 static void ti_free_rx_ring_std(struct ti_softc *);
  244 static int ti_init_rx_ring_jumbo(struct ti_softc *);
  245 static void ti_free_rx_ring_jumbo(struct ti_softc *);
  246 static int ti_init_rx_ring_mini(struct ti_softc *);
  247 static void ti_free_rx_ring_mini(struct ti_softc *);
  248 static void ti_free_tx_ring(struct ti_softc *);
  249 static int ti_init_tx_ring(struct ti_softc *);
  250 
  251 static int ti_64bitslot_war(struct ti_softc *);
  252 static int ti_chipinit(struct ti_softc *);
  253 static int ti_gibinit(struct ti_softc *);
  254 
  255 #ifdef TI_JUMBO_HDRSPLIT
  256 static __inline void ti_hdr_split       (struct mbuf *top, int hdr_len,
  257                                              int pkt_len, int idx);
  258 #endif /* TI_JUMBO_HDRSPLIT */
  259 
  260 static device_method_t ti_methods[] = {
  261         /* Device interface */
  262         DEVMETHOD(device_probe,         ti_probe),
  263         DEVMETHOD(device_attach,        ti_attach),
  264         DEVMETHOD(device_detach,        ti_detach),
  265         DEVMETHOD(device_shutdown,      ti_shutdown),
  266         { 0, 0 }
  267 };
  268 
  269 static driver_t ti_driver = {
  270         "ti",
  271         ti_methods,
  272         sizeof(struct ti_softc)
  273 };
  274 
  275 static devclass_t ti_devclass;
  276 
  277 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
  278 MODULE_DEPEND(ti, pci, 1, 1, 1);
  279 MODULE_DEPEND(ti, ether, 1, 1, 1);
  280 
  281 /*
  282  * Send an instruction or address to the EEPROM, check for ACK.
  283  */
  284 static u_int32_t ti_eeprom_putbyte(sc, byte)
  285         struct ti_softc         *sc;
  286         int                     byte;
  287 {
  288         register int            i, ack = 0;
  289 
  290         /*
  291          * Make sure we're in TX mode.
  292          */
  293         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
  294 
  295         /*
  296          * Feed in each bit and stobe the clock.
  297          */
  298         for (i = 0x80; i; i >>= 1) {
  299                 if (byte & i) {
  300                         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
  301                 } else {
  302                         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
  303                 }
  304                 DELAY(1);
  305                 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  306                 DELAY(1);
  307                 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  308         }
  309 
  310         /*
  311          * Turn off TX mode.
  312          */
  313         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
  314 
  315         /*
  316          * Check for ack.
  317          */
  318         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  319         ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
  320         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  321 
  322         return (ack);
  323 }
  324 
  325 /*
  326  * Read a byte of data stored in the EEPROM at address 'addr.'
  327  * We have to send two address bytes since the EEPROM can hold
  328  * more than 256 bytes of data.
  329  */
  330 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
  331         struct ti_softc         *sc;
  332         int                     addr;
  333         u_int8_t                *dest;
  334 {
  335         register int            i;
  336         u_int8_t                byte = 0;
  337 
  338         EEPROM_START;
  339 
  340         /*
  341          * Send write control code to EEPROM.
  342          */
  343         if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
  344                 printf("ti%d: failed to send write command, status: %x\n",
  345                     sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  346                 return (1);
  347         }
  348 
  349         /*
  350          * Send first byte of address of byte we want to read.
  351          */
  352         if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
  353                 printf("ti%d: failed to send address, status: %x\n",
  354                     sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  355                 return (1);
  356         }
  357         /*
  358          * Send second byte address of byte we want to read.
  359          */
  360         if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
  361                 printf("ti%d: failed to send address, status: %x\n",
  362                     sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  363                 return (1);
  364         }
  365 
  366         EEPROM_STOP;
  367         EEPROM_START;
  368         /*
  369          * Send read control code to EEPROM.
  370          */
  371         if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
  372                 printf("ti%d: failed to send read command, status: %x\n",
  373                     sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  374                 return (1);
  375         }
  376 
  377         /*
  378          * Start reading bits from EEPROM.
  379          */
  380         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
  381         for (i = 0x80; i; i >>= 1) {
  382                 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  383                 DELAY(1);
  384                 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
  385                         byte |= i;
  386                 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  387                 DELAY(1);
  388         }
  389 
  390         EEPROM_STOP;
  391 
  392         /*
  393          * No ACK generated for read, so just return byte.
  394          */
  395 
  396         *dest = byte;
  397 
  398         return (0);
  399 }
  400 
  401 /*
  402  * Read a sequence of bytes from the EEPROM.
  403  */
  404 static int
  405 ti_read_eeprom(sc, dest, off, cnt)
  406         struct ti_softc         *sc;
  407         caddr_t                 dest;
  408         int                     off;
  409         int                     cnt;
  410 {
  411         int                     err = 0, i;
  412         u_int8_t                byte = 0;
  413 
  414         for (i = 0; i < cnt; i++) {
  415                 err = ti_eeprom_getbyte(sc, off + i, &byte);
  416                 if (err)
  417                         break;
  418                 *(dest + i) = byte;
  419         }
  420 
  421         return (err ? 1 : 0);
  422 }
  423 
  424 /*
  425  * NIC memory access function. Can be used to either clear a section
  426  * of NIC local memory or (if buf is non-NULL) copy data into it.
  427  */
  428 static void
  429 ti_mem(sc, addr, len, buf)
  430         struct ti_softc         *sc;
  431         u_int32_t               addr, len;
  432         caddr_t                 buf;
  433 {
  434         int                     segptr, segsize, cnt;
  435         caddr_t                 ti_winbase, ptr;
  436 
  437         segptr = addr;
  438         cnt = len;
  439         ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
  440         ptr = buf;
  441 
  442         while (cnt) {
  443                 if (cnt < TI_WINLEN)
  444                         segsize = cnt;
  445                 else
  446                         segsize = TI_WINLEN - (segptr % TI_WINLEN);
  447                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
  448                 if (buf == NULL)
  449                         bzero((char *)ti_winbase + (segptr &
  450                             (TI_WINLEN - 1)), segsize);
  451                 else {
  452                         bcopy((char *)ptr, (char *)ti_winbase +
  453                             (segptr & (TI_WINLEN - 1)), segsize);
  454                         ptr += segsize;
  455                 }
  456                 segptr += segsize;
  457                 cnt -= segsize;
  458         }
  459 }
  460 
  461 static int
  462 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata)
  463         struct ti_softc         *sc;
  464         u_int32_t               tigon_addr, len;
  465         caddr_t                 buf;
  466         int                     useraddr, readdata;
  467 {
  468         int             segptr, segsize, cnt;
  469         caddr_t         ptr;
  470         u_int32_t       origwin;
  471         u_int8_t        tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
  472         int             resid, segresid;
  473         int             first_pass;
  474 
  475         /*
  476          * At the moment, we don't handle non-aligned cases, we just bail.
  477          * If this proves to be a problem, it will be fixed.
  478          */
  479         if ((readdata == 0)
  480          && (tigon_addr & 0x3)) {
  481                 printf("ti%d: ti_copy_mem: tigon address %#x isn't "
  482                        "word-aligned\n", sc->ti_unit, tigon_addr);
  483                 printf("ti%d: ti_copy_mem: unaligned writes aren't yet "
  484                        "supported\n", sc->ti_unit);
  485                 return (EINVAL);
  486         }
  487 
  488         segptr = tigon_addr & ~0x3;
  489         segresid = tigon_addr - segptr;
  490 
  491         /*
  492          * This is the non-aligned amount left over that we'll need to
  493          * copy.
  494          */
  495         resid = len & 0x3;
  496 
  497         /* Add in the left over amount at the front of the buffer */
  498         resid += segresid;
  499 
  500         cnt = len & ~0x3;
  501         /*
  502          * If resid + segresid is >= 4, add multiples of 4 to the count and
  503          * decrease the residual by that much.
  504          */
  505         cnt += resid & ~0x3;
  506         resid -= resid & ~0x3;
  507 
  508         ptr = buf;
  509 
  510         first_pass = 1;
  511 
  512         /*
  513          * Make sure we aren't interrupted while we're changing the window
  514          * pointer.
  515          */
  516         TI_LOCK(sc);
  517 
  518         /*
  519          * Save the old window base value.
  520          */
  521         origwin = CSR_READ_4(sc, TI_WINBASE);
  522 
  523         while (cnt) {
  524                 bus_size_t ti_offset;
  525 
  526                 if (cnt < TI_WINLEN)
  527                         segsize = cnt;
  528                 else
  529                         segsize = TI_WINLEN - (segptr % TI_WINLEN);
  530                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
  531 
  532                 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
  533 
  534                 if (readdata) {
  535 
  536                         bus_space_read_region_4(sc->ti_btag,
  537                                                 sc->ti_bhandle, ti_offset,
  538                                                 (u_int32_t *)tmparray,
  539                                                 segsize >> 2);
  540                         if (useraddr) {
  541                                 /*
  542                                  * Yeah, this is a little on the kludgy
  543                                  * side, but at least this code is only
  544                                  * used for debugging.
  545                                  */
  546                                 ti_bcopy_swap(tmparray, tmparray2, segsize,
  547                                               TI_SWAP_NTOH);
  548 
  549                                 if (first_pass) {
  550                                         copyout(&tmparray2[segresid], ptr,
  551                                                 segsize - segresid);
  552                                         first_pass = 0;
  553                                 } else
  554                                         copyout(tmparray2, ptr, segsize);
  555                         } else {
  556                                 if (first_pass) {
  557 
  558                                         ti_bcopy_swap(tmparray, tmparray2,
  559                                                       segsize, TI_SWAP_NTOH);
  560                                         bcopy(&tmparray2[segresid], ptr,
  561                                               segsize - segresid);
  562                                         first_pass = 0;
  563                                 } else
  564                                         ti_bcopy_swap(tmparray, ptr, segsize,
  565                                                       TI_SWAP_NTOH);
  566                         }
  567 
  568                 } else {
  569                         if (useraddr) {
  570                                 copyin(ptr, tmparray2, segsize);
  571                                 ti_bcopy_swap(tmparray2, tmparray, segsize,
  572                                               TI_SWAP_HTON);
  573                         } else
  574                                 ti_bcopy_swap(ptr, tmparray, segsize,
  575                                               TI_SWAP_HTON);
  576 
  577                         bus_space_write_region_4(sc->ti_btag,
  578                                                  sc->ti_bhandle, ti_offset,
  579                                                  (u_int32_t *)tmparray,
  580                                                  segsize >> 2);
  581                 }
  582                 segptr += segsize;
  583                 ptr += segsize;
  584                 cnt -= segsize;
  585         }
  586 
  587         /*
  588          * Handle leftover, non-word-aligned bytes.
  589          */
  590         if (resid != 0) {
  591                 u_int32_t       tmpval, tmpval2;
  592                 bus_size_t      ti_offset;
  593 
  594                 /*
  595                  * Set the segment pointer.
  596                  */
  597                 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
  598 
  599                 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
  600 
  601                 /*
  602                  * First, grab whatever is in our source/destination.
  603                  * We'll obviously need this for reads, but also for
  604                  * writes, since we'll be doing read/modify/write.
  605                  */
  606                 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
  607                                         ti_offset, &tmpval, 1);
  608 
  609                 /*
  610                  * Next, translate this from little-endian to big-endian
  611                  * (at least on i386 boxes).
  612                  */
  613                 tmpval2 = ntohl(tmpval);
  614 
  615                 if (readdata) {
  616                         /*
  617                          * If we're reading, just copy the leftover number
  618                          * of bytes from the host byte order buffer to
  619                          * the user's buffer.
  620                          */
  621                         if (useraddr)
  622                                 copyout(&tmpval2, ptr, resid);
  623                         else
  624                                 bcopy(&tmpval2, ptr, resid);
  625                 } else {
  626                         /*
  627                          * If we're writing, first copy the bytes to be
  628                          * written into the network byte order buffer,
  629                          * leaving the rest of the buffer with whatever was
  630                          * originally in there.  Then, swap the bytes
  631                          * around into host order and write them out.
  632                          *
  633                          * XXX KDM the read side of this has been verified
  634                          * to work, but the write side of it has not been
  635                          * verified.  So user beware.
  636                          */
  637                         if (useraddr)
  638                                 copyin(ptr, &tmpval2, resid);
  639                         else
  640                                 bcopy(ptr, &tmpval2, resid);
  641 
  642                         tmpval = htonl(tmpval2);
  643 
  644                         bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
  645                                                  ti_offset, &tmpval, 1);
  646                 }
  647         }
  648 
  649         CSR_WRITE_4(sc, TI_WINBASE, origwin);
  650 
  651         TI_UNLOCK(sc);
  652 
  653         return (0);
  654 }
  655 
  656 static int
  657 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu)
  658         struct ti_softc         *sc;
  659         u_int32_t               tigon_addr, len;
  660         caddr_t                 buf;
  661         int                     useraddr, readdata;
  662         int                     cpu;
  663 {
  664         u_int32_t       segptr;
  665         int             cnt;
  666         u_int32_t       tmpval, tmpval2;
  667         caddr_t         ptr;
  668 
  669         /*
  670          * At the moment, we don't handle non-aligned cases, we just bail.
  671          * If this proves to be a problem, it will be fixed.
  672          */
  673         if (tigon_addr & 0x3) {
  674                 printf("ti%d: ti_copy_scratch: tigon address %#x isn't "
  675                        "word-aligned\n", sc->ti_unit, tigon_addr);
  676                 return (EINVAL);
  677         }
  678 
  679         if (len & 0x3) {
  680                 printf("ti%d: ti_copy_scratch: transfer length %d isn't "
  681                        "word-aligned\n", sc->ti_unit, len);
  682                 return (EINVAL);
  683         }
  684 
  685         segptr = tigon_addr;
  686         cnt = len;
  687         ptr = buf;
  688 
  689         TI_LOCK(sc);
  690 
  691         while (cnt) {
  692                 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
  693 
  694                 if (readdata) {
  695                         tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
  696 
  697                         tmpval = ntohl(tmpval2);
  698 
  699                         /*
  700                          * Note:  I've used this debugging interface
  701                          * extensively with Alteon's 12.3.15 firmware,
  702                          * compiled with GCC 2.7.2.1 and binutils 2.9.1.
  703                          *
  704                          * When you compile the firmware without
  705                          * optimization, which is necessary sometimes in
  706                          * order to properly step through it, you sometimes
  707                          * read out a bogus value of 0xc0017c instead of
  708                          * whatever was supposed to be in that scratchpad
  709                          * location.  That value is on the stack somewhere,
  710                          * but I've never been able to figure out what was
  711                          * causing the problem.
  712                          *
  713                          * The address seems to pop up in random places,
  714                          * often not in the same place on two subsequent
  715                          * reads.
  716                          *
  717                          * In any case, the underlying data doesn't seem
  718                          * to be affected, just the value read out.
  719                          *
  720                          * KDM, 3/7/2000
  721                          */
  722 
  723                         if (tmpval2 == 0xc0017c)
  724                                 printf("ti%d: found 0xc0017c at %#x "
  725                                        "(tmpval2)\n", sc->ti_unit, segptr);
  726 
  727                         if (tmpval == 0xc0017c)
  728                                 printf("ti%d: found 0xc0017c at %#x "
  729                                        "(tmpval)\n", sc->ti_unit, segptr);
  730 
  731                         if (useraddr)
  732                                 copyout(&tmpval, ptr, 4);
  733                         else
  734                                 bcopy(&tmpval, ptr, 4);
  735                 } else {
  736                         if (useraddr)
  737                                 copyin(ptr, &tmpval2, 4);
  738                         else
  739                                 bcopy(ptr, &tmpval2, 4);
  740 
  741                         tmpval = htonl(tmpval2);
  742 
  743                         CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
  744                 }
  745 
  746                 cnt -= 4;
  747                 segptr += 4;
  748                 ptr += 4;
  749         }
  750 
  751         TI_UNLOCK(sc);
  752 
  753         return (0);
  754 }
  755 
  756 static int
  757 ti_bcopy_swap(src, dst, len, swap_type)
  758         const void      *src;
  759         void            *dst;
  760         size_t          len;
  761         ti_swap_type    swap_type;
  762 {
  763         const u_int8_t *tmpsrc;
  764         u_int8_t *tmpdst;
  765         size_t tmplen;
  766 
  767         if (len & 0x3) {
  768                 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
  769                        len);
  770                 return (-1);
  771         }
  772 
  773         tmpsrc = src;
  774         tmpdst = dst;
  775         tmplen = len;
  776 
  777         while (tmplen) {
  778                 if (swap_type == TI_SWAP_NTOH)
  779                         *(u_int32_t *)tmpdst =
  780                                 ntohl(*(const u_int32_t *)tmpsrc);
  781                 else
  782                         *(u_int32_t *)tmpdst =
  783                                 htonl(*(const u_int32_t *)tmpsrc);
  784 
  785                 tmpsrc += 4;
  786                 tmpdst += 4;
  787                 tmplen -= 4;
  788         }
  789 
  790         return (0);
  791 }
  792 
  793 /*
  794  * Load firmware image into the NIC. Check that the firmware revision
  795  * is acceptable and see if we want the firmware for the Tigon 1 or
  796  * Tigon 2.
  797  */
  798 static void
  799 ti_loadfw(sc)
  800         struct ti_softc         *sc;
  801 {
  802         switch (sc->ti_hwrev) {
  803         case TI_HWREV_TIGON:
  804                 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
  805                     tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
  806                     tigonFwReleaseFix != TI_FIRMWARE_FIX) {
  807                         printf("ti%d: firmware revision mismatch; want "
  808                             "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
  809                             TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
  810                             TI_FIRMWARE_FIX, tigonFwReleaseMajor,
  811                             tigonFwReleaseMinor, tigonFwReleaseFix);
  812                         return;
  813                 }
  814                 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
  815                     (caddr_t)tigonFwText);
  816                 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
  817                     (caddr_t)tigonFwData);
  818                 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
  819                     (caddr_t)tigonFwRodata);
  820                 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
  821                 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
  822                 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
  823                 break;
  824         case TI_HWREV_TIGON_II:
  825                 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
  826                     tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
  827                     tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
  828                         printf("ti%d: firmware revision mismatch; want "
  829                             "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
  830                             TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
  831                             TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
  832                             tigon2FwReleaseMinor, tigon2FwReleaseFix);
  833                         return;
  834                 }
  835                 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
  836                     (caddr_t)tigon2FwText);
  837                 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
  838                     (caddr_t)tigon2FwData);
  839                 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
  840                     (caddr_t)tigon2FwRodata);
  841                 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
  842                 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
  843                 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
  844                 break;
  845         default:
  846                 printf("ti%d: can't load firmware: unknown hardware rev\n",
  847                     sc->ti_unit);
  848                 break;
  849         }
  850 }
  851 
  852 /*
  853  * Send the NIC a command via the command ring.
  854  */
  855 static void
  856 ti_cmd(sc, cmd)
  857         struct ti_softc         *sc;
  858         struct ti_cmd_desc      *cmd;
  859 {
  860         u_int32_t               index;
  861 
  862         if (sc->ti_rdata->ti_cmd_ring == NULL)
  863                 return;
  864 
  865         index = sc->ti_cmd_saved_prodidx;
  866         CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
  867         TI_INC(index, TI_CMD_RING_CNT);
  868         CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
  869         sc->ti_cmd_saved_prodidx = index;
  870 }
  871 
  872 /*
  873  * Send the NIC an extended command. The 'len' parameter specifies the
  874  * number of command slots to include after the initial command.
  875  */
  876 static void
  877 ti_cmd_ext(sc, cmd, arg, len)
  878         struct ti_softc         *sc;
  879         struct ti_cmd_desc      *cmd;
  880         caddr_t                 arg;
  881         int                     len;
  882 {
  883         u_int32_t               index;
  884         register int            i;
  885 
  886         if (sc->ti_rdata->ti_cmd_ring == NULL)
  887                 return;
  888 
  889         index = sc->ti_cmd_saved_prodidx;
  890         CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
  891         TI_INC(index, TI_CMD_RING_CNT);
  892         for (i = 0; i < len; i++) {
  893                 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
  894                     *(u_int32_t *)(&arg[i * 4]));
  895                 TI_INC(index, TI_CMD_RING_CNT);
  896         }
  897         CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
  898         sc->ti_cmd_saved_prodidx = index;
  899 }
  900 
  901 /*
  902  * Handle events that have triggered interrupts.
  903  */
  904 static void
  905 ti_handle_events(sc)
  906         struct ti_softc         *sc;
  907 {
  908         struct ti_event_desc    *e;
  909 
  910         if (sc->ti_rdata->ti_event_ring == NULL)
  911                 return;
  912 
  913         while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
  914                 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
  915                 switch (e->ti_event) {
  916                 case TI_EV_LINKSTAT_CHANGED:
  917                         sc->ti_linkstat = e->ti_code;
  918                         if (e->ti_code == TI_EV_CODE_LINK_UP)
  919                                 printf("ti%d: 10/100 link up\n", sc->ti_unit);
  920                         else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
  921                                 printf("ti%d: gigabit link up\n", sc->ti_unit);
  922                         else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
  923                                 printf("ti%d: link down\n", sc->ti_unit);
  924                         break;
  925                 case TI_EV_ERROR:
  926                         if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
  927                                 printf("ti%d: invalid command\n", sc->ti_unit);
  928                         else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
  929                                 printf("ti%d: unknown command\n", sc->ti_unit);
  930                         else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
  931                                 printf("ti%d: bad config data\n", sc->ti_unit);
  932                         break;
  933                 case TI_EV_FIRMWARE_UP:
  934                         ti_init2(sc);
  935                         break;
  936                 case TI_EV_STATS_UPDATED:
  937                         ti_stats_update(sc);
  938                         break;
  939                 case TI_EV_RESET_JUMBO_RING:
  940                 case TI_EV_MCAST_UPDATED:
  941                         /* Who cares. */
  942                         break;
  943                 default:
  944                         printf("ti%d: unknown event: %d\n",
  945                             sc->ti_unit, e->ti_event);
  946                         break;
  947                 }
  948                 /* Advance the consumer index. */
  949                 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
  950                 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
  951         }
  952 }
  953 
  954 #ifdef TI_PRIVATE_JUMBOS
  955 
  956 /*
  957  * Memory management for the jumbo receive ring is a pain in the
  958  * butt. We need to allocate at least 9018 bytes of space per frame,
  959  * _and_ it has to be contiguous (unless you use the extended
  960  * jumbo descriptor format). Using malloc() all the time won't
  961  * work: malloc() allocates memory in powers of two, which means we
  962  * would end up wasting a considerable amount of space by allocating
  963  * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
  964  * to do our own memory management.
  965  *
  966  * The driver needs to allocate a contiguous chunk of memory at boot
  967  * time. We then chop this up ourselves into 9K pieces and use them
  968  * as external mbuf storage.
  969  *
  970  * One issue here is how much memory to allocate. The jumbo ring has
  971  * 256 slots in it, but at 9K per slot than can consume over 2MB of
  972  * RAM. This is a bit much, especially considering we also need
  973  * RAM for the standard ring and mini ring (on the Tigon 2). To
  974  * save space, we only actually allocate enough memory for 64 slots
  975  * by default, which works out to between 500 and 600K. This can
  976  * be tuned by changing a #define in if_tireg.h.
  977  */
  978 
  979 static int
  980 ti_alloc_jumbo_mem(sc)
  981         struct ti_softc         *sc;
  982 {
  983         caddr_t                 ptr;
  984         register int            i;
  985         struct ti_jpool_entry   *entry;
  986 
  987         /* Grab a big chunk o' storage. */
  988         sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
  989                 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
  990 
  991         if (sc->ti_cdata.ti_jumbo_buf == NULL) {
  992                 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
  993                 return (ENOBUFS);
  994         }
  995 
  996         SLIST_INIT(&sc->ti_jfree_listhead);
  997         SLIST_INIT(&sc->ti_jinuse_listhead);
  998 
  999         /*
 1000          * Now divide it up into 9K pieces and save the addresses
 1001          * in an array.
 1002          */
 1003         ptr = sc->ti_cdata.ti_jumbo_buf;
 1004         for (i = 0; i < TI_JSLOTS; i++) {
 1005                 sc->ti_cdata.ti_jslots[i] = ptr;
 1006                 ptr += TI_JLEN;
 1007                 entry = malloc(sizeof(struct ti_jpool_entry),
 1008                                M_DEVBUF, M_NOWAIT);
 1009                 if (entry == NULL) {
 1010                         contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
 1011                                    M_DEVBUF);
 1012                         sc->ti_cdata.ti_jumbo_buf = NULL;
 1013                         printf("ti%d: no memory for jumbo "
 1014                             "buffer queue!\n", sc->ti_unit);
 1015                         return (ENOBUFS);
 1016                 }
 1017                 entry->slot = i;
 1018                 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
 1019         }
 1020 
 1021         return (0);
 1022 }
 1023 
 1024 /*
 1025  * Allocate a jumbo buffer.
 1026  */
 1027 static void *ti_jalloc(sc)
 1028         struct ti_softc         *sc;
 1029 {
 1030         struct ti_jpool_entry   *entry;
 1031 
 1032         entry = SLIST_FIRST(&sc->ti_jfree_listhead);
 1033 
 1034         if (entry == NULL) {
 1035                 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
 1036                 return (NULL);
 1037         }
 1038 
 1039         SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
 1040         SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
 1041         return (sc->ti_cdata.ti_jslots[entry->slot]);
 1042 }
 1043 
 1044 /*
 1045  * Release a jumbo buffer.
 1046  */
 1047 static void
 1048 ti_jfree(buf, args)
 1049         void                    *buf;
 1050         void                    *args;
 1051 {
 1052         struct ti_softc         *sc;
 1053         int                     i;
 1054         struct ti_jpool_entry   *entry;
 1055 
 1056         /* Extract the softc struct pointer. */
 1057         sc = (struct ti_softc *)args;
 1058 
 1059         if (sc == NULL)
 1060                 panic("ti_jfree: didn't get softc pointer!");
 1061 
 1062         /* calculate the slot this buffer belongs to */
 1063         i = ((vm_offset_t)buf
 1064              - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
 1065 
 1066         if ((i < 0) || (i >= TI_JSLOTS))
 1067                 panic("ti_jfree: asked to free buffer that we don't manage!");
 1068 
 1069         entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
 1070         if (entry == NULL)
 1071                 panic("ti_jfree: buffer not in use!");
 1072         entry->slot = i;
 1073         SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
 1074         SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
 1075 }
 1076 
 1077 #endif /* TI_PRIVATE_JUMBOS */
 1078 
 1079 /*
 1080  * Intialize a standard receive ring descriptor.
 1081  */
 1082 static int
 1083 ti_newbuf_std(sc, i, m)
 1084         struct ti_softc         *sc;
 1085         int                     i;
 1086         struct mbuf             *m;
 1087 {
 1088         struct mbuf             *m_new = NULL;
 1089         struct ti_rx_desc       *r;
 1090 
 1091         if (m == NULL) {
 1092                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1093                 if (m_new == NULL)
 1094                         return (ENOBUFS);
 1095 
 1096                 MCLGET(m_new, M_DONTWAIT);
 1097                 if (!(m_new->m_flags & M_EXT)) {
 1098                         m_freem(m_new);
 1099                         return (ENOBUFS);
 1100                 }
 1101                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 1102         } else {
 1103                 m_new = m;
 1104                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 1105                 m_new->m_data = m_new->m_ext.ext_buf;
 1106         }
 1107 
 1108         m_adj(m_new, ETHER_ALIGN);
 1109         sc->ti_cdata.ti_rx_std_chain[i] = m_new;
 1110         r = &sc->ti_rdata->ti_rx_std_ring[i];
 1111         TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
 1112         r->ti_type = TI_BDTYPE_RECV_BD;
 1113         r->ti_flags = 0;
 1114         if (sc->ti_ifp->if_hwassist)
 1115                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
 1116         r->ti_len = m_new->m_len;
 1117         r->ti_idx = i;
 1118 
 1119         return (0);
 1120 }
 1121 
 1122 /*
 1123  * Intialize a mini receive ring descriptor. This only applies to
 1124  * the Tigon 2.
 1125  */
 1126 static int
 1127 ti_newbuf_mini(sc, i, m)
 1128         struct ti_softc         *sc;
 1129         int                     i;
 1130         struct mbuf             *m;
 1131 {
 1132         struct mbuf             *m_new = NULL;
 1133         struct ti_rx_desc       *r;
 1134 
 1135         if (m == NULL) {
 1136                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1137                 if (m_new == NULL) {
 1138                         return (ENOBUFS);
 1139                 }
 1140                 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
 1141         } else {
 1142                 m_new = m;
 1143                 m_new->m_data = m_new->m_pktdat;
 1144                 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
 1145         }
 1146 
 1147         m_adj(m_new, ETHER_ALIGN);
 1148         r = &sc->ti_rdata->ti_rx_mini_ring[i];
 1149         sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
 1150         TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
 1151         r->ti_type = TI_BDTYPE_RECV_BD;
 1152         r->ti_flags = TI_BDFLAG_MINI_RING;
 1153         if (sc->ti_ifp->if_hwassist)
 1154                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
 1155         r->ti_len = m_new->m_len;
 1156         r->ti_idx = i;
 1157 
 1158         return (0);
 1159 }
 1160 
 1161 #ifdef TI_PRIVATE_JUMBOS
 1162 
 1163 /*
 1164  * Initialize a jumbo receive ring descriptor. This allocates
 1165  * a jumbo buffer from the pool managed internally by the driver.
 1166  */
 1167 static int
 1168 ti_newbuf_jumbo(sc, i, m)
 1169         struct ti_softc         *sc;
 1170         int                     i;
 1171         struct mbuf             *m;
 1172 {
 1173         struct mbuf             *m_new = NULL;
 1174         struct ti_rx_desc       *r;
 1175 
 1176         if (m == NULL) {
 1177                 caddr_t                 *buf = NULL;
 1178 
 1179                 /* Allocate the mbuf. */
 1180                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1181                 if (m_new == NULL) {
 1182                         return (ENOBUFS);
 1183                 }
 1184 
 1185                 /* Allocate the jumbo buffer */
 1186                 buf = ti_jalloc(sc);
 1187                 if (buf == NULL) {
 1188                         m_freem(m_new);
 1189                         printf("ti%d: jumbo allocation failed "
 1190                             "-- packet dropped!\n", sc->ti_unit);
 1191                         return (ENOBUFS);
 1192                 }
 1193 
 1194                 /* Attach the buffer to the mbuf. */
 1195                 m_new->m_data = (void *) buf;
 1196                 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
 1197                 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
 1198                     (struct ti_softc *)sc, 0, EXT_NET_DRV);
 1199         } else {
 1200                 m_new = m;
 1201                 m_new->m_data = m_new->m_ext.ext_buf;
 1202                 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
 1203         }
 1204 
 1205         m_adj(m_new, ETHER_ALIGN);
 1206         /* Set up the descriptor. */
 1207         r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
 1208         sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
 1209         TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
 1210         r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
 1211         r->ti_flags = TI_BDFLAG_JUMBO_RING;
 1212         if (sc->ti_ifp->if_hwassist)
 1213                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
 1214         r->ti_len = m_new->m_len;
 1215         r->ti_idx = i;
 1216 
 1217         return (0);
 1218 }
 1219 
 1220 #else
 1221 #include <vm/vm_page.h>
 1222 
 1223 #if (PAGE_SIZE == 4096)
 1224 #define NPAYLOAD 2
 1225 #else
 1226 #define NPAYLOAD 1
 1227 #endif
 1228 
 1229 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
 1230 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
 1231 #define NFS_HDR_LEN (UDP_HDR_LEN)
 1232 static int HDR_LEN =  TCP_HDR_LEN;
 1233 
 1234 
 1235 /*
 1236  * Initialize a jumbo receive ring descriptor. This allocates
 1237  * a jumbo buffer from the pool managed internally by the driver.
 1238  */
 1239 static int
 1240 ti_newbuf_jumbo(sc, idx, m_old)
 1241         struct ti_softc         *sc;
 1242         int                     idx;
 1243         struct mbuf             *m_old;
 1244 {
 1245         struct mbuf             *cur, *m_new = NULL;
 1246         struct mbuf             *m[3] = {NULL, NULL, NULL};
 1247         struct ti_rx_desc_ext   *r;
 1248         vm_page_t               frame;
 1249         static int              color;
 1250                                 /* 1 extra buf to make nobufs easy*/
 1251         struct sf_buf           *sf[3] = {NULL, NULL, NULL};
 1252         int                     i;
 1253 
 1254         if (m_old != NULL) {
 1255                 m_new = m_old;
 1256                 cur = m_old->m_next;
 1257                 for (i = 0; i <= NPAYLOAD; i++){
 1258                         m[i] = cur;
 1259                         cur = cur->m_next;
 1260                 }
 1261         } else {
 1262                 /* Allocate the mbufs. */
 1263                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1264                 if (m_new == NULL) {
 1265                         printf("ti%d: mbuf allocation failed "
 1266                                "-- packet dropped!\n", sc->ti_unit);
 1267                         goto nobufs;
 1268                 }
 1269                 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
 1270                 if (m[NPAYLOAD] == NULL) {
 1271                         printf("ti%d: cluster mbuf allocation failed "
 1272                                "-- packet dropped!\n", sc->ti_unit);
 1273                         goto nobufs;
 1274                 }
 1275                 MCLGET(m[NPAYLOAD], M_DONTWAIT);
 1276                 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
 1277                         printf("ti%d: mbuf allocation failed "
 1278                                "-- packet dropped!\n", sc->ti_unit);
 1279                         goto nobufs;
 1280                 }
 1281                 m[NPAYLOAD]->m_len = MCLBYTES;
 1282 
 1283                 for (i = 0; i < NPAYLOAD; i++){
 1284                         MGET(m[i], M_DONTWAIT, MT_DATA);
 1285                         if (m[i] == NULL) {
 1286                                 printf("ti%d: mbuf allocation failed "
 1287                                        "-- packet dropped!\n", sc->ti_unit);
 1288                                 goto nobufs;
 1289                         }
 1290                         frame = vm_page_alloc(NULL, color++,
 1291                             VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
 1292                             VM_ALLOC_WIRED);
 1293                         if (frame == NULL) {
 1294                                 printf("ti%d: buffer allocation failed "
 1295                                        "-- packet dropped!\n", sc->ti_unit);
 1296                                 printf("      index %d page %d\n", idx, i);
 1297                                 goto nobufs;
 1298                         }
 1299                         sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
 1300                         if (sf[i] == NULL) {
 1301                                 vm_page_lock_queues();
 1302                                 vm_page_unwire(frame, 0);
 1303                                 vm_page_free(frame);
 1304                                 vm_page_unlock_queues();
 1305                                 printf("ti%d: buffer allocation failed "
 1306                                        "-- packet dropped!\n", sc->ti_unit);
 1307                                 printf("      index %d page %d\n", idx, i);
 1308                                 goto nobufs;
 1309                         }
 1310                 }
 1311                 for (i = 0; i < NPAYLOAD; i++){
 1312                 /* Attach the buffer to the mbuf. */
 1313                         m[i]->m_data = (void *)sf_buf_kva(sf[i]);
 1314                         m[i]->m_len = PAGE_SIZE;
 1315                         MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
 1316                             sf_buf_mext, sf[i], 0, EXT_DISPOSABLE);
 1317                         m[i]->m_next = m[i+1];
 1318                 }
 1319                 /* link the buffers to the header */
 1320                 m_new->m_next = m[0];
 1321                 m_new->m_data += ETHER_ALIGN;
 1322                 if (sc->ti_hdrsplit)
 1323                         m_new->m_len = MHLEN - ETHER_ALIGN;
 1324                 else
 1325                         m_new->m_len = HDR_LEN;
 1326                 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
 1327         }
 1328 
 1329         /* Set up the descriptor. */
 1330         r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
 1331         sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
 1332         TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t));
 1333         r->ti_len0 = m_new->m_len;
 1334 
 1335         TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t));
 1336         r->ti_len1 = PAGE_SIZE;
 1337 
 1338         TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t));
 1339         r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
 1340 
 1341         if (PAGE_SIZE == 4096) {
 1342                 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t));
 1343                 r->ti_len3 = MCLBYTES;
 1344         } else {
 1345                 r->ti_len3 = 0;
 1346         }
 1347         r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
 1348 
 1349         r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
 1350 
 1351         if (sc->ti_ifp->if_hwassist)
 1352                 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
 1353 
 1354         r->ti_idx = idx;
 1355 
 1356         return (0);
 1357 
 1358 nobufs:
 1359 
 1360         /*
 1361          * Warning! :
 1362          * This can only be called before the mbufs are strung together.
 1363          * If the mbufs are strung together, m_freem() will free the chain,
 1364          * so that the later mbufs will be freed multiple times.
 1365          */
 1366         if (m_new)
 1367                 m_freem(m_new);
 1368 
 1369         for (i = 0; i < 3; i++) {
 1370                 if (m[i])
 1371                         m_freem(m[i]);
 1372                 if (sf[i])
 1373                         sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
 1374         }
 1375         return (ENOBUFS);
 1376 }
 1377 #endif
 1378 
 1379 
 1380 
 1381 /*
 1382  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 1383  * that's 1MB or memory, which is a lot. For now, we fill only the first
 1384  * 256 ring entries and hope that our CPU is fast enough to keep up with
 1385  * the NIC.
 1386  */
 1387 static int
 1388 ti_init_rx_ring_std(sc)
 1389         struct ti_softc         *sc;
 1390 {
 1391         register int            i;
 1392         struct ti_cmd_desc      cmd;
 1393 
 1394         for (i = 0; i < TI_SSLOTS; i++) {
 1395                 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
 1396                         return (ENOBUFS);
 1397         };
 1398 
 1399         TI_UPDATE_STDPROD(sc, i - 1);
 1400         sc->ti_std = i - 1;
 1401 
 1402         return (0);
 1403 }
 1404 
 1405 static void
 1406 ti_free_rx_ring_std(sc)
 1407         struct ti_softc         *sc;
 1408 {
 1409         register int            i;
 1410 
 1411         for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
 1412                 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
 1413                         m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
 1414                         sc->ti_cdata.ti_rx_std_chain[i] = NULL;
 1415                 }
 1416                 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
 1417                     sizeof(struct ti_rx_desc));
 1418         }
 1419 }
 1420 
 1421 static int
 1422 ti_init_rx_ring_jumbo(sc)
 1423         struct ti_softc         *sc;
 1424 {
 1425         register int            i;
 1426         struct ti_cmd_desc      cmd;
 1427 
 1428         for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
 1429                 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 1430                         return (ENOBUFS);
 1431         };
 1432 
 1433         TI_UPDATE_JUMBOPROD(sc, i - 1);
 1434         sc->ti_jumbo = i - 1;
 1435 
 1436         return (0);
 1437 }
 1438 
 1439 static void
 1440 ti_free_rx_ring_jumbo(sc)
 1441         struct ti_softc         *sc;
 1442 {
 1443         register int            i;
 1444 
 1445         for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
 1446                 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
 1447                         m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
 1448                         sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
 1449                 }
 1450                 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
 1451                     sizeof(struct ti_rx_desc));
 1452         }
 1453 }
 1454 
 1455 static int
 1456 ti_init_rx_ring_mini(sc)
 1457         struct ti_softc         *sc;
 1458 {
 1459         register int            i;
 1460 
 1461         for (i = 0; i < TI_MSLOTS; i++) {
 1462                 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
 1463                         return (ENOBUFS);
 1464         };
 1465 
 1466         TI_UPDATE_MINIPROD(sc, i - 1);
 1467         sc->ti_mini = i - 1;
 1468 
 1469         return (0);
 1470 }
 1471 
 1472 static void
 1473 ti_free_rx_ring_mini(sc)
 1474         struct ti_softc         *sc;
 1475 {
 1476         register int            i;
 1477 
 1478         for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
 1479                 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
 1480                         m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
 1481                         sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
 1482                 }
 1483                 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
 1484                     sizeof(struct ti_rx_desc));
 1485         }
 1486 }
 1487 
 1488 static void
 1489 ti_free_tx_ring(sc)
 1490         struct ti_softc         *sc;
 1491 {
 1492         register int            i;
 1493 
 1494         if (sc->ti_rdata->ti_tx_ring == NULL)
 1495                 return;
 1496 
 1497         for (i = 0; i < TI_TX_RING_CNT; i++) {
 1498                 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
 1499                         m_freem(sc->ti_cdata.ti_tx_chain[i]);
 1500                         sc->ti_cdata.ti_tx_chain[i] = NULL;
 1501                 }
 1502                 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
 1503                     sizeof(struct ti_tx_desc));
 1504         }
 1505 }
 1506 
 1507 static int
 1508 ti_init_tx_ring(sc)
 1509         struct ti_softc         *sc;
 1510 {
 1511         sc->ti_txcnt = 0;
 1512         sc->ti_tx_saved_considx = 0;
 1513         CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
 1514         return (0);
 1515 }
 1516 
 1517 /*
 1518  * The Tigon 2 firmware has a new way to add/delete multicast addresses,
 1519  * but we have to support the old way too so that Tigon 1 cards will
 1520  * work.
 1521  */
 1522 static void
 1523 ti_add_mcast(sc, addr)
 1524         struct ti_softc         *sc;
 1525         struct ether_addr       *addr;
 1526 {
 1527         struct ti_cmd_desc      cmd;
 1528         u_int16_t               *m;
 1529         u_int32_t               ext[2] = {0, 0};
 1530 
 1531         m = (u_int16_t *)&addr->octet[0];
 1532 
 1533         switch (sc->ti_hwrev) {
 1534         case TI_HWREV_TIGON:
 1535                 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
 1536                 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
 1537                 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
 1538                 break;
 1539         case TI_HWREV_TIGON_II:
 1540                 ext[0] = htons(m[0]);
 1541                 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
 1542                 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
 1543                 break;
 1544         default:
 1545                 printf("ti%d: unknown hwrev\n", sc->ti_unit);
 1546                 break;
 1547         }
 1548 }
 1549 
 1550 static void
 1551 ti_del_mcast(sc, addr)
 1552         struct ti_softc         *sc;
 1553         struct ether_addr       *addr;
 1554 {
 1555         struct ti_cmd_desc      cmd;
 1556         u_int16_t               *m;
 1557         u_int32_t               ext[2] = {0, 0};
 1558 
 1559         m = (u_int16_t *)&addr->octet[0];
 1560 
 1561         switch (sc->ti_hwrev) {
 1562         case TI_HWREV_TIGON:
 1563                 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
 1564                 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
 1565                 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
 1566                 break;
 1567         case TI_HWREV_TIGON_II:
 1568                 ext[0] = htons(m[0]);
 1569                 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
 1570                 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
 1571                 break;
 1572         default:
 1573                 printf("ti%d: unknown hwrev\n", sc->ti_unit);
 1574                 break;
 1575         }
 1576 }
 1577 
 1578 /*
 1579  * Configure the Tigon's multicast address filter.
 1580  *
 1581  * The actual multicast table management is a bit of a pain, thanks to
 1582  * slight brain damage on the part of both Alteon and us. With our
 1583  * multicast code, we are only alerted when the multicast address table
 1584  * changes and at that point we only have the current list of addresses:
 1585  * we only know the current state, not the previous state, so we don't
 1586  * actually know what addresses were removed or added. The firmware has
 1587  * state, but we can't get our grubby mits on it, and there is no 'delete
 1588  * all multicast addresses' command. Hence, we have to maintain our own
 1589  * state so we know what addresses have been programmed into the NIC at
 1590  * any given time.
 1591  */
 1592 static void
 1593 ti_setmulti(sc)
 1594         struct ti_softc         *sc;
 1595 {
 1596         struct ifnet            *ifp;
 1597         struct ifmultiaddr      *ifma;
 1598         struct ti_cmd_desc      cmd;
 1599         struct ti_mc_entry      *mc;
 1600         u_int32_t               intrs;
 1601 
 1602         ifp = sc->ti_ifp;
 1603 
 1604         if (ifp->if_flags & IFF_ALLMULTI) {
 1605                 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
 1606                 return;
 1607         } else {
 1608                 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
 1609         }
 1610 
 1611         /* Disable interrupts. */
 1612         intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
 1613         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 1614 
 1615         /* First, zot all the existing filters. */
 1616         while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
 1617                 mc = SLIST_FIRST(&sc->ti_mc_listhead);
 1618                 ti_del_mcast(sc, &mc->mc_addr);
 1619                 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
 1620                 free(mc, M_DEVBUF);
 1621         }
 1622 
 1623         /* Now program new ones. */
 1624         IF_ADDR_LOCK(ifp);
 1625         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 1626                 if (ifma->ifma_addr->sa_family != AF_LINK)
 1627                         continue;
 1628                 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
 1629                 if (mc == NULL) {
 1630                         if_printf(ifp, "no memory for mcast filter entry\n");
 1631                         continue;
 1632                 }
 1633                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 1634                     (char *)&mc->mc_addr, ETHER_ADDR_LEN);
 1635                 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
 1636                 ti_add_mcast(sc, &mc->mc_addr);
 1637         }
 1638         IF_ADDR_UNLOCK(ifp);
 1639 
 1640         /* Re-enable interrupts. */
 1641         CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
 1642 }
 1643 
 1644 /*
 1645  * Check to see if the BIOS has configured us for a 64 bit slot when
 1646  * we aren't actually in one. If we detect this condition, we can work
 1647  * around it on the Tigon 2 by setting a bit in the PCI state register,
 1648  * but for the Tigon 1 we must give up and abort the interface attach.
 1649  */
 1650 static int ti_64bitslot_war(sc)
 1651         struct ti_softc         *sc;
 1652 {
 1653         if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
 1654                 CSR_WRITE_4(sc, 0x600, 0);
 1655                 CSR_WRITE_4(sc, 0x604, 0);
 1656                 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
 1657                 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
 1658                         if (sc->ti_hwrev == TI_HWREV_TIGON)
 1659                                 return (EINVAL);
 1660                         else {
 1661                                 TI_SETBIT(sc, TI_PCI_STATE,
 1662                                     TI_PCISTATE_32BIT_BUS);
 1663                                 return (0);
 1664                         }
 1665                 }
 1666         }
 1667 
 1668         return (0);
 1669 }
 1670 
 1671 /*
 1672  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 1673  * self-test results.
 1674  */
 1675 static int
 1676 ti_chipinit(sc)
 1677         struct ti_softc         *sc;
 1678 {
 1679         u_int32_t               cacheline;
 1680         u_int32_t               pci_writemax = 0;
 1681         u_int32_t               hdrsplit;
 1682 
 1683         /* Initialize link to down state. */
 1684         sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
 1685 
 1686         if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM)
 1687                 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
 1688         else
 1689                 sc->ti_ifp->if_hwassist = 0;
 1690 
 1691         /* Set endianness before we access any non-PCI registers. */
 1692 #if BYTE_ORDER == BIG_ENDIAN
 1693         CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
 1694             TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
 1695 #else
 1696         CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
 1697             TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
 1698 #endif
 1699 
 1700         /* Check the ROM failed bit to see if self-tests passed. */
 1701         if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
 1702                 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
 1703                 return (ENODEV);
 1704         }
 1705 
 1706         /* Halt the CPU. */
 1707         TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
 1708 
 1709         /* Figure out the hardware revision. */
 1710         switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
 1711         case TI_REV_TIGON_I:
 1712                 sc->ti_hwrev = TI_HWREV_TIGON;
 1713                 break;
 1714         case TI_REV_TIGON_II:
 1715                 sc->ti_hwrev = TI_HWREV_TIGON_II;
 1716                 break;
 1717         default:
 1718                 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
 1719                 return (ENODEV);
 1720         }
 1721 
 1722         /* Do special setup for Tigon 2. */
 1723         if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
 1724                 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
 1725                 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
 1726                 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
 1727         }
 1728 
 1729         /*
 1730          * We don't have firmware source for the Tigon 1, so Tigon 1 boards
 1731          * can't do header splitting.
 1732          */
 1733 #ifdef TI_JUMBO_HDRSPLIT
 1734         if (sc->ti_hwrev != TI_HWREV_TIGON)
 1735                 sc->ti_hdrsplit = 1;
 1736         else
 1737                 printf("ti%d: can't do header splitting on a Tigon I board\n",
 1738                        sc->ti_unit);
 1739 #endif /* TI_JUMBO_HDRSPLIT */
 1740 
 1741         /* Set up the PCI state register. */
 1742         CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
 1743         if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
 1744                 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
 1745         }
 1746 
 1747         /* Clear the read/write max DMA parameters. */
 1748         TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
 1749             TI_PCISTATE_READ_MAXDMA));
 1750 
 1751         /* Get cache line size. */
 1752         cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
 1753 
 1754         /*
 1755          * If the system has set enabled the PCI memory write
 1756          * and invalidate command in the command register, set
 1757          * the write max parameter accordingly. This is necessary
 1758          * to use MWI with the Tigon 2.
 1759          */
 1760         if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
 1761                 switch (cacheline) {
 1762                 case 1:
 1763                 case 4:
 1764                 case 8:
 1765                 case 16:
 1766                 case 32:
 1767                 case 64:
 1768                         break;
 1769                 default:
 1770                 /* Disable PCI memory write and invalidate. */
 1771                         if (bootverbose)
 1772                                 printf("ti%d: cache line size %d not "
 1773                                     "supported; disabling PCI MWI\n",
 1774                                     sc->ti_unit, cacheline);
 1775                         CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
 1776                             TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
 1777                         break;
 1778                 }
 1779         }
 1780 
 1781 #ifdef __brokenalpha__
 1782         /*
 1783          * From the Alteon sample driver:
 1784          * Must insure that we do not cross an 8K (bytes) boundary
 1785          * for DMA reads.  Our highest limit is 1K bytes.  This is a
 1786          * restriction on some ALPHA platforms with early revision
 1787          * 21174 PCI chipsets, such as the AlphaPC 164lx
 1788          */
 1789         TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
 1790 #else
 1791         TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
 1792 #endif
 1793 
 1794         /* This sets the min dma param all the way up (0xff). */
 1795         TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
 1796 
 1797         if (sc->ti_hdrsplit)
 1798                 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
 1799         else
 1800                 hdrsplit = 0;
 1801 
 1802         /* Configure DMA variables. */
 1803 #if BYTE_ORDER == BIG_ENDIAN
 1804         CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
 1805             TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
 1806             TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
 1807             TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
 1808 #else /* BYTE_ORDER */
 1809         CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
 1810             TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
 1811             TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
 1812 #endif /* BYTE_ORDER */
 1813 
 1814         /*
 1815          * Only allow 1 DMA channel to be active at a time.
 1816          * I don't think this is a good idea, but without it
 1817          * the firmware racks up lots of nicDmaReadRingFull
 1818          * errors.  This is not compatible with hardware checksums.
 1819          */
 1820         if (sc->ti_ifp->if_hwassist == 0)
 1821                 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
 1822 
 1823         /* Recommended settings from Tigon manual. */
 1824         CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
 1825         CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
 1826 
 1827         if (ti_64bitslot_war(sc)) {
 1828                 printf("ti%d: bios thinks we're in a 64 bit slot, "
 1829                     "but we aren't", sc->ti_unit);
 1830                 return (EINVAL);
 1831         }
 1832 
 1833         return (0);
 1834 }
 1835 
 1836 #define TI_RD_OFF(x)    offsetof(struct ti_ring_data, x)
 1837 
 1838 /*
 1839  * Initialize the general information block and firmware, and
 1840  * start the CPU(s) running.
 1841  */
 1842 static int
 1843 ti_gibinit(sc)
 1844         struct ti_softc         *sc;
 1845 {
 1846         struct ti_rcb           *rcb;
 1847         int                     i;
 1848         struct ifnet            *ifp;
 1849         uint32_t                rdphys;
 1850 
 1851         ifp = sc->ti_ifp;
 1852         rdphys = sc->ti_rdata_phys;
 1853 
 1854         /* Disable interrupts for now. */
 1855         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 1856 
 1857         /*
 1858          * Tell the chip where to find the general information block.
 1859          * While this struct could go into >4GB memory, we allocate it in a
 1860          * single slab with the other descriptors, and those don't seem to
 1861          * support being located in a 64-bit region.
 1862          */
 1863         CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
 1864         CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
 1865 
 1866         /* Load the firmware into SRAM. */
 1867         ti_loadfw(sc);
 1868 
 1869         /* Set up the contents of the general info and ring control blocks. */
 1870 
 1871         /* Set up the event ring and producer pointer. */
 1872         rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
 1873 
 1874         TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
 1875         rcb->ti_flags = 0;
 1876         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
 1877             rdphys + TI_RD_OFF(ti_ev_prodidx_r);
 1878         sc->ti_ev_prodidx.ti_idx = 0;
 1879         CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
 1880         sc->ti_ev_saved_considx = 0;
 1881 
 1882         /* Set up the command ring and producer mailbox. */
 1883         rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
 1884 
 1885         sc->ti_rdata->ti_cmd_ring =
 1886             (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
 1887         TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
 1888         rcb->ti_flags = 0;
 1889         rcb->ti_max_len = 0;
 1890         for (i = 0; i < TI_CMD_RING_CNT; i++) {
 1891                 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
 1892         }
 1893         CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
 1894         CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
 1895         sc->ti_cmd_saved_prodidx = 0;
 1896 
 1897         /*
 1898          * Assign the address of the stats refresh buffer.
 1899          * We re-use the current stats buffer for this to
 1900          * conserve memory.
 1901          */
 1902         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
 1903             rdphys + TI_RD_OFF(ti_info.ti_stats);
 1904 
 1905         /* Set up the standard receive ring. */
 1906         rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
 1907         TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
 1908         rcb->ti_max_len = TI_FRAMELEN;
 1909         rcb->ti_flags = 0;
 1910         if (sc->ti_ifp->if_hwassist)
 1911                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
 1912                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1913         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 1914 
 1915         /* Set up the jumbo receive ring. */
 1916         rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
 1917         TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
 1918 
 1919 #ifdef TI_PRIVATE_JUMBOS
 1920         rcb->ti_max_len = TI_JUMBO_FRAMELEN;
 1921         rcb->ti_flags = 0;
 1922 #else
 1923         rcb->ti_max_len = PAGE_SIZE;
 1924         rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
 1925 #endif
 1926         if (sc->ti_ifp->if_hwassist)
 1927                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
 1928                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1929         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 1930 
 1931         /*
 1932          * Set up the mini ring. Only activated on the
 1933          * Tigon 2 but the slot in the config block is
 1934          * still there on the Tigon 1.
 1935          */
 1936         rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
 1937         TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
 1938         rcb->ti_max_len = MHLEN - ETHER_ALIGN;
 1939         if (sc->ti_hwrev == TI_HWREV_TIGON)
 1940                 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
 1941         else
 1942                 rcb->ti_flags = 0;
 1943         if (sc->ti_ifp->if_hwassist)
 1944                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
 1945                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1946         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 1947 
 1948         /*
 1949          * Set up the receive return ring.
 1950          */
 1951         rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
 1952         TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
 1953         rcb->ti_flags = 0;
 1954         rcb->ti_max_len = TI_RETURN_RING_CNT;
 1955         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
 1956             rdphys + TI_RD_OFF(ti_return_prodidx_r);
 1957 
 1958         /*
 1959          * Set up the tx ring. Note: for the Tigon 2, we have the option
 1960          * of putting the transmit ring in the host's address space and
 1961          * letting the chip DMA it instead of leaving the ring in the NIC's
 1962          * memory and accessing it through the shared memory region. We
 1963          * do this for the Tigon 2, but it doesn't work on the Tigon 1,
 1964          * so we have to revert to the shared memory scheme if we detect
 1965          * a Tigon 1 chip.
 1966          */
 1967         CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
 1968         if (sc->ti_hwrev == TI_HWREV_TIGON) {
 1969                 sc->ti_rdata->ti_tx_ring_nic =
 1970                     (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
 1971         }
 1972         bzero((char *)sc->ti_rdata->ti_tx_ring,
 1973             TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
 1974         rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
 1975         if (sc->ti_hwrev == TI_HWREV_TIGON)
 1976                 rcb->ti_flags = 0;
 1977         else
 1978                 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
 1979         rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 1980         if (sc->ti_ifp->if_hwassist)
 1981                 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
 1982                      TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1983         rcb->ti_max_len = TI_TX_RING_CNT;
 1984         if (sc->ti_hwrev == TI_HWREV_TIGON)
 1985                 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
 1986         else
 1987                 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
 1988         TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
 1989             rdphys + TI_RD_OFF(ti_tx_considx_r);
 1990 
 1991         /* Set up tuneables */
 1992 #if 0
 1993         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
 1994                 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
 1995                     (sc->ti_rx_coal_ticks / 10));
 1996         else
 1997 #endif
 1998                 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
 1999         CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
 2000         CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
 2001         CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
 2002         CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
 2003         CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
 2004 
 2005         /* Turn interrupts on. */
 2006         CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
 2007         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
 2008 
 2009         /* Start CPU. */
 2010         TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
 2011 
 2012         return (0);
 2013 }
 2014 
 2015 static void
 2016 ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 2017 {
 2018         struct ti_softc *sc;
 2019 
 2020         sc = arg;
 2021         if (error || nseg != 1)
 2022                 return;
 2023 
 2024         /*
 2025          * All of the Tigon data structures need to live at <4GB.  This
 2026          * cast is fine since busdma was told about this constraint.
 2027          */
 2028         sc->ti_rdata_phys = (uint32_t)segs[0].ds_addr;
 2029         return;
 2030 }
 2031         
 2032 /*
 2033  * Probe for a Tigon chip. Check the PCI vendor and device IDs
 2034  * against our list and return its name if we find a match.
 2035  */
 2036 static int
 2037 ti_probe(dev)
 2038         device_t                dev;
 2039 {
 2040         struct ti_type          *t;
 2041 
 2042         t = ti_devs;
 2043 
 2044         while (t->ti_name != NULL) {
 2045                 if ((pci_get_vendor(dev) == t->ti_vid) &&
 2046                     (pci_get_device(dev) == t->ti_did)) {
 2047                         device_set_desc(dev, t->ti_name);
 2048                         return (BUS_PROBE_DEFAULT);
 2049                 }
 2050                 t++;
 2051         }
 2052 
 2053         return (ENXIO);
 2054 }
 2055 
 2056 static int
 2057 ti_attach(dev)
 2058         device_t                dev;
 2059 {
 2060         struct ifnet            *ifp;
 2061         struct ti_softc         *sc;
 2062         int                     unit, error = 0, rid;
 2063         u_char                  eaddr[6];
 2064 
 2065         sc = device_get_softc(dev);
 2066         unit = device_get_unit(dev);
 2067         sc->ti_unit = unit;
 2068 
 2069         mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 2070             MTX_DEF | MTX_RECURSE);
 2071         ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
 2072         ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
 2073         if (ifp == NULL) {
 2074                 printf("ti%d: can not if_alloc()\n", sc->ti_unit);
 2075                 error = ENOSPC;
 2076                 goto fail;
 2077         }
 2078         sc->ti_ifp->if_capabilities = IFCAP_HWCSUM |
 2079             IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
 2080         sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
 2081 
 2082         /*
 2083          * Map control/status registers.
 2084          */
 2085         pci_enable_busmaster(dev);
 2086 
 2087         rid = TI_PCI_LOMEM;
 2088         sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 2089             RF_ACTIVE|PCI_RF_DENSE);
 2090 
 2091         if (sc->ti_res == NULL) {
 2092                 printf ("ti%d: couldn't map memory\n", unit);
 2093                 error = ENXIO;
 2094                 goto fail;
 2095         }
 2096 
 2097         sc->ti_btag = rman_get_bustag(sc->ti_res);
 2098         sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
 2099         sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
 2100 
 2101         /* Allocate interrupt */
 2102         rid = 0;
 2103 
 2104         sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 2105             RF_SHAREABLE | RF_ACTIVE);
 2106 
 2107         if (sc->ti_irq == NULL) {
 2108                 printf("ti%d: couldn't map interrupt\n", unit);
 2109                 error = ENXIO;
 2110                 goto fail;
 2111         }
 2112 
 2113         if (ti_chipinit(sc)) {
 2114                 printf("ti%d: chip initialization failed\n", sc->ti_unit);
 2115                 error = ENXIO;
 2116                 goto fail;
 2117         }
 2118 
 2119         /* Zero out the NIC's on-board SRAM. */
 2120         ti_mem(sc, 0x2000, 0x100000 - 0x2000,  NULL);
 2121 
 2122         /* Init again -- zeroing memory may have clobbered some registers. */
 2123         if (ti_chipinit(sc)) {
 2124                 printf("ti%d: chip initialization failed\n", sc->ti_unit);
 2125                 error = ENXIO;
 2126                 goto fail;
 2127         }
 2128 
 2129         /*
 2130          * Get station address from the EEPROM. Note: the manual states
 2131          * that the MAC address is at offset 0x8c, however the data is
 2132          * stored as two longwords (since that's how it's loaded into
 2133          * the NIC). This means the MAC address is actually preceded
 2134          * by two zero bytes. We need to skip over those.
 2135          */
 2136         if (ti_read_eeprom(sc, eaddr,
 2137                                 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
 2138                 printf("ti%d: failed to read station address\n", unit);
 2139                 error = ENXIO;
 2140                 goto fail;
 2141         }
 2142 
 2143         /* Allocate the general information block and ring buffers. */
 2144         if (bus_dma_tag_create(NULL,                    /* parent */
 2145                                 1, 0,                   /* algnmnt, boundary */
 2146                                 BUS_SPACE_MAXADDR,      /* lowaddr */
 2147                                 BUS_SPACE_MAXADDR,      /* highaddr */
 2148                                 NULL, NULL,             /* filter, filterarg */
 2149                                 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
 2150                                 0,                      /* nsegments */
 2151                                 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
 2152                                 0,                      /* flags */
 2153                                 NULL, NULL,             /* lockfunc, lockarg */
 2154                                 &sc->ti_parent_dmat) != 0) {
 2155                 printf("ti%d: Failed to allocate parent dmat\n", sc->ti_unit);
 2156                 error = ENOMEM;
 2157                 goto fail;
 2158         }
 2159 
 2160         if (bus_dma_tag_create(sc->ti_parent_dmat,      /* parent */
 2161                                 PAGE_SIZE, 0,           /* algnmnt, boundary */
 2162                                 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
 2163                                 BUS_SPACE_MAXADDR,      /* highaddr */
 2164                                 NULL, NULL,             /* filter, filterarg */
 2165                                 sizeof(struct ti_ring_data),    /* maxsize */
 2166                                 1,                      /* nsegments */
 2167                                 sizeof(struct ti_ring_data),    /* maxsegsize */
 2168                                 0,                      /* flags */
 2169                                 NULL, NULL,             /* lockfunc, lockarg */
 2170                                 &sc->ti_rdata_dmat) != 0) {
 2171                 printf("ti%d: Failed to allocate rdata dmat\n", sc->ti_unit);
 2172                 error = ENOMEM;
 2173                 goto fail;
 2174         }
 2175 
 2176         if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
 2177                              BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) {
 2178                 printf("ti%d: Failed to allocate rdata memory\n", sc->ti_unit);
 2179                 error = ENOMEM;
 2180                 goto fail;
 2181         }
 2182 
 2183         if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
 2184                             sc->ti_rdata, sizeof(struct ti_ring_data),
 2185                             ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
 2186                 printf("ti%d: Failed to load rdata segments\n", sc->ti_unit);
 2187                 error = ENOMEM;
 2188                 goto fail;
 2189         }
 2190 
 2191         bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
 2192 
 2193         /* Try to allocate memory for jumbo buffers. */
 2194 #ifdef TI_PRIVATE_JUMBOS
 2195         if (ti_alloc_jumbo_mem(sc)) {
 2196                 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
 2197                 error = ENXIO;
 2198                 goto fail;
 2199         }
 2200 #endif
 2201 
 2202         /*
 2203          * We really need a better way to tell a 1000baseTX card
 2204          * from a 1000baseSX one, since in theory there could be
 2205          * OEMed 1000baseTX cards from lame vendors who aren't
 2206          * clever enough to change the PCI ID. For the moment
 2207          * though, the AceNIC is the only copper card available.
 2208          */
 2209         if (pci_get_vendor(dev) == ALT_VENDORID &&
 2210             pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
 2211                 sc->ti_copper = 1;
 2212         /* Ok, it's not the only copper card available. */
 2213         if (pci_get_vendor(dev) == NG_VENDORID &&
 2214             pci_get_device(dev) == NG_DEVICEID_GA620T)
 2215                 sc->ti_copper = 1;
 2216 
 2217         /* Set default tuneable values. */
 2218         sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
 2219 #if 0
 2220         sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
 2221 #endif
 2222         sc->ti_rx_coal_ticks = 170;
 2223         sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
 2224         sc->ti_rx_max_coal_bds = 64;
 2225 #if 0
 2226         sc->ti_tx_max_coal_bds = 128;
 2227 #endif
 2228         sc->ti_tx_max_coal_bds = 32;
 2229         sc->ti_tx_buf_ratio = 21;
 2230 
 2231         /* Set up ifnet structure */
 2232         ifp->if_softc = sc;
 2233         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 2234         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
 2235             IFF_NEEDSGIANT;
 2236         tis[unit] = sc;
 2237         ifp->if_ioctl = ti_ioctl;
 2238         ifp->if_start = ti_start;
 2239         ifp->if_watchdog = ti_watchdog;
 2240         ifp->if_init = ti_init;
 2241         ifp->if_mtu = ETHERMTU;
 2242         ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
 2243 
 2244         /* Set up ifmedia support. */
 2245         if (sc->ti_copper) {
 2246                 /*
 2247                  * Copper cards allow manual 10/100 mode selection,
 2248                  * but not manual 1000baseTX mode selection. Why?
 2249                  * Becuase currently there's no way to specify the
 2250                  * master/slave setting through the firmware interface,
 2251                  * so Alteon decided to just bag it and handle it
 2252                  * via autonegotiation.
 2253                  */
 2254                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 2255                 ifmedia_add(&sc->ifmedia,
 2256                     IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
 2257                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
 2258                 ifmedia_add(&sc->ifmedia,
 2259                     IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
 2260                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
 2261                 ifmedia_add(&sc->ifmedia,
 2262                     IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
 2263         } else {
 2264                 /* Fiber cards don't support 10/100 modes. */
 2265                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
 2266                 ifmedia_add(&sc->ifmedia,
 2267                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 2268         }
 2269         ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 2270         ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
 2271 
 2272         /*
 2273          * We're assuming here that card initialization is a sequential
 2274          * thing.  If it isn't, multiple cards probing at the same time
 2275          * could stomp on the list of softcs here.
 2276          */
 2277 
 2278         /* Register the device */
 2279         sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
 2280                            0600, "ti%d", sc->ti_unit);
 2281         sc->dev->si_drv1 = sc;
 2282 
 2283         /*
 2284          * Call MI attach routine.
 2285          */
 2286         ether_ifattach(ifp, eaddr);
 2287 
 2288         /* Hook interrupt last to avoid having to lock softc */
 2289         error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
 2290            ti_intr, sc, &sc->ti_intrhand);
 2291 
 2292         if (error) {
 2293                 printf("ti%d: couldn't set up irq\n", unit);
 2294                 ether_ifdetach(ifp);
 2295                 goto fail;
 2296         }
 2297 
 2298 fail:
 2299         if (sc && error)
 2300                 ti_detach(dev);
 2301 
 2302         return (error);
 2303 }
 2304 
 2305 /*
 2306  * Shutdown hardware and free up resources. This can be called any
 2307  * time after the mutex has been initialized. It is called in both
 2308  * the error case in attach and the normal detach case so it needs
 2309  * to be careful about only freeing resources that have actually been
 2310  * allocated.
 2311  */
 2312 static int
 2313 ti_detach(dev)
 2314         device_t                dev;
 2315 {
 2316         struct ti_softc         *sc;
 2317         struct ifnet            *ifp;
 2318 
 2319         sc = device_get_softc(dev);
 2320         if (sc->dev)
 2321                 destroy_dev(sc->dev);
 2322         KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
 2323         TI_LOCK(sc);
 2324         ifp = sc->ti_ifp;
 2325 
 2326         /* These should only be active if attach succeeded */
 2327         if (device_is_attached(dev)) {
 2328                 ti_stop(sc);
 2329                 ether_ifdetach(ifp);
 2330                 bus_generic_detach(dev);
 2331         }
 2332         if (ifp)
 2333                 if_free(ifp);
 2334         ifmedia_removeall(&sc->ifmedia);
 2335 
 2336         if (sc->ti_rdata)
 2337                 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
 2338                                 sc->ti_rdata_dmamap);
 2339         if (sc->ti_rdata_dmat)
 2340                 bus_dma_tag_destroy(sc->ti_rdata_dmat);
 2341         if (sc->ti_parent_dmat)
 2342                 bus_dma_tag_destroy(sc->ti_parent_dmat);
 2343         if (sc->ti_intrhand)
 2344                 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
 2345         if (sc->ti_irq)
 2346                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
 2347         if (sc->ti_res) {
 2348                 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
 2349                     sc->ti_res);
 2350         }
 2351 
 2352 #ifdef TI_PRIVATE_JUMBOS
 2353         if (sc->ti_cdata.ti_jumbo_buf)
 2354                 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
 2355 #endif
 2356         if (sc->ti_rdata)
 2357                 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
 2358 
 2359         TI_UNLOCK(sc);
 2360         mtx_destroy(&sc->ti_mtx);
 2361 
 2362         return (0);
 2363 }
 2364 
 2365 #ifdef TI_JUMBO_HDRSPLIT
 2366 /*
 2367  * If hdr_len is 0, that means that header splitting wasn't done on
 2368  * this packet for some reason.  The two most likely reasons are that
 2369  * the protocol isn't a supported protocol for splitting, or this
 2370  * packet had a fragment offset that wasn't 0.
 2371  *
 2372  * The header length, if it is non-zero, will always be the length of
 2373  * the headers on the packet, but that length could be longer than the
 2374  * first mbuf.  So we take the minimum of the two as the actual
 2375  * length.
 2376  */
 2377 static __inline void
 2378 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
 2379 {
 2380         int i = 0;
 2381         int lengths[4] = {0, 0, 0, 0};
 2382         struct mbuf *m, *mp;
 2383 
 2384         if (hdr_len != 0)
 2385                 top->m_len = min(hdr_len, top->m_len);
 2386         pkt_len -= top->m_len;
 2387         lengths[i++] = top->m_len;
 2388 
 2389         mp = top;
 2390         for (m = top->m_next; m && pkt_len; m = m->m_next) {
 2391                 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
 2392                 pkt_len -= m->m_len;
 2393                 lengths[i++] = m->m_len;
 2394                 mp = m;
 2395         }
 2396 
 2397 #if 0
 2398         if (hdr_len != 0)
 2399                 printf("got split packet: ");
 2400         else
 2401                 printf("got non-split packet: ");
 2402 
 2403         printf("%d,%d,%d,%d = %d\n", lengths[0],
 2404             lengths[1], lengths[2], lengths[3],
 2405             lengths[0] + lengths[1] + lengths[2] +
 2406             lengths[3]);
 2407 #endif
 2408 
 2409         if (pkt_len)
 2410                 panic("header splitting didn't");
 2411 
 2412         if (m) {
 2413                 m_freem(m);
 2414                 mp->m_next = NULL;
 2415 
 2416         }
 2417         if (mp->m_next != NULL)
 2418                 panic("ti_hdr_split: last mbuf in chain should be null");
 2419 }
 2420 #endif /* TI_JUMBO_HDRSPLIT */
 2421 
 2422 /*
 2423  * Frame reception handling. This is called if there's a frame
 2424  * on the receive return list.
 2425  *
 2426  * Note: we have to be able to handle three possibilities here:
 2427  * 1) the frame is from the mini receive ring (can only happen)
 2428  *    on Tigon 2 boards)
 2429  * 2) the frame is from the jumbo recieve ring
 2430  * 3) the frame is from the standard receive ring
 2431  */
 2432 
 2433 static void
 2434 ti_rxeof(sc)
 2435         struct ti_softc         *sc;
 2436 {
 2437         struct ifnet            *ifp;
 2438         struct ti_cmd_desc      cmd;
 2439 
 2440         TI_LOCK_ASSERT(sc);
 2441 
 2442         ifp = sc->ti_ifp;
 2443 
 2444         while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
 2445                 struct ti_rx_desc       *cur_rx;
 2446                 u_int32_t               rxidx;
 2447                 struct mbuf             *m = NULL;
 2448                 u_int16_t               vlan_tag = 0;
 2449                 int                     have_tag = 0;
 2450 
 2451                 cur_rx =
 2452                     &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
 2453                 rxidx = cur_rx->ti_idx;
 2454                 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
 2455 
 2456                 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
 2457                         have_tag = 1;
 2458                         vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
 2459                 }
 2460 
 2461                 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
 2462 
 2463                         TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
 2464                         m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
 2465                         sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
 2466                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
 2467                                 ifp->if_ierrors++;
 2468                                 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
 2469                                 continue;
 2470                         }
 2471                         if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
 2472                                 ifp->if_ierrors++;
 2473                                 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
 2474                                 continue;
 2475                         }
 2476 #ifdef TI_PRIVATE_JUMBOS
 2477                         m->m_len = cur_rx->ti_len;
 2478 #else /* TI_PRIVATE_JUMBOS */
 2479 #ifdef TI_JUMBO_HDRSPLIT
 2480                         if (sc->ti_hdrsplit)
 2481                                 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
 2482                                              cur_rx->ti_len, rxidx);
 2483                         else
 2484 #endif /* TI_JUMBO_HDRSPLIT */
 2485                         m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
 2486 #endif /* TI_PRIVATE_JUMBOS */
 2487                 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
 2488                         TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
 2489                         m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
 2490                         sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
 2491                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
 2492                                 ifp->if_ierrors++;
 2493                                 ti_newbuf_mini(sc, sc->ti_mini, m);
 2494                                 continue;
 2495                         }
 2496                         if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
 2497                                 ifp->if_ierrors++;
 2498                                 ti_newbuf_mini(sc, sc->ti_mini, m);
 2499                                 continue;
 2500                         }
 2501                         m->m_len = cur_rx->ti_len;
 2502                 } else {
 2503                         TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
 2504                         m = sc->ti_cdata.ti_rx_std_chain[rxidx];
 2505                         sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
 2506                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
 2507                                 ifp->if_ierrors++;
 2508                                 ti_newbuf_std(sc, sc->ti_std, m);
 2509                                 continue;
 2510                         }
 2511                         if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
 2512                                 ifp->if_ierrors++;
 2513                                 ti_newbuf_std(sc, sc->ti_std, m);
 2514                                 continue;
 2515                         }
 2516                         m->m_len = cur_rx->ti_len;
 2517                 }
 2518 
 2519                 m->m_pkthdr.len = cur_rx->ti_len;
 2520                 ifp->if_ipackets++;
 2521                 m->m_pkthdr.rcvif = ifp;
 2522 
 2523                 if (ifp->if_hwassist) {
 2524                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
 2525                             CSUM_DATA_VALID;
 2526                         if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
 2527                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
 2528                         m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
 2529                 }
 2530 
 2531                 /*
 2532                  * If we received a packet with a vlan tag,
 2533                  * tag it before passing the packet upward.
 2534                  */
 2535                 if (have_tag) {
 2536                         VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
 2537                         if (m == NULL)
 2538                                 continue;
 2539                 }
 2540                 TI_UNLOCK(sc);
 2541                 (*ifp->if_input)(ifp, m);
 2542                 TI_LOCK(sc);
 2543         }
 2544 
 2545         /* Only necessary on the Tigon 1. */
 2546         if (sc->ti_hwrev == TI_HWREV_TIGON)
 2547                 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
 2548                     sc->ti_rx_saved_considx);
 2549 
 2550         TI_UPDATE_STDPROD(sc, sc->ti_std);
 2551         TI_UPDATE_MINIPROD(sc, sc->ti_mini);
 2552         TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
 2553 }
 2554 
 2555 static void
 2556 ti_txeof(sc)
 2557         struct ti_softc         *sc;
 2558 {
 2559         struct ti_tx_desc       *cur_tx = NULL;
 2560         struct ifnet            *ifp;
 2561 
 2562         ifp = sc->ti_ifp;
 2563 
 2564         /*
 2565          * Go through our tx ring and free mbufs for those
 2566          * frames that have been sent.
 2567          */
 2568         while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
 2569                 u_int32_t               idx = 0;
 2570 
 2571                 idx = sc->ti_tx_saved_considx;
 2572                 if (sc->ti_hwrev == TI_HWREV_TIGON) {
 2573                         if (idx > 383)
 2574                                 CSR_WRITE_4(sc, TI_WINBASE,
 2575                                     TI_TX_RING_BASE + 6144);
 2576                         else if (idx > 255)
 2577                                 CSR_WRITE_4(sc, TI_WINBASE,
 2578                                     TI_TX_RING_BASE + 4096);
 2579                         else if (idx > 127)
 2580                                 CSR_WRITE_4(sc, TI_WINBASE,
 2581                                     TI_TX_RING_BASE + 2048);
 2582                         else
 2583                                 CSR_WRITE_4(sc, TI_WINBASE,
 2584                                     TI_TX_RING_BASE);
 2585                         cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
 2586                 } else
 2587                         cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
 2588                 if (cur_tx->ti_flags & TI_BDFLAG_END)
 2589                         ifp->if_opackets++;
 2590                 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
 2591                         m_freem(sc->ti_cdata.ti_tx_chain[idx]);
 2592                         sc->ti_cdata.ti_tx_chain[idx] = NULL;
 2593                 }
 2594                 sc->ti_txcnt--;
 2595                 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
 2596                 ifp->if_timer = 0;
 2597         }
 2598 
 2599         if (cur_tx != NULL)
 2600                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 2601 }
 2602 
 2603 static void
 2604 ti_intr(xsc)
 2605         void                    *xsc;
 2606 {
 2607         struct ti_softc         *sc;
 2608         struct ifnet            *ifp;
 2609 
 2610         sc = xsc;
 2611         TI_LOCK(sc);
 2612         ifp = sc->ti_ifp;
 2613 
 2614 /*#ifdef notdef*/
 2615         /* Avoid this for now -- checking this register is expensive. */
 2616         /* Make sure this is really our interrupt. */
 2617         if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
 2618                 TI_UNLOCK(sc);
 2619                 return;
 2620         }
 2621 /*#endif*/
 2622 
 2623         /* Ack interrupt and stop others from occuring. */
 2624         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 2625 
 2626         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 2627                 /* Check RX return ring producer/consumer */
 2628                 ti_rxeof(sc);
 2629 
 2630                 /* Check TX ring producer/consumer */
 2631                 ti_txeof(sc);
 2632         }
 2633 
 2634         ti_handle_events(sc);
 2635 
 2636         /* Re-enable interrupts. */
 2637         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
 2638 
 2639         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
 2640             ifp->if_snd.ifq_head != NULL)
 2641                 ti_start(ifp);
 2642 
 2643         TI_UNLOCK(sc);
 2644 }
 2645 
 2646 static void
 2647 ti_stats_update(sc)
 2648         struct ti_softc         *sc;
 2649 {
 2650         struct ifnet            *ifp;
 2651 
 2652         ifp = sc->ti_ifp;
 2653 
 2654         ifp->if_collisions +=
 2655            (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
 2656            sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
 2657            sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
 2658            sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
 2659            ifp->if_collisions;
 2660 }
 2661 
 2662 /*
 2663  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
 2664  * pointers to descriptors.
 2665  */
 2666 static int
 2667 ti_encap(sc, m_head, txidx)
 2668         struct ti_softc         *sc;
 2669         struct mbuf             *m_head;
 2670         u_int32_t               *txidx;
 2671 {
 2672         struct ti_tx_desc       *f = NULL;
 2673         struct mbuf             *m;
 2674         u_int32_t               frag, cur, cnt = 0;
 2675         u_int16_t               csum_flags = 0;
 2676         struct m_tag            *mtag;
 2677 
 2678         m = m_head;
 2679         cur = frag = *txidx;
 2680 
 2681         if (m_head->m_pkthdr.csum_flags) {
 2682                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
 2683                         csum_flags |= TI_BDFLAG_IP_CKSUM;
 2684                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
 2685                         csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
 2686                 if (m_head->m_flags & M_LASTFRAG)
 2687                         csum_flags |= TI_BDFLAG_IP_FRAG_END;
 2688                 else if (m_head->m_flags & M_FRAG)
 2689                         csum_flags |= TI_BDFLAG_IP_FRAG;
 2690         }
 2691 
 2692         mtag = VLAN_OUTPUT_TAG(sc->ti_ifp, m);
 2693 
 2694         /*
 2695          * Start packing the mbufs in this chain into
 2696          * the fragment pointers. Stop when we run out
 2697          * of fragments or hit the end of the mbuf chain.
 2698          */
 2699         for (m = m_head; m != NULL; m = m->m_next) {
 2700                 if (m->m_len != 0) {
 2701                         if (sc->ti_hwrev == TI_HWREV_TIGON) {
 2702                                 if (frag > 383)
 2703                                         CSR_WRITE_4(sc, TI_WINBASE,
 2704                                             TI_TX_RING_BASE + 6144);
 2705                                 else if (frag > 255)
 2706                                         CSR_WRITE_4(sc, TI_WINBASE,
 2707                                             TI_TX_RING_BASE + 4096);
 2708                                 else if (frag > 127)
 2709                                         CSR_WRITE_4(sc, TI_WINBASE,
 2710                                             TI_TX_RING_BASE + 2048);
 2711                                 else
 2712                                         CSR_WRITE_4(sc, TI_WINBASE,
 2713                                             TI_TX_RING_BASE);
 2714                                 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
 2715                         } else
 2716                                 f = &sc->ti_rdata->ti_tx_ring[frag];
 2717                         if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
 2718                                 break;
 2719                         TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
 2720                         f->ti_len = m->m_len;
 2721                         f->ti_flags = csum_flags;
 2722 
 2723                         if (mtag != NULL) {
 2724                                 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
 2725                                 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff;
 2726                         } else {
 2727                                 f->ti_vlan_tag = 0;
 2728                         }
 2729 
 2730                         /*
 2731                          * Sanity check: avoid coming within 16 descriptors
 2732                          * of the end of the ring.
 2733                          */
 2734                         if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
 2735                                 return (ENOBUFS);
 2736                         cur = frag;
 2737                         TI_INC(frag, TI_TX_RING_CNT);
 2738                         cnt++;
 2739                 }
 2740         }
 2741 
 2742         if (m != NULL)
 2743                 return (ENOBUFS);
 2744 
 2745         if (frag == sc->ti_tx_saved_considx)
 2746                 return (ENOBUFS);
 2747 
 2748         if (sc->ti_hwrev == TI_HWREV_TIGON)
 2749                 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
 2750                     TI_BDFLAG_END;
 2751         else
 2752                 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
 2753         sc->ti_cdata.ti_tx_chain[cur] = m_head;
 2754         sc->ti_txcnt += cnt;
 2755 
 2756         *txidx = frag;
 2757 
 2758         return (0);
 2759 }
 2760 
 2761 /*
 2762  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 2763  * to the mbuf data regions directly in the transmit descriptors.
 2764  */
 2765 static void
 2766 ti_start(ifp)
 2767         struct ifnet            *ifp;
 2768 {
 2769         struct ti_softc         *sc;
 2770         struct mbuf             *m_head = NULL;
 2771         u_int32_t               prodidx = 0;
 2772 
 2773         sc = ifp->if_softc;
 2774         TI_LOCK(sc);
 2775 
 2776         prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
 2777 
 2778         while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
 2779                 IF_DEQUEUE(&ifp->if_snd, m_head);
 2780                 if (m_head == NULL)
 2781                         break;
 2782 
 2783                 /*
 2784                  * XXX
 2785                  * safety overkill.  If this is a fragmented packet chain
 2786                  * with delayed TCP/UDP checksums, then only encapsulate
 2787                  * it if we have enough descriptors to handle the entire
 2788                  * chain at once.
 2789                  * (paranoia -- may not actually be needed)
 2790                  */
 2791                 if (m_head->m_flags & M_FIRSTFRAG &&
 2792                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
 2793                         if ((TI_TX_RING_CNT - sc->ti_txcnt) <
 2794                             m_head->m_pkthdr.csum_data + 16) {
 2795                                 IF_PREPEND(&ifp->if_snd, m_head);
 2796                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 2797                                 break;
 2798                         }
 2799                 }
 2800 
 2801                 /*
 2802                  * Pack the data into the transmit ring. If we
 2803                  * don't have room, set the OACTIVE flag and wait
 2804                  * for the NIC to drain the ring.
 2805                  */
 2806                 if (ti_encap(sc, m_head, &prodidx)) {
 2807                         IF_PREPEND(&ifp->if_snd, m_head);
 2808                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 2809                         break;
 2810                 }
 2811 
 2812                 /*
 2813                  * If there's a BPF listener, bounce a copy of this frame
 2814                  * to him.
 2815                  */
 2816                 BPF_MTAP(ifp, m_head);
 2817         }
 2818 
 2819         /* Transmit */
 2820         CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
 2821 
 2822         /*
 2823          * Set a timeout in case the chip goes out to lunch.
 2824          */
 2825         ifp->if_timer = 5;
 2826         TI_UNLOCK(sc);
 2827 }
 2828 
 2829 static void
 2830 ti_init(xsc)
 2831         void                    *xsc;
 2832 {
 2833         struct ti_softc         *sc = xsc;
 2834 
 2835         /* Cancel pending I/O and flush buffers. */
 2836         ti_stop(sc);
 2837 
 2838         TI_LOCK(sc);
 2839         /* Init the gen info block, ring control blocks and firmware. */
 2840         if (ti_gibinit(sc)) {
 2841                 printf("ti%d: initialization failure\n", sc->ti_unit);
 2842                 TI_UNLOCK(sc);
 2843                 return;
 2844         }
 2845 
 2846         TI_UNLOCK(sc);
 2847 }
 2848 
 2849 static void ti_init2(sc)
 2850         struct ti_softc         *sc;
 2851 {
 2852         struct ti_cmd_desc      cmd;
 2853         struct ifnet            *ifp;
 2854         u_int16_t               *m;
 2855         struct ifmedia          *ifm;
 2856         int                     tmp;
 2857 
 2858         ifp = sc->ti_ifp;
 2859 
 2860         /* Specify MTU and interface index. */
 2861         CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
 2862         CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
 2863             ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
 2864         TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
 2865 
 2866         /* Load our MAC address. */
 2867         m = (u_int16_t *)&IFP2ENADDR(sc->ti_ifp)[0];
 2868         CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
 2869         CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
 2870         TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
 2871 
 2872         /* Enable or disable promiscuous mode as needed. */
 2873         if (ifp->if_flags & IFF_PROMISC) {
 2874                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
 2875         } else {
 2876                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
 2877         }
 2878 
 2879         /* Program multicast filter. */
 2880         ti_setmulti(sc);
 2881 
 2882         /*
 2883          * If this is a Tigon 1, we should tell the
 2884          * firmware to use software packet filtering.
 2885          */
 2886         if (sc->ti_hwrev == TI_HWREV_TIGON) {
 2887                 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
 2888         }
 2889 
 2890         /* Init RX ring. */
 2891         ti_init_rx_ring_std(sc);
 2892 
 2893         /* Init jumbo RX ring. */
 2894         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
 2895                 ti_init_rx_ring_jumbo(sc);
 2896 
 2897         /*
 2898          * If this is a Tigon 2, we can also configure the
 2899          * mini ring.
 2900          */
 2901         if (sc->ti_hwrev == TI_HWREV_TIGON_II)
 2902                 ti_init_rx_ring_mini(sc);
 2903 
 2904         CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
 2905         sc->ti_rx_saved_considx = 0;
 2906 
 2907         /* Init TX ring. */
 2908         ti_init_tx_ring(sc);
 2909 
 2910         /* Tell firmware we're alive. */
 2911         TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
 2912 
 2913         /* Enable host interrupts. */
 2914         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
 2915 
 2916         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 2917         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 2918 
 2919         /*
 2920          * Make sure to set media properly. We have to do this
 2921          * here since we have to issue commands in order to set
 2922          * the link negotiation and we can't issue commands until
 2923          * the firmware is running.
 2924          */
 2925         ifm = &sc->ifmedia;
 2926         tmp = ifm->ifm_media;
 2927         ifm->ifm_media = ifm->ifm_cur->ifm_media;
 2928         ti_ifmedia_upd(ifp);
 2929         ifm->ifm_media = tmp;
 2930 }
 2931 
 2932 /*
 2933  * Set media options.
 2934  */
 2935 static int
 2936 ti_ifmedia_upd(ifp)
 2937         struct ifnet            *ifp;
 2938 {
 2939         struct ti_softc         *sc;
 2940         struct ifmedia          *ifm;
 2941         struct ti_cmd_desc      cmd;
 2942         u_int32_t               flowctl;
 2943 
 2944         sc = ifp->if_softc;
 2945         ifm = &sc->ifmedia;
 2946 
 2947         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 2948                 return (EINVAL);
 2949 
 2950         flowctl = 0;
 2951 
 2952         switch (IFM_SUBTYPE(ifm->ifm_media)) {
 2953         case IFM_AUTO:
 2954                 /*
 2955                  * Transmit flow control doesn't work on the Tigon 1.
 2956                  */
 2957                 flowctl = TI_GLNK_RX_FLOWCTL_Y;
 2958 
 2959                 /*
 2960                  * Transmit flow control can also cause problems on the
 2961                  * Tigon 2, apparantly with both the copper and fiber
 2962                  * boards.  The symptom is that the interface will just
 2963                  * hang.  This was reproduced with Alteon 180 switches.
 2964                  */
 2965 #if 0
 2966                 if (sc->ti_hwrev != TI_HWREV_TIGON)
 2967                         flowctl |= TI_GLNK_TX_FLOWCTL_Y;
 2968 #endif
 2969 
 2970                 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
 2971                     TI_GLNK_FULL_DUPLEX| flowctl |
 2972                     TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
 2973 
 2974                 flowctl = TI_LNK_RX_FLOWCTL_Y;
 2975 #if 0
 2976                 if (sc->ti_hwrev != TI_HWREV_TIGON)
 2977                         flowctl |= TI_LNK_TX_FLOWCTL_Y;
 2978 #endif
 2979 
 2980                 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
 2981                     TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
 2982                     TI_LNK_AUTONEGENB|TI_LNK_ENB);
 2983                 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
 2984                     TI_CMD_CODE_NEGOTIATE_BOTH, 0);
 2985                 break;
 2986         case IFM_1000_SX:
 2987         case IFM_1000_T:
 2988                 flowctl = TI_GLNK_RX_FLOWCTL_Y;
 2989 #if 0
 2990                 if (sc->ti_hwrev != TI_HWREV_TIGON)
 2991                         flowctl |= TI_GLNK_TX_FLOWCTL_Y;
 2992 #endif
 2993 
 2994                 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
 2995                     flowctl |TI_GLNK_ENB);
 2996                 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
 2997                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
 2998                         TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
 2999                 }
 3000                 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
 3001                     TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
 3002                 break;
 3003         case IFM_100_FX:
 3004         case IFM_10_FL:
 3005         case IFM_100_TX:
 3006         case IFM_10_T:
 3007                 flowctl = TI_LNK_RX_FLOWCTL_Y;
 3008 #if 0
 3009                 if (sc->ti_hwrev != TI_HWREV_TIGON)
 3010                         flowctl |= TI_LNK_TX_FLOWCTL_Y;
 3011 #endif
 3012 
 3013                 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
 3014                 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
 3015                 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
 3016                     IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
 3017                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
 3018                 } else {
 3019                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
 3020                 }
 3021                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
 3022                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
 3023                 } else {
 3024                         TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
 3025                 }
 3026                 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
 3027                     TI_CMD_CODE_NEGOTIATE_10_100, 0);
 3028                 break;
 3029         }
 3030 
 3031         return (0);
 3032 }
 3033 
 3034 /*
 3035  * Report current media status.
 3036  */
 3037 static void
 3038 ti_ifmedia_sts(ifp, ifmr)
 3039         struct ifnet            *ifp;
 3040         struct ifmediareq       *ifmr;
 3041 {
 3042         struct ti_softc         *sc;
 3043         u_int32_t               media = 0;
 3044 
 3045         sc = ifp->if_softc;
 3046 
 3047         ifmr->ifm_status = IFM_AVALID;
 3048         ifmr->ifm_active = IFM_ETHER;
 3049 
 3050         if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
 3051                 return;
 3052 
 3053         ifmr->ifm_status |= IFM_ACTIVE;
 3054 
 3055         if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
 3056                 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
 3057                 if (sc->ti_copper)
 3058                         ifmr->ifm_active |= IFM_1000_T;
 3059                 else
 3060                         ifmr->ifm_active |= IFM_1000_SX;
 3061                 if (media & TI_GLNK_FULL_DUPLEX)
 3062                         ifmr->ifm_active |= IFM_FDX;
 3063                 else
 3064                         ifmr->ifm_active |= IFM_HDX;
 3065         } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
 3066                 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
 3067                 if (sc->ti_copper) {
 3068                         if (media & TI_LNK_100MB)
 3069                                 ifmr->ifm_active |= IFM_100_TX;
 3070                         if (media & TI_LNK_10MB)
 3071                                 ifmr->ifm_active |= IFM_10_T;
 3072                 } else {
 3073                         if (media & TI_LNK_100MB)
 3074                                 ifmr->ifm_active |= IFM_100_FX;
 3075                         if (media & TI_LNK_10MB)
 3076                                 ifmr->ifm_active |= IFM_10_FL;
 3077                 }
 3078                 if (media & TI_LNK_FULL_DUPLEX)
 3079                         ifmr->ifm_active |= IFM_FDX;
 3080                 if (media & TI_LNK_HALF_DUPLEX)
 3081                         ifmr->ifm_active |= IFM_HDX;
 3082         }
 3083 }
 3084 
 3085 static int
 3086 ti_ioctl(ifp, command, data)
 3087         struct ifnet            *ifp;
 3088         u_long                  command;
 3089         caddr_t                 data;
 3090 {
 3091         struct ti_softc         *sc = ifp->if_softc;
 3092         struct ifreq            *ifr = (struct ifreq *) data;
 3093         int                     mask, error = 0;
 3094         struct ti_cmd_desc      cmd;
 3095 
 3096         TI_LOCK(sc);
 3097 
 3098         switch (command) {
 3099         case SIOCSIFMTU:
 3100                 if (ifr->ifr_mtu > TI_JUMBO_MTU)
 3101                         error = EINVAL;
 3102                 else {
 3103                         ifp->if_mtu = ifr->ifr_mtu;
 3104                         ti_init(sc);
 3105                 }
 3106                 break;
 3107         case SIOCSIFFLAGS:
 3108                 if (ifp->if_flags & IFF_UP) {
 3109                         /*
 3110                          * If only the state of the PROMISC flag changed,
 3111                          * then just use the 'set promisc mode' command
 3112                          * instead of reinitializing the entire NIC. Doing
 3113                          * a full re-init means reloading the firmware and
 3114                          * waiting for it to start up, which may take a
 3115                          * second or two.
 3116                          */
 3117                         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
 3118                             ifp->if_flags & IFF_PROMISC &&
 3119                             !(sc->ti_if_flags & IFF_PROMISC)) {
 3120                                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
 3121                                     TI_CMD_CODE_PROMISC_ENB, 0);
 3122                         } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
 3123                             !(ifp->if_flags & IFF_PROMISC) &&
 3124                             sc->ti_if_flags & IFF_PROMISC) {
 3125                                 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
 3126                                     TI_CMD_CODE_PROMISC_DIS, 0);
 3127                         } else
 3128                                 ti_init(sc);
 3129                 } else {
 3130                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 3131                                 ti_stop(sc);
 3132                         }
 3133                 }
 3134                 sc->ti_if_flags = ifp->if_flags;
 3135                 error = 0;
 3136                 break;
 3137         case SIOCADDMULTI:
 3138         case SIOCDELMULTI:
 3139                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 3140                         ti_setmulti(sc);
 3141                         error = 0;
 3142                 }
 3143                 break;
 3144         case SIOCSIFMEDIA:
 3145         case SIOCGIFMEDIA:
 3146                 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
 3147                 break;
 3148         case SIOCSIFCAP:
 3149                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 3150                 if (mask & IFCAP_HWCSUM) {
 3151                         if (IFCAP_HWCSUM & ifp->if_capenable)
 3152                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
 3153                         else
 3154                                 ifp->if_capenable |= IFCAP_HWCSUM;
 3155                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 3156                                 ti_init(sc);
 3157                 }
 3158                 error = 0;
 3159                 break;
 3160         default:
 3161                 error = ether_ioctl(ifp, command, data);
 3162                 break;
 3163         }
 3164 
 3165         TI_UNLOCK(sc);
 3166 
 3167         return (error);
 3168 }
 3169 
 3170 static int
 3171 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
 3172 {
 3173         struct ti_softc *sc;
 3174 
 3175         sc = dev->si_drv1;
 3176         if (sc == NULL)
 3177                 return (ENODEV);
 3178 
 3179         TI_LOCK(sc);
 3180         sc->ti_flags |= TI_FLAG_DEBUGING;
 3181         TI_UNLOCK(sc);
 3182 
 3183         return (0);
 3184 }
 3185 
 3186 static int
 3187 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
 3188 {
 3189         struct ti_softc *sc;
 3190 
 3191         sc = dev->si_drv1;
 3192         if (sc == NULL)
 3193                 return (ENODEV);
 3194 
 3195         TI_LOCK(sc);
 3196         sc->ti_flags &= ~TI_FLAG_DEBUGING;
 3197         TI_UNLOCK(sc);
 3198 
 3199         return (0);
 3200 }
 3201 
 3202 /*
 3203  * This ioctl routine goes along with the Tigon character device.
 3204  */
 3205 static int
 3206 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, struct thread *td)
 3207 {
 3208         int error;
 3209         struct ti_softc *sc;
 3210 
 3211         sc = dev->si_drv1;
 3212         if (sc == NULL)
 3213                 return (ENODEV);
 3214 
 3215         error = 0;
 3216 
 3217         switch (cmd) {
 3218         case TIIOCGETSTATS:
 3219         {
 3220                 struct ti_stats *outstats;
 3221 
 3222                 outstats = (struct ti_stats *)addr;
 3223 
 3224                 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
 3225                       sizeof(struct ti_stats));
 3226                 break;
 3227         }
 3228         case TIIOCGETPARAMS:
 3229         {
 3230                 struct ti_params        *params;
 3231 
 3232                 params = (struct ti_params *)addr;
 3233 
 3234                 params->ti_stat_ticks = sc->ti_stat_ticks;
 3235                 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
 3236                 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
 3237                 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
 3238                 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
 3239                 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
 3240                 params->param_mask = TI_PARAM_ALL;
 3241 
 3242                 error = 0;
 3243 
 3244                 break;
 3245         }
 3246         case TIIOCSETPARAMS:
 3247         {
 3248                 struct ti_params *params;
 3249 
 3250                 params = (struct ti_params *)addr;
 3251 
 3252                 if (params->param_mask & TI_PARAM_STAT_TICKS) {
 3253                         sc->ti_stat_ticks = params->ti_stat_ticks;
 3254                         CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
 3255                 }
 3256 
 3257                 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
 3258                         sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
 3259                         CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
 3260                                     sc->ti_rx_coal_ticks);
 3261                 }
 3262 
 3263                 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
 3264                         sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
 3265                         CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
 3266                                     sc->ti_tx_coal_ticks);
 3267                 }
 3268 
 3269                 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
 3270                         sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
 3271                         CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
 3272                                     sc->ti_rx_max_coal_bds);
 3273                 }
 3274 
 3275                 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
 3276                         sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
 3277                         CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
 3278                                     sc->ti_tx_max_coal_bds);
 3279                 }
 3280 
 3281                 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
 3282                         sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
 3283                         CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
 3284                                     sc->ti_tx_buf_ratio);
 3285                 }
 3286 
 3287                 error = 0;
 3288 
 3289                 break;
 3290         }
 3291         case TIIOCSETTRACE: {
 3292                 ti_trace_type   trace_type;
 3293 
 3294                 trace_type = *(ti_trace_type *)addr;
 3295 
 3296                 /*
 3297                  * Set tracing to whatever the user asked for.  Setting
 3298                  * this register to 0 should have the effect of disabling
 3299                  * tracing.
 3300                  */
 3301                 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
 3302 
 3303                 error = 0;
 3304 
 3305                 break;
 3306         }
 3307         case TIIOCGETTRACE: {
 3308                 struct ti_trace_buf     *trace_buf;
 3309                 u_int32_t               trace_start, cur_trace_ptr, trace_len;
 3310 
 3311                 trace_buf = (struct ti_trace_buf *)addr;
 3312 
 3313                 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
 3314                 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
 3315                 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
 3316 
 3317 #if 0
 3318                 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, "
 3319                        "trace_len = %d\n", sc->ti_unit, trace_start,
 3320                        cur_trace_ptr, trace_len);
 3321                 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit,
 3322                        trace_buf->buf_len);
 3323 #endif
 3324 
 3325                 error = ti_copy_mem(sc, trace_start, min(trace_len,
 3326                                     trace_buf->buf_len),
 3327                                     (caddr_t)trace_buf->buf, 1, 1);
 3328 
 3329                 if (error == 0) {
 3330                         trace_buf->fill_len = min(trace_len,
 3331                                                   trace_buf->buf_len);
 3332                         if (cur_trace_ptr < trace_start)
 3333                                 trace_buf->cur_trace_ptr =
 3334                                         trace_start - cur_trace_ptr;
 3335                         else
 3336                                 trace_buf->cur_trace_ptr =
 3337                                         cur_trace_ptr - trace_start;
 3338                 } else
 3339                         trace_buf->fill_len = 0;
 3340 
 3341                 break;
 3342         }
 3343 
 3344         /*
 3345          * For debugging, five ioctls are needed:
 3346          * ALT_ATTACH
 3347          * ALT_READ_TG_REG
 3348          * ALT_WRITE_TG_REG
 3349          * ALT_READ_TG_MEM
 3350          * ALT_WRITE_TG_MEM
 3351          */
 3352         case ALT_ATTACH:
 3353                 /*
 3354                  * From what I can tell, Alteon's Solaris Tigon driver
 3355                  * only has one character device, so you have to attach
 3356                  * to the Tigon board you're interested in.  This seems
 3357                  * like a not-so-good way to do things, since unless you
 3358                  * subsequently specify the unit number of the device
 3359                  * you're interested in in every ioctl, you'll only be
 3360                  * able to debug one board at a time.
 3361                  */
 3362                 error = 0;
 3363                 break;
 3364         case ALT_READ_TG_MEM:
 3365         case ALT_WRITE_TG_MEM:
 3366         {
 3367                 struct tg_mem *mem_param;
 3368                 u_int32_t sram_end, scratch_end;
 3369 
 3370                 mem_param = (struct tg_mem *)addr;
 3371 
 3372                 if (sc->ti_hwrev == TI_HWREV_TIGON) {
 3373                         sram_end = TI_END_SRAM_I;
 3374                         scratch_end = TI_END_SCRATCH_I;
 3375                 } else {
 3376                         sram_end = TI_END_SRAM_II;
 3377                         scratch_end = TI_END_SCRATCH_II;
 3378                 }
 3379 
 3380                 /*
 3381                  * For now, we'll only handle accessing regular SRAM,
 3382                  * nothing else.
 3383                  */
 3384                 if ((mem_param->tgAddr >= TI_BEG_SRAM)
 3385                  && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
 3386                         /*
 3387                          * In this instance, we always copy to/from user
 3388                          * space, so the user space argument is set to 1.
 3389                          */
 3390                         error = ti_copy_mem(sc, mem_param->tgAddr,
 3391                                             mem_param->len,
 3392                                             mem_param->userAddr, 1,
 3393                                             (cmd == ALT_READ_TG_MEM) ? 1 : 0);
 3394                 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
 3395                         && (mem_param->tgAddr <= scratch_end)) {
 3396                         error = ti_copy_scratch(sc, mem_param->tgAddr,
 3397                                                 mem_param->len,
 3398                                                 mem_param->userAddr, 1,
 3399                                                 (cmd == ALT_READ_TG_MEM) ?
 3400                                                 1 : 0, TI_PROCESSOR_A);
 3401                 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
 3402                         && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
 3403                         if (sc->ti_hwrev == TI_HWREV_TIGON) {
 3404                                 printf("ti%d:  invalid memory range for "
 3405                                        "Tigon I\n", sc->ti_unit);
 3406                                 error = EINVAL;
 3407                                 break;
 3408                         }
 3409                         error = ti_copy_scratch(sc, mem_param->tgAddr -
 3410                                                 TI_SCRATCH_DEBUG_OFF,
 3411                                                 mem_param->len,
 3412                                                 mem_param->userAddr, 1,
 3413                                                 (cmd == ALT_READ_TG_MEM) ?
 3414                                                 1 : 0, TI_PROCESSOR_B);
 3415                 } else {
 3416                         printf("ti%d: memory address %#x len %d is out of "
 3417                                "supported range\n", sc->ti_unit,
 3418                                 mem_param->tgAddr, mem_param->len);
 3419                         error = EINVAL;
 3420                 }
 3421 
 3422                 break;
 3423         }
 3424         case ALT_READ_TG_REG:
 3425         case ALT_WRITE_TG_REG:
 3426         {
 3427                 struct tg_reg   *regs;
 3428                 u_int32_t       tmpval;
 3429 
 3430                 regs = (struct tg_reg *)addr;
 3431 
 3432                 /*
 3433                  * Make sure the address in question isn't out of range.
 3434                  */
 3435                 if (regs->addr > TI_REG_MAX) {
 3436                         error = EINVAL;
 3437                         break;
 3438                 }
 3439                 if (cmd == ALT_READ_TG_REG) {
 3440                         bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
 3441                                                 regs->addr, &tmpval, 1);
 3442                         regs->data = ntohl(tmpval);
 3443 #if 0
 3444                         if ((regs->addr == TI_CPU_STATE)
 3445                          || (regs->addr == TI_CPU_CTL_B)) {
 3446                                 printf("ti%d: register %#x = %#x\n",
 3447                                        sc->ti_unit, regs->addr, tmpval);
 3448                         }
 3449 #endif
 3450                 } else {
 3451                         tmpval = htonl(regs->data);
 3452                         bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
 3453                                                  regs->addr, &tmpval, 1);
 3454                 }
 3455 
 3456                 break;
 3457         }
 3458         default:
 3459                 error = ENOTTY;
 3460                 break;
 3461         }
 3462         return (error);
 3463 }
 3464 
 3465 static void
 3466 ti_watchdog(ifp)
 3467         struct ifnet            *ifp;
 3468 {
 3469         struct ti_softc         *sc;
 3470 
 3471         sc = ifp->if_softc;
 3472         TI_LOCK(sc);
 3473 
 3474         /*
 3475          * When we're debugging, the chip is often stopped for long periods
 3476          * of time, and that would normally cause the watchdog timer to fire.
 3477          * Since that impedes debugging, we don't want to do that.
 3478          */
 3479         if (sc->ti_flags & TI_FLAG_DEBUGING) {
 3480                 TI_UNLOCK(sc);
 3481                 return;
 3482         }
 3483 
 3484         printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
 3485         ti_stop(sc);
 3486         ti_init(sc);
 3487 
 3488         ifp->if_oerrors++;
 3489         TI_UNLOCK(sc);
 3490 }
 3491 
 3492 /*
 3493  * Stop the adapter and free any mbufs allocated to the
 3494  * RX and TX lists.
 3495  */
 3496 static void
 3497 ti_stop(sc)
 3498         struct ti_softc         *sc;
 3499 {
 3500         struct ifnet            *ifp;
 3501         struct ti_cmd_desc      cmd;
 3502 
 3503         TI_LOCK(sc);
 3504 
 3505         ifp = sc->ti_ifp;
 3506 
 3507         /* Disable host interrupts. */
 3508         CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 3509         /*
 3510          * Tell firmware we're shutting down.
 3511          */
 3512         TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
 3513 
 3514         /* Halt and reinitialize. */
 3515         ti_chipinit(sc);
 3516         ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
 3517         ti_chipinit(sc);
 3518 
 3519         /* Free the RX lists. */
 3520         ti_free_rx_ring_std(sc);
 3521 
 3522         /* Free jumbo RX list. */
 3523         ti_free_rx_ring_jumbo(sc);
 3524 
 3525         /* Free mini RX list. */
 3526         ti_free_rx_ring_mini(sc);
 3527 
 3528         /* Free TX buffers. */
 3529         ti_free_tx_ring(sc);
 3530 
 3531         sc->ti_ev_prodidx.ti_idx = 0;
 3532         sc->ti_return_prodidx.ti_idx = 0;
 3533         sc->ti_tx_considx.ti_idx = 0;
 3534         sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
 3535 
 3536         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 3537         TI_UNLOCK(sc);
 3538 }
 3539 
 3540 /*
 3541  * Stop all chip I/O so that the kernel's probe routines don't
 3542  * get confused by errant DMAs when rebooting.
 3543  */
 3544 static void
 3545 ti_shutdown(dev)
 3546         device_t                dev;
 3547 {
 3548         struct ti_softc         *sc;
 3549 
 3550         sc = device_get_softc(dev);
 3551         TI_LOCK(sc);
 3552         ti_chipinit(sc);
 3553         TI_UNLOCK(sc);
 3554 }

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