Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_tireg.h
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. 41 * The first group of registers are actually copies of the PCI 42 * configuration space registers. 43 */ 44 45 #define TI_PCI_ID 0x000 /* PCI device/vendor ID */ 46 #define TI_PCI_CMDSTAT 0x004 47 #define TI_PCI_CLASSCODE 0x008 48 #define TI_PCI_BIST 0x00C 49 #define TI_PCI_LOMEM 0x010 /* Shared memory base address */ 50 #define TI_PCI_SUBSYS 0x02C 51 #define TI_PCI_ROMBASE 0x030 52 #define TI_PCI_INT 0x03C 53 54 #ifndef PCIM_CMD_MWIEN 55 #define PCIM_CMD_MWIEN 0x0010 56 #endif 57 58 /* 59 * Alteon AceNIC PCI vendor/device ID. 60 */ 61 #define ALT_VENDORID 0x12AE 62 #define ALT_DEVICEID_ACENIC 0x0001 63 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 64 65 /* 66 * 3Com 3c985 PCI vendor/device ID. 67 */ 68 #define TC_VENDORID 0x10B7 69 #define TC_DEVICEID_3C985 0x0001 70 71 /* 72 * Netgear GA620 PCI vendor/device ID. 73 */ 74 #define NG_VENDORID 0x1385 75 #define NG_DEVICEID_GA620 0x620A 76 #define NG_DEVICEID_GA620T 0x630A 77 78 /* 79 * SGI device/vendor ID. 80 */ 81 #define SGI_VENDORID 0x10A9 82 #define SGI_DEVICEID_TIGON 0x0009 83 84 /* 85 * DEC vendor ID, Farallon device ID. Apparently, Farallon used 86 * the DEC vendor ID in their cards by mistake. 87 */ 88 #define DEC_VENDORID 0x1011 89 #define DEC_DEVICEID_FARALLON_PN9000SX 0x001a 90 91 /* 92 * Tigon configuration and control registers. 93 */ 94 #define TI_MISC_HOST_CTL 0x040 95 #define TI_MISC_LOCAL_CTL 0x044 96 #define TI_SEM_AB 0x048 /* Tigon 2 only */ 97 #define TI_MISC_CONF 0x050 /* Tigon 2 only */ 98 #define TI_TIMER_BITS 0x054 99 #define TI_TIMERREF 0x058 100 #define TI_PCI_STATE 0x05C 101 #define TI_MAIN_EVENT_A 0x060 102 #define TI_MAILBOX_EVENT_A 0x064 103 #define TI_WINBASE 0x068 104 #define TI_WINDATA 0x06C 105 #define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */ 106 #define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */ 107 #define TI_TIMERREF_B 0x078 /* Tigon 2 only */ 108 #define TI_SERIAL 0x07C 109 110 /* 111 * Misc host control bits. 112 */ 113 #define TI_MHC_INTSTATE 0x00000001 114 #define TI_MHC_CLEARINT 0x00000002 115 #define TI_MHC_RESET 0x00000008 116 #define TI_MHC_BYTE_SWAP_ENB 0x00000010 117 #define TI_MHC_WORD_SWAP_ENB 0x00000020 118 #define TI_MHC_MASK_INTS 0x00000040 119 #define TI_MHC_CHIP_REV_MASK 0xF0000000 120 121 #define TI_MHC_BIGENDIAN_INIT \ 122 (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 123 124 #define TI_MHC_LITTLEENDIAN_INIT \ 125 (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 126 127 /* 128 * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2. 129 * Rev 5 is also the Tigon 2, but is a broken version which was never 130 * used in any actual hardware, so we ignore it. 131 */ 132 #define TI_REV_TIGON_I 0x40000000 133 #define TI_REV_TIGON_II 0x60000000 134 135 /* 136 * Firmware revision that we want. 137 */ 138 #define TI_FIRMWARE_MAJOR 0xc 139 #define TI_FIRMWARE_MINOR 0x4 140 #define TI_FIRMWARE_FIX 0xd 141 142 /* 143 * Miscelaneous Local Control register. 144 */ 145 #define TI_MLC_EE_WRITE_ENB 0x00000010 146 #define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 147 #define TI_MLC_LOCALADDR_21 0x00004000 148 #define TI_MLC_LOCALADDR_22 0x00008000 149 #define TI_MLC_SBUS_WRITEERR 0x00080000 150 #define TI_MLC_EE_CLK 0x00100000 151 #define TI_MLC_EE_TXEN 0x00200000 152 #define TI_MLC_EE_DOUT 0x00400000 153 #define TI_MLC_EE_DIN 0x00800000 154 155 /* Possible memory sizes. */ 156 #define TI_MLC_SRAM_BANK_DISA 0x00000000 157 #define TI_MLC_SRAM_BANK_1024K 0x00000100 158 #define TI_MLC_SRAM_BANK_512K 0x00000200 159 #define TI_MLC_SRAM_BANK_256K 0x00000300 160 161 /* 162 * Offset of MAC address inside EEPROM. 163 */ 164 #define TI_EE_MAC_OFFSET 0x8c 165 166 #define TI_DMA_ASSIST 0x11C 167 #define TI_CPU_STATE 0x140 168 #define TI_CPU_PROGRAM_COUNTER 0x144 169 #define TI_SRAM_ADDR 0x154 170 #define TI_SRAM_DATA 0x158 171 #define TI_GEN_0 0x180 172 #define TI_GEN_X 0x1FC 173 #define TI_MAC_TX_STATE 0x200 174 #define TI_MAC_RX_STATE 0x220 175 #define TI_CPU_CTL_B 0x240 /* Tigon 2 only */ 176 #define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */ 177 #define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */ 178 #define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */ 179 #define TI_GEN_B_0 0x280 /* Tigon 2 only */ 180 #define TI_GEN_B_X 0x2FC /* Tigon 2 only */ 181 182 /* 183 * Misc config register. 184 */ 185 #define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */ 186 187 /* 188 * PCI state register. 189 */ 190 #define TI_PCISTATE_FORCE_RESET 0x00000001 191 #define TI_PCISTATE_PROVIDE_LEN 0x00000002 192 #define TI_PCISTATE_READ_MAXDMA 0x0000001C 193 #define TI_PCISTATE_WRITE_MAXDMA 0x000000E0 194 #define TI_PCISTATE_MINDMA 0x0000FF00 195 #define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000 196 #define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000 197 #define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000 198 #define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000 199 #define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */ 200 #define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */ 201 #define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */ 202 #define TI_PCISTATE_READ_CMD 0x0F000000 203 #define TI_PCISTATE_WRITE_CMD 0xF0000000 204 205 #define TI_PCI_READMAX_4 0x04 206 #define TI_PCI_READMAX_16 0x08 207 #define TI_PCI_READMAX_32 0x0C 208 #define TI_PCI_READMAX_64 0x10 209 #define TI_PCI_READMAX_128 0x14 210 #define TI_PCI_READMAX_256 0x18 211 #define TI_PCI_READMAX_1024 0x1C 212 213 #define TI_PCI_WRITEMAX_4 0x20 214 #define TI_PCI_WRITEMAX_16 0x40 215 #define TI_PCI_WRITEMAX_32 0x60 216 #define TI_PCI_WRITEMAX_64 0x80 217 #define TI_PCI_WRITEMAX_128 0xA0 218 #define TI_PCI_WRITEMAX_256 0xC0 219 #define TI_PCI_WRITEMAX_1024 0xE0 220 221 #define TI_PCI_READ_CMD 0x06000000 222 #define TI_PCI_WRITE_CMD 0x70000000 223 224 /* 225 * DMA state register. 226 */ 227 #define TI_DMASTATE_ENABLE 0x00000001 228 #define TI_DMASTATE_PAUSE 0x00000002 229 230 /* 231 * CPU state register. 232 */ 233 #define TI_CPUSTATE_RESET 0x00000001 234 #define TI_CPUSTATE_STEP 0x00000002 235 #define TI_CPUSTATE_ROMFAIL 0x00000010 236 #define TI_CPUSTATE_HALT 0x00010000 237 /* 238 * MAC TX state register 239 */ 240 #define TI_TXSTATE_RESET 0x00000001 241 #define TI_TXSTATE_ENB 0x00000002 242 #define TI_TXSTATE_STOP 0x00000004 243 244 /* 245 * MAC RX state register 246 */ 247 #define TI_RXSTATE_RESET 0x00000001 248 #define TI_RXSTATE_ENB 0x00000002 249 #define TI_RXSTATE_STOP 0x00000004 250 251 /* 252 * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes 253 * split into 64 bit registers. Only the lower 32 bits of each mailbox 254 * are used. 255 */ 256 #define TI_MB_HOSTINTR_HI 0x500 257 #define TI_MB_HOSTINTR_LO 0x504 258 #define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO 259 #define TI_MB_CMDPROD_IDX_HI 0x508 260 #define TI_MB_CMDPROD_IDX_LO 0x50C 261 #define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO 262 #define TI_MB_SENDPROD_IDX_HI 0x510 263 #define TI_MB_SENDPROD_IDX_LO 0x514 264 #define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO 265 #define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */ 266 #define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */ 267 #define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO 268 #define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */ 269 #define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */ 270 #define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO 271 #define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */ 272 #define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */ 273 #define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO 274 #define TI_MB_RSVD 0x530 275 276 /* 277 * Tigon 2 general communication registers. These are 64 and 32 bit 278 * registers which are only valid after the firmware has been 279 * loaded and started. They actually exist in NIC memory but are 280 * mapped into the host memory via the shared memory region. 281 * 282 * The NIC internally maps these registers starting at address 0, 283 * so to determine the NIC address of any of these registers, we 284 * subtract 0x600 (the address of the first register). 285 */ 286 287 #define TI_GCR_BASE 0x600 288 #define TI_GCR_MACADDR 0x600 289 #define TI_GCR_PAR0 0x600 290 #define TI_GCR_PAR1 0x604 291 #define TI_GCR_GENINFO_HI 0x608 292 #define TI_GCR_GENINFO_LO 0x60C 293 #define TI_GCR_MCASTADDR 0x610 /* obsolete */ 294 #define TI_GCR_MAR0 0x610 /* obsolete */ 295 #define TI_GCR_MAR1 0x614 /* obsolete */ 296 #define TI_GCR_OPMODE 0x618 297 #define TI_GCR_DMA_READCFG 0x61C 298 #define TI_GCR_DMA_WRITECFG 0x620 299 #define TI_GCR_TX_BUFFER_RATIO 0x624 300 #define TI_GCR_EVENTCONS_IDX 0x628 301 #define TI_GCR_CMDCONS_IDX 0x62C 302 #define TI_GCR_TUNEPARMS 0x630 303 #define TI_GCR_RX_COAL_TICKS 0x630 304 #define TI_GCR_TX_COAL_TICKS 0x634 305 #define TI_GCR_STAT_TICKS 0x638 306 #define TI_GCR_TX_MAX_COAL_BD 0x63C 307 #define TI_GCR_RX_MAX_COAL_BD 0x640 308 #define TI_GCR_NIC_TRACING 0x644 309 #define TI_GCR_GLINK 0x648 310 #define TI_GCR_LINK 0x64C 311 #define TI_GCR_NICTRACE_PTR 0x650 312 #define TI_GCR_NICTRACE_START 0x654 313 #define TI_GCR_NICTRACE_LEN 0x658 314 #define TI_GCR_IFINDEX 0x65C 315 #define TI_GCR_IFMTU 0x660 316 #define TI_GCR_MASK_INTRS 0x664 317 #define TI_GCR_GLINK_STAT 0x668 318 #define TI_GCR_LINK_STAT 0x66C 319 #define TI_GCR_RXRETURNCONS_IDX 0x680 320 #define TI_GCR_CMDRING 0x700 321 322 #define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE); 323 324 /* 325 * Local memory window. The local memory window is a 2K shared 326 * memory region which can be used to access the NIC's internal 327 * SRAM. The window can be mapped to a given 2K region using 328 * the TI_WINDOW_BASE register. 329 */ 330 #define TI_WINDOW 0x800 331 #define TI_WINLEN 0x800 332 333 #define TI_TICKS_PER_SEC 1000000 334 335 /* 336 * Operation mode register. 337 */ 338 #define TI_OPMODE_BYTESWAP_BD 0x00000002 339 #define TI_OPMODE_WORDSWAP_BD 0x00000004 340 #define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implimented */ 341 #define TI_OPMODE_BYTESWAP_DATA 0x00000010 342 #define TI_OPMODE_1_DMA_ACTIVE 0x00000040 343 #define TI_OPMODE_SBUS 0x00000100 344 #define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200 345 #define TI_OPMODE_INCLUDE_CRC 0x00000400 346 #define TI_OPMODE_RX_BADFRAMES 0x00000800 347 #define TI_OPMODE_NO_EVENT_INTRS 0x00001000 348 #define TI_OPMODE_NO_TX_INTRS 0x00002000 349 #define TI_OPMODE_NO_RX_INTRS 0x00004000 350 #define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implimented */ 351 352 /* 353 * DMA configuration thresholds. 354 */ 355 #define TI_DMA_STATE_THRESH_16W 0x00000100 356 #define TI_DMA_STATE_THRESH_8W 0x00000080 357 #define TI_DMA_STATE_THRESH_4W 0x00000040 358 #define TI_DMA_STATE_THRESH_2W 0x00000020 359 #define TI_DMA_STATE_THRESH_1W 0x00000010 360 361 #define TI_DMA_STATE_FORCE_32_BIT 0x00000008 362 363 /* 364 * Gigabit link status bits. 365 */ 366 #define TI_GLNK_SENSE_NO_BEG 0x00002000 367 #define TI_GLNK_LOOPBACK 0x00004000 368 #define TI_GLNK_PREF 0x00008000 369 #define TI_GLNK_1000MB 0x00040000 370 #define TI_GLNK_FULL_DUPLEX 0x00080000 371 #define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 372 #define TI_GLNK_RX_FLOWCTL_Y 0x00800000 373 #define TI_GLNK_AUTONEGENB 0x20000000 374 #define TI_GLNK_ENB 0x40000000 375 376 /* 377 * Link status bits. 378 */ 379 #define TI_LNK_LOOPBACK 0x00004000 380 #define TI_LNK_PREF 0x00008000 381 #define TI_LNK_10MB 0x00010000 382 #define TI_LNK_100MB 0x00020000 383 #define TI_LNK_1000MB 0x00040000 384 #define TI_LNK_FULL_DUPLEX 0x00080000 385 #define TI_LNK_HALF_DUPLEX 0x00100000 386 #define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 387 #define TI_LNK_RX_FLOWCTL_Y 0x00800000 388 #define TI_LNK_AUTONEGENB 0x20000000 389 #define TI_LNK_ENB 0x40000000 390 391 /* 392 * Ring size constants. 393 */ 394 #define TI_EVENT_RING_CNT 256 395 #define TI_CMD_RING_CNT 64 396 #define TI_STD_RX_RING_CNT 512 397 #define TI_JUMBO_RX_RING_CNT 256 398 #define TI_MINI_RX_RING_CNT 1024 399 #define TI_RETURN_RING_CNT 2048 400 401 /* 402 * Possible TX ring sizes. 403 */ 404 #define TI_TX_RING_CNT_128 128 405 #define TI_TX_RING_BASE_128 0x3800 406 407 #define TI_TX_RING_CNT_256 256 408 #define TI_TX_RING_BASE_256 0x3000 409 410 #define TI_TX_RING_CNT_512 512 411 #define TI_TX_RING_BASE_512 0x2000 412 413 #define TI_TX_RING_CNT TI_TX_RING_CNT_512 414 #define TI_TX_RING_BASE TI_TX_RING_BASE_512 415 416 /* 417 * The Tigon can have up to 8MB of external SRAM, however the Tigon 1 418 * is limited to 2MB total, and in general I think most adapters have 419 * around 1MB. We use this value for zeroing the NIC's SRAM, so to 420 * be safe we use the largest possible value (zeroing memory that 421 * isn't there doesn't hurt anything). 422 */ 423 #define TI_MEM_MAX 0x7FFFFF 424 425 /* 426 * Even on the alpha, pci addresses are 32-bit quantities 427 */ 428 429 #ifdef __64_bit_pci_addressing__ 430 typedef struct { 431 u_int64_t ti_addr; 432 } ti_hostaddr; 433 #define TI_HOSTADDR(x) x.ti_addr 434 #else 435 typedef struct { 436 u_int32_t ti_addr_hi; 437 u_int32_t ti_addr_lo; 438 } ti_hostaddr; 439 #define TI_HOSTADDR(x) x.ti_addr_lo 440 #endif 441 442 /* 443 * Ring control block structure. The rules for the max_len field 444 * are as follows: 445 * 446 * For the send ring, max_len indicates the number of entries in the 447 * ring (128, 256 or 512). 448 * 449 * For the standard receive ring, max_len indicates the threshold 450 * used to decide when a frame should be put in the jumbo receive ring 451 * instead of the standard one. 452 * 453 * For the mini ring, max_len indicates the size of the buffers in the 454 * ring. This is the value used to decide when a frame is small enough 455 * to be placed in the mini ring. 456 * 457 * For the return receive ring, max_len indicates the number of entries 458 * in the ring. It can be one of 2048, 1024 or 0 (which is the same as 459 * 2048 for backwards compatibility). The value 1024 can only be used 460 * if the mini ring is disabled. 461 */ 462 struct ti_rcb { 463 ti_hostaddr ti_hostaddr; 464 #if BYTE_ORDER == BIG_ENDIAN 465 u_int16_t ti_max_len; 466 u_int16_t ti_flags; 467 #else 468 u_int16_t ti_flags; 469 u_int16_t ti_max_len; 470 #endif 471 u_int32_t ti_unused; 472 }; 473 474 #define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001 475 #define TI_RCB_FLAG_IP_CKSUM 0x00000002 476 #define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008 477 #define TI_RCB_FLAG_VLAN_ASSIST 0x00000010 478 #define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020 479 #define TI_RCB_FLAG_HOST_RING 0x00000040 480 #define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080 481 #define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100 482 #define TI_RCB_FLAG_RING_DISABLED 0x00000200 483 484 struct ti_producer { 485 u_int32_t ti_idx; 486 u_int32_t ti_unused; 487 }; 488 489 /* 490 * Tigon statistics counters. 491 */ 492 struct ti_stats { 493 /* 494 * MAC stats, taken from RFC 1643, ethernet-like MIB 495 */ 496 volatile u_int32_t dot3StatsAlignmentErrors; /* 0 */ 497 volatile u_int32_t dot3StatsFCSErrors; /* 1 */ 498 volatile u_int32_t dot3StatsSingleCollisionFrames; /* 2 */ 499 volatile u_int32_t dot3StatsMultipleCollisionFrames; /* 3 */ 500 volatile u_int32_t dot3StatsSQETestErrors; /* 4 */ 501 volatile u_int32_t dot3StatsDeferredTransmissions; /* 5 */ 502 volatile u_int32_t dot3StatsLateCollisions; /* 6 */ 503 volatile u_int32_t dot3StatsExcessiveCollisions; /* 7 */ 504 volatile u_int32_t dot3StatsInternalMacTransmitErrors; /* 8 */ 505 volatile u_int32_t dot3StatsCarrierSenseErrors; /* 9 */ 506 volatile u_int32_t dot3StatsFrameTooLongs; /* 10 */ 507 volatile u_int32_t dot3StatsInternalMacReceiveErrors; /* 11 */ 508 /* 509 * interface stats, taken from RFC 1213, MIB-II, interfaces group 510 */ 511 volatile u_int32_t ifIndex; /* 12 */ 512 volatile u_int32_t ifType; /* 13 */ 513 volatile u_int32_t ifMtu; /* 14 */ 514 volatile u_int32_t ifSpeed; /* 15 */ 515 volatile u_int32_t ifAdminStatus; /* 16 */ 516 #define IF_ADMIN_STATUS_UP 1 517 #define IF_ADMIN_STATUS_DOWN 2 518 #define IF_ADMIN_STATUS_TESTING 3 519 volatile u_int32_t ifOperStatus; /* 17 */ 520 #define IF_OPER_STATUS_UP 1 521 #define IF_OPER_STATUS_DOWN 2 522 #define IF_OPER_STATUS_TESTING 3 523 #define IF_OPER_STATUS_UNKNOWN 4 524 #define IF_OPER_STATUS_DORMANT 5 525 volatile u_int32_t ifLastChange; /* 18 */ 526 volatile u_int32_t ifInDiscards; /* 19 */ 527 volatile u_int32_t ifInErrors; /* 20 */ 528 volatile u_int32_t ifInUnknownProtos; /* 21 */ 529 volatile u_int32_t ifOutDiscards; /* 22 */ 530 volatile u_int32_t ifOutErrors; /* 23 */ 531 volatile u_int32_t ifOutQLen; /* deprecated */ /* 24 */ 532 volatile u_int8_t ifPhysAddress[8]; /* 8 bytes */ /* 25 - 26 */ 533 volatile u_int8_t ifDescr[32]; /* 27 - 34 */ 534 u_int32_t alignIt; /* align to 64 bit for u_int64_ts following */ 535 /* 536 * more interface stats, taken from RFC 1573, MIB-IIupdate, 537 * interfaces group 538 */ 539 volatile u_int64_t ifHCInOctets; /* 36 - 37 */ 540 volatile u_int64_t ifHCInUcastPkts; /* 38 - 39 */ 541 volatile u_int64_t ifHCInMulticastPkts; /* 40 - 41 */ 542 volatile u_int64_t ifHCInBroadcastPkts; /* 42 - 43 */ 543 volatile u_int64_t ifHCOutOctets; /* 44 - 45 */ 544 volatile u_int64_t ifHCOutUcastPkts; /* 46 - 47 */ 545 volatile u_int64_t ifHCOutMulticastPkts; /* 48 - 49 */ 546 volatile u_int64_t ifHCOutBroadcastPkts; /* 50 - 51 */ 547 volatile u_int32_t ifLinkUpDownTrapEnable; /* 52 */ 548 volatile u_int32_t ifHighSpeed; /* 53 */ 549 volatile u_int32_t ifPromiscuousMode; /* 54 */ 550 volatile u_int32_t ifConnectorPresent; /* follow link state 55 */ 551 /* 552 * Host Commands 553 */ 554 volatile u_int32_t nicCmdsHostState; /* 56 */ 555 volatile u_int32_t nicCmdsFDRFiltering; /* 57 */ 556 volatile u_int32_t nicCmdsSetRecvProdIndex; /* 58 */ 557 volatile u_int32_t nicCmdsUpdateGencommStats; /* 59 */ 558 volatile u_int32_t nicCmdsResetJumboRing; /* 60 */ 559 volatile u_int32_t nicCmdsAddMCastAddr; /* 61 */ 560 volatile u_int32_t nicCmdsDelMCastAddr; /* 62 */ 561 volatile u_int32_t nicCmdsSetPromiscMode; /* 63 */ 562 volatile u_int32_t nicCmdsLinkNegotiate; /* 64 */ 563 volatile u_int32_t nicCmdsSetMACAddr; /* 65 */ 564 volatile u_int32_t nicCmdsClearProfile; /* 66 */ 565 volatile u_int32_t nicCmdsSetMulticastMode; /* 67 */ 566 volatile u_int32_t nicCmdsClearStats; /* 68 */ 567 volatile u_int32_t nicCmdsSetRecvJumboProdIndex; /* 69 */ 568 volatile u_int32_t nicCmdsSetRecvMiniProdIndex; /* 70 */ 569 volatile u_int32_t nicCmdsRefreshStats; /* 71 */ 570 volatile u_int32_t nicCmdsUnknown; /* 72 */ 571 /* 572 * NIC Events 573 */ 574 volatile u_int32_t nicEventsNICFirmwareOperational; /* 73 */ 575 volatile u_int32_t nicEventsStatsUpdated; /* 74 */ 576 volatile u_int32_t nicEventsLinkStateChanged; /* 75 */ 577 volatile u_int32_t nicEventsError; /* 76 */ 578 volatile u_int32_t nicEventsMCastListUpdated; /* 77 */ 579 volatile u_int32_t nicEventsResetJumboRing; /* 78 */ 580 /* 581 * Ring manipulation 582 */ 583 volatile u_int32_t nicRingSetSendProdIndex; /* 79 */ 584 volatile u_int32_t nicRingSetSendConsIndex; /* 80 */ 585 volatile u_int32_t nicRingSetRecvReturnProdIndex; /* 81 */ 586 /* 587 * Interrupts 588 */ 589 volatile u_int32_t nicInterrupts; /* 82 */ 590 volatile u_int32_t nicAvoidedInterrupts; /* 83 */ 591 /* 592 * BD Coalessing Thresholds 593 */ 594 volatile u_int32_t nicEventThresholdHit; /* 84 */ 595 volatile u_int32_t nicSendThresholdHit; /* 85 */ 596 volatile u_int32_t nicRecvThresholdHit; /* 86 */ 597 /* 598 * DMA Attentions 599 */ 600 volatile u_int32_t nicDmaRdOverrun; /* 87 */ 601 volatile u_int32_t nicDmaRdUnderrun; /* 88 */ 602 volatile u_int32_t nicDmaWrOverrun; /* 89 */ 603 volatile u_int32_t nicDmaWrUnderrun; /* 90 */ 604 volatile u_int32_t nicDmaWrMasterAborts; /* 91 */ 605 volatile u_int32_t nicDmaRdMasterAborts; /* 92 */ 606 /* 607 * NIC Resources 608 */ 609 volatile u_int32_t nicDmaWriteRingFull; /* 93 */ 610 volatile u_int32_t nicDmaReadRingFull; /* 94 */ 611 volatile u_int32_t nicEventRingFull; /* 95 */ 612 volatile u_int32_t nicEventProducerRingFull; /* 96 */ 613 volatile u_int32_t nicTxMacDescrRingFull; /* 97 */ 614 volatile u_int32_t nicOutOfTxBufSpaceFrameRetry; /* 98 */ 615 volatile u_int32_t nicNoMoreWrDMADescriptors; /* 99 */ 616 volatile u_int32_t nicNoMoreRxBDs; /* 100 */ 617 volatile u_int32_t nicNoSpaceInReturnRing; /* 101 */ 618 volatile u_int32_t nicSendBDs; /* current count 102 */ 619 volatile u_int32_t nicRecvBDs; /* current count 103 */ 620 volatile u_int32_t nicJumboRecvBDs; /* current count 104 */ 621 volatile u_int32_t nicMiniRecvBDs; /* current count 105 */ 622 volatile u_int32_t nicTotalRecvBDs; /* current count 106 */ 623 volatile u_int32_t nicTotalSendBDs; /* current count 107 */ 624 volatile u_int32_t nicJumboSpillOver; /* 108 */ 625 volatile u_int32_t nicSbusHangCleared; /* 109 */ 626 volatile u_int32_t nicEnqEventDelayed; /* 110 */ 627 /* 628 * Stats from MAC rx completion 629 */ 630 volatile u_int32_t nicMacRxLateColls; /* 111 */ 631 volatile u_int32_t nicMacRxLinkLostDuringPkt; /* 112 */ 632 volatile u_int32_t nicMacRxPhyDecodeErr; /* 113 */ 633 volatile u_int32_t nicMacRxMacAbort; /* 114 */ 634 volatile u_int32_t nicMacRxTruncNoResources; /* 115 */ 635 /* 636 * Stats from the mac_stats area 637 */ 638 volatile u_int32_t nicMacRxDropUla; /* 116 */ 639 volatile u_int32_t nicMacRxDropMcast; /* 117 */ 640 volatile u_int32_t nicMacRxFlowControl; /* 118 */ 641 volatile u_int32_t nicMacRxDropSpace; /* 119 */ 642 volatile u_int32_t nicMacRxColls; /* 120 */ 643 /* 644 * MAC RX Attentions 645 */ 646 volatile u_int32_t nicMacRxTotalAttns; /* 121 */ 647 volatile u_int32_t nicMacRxLinkAttns; /* 122 */ 648 volatile u_int32_t nicMacRxSyncAttns; /* 123 */ 649 volatile u_int32_t nicMacRxConfigAttns; /* 124 */ 650 volatile u_int32_t nicMacReset; /* 125 */ 651 volatile u_int32_t nicMacRxBufDescrAttns; /* 126 */ 652 volatile u_int32_t nicMacRxBufAttns; /* 127 */ 653 volatile u_int32_t nicMacRxZeroFrameCleanup; /* 128 */ 654 volatile u_int32_t nicMacRxOneFrameCleanup; /* 129 */ 655 volatile u_int32_t nicMacRxMultipleFrameCleanup; /* 130 */ 656 volatile u_int32_t nicMacRxTimerCleanup; /* 131 */ 657 volatile u_int32_t nicMacRxDmaCleanup; /* 132 */ 658 /* 659 * Stats from the mac_stats area 660 */ 661 volatile u_int32_t nicMacTxCollisionHistogram[15]; /* 133 */ 662 /* 663 * MAC TX Attentions 664 */ 665 volatile u_int32_t nicMacTxTotalAttns; /* 134 */ 666 /* 667 * NIC Profile 668 */ 669 volatile u_int32_t nicProfile[32]; /* 135 */ 670 /* 671 * Pat to 1024 bytes. 672 */ 673 u_int32_t pad[75]; 674 }; 675 /* 676 * Tigon general information block. This resides in host memory 677 * and contains the status counters, ring control blocks and 678 * producer pointers. 679 */ 680 681 struct ti_gib { 682 struct ti_stats ti_stats; 683 struct ti_rcb ti_ev_rcb; 684 struct ti_rcb ti_cmd_rcb; 685 struct ti_rcb ti_tx_rcb; 686 struct ti_rcb ti_std_rx_rcb; 687 struct ti_rcb ti_jumbo_rx_rcb; 688 struct ti_rcb ti_mini_rx_rcb; 689 struct ti_rcb ti_return_rcb; 690 ti_hostaddr ti_ev_prodidx_ptr; 691 ti_hostaddr ti_return_prodidx_ptr; 692 ti_hostaddr ti_tx_considx_ptr; 693 ti_hostaddr ti_refresh_stats_ptr; 694 }; 695 696 /* 697 * Buffer descriptor structures. There are basically three types 698 * of structures: normal receive descriptors, extended receive 699 * descriptors and transmit descriptors. The extended receive 700 * descriptors are optionally used only for the jumbo receive ring. 701 */ 702 703 struct ti_rx_desc { 704 ti_hostaddr ti_addr; 705 #if BYTE_ORDER == BIG_ENDIAN 706 u_int16_t ti_idx; 707 u_int16_t ti_len; 708 #else 709 u_int16_t ti_len; 710 u_int16_t ti_idx; 711 #endif 712 #if BYTE_ORDER == BIG_ENDIAN 713 u_int16_t ti_type; 714 u_int16_t ti_flags; 715 #else 716 u_int16_t ti_flags; 717 u_int16_t ti_type; 718 #endif 719 #if BYTE_ORDER == BIG_ENDIAN 720 u_int16_t ti_ip_cksum; 721 u_int16_t ti_tcp_udp_cksum; 722 #else 723 u_int16_t ti_tcp_udp_cksum; 724 u_int16_t ti_ip_cksum; 725 #endif 726 #if BYTE_ORDER == BIG_ENDIAN 727 u_int16_t ti_error_flags; 728 u_int16_t ti_vlan_tag; 729 #else 730 u_int16_t ti_vlan_tag; 731 u_int16_t ti_error_flags; 732 #endif 733 u_int32_t ti_rsvd; 734 u_int32_t ti_opaque; 735 }; 736 737 struct ti_rx_desc_ext { 738 ti_hostaddr ti_addr1; 739 ti_hostaddr ti_addr2; 740 ti_hostaddr ti_addr3; 741 #if BYTE_ORDER == BIG_ENDIAN 742 u_int16_t ti_len1; 743 u_int16_t ti_len2; 744 #else 745 u_int16_t ti_len2; 746 u_int16_t ti_len1; 747 #endif 748 #if BYTE_ORDER == BIG_ENDIAN 749 u_int16_t ti_len3; 750 u_int16_t ti_rsvd0; 751 #else 752 u_int16_t ti_rsvd0; 753 u_int16_t ti_len3; 754 #endif 755 ti_hostaddr ti_addr0; 756 #if BYTE_ORDER == BIG_ENDIAN 757 u_int16_t ti_idx; 758 u_int16_t ti_len0; 759 #else 760 u_int16_t ti_len0; 761 u_int16_t ti_idx; 762 #endif 763 #if BYTE_ORDER == BIG_ENDIAN 764 u_int16_t ti_type; 765 u_int16_t ti_flags; 766 #else 767 u_int16_t ti_flags; 768 u_int16_t ti_type; 769 #endif 770 #if BYTE_ORDER == BIG_ENDIAN 771 u_int16_t ti_ip_cksum; 772 u_int16_t ti_tcp_udp_cksum; 773 #else 774 u_int16_t ti_tcp_udp_cksum; 775 u_int16_t ti_ip_cksum; 776 #endif 777 #if BYTE_ORDER == BIG_ENDIAN 778 u_int16_t ti_error_flags; 779 u_int16_t ti_vlan_tag; 780 #else 781 u_int16_t ti_vlan_tag; 782 u_int16_t ti_error_flags; 783 #endif 784 u_int32_t ti_rsvd1; 785 u_int32_t ti_opaque; 786 }; 787 788 /* 789 * Transmit descriptors are, mercifully, very small. 790 */ 791 struct ti_tx_desc { 792 ti_hostaddr ti_addr; 793 #if BYTE_ORDER == BIG_ENDIAN 794 u_int16_t ti_len; 795 u_int16_t ti_flags; 796 #else 797 u_int16_t ti_flags; 798 u_int16_t ti_len; 799 #endif 800 #if BYTE_ORDER == BIG_ENDIAN 801 u_int16_t ti_rsvd; 802 u_int16_t ti_vlan_tag; 803 #else 804 u_int16_t ti_vlan_tag; 805 u_int16_t ti_rsvd; 806 #endif 807 }; 808 809 /* 810 * NOTE! On the Alpha, we have an alignment constraint. 811 * The first thing in the packet is a 14-byte Ethernet header. 812 * This means that the packet is misaligned. To compensate, 813 * we actually offset the data 2 bytes into the cluster. This 814 * alignes the packet after the Ethernet header at a 32-bit 815 * boundary. 816 */ 817 818 #define ETHER_ALIGN 2 819 820 #define TI_FRAMELEN 1518 821 #define TI_JUMBO_FRAMELEN 9018 822 #define TI_JUMBO_MTU (TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 823 #define TI_PAGE_SIZE PAGE_SIZE 824 #define TI_MIN_FRAMELEN 60 825 826 /* 827 * Buffer descriptor error flags. 828 */ 829 #define TI_BDERR_CRC 0x0001 830 #define TI_BDERR_COLLDETECT 0x0002 831 #define TI_BDERR_LINKLOST 0x0004 832 #define TI_BDERR_DECODE 0x0008 833 #define TI_BDERR_ODD_NIBBLES 0x0010 834 #define TI_BDERR_MAC_ABRT 0x0020 835 #define TI_BDERR_RUNT 0x0040 836 #define TI_BDERR_TRUNC 0x0080 837 #define TI_BDERR_GIANT 0x0100 838 839 /* 840 * Buffer descriptor flags. 841 */ 842 #define TI_BDFLAG_TCP_UDP_CKSUM 0x0001 843 #define TI_BDFLAG_IP_CKSUM 0x0002 844 #define TI_BDFLAG_END 0x0004 845 #define TI_BDFLAG_MORE 0x0008 846 #define TI_BDFLAG_JUMBO_RING 0x0010 847 #define TI_BDFLAG_UCAST_PKT 0x0020 848 #define TI_BDFLAG_MCAST_PKT 0x0040 849 #define TI_BDFLAG_BCAST_PKT 0x0060 850 #define TI_BDFLAG_IP_FRAG 0x0080 851 #define TI_BDFLAG_IP_FRAG_END 0x0100 852 #define TI_BDFLAG_VLAN_TAG 0x0200 853 #define TI_BDFLAG_ERROR 0x0400 854 #define TI_BDFLAG_COAL_NOW 0x0800 855 #define TI_BDFLAG_MINI_RING 0x1000 856 857 /* 858 * Descriptor type flags. I think these only have meaning for 859 * the Tigon 1. I had to extract them from the sample driver source 860 * since they aren't in the manual. 861 */ 862 #define TI_BDTYPE_TYPE_NULL 0x0000 863 #define TI_BDTYPE_SEND_BD 0x0001 864 #define TI_BDTYPE_RECV_BD 0x0002 865 #define TI_BDTYPE_RECV_JUMBO_BD 0x0003 866 #define TI_BDTYPE_RECV_BD_LAST 0x0004 867 #define TI_BDTYPE_SEND_DATA 0x0005 868 #define TI_BDTYPE_SEND_DATA_LAST 0x0006 869 #define TI_BDTYPE_RECV_DATA 0x0007 870 #define TI_BDTYPE_RECV_DATA_LAST 0x000b 871 #define TI_BDTYPE_EVENT_RUPT 0x000c 872 #define TI_BDTYPE_EVENT_NO_RUPT 0x000d 873 #define TI_BDTYPE_ODD_START 0x000e 874 #define TI_BDTYPE_UPDATE_STATS 0x000f 875 #define TI_BDTYPE_SEND_DUMMY_DMA 0x0010 876 #define TI_BDTYPE_EVENT_PROD 0x0011 877 #define TI_BDTYPE_TX_CONS 0x0012 878 #define TI_BDTYPE_RX_PROD 0x0013 879 #define TI_BDTYPE_REFRESH_STATS 0x0014 880 #define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015 881 #define TI_BDTYPE_SEND_DATA_COAL 0x0016 882 #define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017 883 #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018 884 #define TI_BDTYPE_TX_CONS_NO_INTR 0x0019 885 886 /* 887 * Tigon command structure. 888 */ 889 struct ti_cmd_desc { 890 #if BYTE_ORDER == BIG_ENDIAN 891 u_int32_t ti_cmd:8; 892 u_int32_t ti_code:12; 893 u_int32_t ti_idx:12; 894 #else 895 u_int32_t ti_idx:12; 896 u_int32_t ti_code:12; 897 u_int32_t ti_cmd:8; 898 #endif 899 }; 900 901 #define TI_CMD_HOST_STATE 0x01 902 #define TI_CMD_CODE_STACK_UP 0x01 903 #define TI_CMD_CODE_STACK_DOWN 0x02 904 905 /* 906 * This command enables software address filtering. It's a workaround 907 * for a bug in the Tigon 1 and not implemented for the Tigon 2. 908 */ 909 #define TI_CMD_FDR_FILTERING 0x02 910 #define TI_CMD_CODE_FILT_ENB 0x01 911 #define TI_CMD_CODE_FILT_DIS 0x02 912 913 #define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */ 914 #define TI_CMD_UPDATE_GENCOM 0x04 915 #define TI_CMD_RESET_JUMBO_RING 0x05 916 #define TI_CMD_SET_PARTIAL_RX_CNT 0x06 917 #define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */ 918 #define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */ 919 920 #define TI_CMD_SET_PROMISC_MODE 0x0A 921 #define TI_CMD_CODE_PROMISC_ENB 0x01 922 #define TI_CMD_CODE_PROMISC_DIS 0x02 923 924 #define TI_CMD_LINK_NEGOTIATION 0x0B 925 #define TI_CMD_CODE_NEGOTIATE_BOTH 0x00 926 #define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01 927 #define TI_CMD_CODE_NEGOTIATE_10_100 0x02 928 929 #define TI_CMD_SET_MAC_ADDR 0x0C 930 #define TI_CMD_CLR_PROFILE 0x0D 931 932 #define TI_CMD_SET_ALLMULTI 0x0E 933 #define TI_CMD_CODE_ALLMULTI_ENB 0x01 934 #define TI_CMD_CODE_ALLMULTI_DIS 0x02 935 936 #define TI_CMD_CLR_STATS 0x0F 937 #define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */ 938 #define TI_CMD_RFRSH_STATS 0x11 939 940 #define TI_CMD_EXT_ADD_MCAST 0x12 941 #define TI_CMD_EXT_DEL_MCAST 0x13 942 943 /* 944 * Utility macros to make issuing commands a little simpler. Assumes 945 * that 'sc' and 'cmd' are in local scope. 946 */ 947 #define TI_DO_CMD(x, y, z) \ 948 cmd.ti_cmd = x; \ 949 cmd.ti_code = y; \ 950 cmd.ti_idx = z; \ 951 ti_cmd(sc, &cmd); 952 953 #define TI_DO_CMD_EXT(x, y, z, v, w) \ 954 cmd.ti_cmd = x; \ 955 cmd.ti_code = y; \ 956 cmd.ti_idx = z; \ 957 ti_cmd_ext(sc, &cmd, v, w); 958 959 /* 960 * Other utility macros. 961 */ 962 #define TI_INC(x, y) (x) = (x + 1) % y 963 964 #define TI_UPDATE_JUMBOPROD(x, y) \ 965 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 966 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y); \ 967 } else { \ 968 CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y); \ 969 } 970 971 #define TI_UPDATE_MINIPROD(x, y) \ 972 CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y); 973 974 #define TI_UPDATE_STDPROD(x, y) \ 975 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 976 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y); \ 977 } else { \ 978 CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y); \ 979 } 980 981 982 /* 983 * Tigon event structure. 984 */ 985 struct ti_event_desc { 986 #if BYTE_ORDER == BIG_ENDIAN 987 u_int32_t ti_event:8; 988 u_int32_t ti_code:12; 989 u_int32_t ti_idx:12; 990 #else 991 u_int32_t ti_idx:12; 992 u_int32_t ti_code:12; 993 u_int32_t ti_event:8; 994 #endif 995 u_int32_t ti_rsvd; 996 }; 997 998 /* 999 * Tigon events. 1000 */ 1001 #define TI_EV_FIRMWARE_UP 0x01 1002 #define TI_EV_STATS_UPDATED 0x04 1003 1004 #define TI_EV_LINKSTAT_CHANGED 0x06 1005 #define TI_EV_CODE_GIG_LINK_UP 0x01 1006 #define TI_EV_CODE_LINK_DOWN 0x02 1007 #define TI_EV_CODE_LINK_UP 0x03 1008 1009 #define TI_EV_ERROR 0x07 1010 #define TI_EV_CODE_ERR_INVAL_CMD 0x01 1011 #define TI_EV_CODE_ERR_UNIMP_CMD 0x02 1012 #define TI_EV_CODE_ERR_BADCFG 0x03 1013 1014 #define TI_EV_MCAST_UPDATED 0x08 1015 #define TI_EV_CODE_MCAST_ADD 0x01 1016 #define TI_EV_CODE_MCAST_DEL 0x02 1017 1018 #define TI_EV_RESET_JUMBO_RING 0x09 1019 /* 1020 * Register access macros. The Tigon always uses memory mapped register 1021 * accesses and all registers must be accessed with 32 bit operations. 1022 */ 1023 1024 #define CSR_WRITE_4(sc, reg, val) \ 1025 bus_space_write_4(sc->ti_btag, sc->ti_bhandle, reg, val) 1026 1027 #define CSR_READ_4(sc, reg) \ 1028 bus_space_read_4(sc->ti_btag, sc->ti_bhandle, reg) 1029 1030 #define TI_SETBIT(sc, reg, x) \ 1031 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 1032 #define TI_CLRBIT(sc, reg, x) \ 1033 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 1034 1035 /* 1036 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 1037 * values are tuneable. They control the actual amount of buffers 1038 * allocated for the standard, mini and jumbo receive rings. 1039 */ 1040 1041 #define TI_SSLOTS 256 1042 #define TI_MSLOTS 256 1043 #define TI_JSLOTS 384 1044 1045 #define TI_JRAWLEN (TI_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t)) 1046 #define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \ 1047 (TI_JRAWLEN % sizeof(u_int64_t)))) 1048 #define TI_JPAGESZ PAGE_SIZE 1049 #define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ) 1050 #define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID) 1051 1052 struct ti_jslot { 1053 caddr_t ti_buf; 1054 int ti_inuse; 1055 }; 1056 1057 /* 1058 * Ring structures. Most of these reside in host memory and we tell 1059 * the NIC where they are via the ring control blocks. The exceptions 1060 * are the tx and command rings, which live in NIC memory and which 1061 * we access via the shared memory window. 1062 */ 1063 struct ti_ring_data { 1064 struct ti_rx_desc ti_rx_std_ring[TI_STD_RX_RING_CNT]; 1065 struct ti_rx_desc ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT]; 1066 struct ti_rx_desc ti_rx_mini_ring[TI_MINI_RX_RING_CNT]; 1067 struct ti_rx_desc ti_rx_return_ring[TI_RETURN_RING_CNT]; 1068 struct ti_event_desc ti_event_ring[TI_EVENT_RING_CNT]; 1069 struct ti_tx_desc ti_tx_ring[TI_TX_RING_CNT]; 1070 /* 1071 * Make sure producer structures are aligned on 32-byte cache 1072 * line boundaries. 1073 */ 1074 struct ti_producer ti_ev_prodidx_r; 1075 u_int32_t ti_pad0[6]; 1076 struct ti_producer ti_return_prodidx_r; 1077 u_int32_t ti_pad1[6]; 1078 struct ti_producer ti_tx_considx_r; 1079 u_int32_t ti_pad2[6]; 1080 struct ti_tx_desc *ti_tx_ring_nic;/* pointer to shared mem */ 1081 struct ti_cmd_desc *ti_cmd_ring; /* pointer to shared mem */ 1082 struct ti_gib ti_info; 1083 }; 1084 1085 /* 1086 * Mbuf pointers. We need these to keep track of the virtual addresses 1087 * of our mbuf chains since we can only convert from physical to virtual, 1088 * not the other way around. 1089 */ 1090 struct ti_chain_data { 1091 struct mbuf *ti_tx_chain[TI_TX_RING_CNT]; 1092 struct mbuf *ti_rx_std_chain[TI_STD_RX_RING_CNT]; 1093 struct mbuf *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT]; 1094 struct mbuf *ti_rx_mini_chain[TI_MINI_RX_RING_CNT]; 1095 /* Stick the jumbo mem management stuff here too. */ 1096 struct ti_jslot ti_jslots[TI_JSLOTS]; 1097 void *ti_jumbo_buf; 1098 }; 1099 1100 struct ti_type { 1101 u_int16_t ti_vid; 1102 u_int16_t ti_did; 1103 char *ti_name; 1104 }; 1105 1106 #define TI_HWREV_TIGON 0x01 1107 #define TI_HWREV_TIGON_II 0x02 1108 #define TI_TIMEOUT 1000 1109 #define TI_TXCONS_UNSET 0xFFFF /* impossible value */ 1110 1111 struct ti_mc_entry { 1112 struct ether_addr mc_addr; 1113 SLIST_ENTRY(ti_mc_entry) mc_entries; 1114 }; 1115 1116 struct ti_jpool_entry { 1117 int slot; 1118 SLIST_ENTRY(ti_jpool_entry) jpool_entries; 1119 }; 1120 1121 struct ti_softc { 1122 struct arpcom arpcom; /* interface info */ 1123 bus_space_handle_t ti_bhandle; 1124 vm_offset_t ti_vhandle; 1125 bus_space_tag_t ti_btag; 1126 void *ti_intrhand; 1127 struct resource *ti_irq; 1128 struct resource *ti_res; 1129 struct ifmedia ifmedia; /* media info */ 1130 u_int8_t ti_unit; /* interface number */ 1131 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1132 u_int8_t ti_copper; /* 1000baseTX card */ 1133 u_int8_t ti_linkstat; /* Link state */ 1134 struct ti_ring_data *ti_rdata; /* rings */ 1135 struct ti_chain_data ti_cdata; /* mbufs */ 1136 #define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r 1137 #define ti_return_prodidx ti_rdata->ti_return_prodidx_r 1138 #define ti_tx_considx ti_rdata->ti_tx_considx_r 1139 u_int16_t ti_tx_saved_considx; 1140 u_int16_t ti_rx_saved_considx; 1141 u_int16_t ti_ev_saved_considx; 1142 u_int16_t ti_cmd_saved_prodidx; 1143 u_int16_t ti_std; /* current std ring head */ 1144 u_int16_t ti_mini; /* current mini ring head */ 1145 u_int16_t ti_jumbo; /* current jumo ring head */ 1146 SLIST_HEAD(__ti_mchead, ti_mc_entry) ti_mc_listhead; 1147 SLIST_HEAD(__ti_jfreehead, ti_jpool_entry) ti_jfree_listhead; 1148 SLIST_HEAD(__ti_jinusehead, ti_jpool_entry) ti_jinuse_listhead; 1149 u_int32_t ti_stat_ticks; 1150 u_int32_t ti_rx_coal_ticks; 1151 u_int32_t ti_tx_coal_ticks; 1152 u_int32_t ti_rx_max_coal_bds; 1153 u_int32_t ti_tx_max_coal_bds; 1154 u_int32_t ti_tx_buf_ratio; 1155 int ti_if_flags; 1156 int ti_txcnt; 1157 }; 1158 1159 /* 1160 * Microchip Technology 24Cxx EEPROM control bytes 1161 */ 1162 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 1163 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 1164 1165 /* 1166 * Note that EEPROM_START leaves transmission enabled. 1167 */ 1168 #define EEPROM_START \ 1169 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\ 1170 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */ \ 1171 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\ 1172 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\ 1173 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1174 1175 /* 1176 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 1177 * that no further data can be written to the EEPROM I/O pin. 1178 */ 1179 #define EEPROM_STOP \ 1180 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */ \ 1181 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \ 1182 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */ \ 1183 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */ \ 1184 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */ \ 1185 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */ \ 1186 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1187 1188 1189 #ifdef __alpha__ 1190 #undef vtophys 1191 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1192 #endif
Cache object: 72593676905d4bbd39dad67cfdfaf843
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