The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_tireg.h

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    1 /*-
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: src/sys/pci/if_tireg.h,v 1.28.2.1 2005/01/31 23:26:51 imp Exp $
   33  */
   34 
   35 /*
   36  * Tigon register offsets. These are memory mapped registers
   37  * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
   38  * Each register must be accessed using 32 bit operations.
   39  *
   40  * All reegisters are accessed through a 16K shared memory block.
   41  * The first group of registers are actually copies of the PCI
   42  * configuration space registers.
   43  */
   44 
   45 #define TI_PCI_ID                       0x000 /* PCI device/vendor ID */
   46 #define TI_PCI_CMDSTAT                  0x004
   47 #define TI_PCI_CLASSCODE                0x008
   48 #define TI_PCI_BIST                     0x00C
   49 #define TI_PCI_LOMEM                    0x010 /* Shared memory base address */
   50 #define TI_PCI_SUBSYS                   0x02C
   51 #define TI_PCI_ROMBASE                  0x030
   52 #define TI_PCI_INT                      0x03C
   53 
   54 #ifndef PCIM_CMD_MWIEN
   55 #define PCIM_CMD_MWIEN                  0x0010
   56 #endif
   57 
   58 /*
   59  * Alteon AceNIC PCI vendor/device ID.
   60  */
   61 #define ALT_VENDORID                    0x12AE
   62 #define ALT_DEVICEID_ACENIC             0x0001
   63 #define ALT_DEVICEID_ACENIC_COPPER      0x0002
   64 
   65 /*
   66  * 3Com 3c985 PCI vendor/device ID.
   67  */
   68 #define TC_VENDORID                     0x10B7
   69 #define TC_DEVICEID_3C985               0x0001
   70 
   71 /*
   72  * Netgear GA620 PCI vendor/device ID.
   73  */
   74 #define NG_VENDORID                     0x1385
   75 #define NG_DEVICEID_GA620               0x620A
   76 #define NG_DEVICEID_GA620T              0x630A
   77 
   78 /*
   79  * SGI device/vendor ID.
   80  */
   81 #define SGI_VENDORID                    0x10A9
   82 #define SGI_DEVICEID_TIGON              0x0009
   83 
   84 /*
   85  * DEC vendor ID, Farallon device ID. Apparently, Farallon used
   86  * the DEC vendor ID in their cards by mistake.
   87  */
   88 #define DEC_VENDORID                    0x1011
   89 #define DEC_DEVICEID_FARALLON_PN9000SX  0x001a
   90 
   91 /*
   92  * Tigon configuration and control registers.
   93  */
   94 #define TI_MISC_HOST_CTL                0x040
   95 #define TI_MISC_LOCAL_CTL               0x044
   96 #define TI_SEM_AB                       0x048 /* Tigon 2 only */
   97 #define TI_MISC_CONF                    0x050 /* Tigon 2 only */
   98 #define TI_TIMER_BITS                   0x054
   99 #define TI_TIMERREF                     0x058
  100 #define TI_PCI_STATE                    0x05C
  101 #define TI_MAIN_EVENT_A                 0x060
  102 #define TI_MAILBOX_EVENT_A              0x064
  103 #define TI_WINBASE                      0x068
  104 #define TI_WINDATA                      0x06C
  105 #define TI_MAIN_EVENT_B                 0x070 /* Tigon 2 only */
  106 #define TI_MAILBOX_EVENT_B              0x074 /* Tigon 2 only */
  107 #define TI_TIMERREF_B                   0x078 /* Tigon 2 only */
  108 #define TI_SERIAL                       0x07C
  109 
  110 /*
  111  * Misc host control bits.
  112  */
  113 #define TI_MHC_INTSTATE                 0x00000001
  114 #define TI_MHC_CLEARINT                 0x00000002
  115 #define TI_MHC_RESET                    0x00000008
  116 #define TI_MHC_BYTE_SWAP_ENB            0x00000010
  117 #define TI_MHC_WORD_SWAP_ENB            0x00000020
  118 #define TI_MHC_MASK_INTS                0x00000040
  119 #define TI_MHC_CHIP_REV_MASK            0xF0000000
  120 
  121 #define TI_MHC_BIGENDIAN_INIT   \
  122         (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
  123 
  124 #define TI_MHC_LITTLEENDIAN_INIT        \
  125         (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
  126 
  127 /*
  128  * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2.
  129  * Rev 5 is also the Tigon 2, but is a broken version which was never
  130  * used in any actual hardware, so we ignore it.
  131  */
  132 #define TI_REV_TIGON_I                  0x40000000
  133 #define TI_REV_TIGON_II                 0x60000000
  134 
  135 /*
  136  * Firmware revision that we want.
  137  */
  138 #define TI_FIRMWARE_MAJOR               0xc
  139 #define TI_FIRMWARE_MINOR               0x4
  140 #define TI_FIRMWARE_FIX                 0xb
  141 
  142 /*
  143  * Miscelaneous Local Control register.
  144  */
  145 #define TI_MLC_EE_WRITE_ENB             0x00000010
  146 #define TI_MLC_SRAM_BANK_SIZE           0x00000300 /* Tigon 2 only */
  147 #define TI_MLC_LOCALADDR_21             0x00004000
  148 #define TI_MLC_LOCALADDR_22             0x00008000
  149 #define TI_MLC_SBUS_WRITEERR            0x00080000
  150 #define TI_MLC_EE_CLK                   0x00100000
  151 #define TI_MLC_EE_TXEN                  0x00200000
  152 #define TI_MLC_EE_DOUT                  0x00400000
  153 #define TI_MLC_EE_DIN                   0x00800000
  154 
  155 /* Possible memory sizes. */
  156 #define TI_MLC_SRAM_BANK_DISA           0x00000000
  157 #define TI_MLC_SRAM_BANK_1024K          0x00000100
  158 #define TI_MLC_SRAM_BANK_512K           0x00000200
  159 #define TI_MLC_SRAM_BANK_256K           0x00000300
  160 
  161 /*
  162  * Offset of MAC address inside EEPROM.
  163  */
  164 #define TI_EE_MAC_OFFSET                0x8c
  165 
  166 #define TI_DMA_ASSIST                   0x11C
  167 #define TI_CPU_STATE                    0x140
  168 #define TI_CPU_PROGRAM_COUNTER          0x144
  169 #define TI_SRAM_ADDR                    0x154
  170 #define TI_SRAM_DATA                    0x158
  171 #define TI_GEN_0                        0x180
  172 #define TI_GEN_X                        0x1FC
  173 #define TI_MAC_TX_STATE                 0x200
  174 #define TI_MAC_RX_STATE                 0x220
  175 #define TI_CPU_CTL_B                    0x240 /* Tigon 2 only */
  176 #define TI_CPU_PROGRAM_COUNTER_B        0x244 /* Tigon 2 only */
  177 #define TI_SRAM_ADDR_B                  0x254 /* Tigon 2 only */
  178 #define TI_SRAM_DATA_B                  0x258 /* Tigon 2 only */
  179 #define TI_GEN_B_0                      0x280 /* Tigon 2 only */
  180 #define TI_GEN_B_X                      0x2FC /* Tigon 2 only */
  181 
  182 /*
  183  * Misc config register.
  184  */
  185 #define TI_MCR_SRAM_SYNCHRONOUS         0x00100000 /* Tigon 2 only */
  186 
  187 /*
  188  * PCI state register.
  189  */
  190 #define TI_PCISTATE_FORCE_RESET         0x00000001
  191 #define TI_PCISTATE_PROVIDE_LEN         0x00000002
  192 #define TI_PCISTATE_READ_MAXDMA         0x0000001C
  193 #define TI_PCISTATE_WRITE_MAXDMA        0x000000E0
  194 #define TI_PCISTATE_MINDMA              0x0000FF00
  195 #define TI_PCISTATE_FIFO_RETRY_ENB      0x00010000
  196 #define TI_PCISTATE_USE_MEM_RD_MULT     0x00020000
  197 #define TI_PCISTATE_NO_SWAP_READ_DMA    0x00040000
  198 #define TI_PCISTATE_NO_SWAP_WRITE_DMA   0x00080000
  199 #define TI_PCISTATE_66MHZ_BUS           0x00080000 /* Tigon 2 only */
  200 #define TI_PCISTATE_32BIT_BUS           0x00100000 /* Tigon 2 only */
  201 #define TI_PCISTATE_ENB_BYTE_ENABLES    0x00800000 /* Tigon 2 only */
  202 #define TI_PCISTATE_READ_CMD            0x0F000000
  203 #define TI_PCISTATE_WRITE_CMD           0xF0000000
  204 
  205 #define TI_PCI_READMAX_4                0x04
  206 #define TI_PCI_READMAX_16               0x08
  207 #define TI_PCI_READMAX_32               0x0C
  208 #define TI_PCI_READMAX_64               0x10
  209 #define TI_PCI_READMAX_128              0x14
  210 #define TI_PCI_READMAX_256              0x18
  211 #define TI_PCI_READMAX_1024             0x1C
  212 
  213 #define TI_PCI_WRITEMAX_4               0x20
  214 #define TI_PCI_WRITEMAX_16              0x40
  215 #define TI_PCI_WRITEMAX_32              0x60
  216 #define TI_PCI_WRITEMAX_64              0x80
  217 #define TI_PCI_WRITEMAX_128             0xA0
  218 #define TI_PCI_WRITEMAX_256             0xC0
  219 #define TI_PCI_WRITEMAX_1024            0xE0
  220 
  221 #define TI_PCI_READ_CMD                 0x06000000
  222 #define TI_PCI_WRITE_CMD                0x70000000
  223 
  224 /*
  225  * DMA state register.
  226  */
  227 #define TI_DMASTATE_ENABLE              0x00000001
  228 #define TI_DMASTATE_PAUSE               0x00000002
  229 
  230 /*
  231  * CPU state register.
  232  */
  233 #define TI_CPUSTATE_RESET               0x00000001
  234 #define TI_CPUSTATE_STEP                0x00000002
  235 #define TI_CPUSTATE_ROMFAIL             0x00000010
  236 #define TI_CPUSTATE_HALT                0x00010000
  237 /*
  238  * MAC TX state register
  239  */
  240 #define TI_TXSTATE_RESET                0x00000001
  241 #define TI_TXSTATE_ENB                  0x00000002
  242 #define TI_TXSTATE_STOP                 0x00000004
  243 
  244 /*
  245  * MAC RX state register
  246  */
  247 #define TI_RXSTATE_RESET                0x00000001
  248 #define TI_RXSTATE_ENB                  0x00000002
  249 #define TI_RXSTATE_STOP                 0x00000004
  250 
  251 /*
  252  * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes
  253  * split into 64 bit registers. Only the lower 32 bits of each mailbox
  254  * are used.
  255  */
  256 #define TI_MB_HOSTINTR_HI               0x500
  257 #define TI_MB_HOSTINTR_LO               0x504
  258 #define TI_MB_HOSTINTR                  TI_MB_HOSTINTR_LO
  259 #define TI_MB_CMDPROD_IDX_HI            0x508
  260 #define TI_MB_CMDPROD_IDX_LO            0x50C
  261 #define TI_MB_CMDPROD_IDX               TI_MB_CMDPROD_IDX_LO
  262 #define TI_MB_SENDPROD_IDX_HI           0x510
  263 #define TI_MB_SENDPROD_IDX_LO           0x514
  264 #define TI_MB_SENDPROD_IDX              TI_MB_SENDPROD_IDX_LO
  265 #define TI_MB_STDRXPROD_IDX_HI          0x518 /* Tigon 2 only */
  266 #define TI_MB_STDRXPROD_IDX_LO          0x51C /* Tigon 2 only */
  267 #define TI_MB_STDRXPROD_IDX             TI_MB_STDRXPROD_IDX_LO
  268 #define TI_MB_JUMBORXPROD_IDX_HI        0x520 /* Tigon 2 only */
  269 #define TI_MB_JUMBORXPROD_IDX_LO        0x524 /* Tigon 2 only */
  270 #define TI_MB_JUMBORXPROD_IDX           TI_MB_JUMBORXPROD_IDX_LO
  271 #define TI_MB_MINIRXPROD_IDX_HI         0x528 /* Tigon 2 only */
  272 #define TI_MB_MINIRXPROD_IDX_LO         0x52C /* Tigon 2 only */
  273 #define TI_MB_MINIRXPROD_IDX            TI_MB_MINIRXPROD_IDX_LO
  274 #define TI_MB_RSVD                      0x530
  275 
  276 /*
  277  * Tigon 2 general communication registers. These are 64 and 32 bit
  278  * registers which are only valid after the firmware has been
  279  * loaded and started. They actually exist in NIC memory but are
  280  * mapped into the host memory via the shared memory region.
  281  *
  282  * The NIC internally maps these registers starting at address 0,
  283  * so to determine the NIC address of any of these registers, we
  284  * subtract 0x600 (the address of the first register).
  285  */
  286 
  287 #define TI_GCR_BASE                     0x600
  288 #define TI_GCR_MACADDR                  0x600
  289 #define TI_GCR_PAR0                     0x600
  290 #define TI_GCR_PAR1                     0x604
  291 #define TI_GCR_GENINFO_HI               0x608
  292 #define TI_GCR_GENINFO_LO               0x60C
  293 #define TI_GCR_MCASTADDR                0x610 /* obsolete */
  294 #define TI_GCR_MAR0                     0x610 /* obsolete */
  295 #define TI_GCR_MAR1                     0x614 /* obsolete */
  296 #define TI_GCR_OPMODE                   0x618
  297 #define TI_GCR_DMA_READCFG              0x61C
  298 #define TI_GCR_DMA_WRITECFG             0x620
  299 #define TI_GCR_TX_BUFFER_RATIO          0x624
  300 #define TI_GCR_EVENTCONS_IDX            0x628
  301 #define TI_GCR_CMDCONS_IDX              0x62C
  302 #define TI_GCR_TUNEPARMS                0x630
  303 #define TI_GCR_RX_COAL_TICKS            0x630
  304 #define TI_GCR_TX_COAL_TICKS            0x634
  305 #define TI_GCR_STAT_TICKS               0x638
  306 #define TI_GCR_TX_MAX_COAL_BD           0x63C
  307 #define TI_GCR_RX_MAX_COAL_BD           0x640
  308 #define TI_GCR_NIC_TRACING              0x644
  309 #define TI_GCR_GLINK                    0x648
  310 #define TI_GCR_LINK                     0x64C
  311 #define TI_GCR_NICTRACE_PTR             0x650
  312 #define TI_GCR_NICTRACE_START           0x654
  313 #define TI_GCR_NICTRACE_LEN             0x658
  314 #define TI_GCR_IFINDEX                  0x65C
  315 #define TI_GCR_IFMTU                    0x660
  316 #define TI_GCR_MASK_INTRS               0x664
  317 #define TI_GCR_GLINK_STAT               0x668
  318 #define TI_GCR_LINK_STAT                0x66C
  319 #define TI_GCR_RXRETURNCONS_IDX         0x680
  320 #define TI_GCR_CMDRING                  0x700
  321 
  322 #define TI_GCR_NIC_ADDR(x)              (x - TI_GCR_BASE);
  323 
  324 /*
  325  * Local memory window. The local memory window is a 2K shared
  326  * memory region which can be used to access the NIC's internal
  327  * SRAM. The window can be mapped to a given 2K region using
  328  * the TI_WINDOW_BASE register.
  329  */
  330 #define TI_WINDOW                       0x800
  331 #define TI_WINLEN                       0x800
  332 
  333 #define TI_TICKS_PER_SEC                1000000
  334 
  335 /*
  336  * Operation mode register.
  337  */
  338 #define TI_OPMODE_BYTESWAP_BD           0x00000002
  339 #define TI_OPMODE_WORDSWAP_BD           0x00000004
  340 #define TI_OPMODE_WARN_ENB              0x00000008 /* not yet implimented */
  341 #define TI_OPMODE_BYTESWAP_DATA         0x00000010
  342 #define TI_OPMODE_1_DMA_ACTIVE          0x00000040
  343 #define TI_OPMODE_SBUS                  0x00000100
  344 #define TI_OPMODE_DONT_FRAG_JUMBO       0x00000200
  345 #define TI_OPMODE_INCLUDE_CRC           0x00000400
  346 #define TI_OPMODE_RX_BADFRAMES          0x00000800
  347 #define TI_OPMODE_NO_EVENT_INTRS        0x00001000
  348 #define TI_OPMODE_NO_TX_INTRS           0x00002000
  349 #define TI_OPMODE_NO_RX_INTRS           0x00004000
  350 #define TI_OPMODE_FATAL_ENB             0x40000000 /* not yet implimented */
  351 #define TI_OPMODE_JUMBO_HDRSPLIT        0x00008000
  352 
  353 /*
  354  * DMA configuration thresholds.
  355  */
  356 #define TI_DMA_STATE_THRESH_16W         0x00000100
  357 #define TI_DMA_STATE_THRESH_8W          0x00000080
  358 #define TI_DMA_STATE_THRESH_4W          0x00000040
  359 #define TI_DMA_STATE_THRESH_2W          0x00000020
  360 #define TI_DMA_STATE_THRESH_1W          0x00000010
  361 
  362 #define TI_DMA_STATE_FORCE_32_BIT       0x00000008
  363 
  364 /*
  365  * Gigabit link status bits.
  366  */
  367 #define TI_GLNK_SENSE_NO_BEG            0x00002000
  368 #define TI_GLNK_LOOPBACK                0x00004000
  369 #define TI_GLNK_PREF                    0x00008000
  370 #define TI_GLNK_1000MB                  0x00040000
  371 #define TI_GLNK_FULL_DUPLEX             0x00080000
  372 #define TI_GLNK_TX_FLOWCTL_Y            0x00200000 /* Tigon 2 only */
  373 #define TI_GLNK_RX_FLOWCTL_Y            0x00800000
  374 #define TI_GLNK_AUTONEGENB              0x20000000
  375 #define TI_GLNK_ENB                     0x40000000
  376 
  377 /*
  378  * Link status bits.
  379  */
  380 #define TI_LNK_LOOPBACK                 0x00004000
  381 #define TI_LNK_PREF                     0x00008000
  382 #define TI_LNK_10MB                     0x00010000
  383 #define TI_LNK_100MB                    0x00020000
  384 #define TI_LNK_1000MB                   0x00040000
  385 #define TI_LNK_FULL_DUPLEX              0x00080000
  386 #define TI_LNK_HALF_DUPLEX              0x00100000
  387 #define TI_LNK_TX_FLOWCTL_Y             0x00200000 /* Tigon 2 only */
  388 #define TI_LNK_RX_FLOWCTL_Y             0x00800000
  389 #define TI_LNK_AUTONEGENB               0x20000000
  390 #define TI_LNK_ENB                      0x40000000
  391 
  392 /*
  393  * Ring size constants.
  394  */
  395 #define TI_EVENT_RING_CNT       256
  396 #define TI_CMD_RING_CNT         64
  397 #define TI_STD_RX_RING_CNT      512
  398 #define TI_JUMBO_RX_RING_CNT    256
  399 #define TI_MINI_RX_RING_CNT     1024
  400 #define TI_RETURN_RING_CNT      2048
  401 
  402 /*
  403  * Possible TX ring sizes.
  404  */
  405 #define TI_TX_RING_CNT_128      128
  406 #define TI_TX_RING_BASE_128     0x3800
  407 
  408 #define TI_TX_RING_CNT_256      256
  409 #define TI_TX_RING_BASE_256     0x3000
  410 
  411 #define TI_TX_RING_CNT_512      512
  412 #define TI_TX_RING_BASE_512     0x2000
  413 
  414 #define TI_TX_RING_CNT          TI_TX_RING_CNT_512
  415 #define TI_TX_RING_BASE         TI_TX_RING_BASE_512
  416 
  417 /*
  418  * The Tigon can have up to 8MB of external SRAM, however the Tigon 1
  419  * is limited to 2MB total, and in general I think most adapters have
  420  * around 1MB. We use this value for zeroing the NIC's SRAM, so to
  421  * be safe we use the largest possible value (zeroing memory that
  422  * isn't there doesn't hurt anything).
  423  */
  424 #define TI_MEM_MAX              0x7FFFFF
  425 
  426 /*
  427  * Maximum register address on the Tigon.
  428  */
  429 #define TI_REG_MAX              0x3fff
  430 
  431 /*
  432  * These values were taken from Alteon's tg.h.
  433  */
  434 #define TI_BEG_SRAM     0x0             /* host thinks it's here */
  435 #define TI_BEG_SCRATCH  0xc00000        /* beg of scratch pad area */
  436 #define TI_END_SRAM_II     0x800000        /* end of SRAM, for 2 MB stuffed */
  437 #define TI_END_SCRATCH_II  0xc04000        /* end of scratch pad CPU A (16KB) */
  438 #define TI_END_SCRATCH_B 0xc02000       /* end of scratch pad CPU B (8KB) */
  439 #define TI_BEG_SCRATCH_B_DEBUG 0xd00000 /* beg of scratch pad for ioctl */
  440 #define TI_END_SCRATCH_B_DEBUG 0xd02000 /* end of scratch pad for ioctl */
  441 #define TI_SCRATCH_DEBUG_OFF 0x100000   /* offset for ioctl usage */
  442 #define TI_END_SRAM_I     0x200000        /* end of SRAM, for 2 MB stuffed */
  443 #define TI_END_SCRATCH_I  0xc00800        /* end of scratch pad area (2KB) */
  444 #define TI_BEG_PROM     0x40000000      /* beg of PROM, special access */
  445 #define TI_BEG_FLASH    0x80000000      /* beg of EEPROM, special access */
  446 #define TI_END_FLASH    0x80100000      /* end of EEPROM for 1 MB stuff */
  447 #define TI_BEG_SER_EEPROM 0xa0000000    /* beg of Serial EEPROM (fake out) */
  448 #define TI_END_SER_EEPROM 0xa0002000    /* end of Serial EEPROM (fake out) */
  449 #define TI_BEG_REGS     0xc0000000      /* beg of register area */
  450 #define TI_END_REGS     0xc0000400      /* end of register area */
  451 #define TI_END_WRITE_REGS 0xc0000180    /* can't write GPRs currently */
  452 #define TI_BEG_REGS2    0xc0000200      /* beg of second writeable reg area */
  453 /* the EEPROM is byte addressable in a pretty odd way */
  454 #define EEPROM_BYTE_LOC 0xff000000      
  455 
  456 /*
  457  * From Alteon's tg.h.
  458  */
  459 #define TI_PROCESSOR_A          0
  460 #define TI_PROCESSOR_B          1
  461 #define TI_CPU_A                TG_PROCESSOR_A
  462 #define TI_CPU_B                TG_PROCESSOR_B
  463 
  464 /*
  465  * Following macro can be used to access to any of the CPU registers
  466  * It will adjust the address appropriately.
  467  * Parameters:
  468  *      reg - The register to access, e.g TI_CPU_CONTROL
  469  *      cpu - cpu, i.e PROCESSOR_A or PROCESSOR_B (or TI_CPU_A or TI_CPU_B)
  470  */
  471 #define CPU_REG(reg, cpu) ((reg) + (cpu) * 0x100)
  472 
  473 /*
  474  * Even on the alpha, pci addresses are 32-bit quantities
  475  */
  476 
  477 #ifdef __64_bit_pci_addressing__ 
  478 typedef struct {
  479         u_int64_t               ti_addr;
  480 } ti_hostaddr;
  481 #define TI_HOSTADDR(x)  x.ti_addr
  482 #else
  483 typedef struct {
  484         u_int32_t               ti_addr_hi;
  485         u_int32_t               ti_addr_lo;
  486 } ti_hostaddr;
  487 #define TI_HOSTADDR(x)  x.ti_addr_lo
  488 #endif
  489 
  490 /*
  491  * Ring control block structure. The rules for the max_len field
  492  * are as follows:
  493  * 
  494  * For the send ring, max_len indicates the number of entries in the
  495  * ring (128, 256 or 512).
  496  *
  497  * For the standard receive ring, max_len indicates the threshold
  498  * used to decide when a frame should be put in the jumbo receive ring
  499  * instead of the standard one.
  500  *
  501  * For the mini ring, max_len indicates the size of the buffers in the
  502  * ring. This is the value used to decide when a frame is small enough
  503  * to be placed in the mini ring.
  504  *
  505  * For the return receive ring, max_len indicates the number of entries
  506  * in the ring. It can be one of 2048, 1024 or 0 (which is the same as
  507  * 2048 for backwards compatibility). The value 1024 can only be used
  508  * if the mini ring is disabled.
  509  */
  510 struct ti_rcb {
  511         ti_hostaddr             ti_hostaddr;
  512 #if BYTE_ORDER == BIG_ENDIAN
  513         u_int16_t               ti_max_len;
  514         u_int16_t               ti_flags;
  515 #else
  516         u_int16_t               ti_flags;
  517         u_int16_t               ti_max_len;
  518 #endif
  519         u_int32_t               ti_unused;
  520 };
  521 
  522 #define TI_RCB_FLAG_TCP_UDP_CKSUM       0x00000001
  523 #define TI_RCB_FLAG_IP_CKSUM            0x00000002
  524 #define TI_RCB_FLAG_NO_PHDR_CKSUM       0x00000008
  525 #define TI_RCB_FLAG_VLAN_ASSIST         0x00000010
  526 #define TI_RCB_FLAG_COAL_UPD_ONLY       0x00000020
  527 #define TI_RCB_FLAG_HOST_RING           0x00000040
  528 #define TI_RCB_FLAG_IEEE_SNAP_CKSUM     0x00000080
  529 #define TI_RCB_FLAG_USE_EXT_RX_BD       0x00000100
  530 #define TI_RCB_FLAG_RING_DISABLED       0x00000200
  531 
  532 struct ti_producer {
  533         u_int32_t               ti_idx;
  534         u_int32_t               ti_unused;
  535 };
  536 
  537 /*
  538  * Tigon general information block. This resides in host memory
  539  * and contains the status counters, ring control blocks and
  540  * producer pointers.
  541  */
  542 
  543 struct ti_gib {
  544         struct ti_stats         ti_stats;
  545         struct ti_rcb           ti_ev_rcb;
  546         struct ti_rcb           ti_cmd_rcb;
  547         struct ti_rcb           ti_tx_rcb;
  548         struct ti_rcb           ti_std_rx_rcb;
  549         struct ti_rcb           ti_jumbo_rx_rcb;
  550         struct ti_rcb           ti_mini_rx_rcb;
  551         struct ti_rcb           ti_return_rcb;
  552         ti_hostaddr             ti_ev_prodidx_ptr;
  553         ti_hostaddr             ti_return_prodidx_ptr;
  554         ti_hostaddr             ti_tx_considx_ptr;
  555         ti_hostaddr             ti_refresh_stats_ptr;
  556 };
  557 
  558 /*
  559  * Buffer descriptor structures. There are basically three types
  560  * of structures: normal receive descriptors, extended receive
  561  * descriptors and transmit descriptors. The extended receive
  562  * descriptors are optionally used only for the jumbo receive ring.
  563  */
  564 
  565 struct ti_rx_desc {
  566         ti_hostaddr             ti_addr;
  567 #if BYTE_ORDER == BIG_ENDIAN
  568         u_int16_t               ti_idx;
  569         u_int16_t               ti_len;
  570 #else
  571         u_int16_t               ti_len;
  572         u_int16_t               ti_idx;
  573 #endif
  574 #if BYTE_ORDER == BIG_ENDIAN
  575         u_int16_t               ti_type;
  576         u_int16_t               ti_flags;
  577 #else
  578         u_int16_t               ti_flags;
  579         u_int16_t               ti_type;
  580 #endif
  581 #if BYTE_ORDER == BIG_ENDIAN
  582         u_int16_t               ti_ip_cksum;
  583         u_int16_t               ti_tcp_udp_cksum;
  584 #else
  585         u_int16_t               ti_tcp_udp_cksum;
  586         u_int16_t               ti_ip_cksum;
  587 #endif
  588 #if BYTE_ORDER == BIG_ENDIAN
  589         u_int16_t               ti_error_flags;
  590         u_int16_t               ti_vlan_tag;
  591 #else
  592         u_int16_t               ti_vlan_tag;
  593         u_int16_t               ti_error_flags;
  594 #endif
  595         u_int32_t               ti_rsvd;
  596         u_int32_t               ti_opaque;
  597 };
  598 
  599 struct ti_rx_desc_ext {
  600         ti_hostaddr             ti_addr1;
  601         ti_hostaddr             ti_addr2;
  602         ti_hostaddr             ti_addr3;
  603 #if BYTE_ORDER == BIG_ENDIAN
  604         u_int16_t               ti_len1;
  605         u_int16_t               ti_len2;
  606 #else
  607         u_int16_t               ti_len2;
  608         u_int16_t               ti_len1;
  609 #endif
  610 #if BYTE_ORDER == BIG_ENDIAN
  611         u_int16_t               ti_len3;
  612         u_int16_t               ti_rsvd0;
  613 #else
  614         u_int16_t               ti_rsvd0;
  615         u_int16_t               ti_len3;
  616 #endif
  617         ti_hostaddr             ti_addr0;
  618 #if BYTE_ORDER == BIG_ENDIAN
  619         u_int16_t               ti_idx;
  620         u_int16_t               ti_len0;
  621 #else
  622         u_int16_t               ti_len0;
  623         u_int16_t               ti_idx;
  624 #endif
  625 #if BYTE_ORDER == BIG_ENDIAN
  626         u_int16_t               ti_type;
  627         u_int16_t               ti_flags;
  628 #else
  629         u_int16_t               ti_flags;
  630         u_int16_t               ti_type;
  631 #endif
  632 #if BYTE_ORDER == BIG_ENDIAN
  633         u_int16_t               ti_ip_cksum;
  634         u_int16_t               ti_tcp_udp_cksum;
  635 #else
  636         u_int16_t               ti_tcp_udp_cksum;
  637         u_int16_t               ti_ip_cksum;
  638 #endif
  639 #if BYTE_ORDER == BIG_ENDIAN
  640         u_int16_t               ti_error_flags;
  641         u_int16_t               ti_vlan_tag;
  642 #else
  643         u_int16_t               ti_vlan_tag;
  644         u_int16_t               ti_error_flags;
  645 #endif
  646         u_int32_t               ti_rsvd1;
  647         u_int32_t               ti_opaque;
  648 };
  649 
  650 /*
  651  * Transmit descriptors are, mercifully, very small.
  652  */
  653 struct ti_tx_desc {
  654         ti_hostaddr             ti_addr;
  655 #if BYTE_ORDER == BIG_ENDIAN
  656         u_int16_t               ti_len;
  657         u_int16_t               ti_flags;
  658 #else
  659         u_int16_t               ti_flags;
  660         u_int16_t               ti_len;
  661 #endif
  662 #if BYTE_ORDER == BIG_ENDIAN
  663         u_int16_t               ti_rsvd;
  664         u_int16_t               ti_vlan_tag;
  665 #else
  666         u_int16_t               ti_vlan_tag;
  667         u_int16_t               ti_rsvd;
  668 #endif
  669 };
  670 
  671 /*
  672  * NOTE!  On the Alpha, we have an alignment constraint.
  673  * The first thing in the packet is a 14-byte Ethernet header.
  674  * This means that the packet is misaligned.  To compensate,
  675  * we actually offset the data 2 bytes into the cluster.  This
  676  * alignes the packet after the Ethernet header at a 32-bit
  677  * boundary.
  678  */
  679 
  680 #define ETHER_ALIGN 2
  681 
  682 #define TI_FRAMELEN             1518
  683 #define TI_JUMBO_FRAMELEN       9018
  684 #define TI_JUMBO_MTU            (TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
  685 #define TI_PAGE_SIZE            PAGE_SIZE
  686 #define TI_MIN_FRAMELEN         60
  687 
  688 /*
  689  * Buffer descriptor error flags.
  690  */
  691 #define TI_BDERR_CRC                    0x0001
  692 #define TI_BDERR_COLLDETECT             0x0002
  693 #define TI_BDERR_LINKLOST               0x0004
  694 #define TI_BDERR_DECODE                 0x0008
  695 #define TI_BDERR_ODD_NIBBLES            0x0010
  696 #define TI_BDERR_MAC_ABRT               0x0020
  697 #define TI_BDERR_RUNT                   0x0040
  698 #define TI_BDERR_TRUNC                  0x0080
  699 #define TI_BDERR_GIANT                  0x0100
  700 
  701 /*
  702  * Buffer descriptor flags.
  703  */
  704 #define TI_BDFLAG_TCP_UDP_CKSUM         0x0001
  705 #define TI_BDFLAG_IP_CKSUM              0x0002
  706 #define TI_BDFLAG_END                   0x0004
  707 #define TI_BDFLAG_MORE                  0x0008
  708 #define TI_BDFLAG_JUMBO_RING            0x0010
  709 #define TI_BDFLAG_UCAST_PKT             0x0020
  710 #define TI_BDFLAG_MCAST_PKT             0x0040
  711 #define TI_BDFLAG_BCAST_PKT             0x0060
  712 #define TI_BDFLAG_IP_FRAG               0x0080
  713 #define TI_BDFLAG_IP_FRAG_END           0x0100
  714 #define TI_BDFLAG_VLAN_TAG              0x0200
  715 #define TI_BDFLAG_ERROR                 0x0400
  716 #define TI_BDFLAG_COAL_NOW              0x0800
  717 #define TI_BDFLAG_MINI_RING             0x1000
  718 
  719 /*
  720  * Descriptor type flags. I think these only have meaning for
  721  * the Tigon 1. I had to extract them from the sample driver source
  722  * since they aren't in the manual.
  723  */
  724 #define TI_BDTYPE_TYPE_NULL                     0x0000
  725 #define TI_BDTYPE_SEND_BD                       0x0001
  726 #define TI_BDTYPE_RECV_BD                       0x0002
  727 #define TI_BDTYPE_RECV_JUMBO_BD                 0x0003
  728 #define TI_BDTYPE_RECV_BD_LAST                  0x0004
  729 #define TI_BDTYPE_SEND_DATA                     0x0005
  730 #define TI_BDTYPE_SEND_DATA_LAST                0x0006
  731 #define TI_BDTYPE_RECV_DATA                     0x0007
  732 #define TI_BDTYPE_RECV_DATA_LAST                0x000b
  733 #define TI_BDTYPE_EVENT_RUPT                    0x000c
  734 #define TI_BDTYPE_EVENT_NO_RUPT                 0x000d
  735 #define TI_BDTYPE_ODD_START                     0x000e
  736 #define TI_BDTYPE_UPDATE_STATS                  0x000f
  737 #define TI_BDTYPE_SEND_DUMMY_DMA                0x0010
  738 #define TI_BDTYPE_EVENT_PROD                    0x0011
  739 #define TI_BDTYPE_TX_CONS                       0x0012
  740 #define TI_BDTYPE_RX_PROD                       0x0013
  741 #define TI_BDTYPE_REFRESH_STATS                 0x0014
  742 #define TI_BDTYPE_SEND_DATA_LAST_VLAN           0x0015
  743 #define TI_BDTYPE_SEND_DATA_COAL                0x0016
  744 #define TI_BDTYPE_SEND_DATA_LAST_COAL           0x0017
  745 #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL      0x0018
  746 #define TI_BDTYPE_TX_CONS_NO_INTR               0x0019
  747 
  748 /*
  749  * Tigon command structure.
  750  */
  751 struct ti_cmd_desc {
  752 #if BYTE_ORDER == BIG_ENDIAN
  753         u_int32_t               ti_cmd:8;
  754         u_int32_t               ti_code:12;
  755         u_int32_t               ti_idx:12;
  756 #else
  757         u_int32_t               ti_idx:12;
  758         u_int32_t               ti_code:12;
  759         u_int32_t               ti_cmd:8;
  760 #endif
  761 };
  762 
  763 #define TI_CMD_HOST_STATE               0x01
  764 #define TI_CMD_CODE_STACK_UP            0x01
  765 #define TI_CMD_CODE_STACK_DOWN          0x02
  766 
  767 /*
  768  * This command enables software address filtering. It's a workaround
  769  * for a bug in the Tigon 1 and not implemented for the Tigon 2.
  770  */
  771 #define TI_CMD_FDR_FILTERING            0x02
  772 #define TI_CMD_CODE_FILT_ENB            0x01
  773 #define TI_CMD_CODE_FILT_DIS            0x02
  774 
  775 #define TI_CMD_SET_RX_PROD_IDX          0x03 /* obsolete */
  776 #define TI_CMD_UPDATE_GENCOM            0x04
  777 #define TI_CMD_RESET_JUMBO_RING         0x05
  778 #define TI_CMD_SET_PARTIAL_RX_CNT       0x06
  779 #define TI_CMD_ADD_MCAST_ADDR           0x08 /* obsolete */
  780 #define TI_CMD_DEL_MCAST_ADDR           0x09 /* obsolete */
  781 
  782 #define TI_CMD_SET_PROMISC_MODE         0x0A
  783 #define TI_CMD_CODE_PROMISC_ENB         0x01
  784 #define TI_CMD_CODE_PROMISC_DIS         0x02
  785 
  786 #define TI_CMD_LINK_NEGOTIATION         0x0B
  787 #define TI_CMD_CODE_NEGOTIATE_BOTH      0x00
  788 #define TI_CMD_CODE_NEGOTIATE_GIGABIT   0x01
  789 #define TI_CMD_CODE_NEGOTIATE_10_100    0x02
  790 
  791 #define TI_CMD_SET_MAC_ADDR             0x0C
  792 #define TI_CMD_CLR_PROFILE              0x0D
  793 
  794 #define TI_CMD_SET_ALLMULTI             0x0E
  795 #define TI_CMD_CODE_ALLMULTI_ENB        0x01
  796 #define TI_CMD_CODE_ALLMULTI_DIS        0x02
  797 
  798 #define TI_CMD_CLR_STATS                0x0F
  799 #define TI_CMD_SET_RX_JUMBO_PROD_IDX    0x10 /* obsolete */
  800 #define TI_CMD_RFRSH_STATS              0x11
  801 
  802 #define TI_CMD_EXT_ADD_MCAST            0x12
  803 #define TI_CMD_EXT_DEL_MCAST            0x13
  804 
  805 /*
  806  * Utility macros to make issuing commands a little simpler. Assumes
  807  * that 'sc' and 'cmd' are in local scope.
  808  */
  809 #define TI_DO_CMD(x, y, z)              \
  810         cmd.ti_cmd = (x);               \
  811         cmd.ti_code = (y);              \
  812         cmd.ti_idx = (z);               \
  813         ti_cmd(sc, &cmd);
  814 
  815 #define TI_DO_CMD_EXT(x, y, z, v, w)    \
  816         cmd.ti_cmd = (x);               \
  817         cmd.ti_code = (y);              \
  818         cmd.ti_idx = (z);               \
  819         ti_cmd_ext(sc, &cmd, (v), (w));
  820 
  821 /*
  822  * Other utility macros.
  823  */
  824 #define TI_INC(x, y)    (x) = (x + 1) % y
  825 
  826 #define TI_UPDATE_JUMBOPROD(x, y)                                       \
  827         if (x->ti_hwrev == TI_HWREV_TIGON) {                            \
  828                 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y);  \
  829         } else {                                                        \
  830                 CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y);               \
  831         }
  832 
  833 #define TI_UPDATE_MINIPROD(x, y)                                        \
  834                 CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y);
  835 
  836 #define TI_UPDATE_STDPROD(x, y)                                         \
  837         if (x->ti_hwrev == TI_HWREV_TIGON) {                            \
  838                 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y);                \
  839         } else {                                                        \
  840                 CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y);                 \
  841         }
  842 
  843 
  844 /*
  845  * Tigon event structure.
  846  */
  847 struct ti_event_desc {
  848 #if BYTE_ORDER == BIG_ENDIAN
  849         u_int32_t               ti_event:8;
  850         u_int32_t               ti_code:12;
  851         u_int32_t               ti_idx:12;
  852 #else
  853         u_int32_t               ti_idx:12;
  854         u_int32_t               ti_code:12;
  855         u_int32_t               ti_event:8;
  856 #endif
  857         u_int32_t               ti_rsvd;
  858 };
  859 
  860 /*
  861  * Tigon events.
  862  */
  863 #define TI_EV_FIRMWARE_UP               0x01
  864 #define TI_EV_STATS_UPDATED             0x04
  865 
  866 #define TI_EV_LINKSTAT_CHANGED          0x06
  867 #define TI_EV_CODE_GIG_LINK_UP          0x01
  868 #define TI_EV_CODE_LINK_DOWN            0x02
  869 #define TI_EV_CODE_LINK_UP              0x03
  870 
  871 #define TI_EV_ERROR                     0x07
  872 #define TI_EV_CODE_ERR_INVAL_CMD        0x01
  873 #define TI_EV_CODE_ERR_UNIMP_CMD        0x02
  874 #define TI_EV_CODE_ERR_BADCFG           0x03
  875 
  876 #define TI_EV_MCAST_UPDATED             0x08
  877 #define TI_EV_CODE_MCAST_ADD            0x01
  878 #define TI_EV_CODE_MCAST_DEL            0x02
  879 
  880 #define TI_EV_RESET_JUMBO_RING          0x09
  881 /*
  882  * Register access macros. The Tigon always uses memory mapped register
  883  * accesses and all registers must be accessed with 32 bit operations.
  884  */
  885 
  886 #define CSR_WRITE_4(sc, reg, val)       \
  887         bus_space_write_4(sc->ti_btag, sc->ti_bhandle, reg, val)
  888 
  889 #define CSR_READ_4(sc, reg)             \
  890         bus_space_read_4(sc->ti_btag, sc->ti_bhandle, reg)
  891 
  892 #define TI_SETBIT(sc, reg, x)   \
  893         CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
  894 #define TI_CLRBIT(sc, reg, x)   \
  895         CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
  896 
  897 /*
  898  * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
  899  * values are tuneable. They control the actual amount of buffers
  900  * allocated for the standard, mini and jumbo receive rings.
  901  */
  902 
  903 #define TI_SSLOTS       256
  904 #define TI_MSLOTS       256
  905 #define TI_JSLOTS       384
  906 
  907 #define TI_JRAWLEN (TI_JUMBO_FRAMELEN + ETHER_ALIGN)
  908 #define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \
  909         (TI_JRAWLEN % sizeof(u_int64_t))))
  910 #define TI_JPAGESZ PAGE_SIZE
  911 #define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ)
  912 #define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID)
  913 
  914 /*
  915  * Ring structures. Most of these reside in host memory and we tell
  916  * the NIC where they are via the ring control blocks. The exceptions
  917  * are the tx and command rings, which live in NIC memory and which
  918  * we access via the shared memory window.
  919  */
  920 struct ti_ring_data {
  921         struct ti_rx_desc       ti_rx_std_ring[TI_STD_RX_RING_CNT];
  922 #ifdef PRIVATE_JUMBOS
  923         struct ti_rx_desc       ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT];
  924 #else
  925         struct ti_rx_desc_ext   ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT];
  926 #endif
  927         struct ti_rx_desc       ti_rx_mini_ring[TI_MINI_RX_RING_CNT];
  928         struct ti_rx_desc       ti_rx_return_ring[TI_RETURN_RING_CNT];
  929         struct ti_event_desc    ti_event_ring[TI_EVENT_RING_CNT];
  930         struct ti_tx_desc       ti_tx_ring[TI_TX_RING_CNT];
  931         /*
  932          * Make sure producer structures are aligned on 32-byte cache
  933          * line boundaries.
  934          */
  935         struct ti_producer      ti_ev_prodidx_r;
  936         u_int32_t               ti_pad0[6];
  937         struct ti_producer      ti_return_prodidx_r;
  938         u_int32_t               ti_pad1[6];
  939         struct ti_producer      ti_tx_considx_r;
  940         u_int32_t               ti_pad2[6];
  941         struct ti_tx_desc       *ti_tx_ring_nic;/* pointer to shared mem */
  942         struct ti_cmd_desc      *ti_cmd_ring;   /* pointer to shared mem */
  943         struct ti_gib           ti_info;
  944 };
  945 
  946 /*
  947  * Mbuf pointers. We need these to keep track of the virtual addresses
  948  * of our mbuf chains since we can only convert from physical to virtual,
  949  * not the other way around.
  950  */
  951 struct ti_chain_data {
  952         struct mbuf             *ti_tx_chain[TI_TX_RING_CNT];
  953         struct mbuf             *ti_rx_std_chain[TI_STD_RX_RING_CNT];
  954         struct mbuf             *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT];
  955         struct mbuf             *ti_rx_mini_chain[TI_MINI_RX_RING_CNT];
  956         /* Stick the jumbo mem management stuff here too. */
  957         caddr_t                 ti_jslots[TI_JSLOTS];
  958         void                    *ti_jumbo_buf;
  959 };
  960 
  961 struct ti_type {
  962         u_int16_t               ti_vid;
  963         u_int16_t               ti_did;
  964         char                    *ti_name;
  965 };
  966 
  967 #define TI_HWREV_TIGON          0x01
  968 #define TI_HWREV_TIGON_II       0x02
  969 #define TI_TIMEOUT              1000
  970 #define TI_TXCONS_UNSET         0xFFFF  /* impossible value */
  971 
  972 struct ti_mc_entry {
  973         struct ether_addr               mc_addr;
  974         SLIST_ENTRY(ti_mc_entry)        mc_entries;
  975 };
  976 
  977 struct ti_jpool_entry {
  978         int                             slot;
  979         SLIST_ENTRY(ti_jpool_entry)     jpool_entries;
  980 };
  981 
  982 typedef enum {
  983         TI_FLAG_NONE            = 0x00,
  984         TI_FLAG_DEBUGING        = 0x01,
  985         TI_FLAG_WAIT_FOR_LINK   = 0x02
  986 } ti_flag_vals;
  987 
  988 struct ti_softc {
  989         STAILQ_ENTRY(ti_softc)  ti_links;
  990         struct arpcom           arpcom;         /* interface info */
  991         bus_space_handle_t      ti_bhandle;
  992         vm_offset_t             ti_vhandle;
  993         bus_space_tag_t         ti_btag;
  994         void                    *ti_intrhand;
  995         struct resource         *ti_irq;
  996         struct resource         *ti_res;
  997         struct ifmedia          ifmedia;        /* media info */
  998         u_int8_t                ti_unit;        /* interface number */
  999         u_int8_t                ti_hwrev;       /* Tigon rev (1 or 2) */
 1000         u_int8_t                ti_copper;      /* 1000baseTX card */
 1001         u_int8_t                ti_linkstat;    /* Link state */
 1002         int                     ti_hdrsplit;    /* enable header splitting */
 1003         struct ti_ring_data     *ti_rdata;      /* rings */
 1004         struct ti_chain_data    ti_cdata;       /* mbufs */
 1005 #define ti_ev_prodidx           ti_rdata->ti_ev_prodidx_r
 1006 #define ti_return_prodidx       ti_rdata->ti_return_prodidx_r
 1007 #define ti_tx_considx           ti_rdata->ti_tx_considx_r
 1008         u_int16_t               ti_tx_saved_considx;
 1009         u_int16_t               ti_rx_saved_considx;
 1010         u_int16_t               ti_ev_saved_considx;
 1011         u_int16_t               ti_cmd_saved_prodidx;
 1012         u_int16_t               ti_std;         /* current std ring head */
 1013         u_int16_t               ti_mini;        /* current mini ring head */
 1014         u_int16_t               ti_jumbo;       /* current jumo ring head */
 1015         SLIST_HEAD(__ti_mchead, ti_mc_entry)    ti_mc_listhead;
 1016         SLIST_HEAD(__ti_jfreehead, ti_jpool_entry)      ti_jfree_listhead;
 1017         SLIST_HEAD(__ti_jinusehead, ti_jpool_entry)     ti_jinuse_listhead;
 1018         u_int32_t               ti_stat_ticks;
 1019         u_int32_t               ti_rx_coal_ticks;
 1020         u_int32_t               ti_tx_coal_ticks;
 1021         u_int32_t               ti_rx_max_coal_bds;
 1022         u_int32_t               ti_tx_max_coal_bds;
 1023         u_int32_t               ti_tx_buf_ratio;
 1024         int                     ti_if_flags;
 1025         int                     ti_txcnt;
 1026         struct mtx              ti_mtx;
 1027         ti_flag_vals            ti_flags;
 1028         struct cdev *dev;
 1029 };
 1030 
 1031 #define TI_LOCK(_sc)            mtx_lock(&(_sc)->ti_mtx)
 1032 #define TI_UNLOCK(_sc)          mtx_unlock(&(_sc)->ti_mtx)
 1033 #define TI_LOCK_ASSERT(_sc)     mtx_assert(&(_sc)->ti_mtx, MA_OWNED)
 1034 
 1035 /*
 1036  * Microchip Technology 24Cxx EEPROM control bytes
 1037  */
 1038 #define EEPROM_CTL_READ                 0xA1    /* 0101 0001 */
 1039 #define EEPROM_CTL_WRITE                0xA0    /* 0101 0000 */
 1040 
 1041 /*
 1042  * Note that EEPROM_START leaves transmission enabled.
 1043  */
 1044 #define EEPROM_START                                                    \
 1045         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\
 1046         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */       \
 1047         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\
 1048         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\
 1049         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */
 1050 
 1051 /*
 1052  * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so
 1053  * that no further data can be written to the EEPROM I/O pin.
 1054  */
 1055 #define EEPROM_STOP                                                     \
 1056         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */    \
 1057         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */  \
 1058         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */  \
 1059         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */     \
 1060         TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */        \
 1061         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */   \
 1062         TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */
 1063 
 1064 
 1065 #ifdef __alpha__
 1066 #undef vtophys
 1067 #define vtophys(va)             alpha_XXX_dmamap((vm_offset_t)va)
 1068 #endif

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