The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_tl.c

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    1 /*
    2  * Copyright (c) 1997, 1998
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD$
   33  */
   34 
   35 /*
   36  * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
   37  * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
   38  * the National Semiconductor DP83840A physical interface and the
   39  * Microchip Technology 24Cxx series serial EEPROM.
   40  *
   41  * Written using the following four documents:
   42  *
   43  * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
   44  * National Semiconductor DP83840A data sheet (www.national.com)
   45  * Microchip Technology 24C02C data sheet (www.microchip.com)
   46  * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
   47  * 
   48  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   49  * Electrical Engineering Department
   50  * Columbia University, New York City
   51  */
   52 
   53 /*
   54  * Some notes about the ThunderLAN:
   55  *
   56  * The ThunderLAN controller is a single chip containing PCI controller
   57  * logic, approximately 3K of on-board SRAM, a LAN controller, and media
   58  * independent interface (MII) bus. The MII allows the ThunderLAN chip to
   59  * control up to 32 different physical interfaces (PHYs). The ThunderLAN
   60  * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
   61  * to act as a complete ethernet interface.
   62  *
   63  * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
   64  * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
   65  * in full or half duplex. Some of the Compaq Deskpro machines use a
   66  * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
   67  * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
   68  * concert with the ThunderLAN's internal PHY to provide full 10/100
   69  * support. This is cheaper than using a standalone external PHY for both
   70  * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
   71  * A serial EEPROM is also attached to the ThunderLAN chip to provide
   72  * power-up default register settings and for storing the adapter's
   73  * station address. Although not supported by this driver, the ThunderLAN
   74  * chip can also be connected to token ring PHYs.
   75  *
   76  * The ThunderLAN has a set of registers which can be used to issue
   77  * commands, acknowledge interrupts, and to manipulate other internal
   78  * registers on its DIO bus. The primary registers can be accessed
   79  * using either programmed I/O (inb/outb) or via PCI memory mapping,
   80  * depending on how the card is configured during the PCI probing
   81  * phase. It is even possible to have both PIO and memory mapped
   82  * access turned on at the same time.
   83  * 
   84  * Frame reception and transmission with the ThunderLAN chip is done
   85  * using frame 'lists.' A list structure looks more or less like this:
   86  *
   87  * struct tl_frag {
   88  *      u_int32_t               fragment_address;
   89  *      u_int32_t               fragment_size;
   90  * };
   91  * struct tl_list {
   92  *      u_int32_t               forward_pointer;
   93  *      u_int16_t               cstat;
   94  *      u_int16_t               frame_size;
   95  *      struct tl_frag          fragments[10];
   96  * };
   97  *
   98  * The forward pointer in the list header can be either a 0 or the address
   99  * of another list, which allows several lists to be linked together. Each
  100  * list contains up to 10 fragment descriptors. This means the chip allows
  101  * ethernet frames to be broken up into up to 10 chunks for transfer to
  102  * and from the SRAM. Note that the forward pointer and fragment buffer
  103  * addresses are physical memory addresses, not virtual. Note also that
  104  * a single ethernet frame can not span lists: if the host wants to
  105  * transmit a frame and the frame data is split up over more than 10
  106  * buffers, the frame has to collapsed before it can be transmitted.
  107  *
  108  * To receive frames, the driver sets up a number of lists and populates
  109  * the fragment descriptors, then it sends an RX GO command to the chip.
  110  * When a frame is received, the chip will DMA it into the memory regions
  111  * specified by the fragment descriptors and then trigger an RX 'end of
  112  * frame interrupt' when done. The driver may choose to use only one
  113  * fragment per list; this may result is slighltly less efficient use
  114  * of memory in exchange for improving performance.
  115  *
  116  * To transmit frames, the driver again sets up lists and fragment
  117  * descriptors, only this time the buffers contain frame data that
  118  * is to be DMA'ed into the chip instead of out of it. Once the chip
  119  * has transfered the data into its on-board SRAM, it will trigger a
  120  * TX 'end of frame' interrupt. It will also generate an 'end of channel'
  121  * interrupt when it reaches the end of the list.
  122  */
  123 
  124 /*
  125  * Some notes about this driver:
  126  *
  127  * The ThunderLAN chip provides a couple of different ways to organize
  128  * reception, transmission and interrupt handling. The simplest approach
  129  * is to use one list each for transmission and reception. In this mode,
  130  * the ThunderLAN will generate two interrupts for every received frame
  131  * (one RX EOF and one RX EOC) and two for each transmitted frame (one
  132  * TX EOF and one TX EOC). This may make the driver simpler but it hurts
  133  * performance to have to handle so many interrupts.
  134  *
  135  * Initially I wanted to create a circular list of receive buffers so
  136  * that the ThunderLAN chip would think there was an infinitely long
  137  * receive channel and never deliver an RXEOC interrupt. However this
  138  * doesn't work correctly under heavy load: while the manual says the
  139  * chip will trigger an RXEOF interrupt each time a frame is copied into
  140  * memory, you can't count on the chip waiting around for you to acknowledge
  141  * the interrupt before it starts trying to DMA the next frame. The result
  142  * is that the chip might traverse the entire circular list and then wrap
  143  * around before you have a chance to do anything about it. Consequently,
  144  * the receive list is terminated (with a 0 in the forward pointer in the
  145  * last element). Each time an RXEOF interrupt arrives, the used list
  146  * is shifted to the end of the list. This gives the appearance of an
  147  * infinitely large RX chain so long as the driver doesn't fall behind
  148  * the chip and allow all of the lists to be filled up.
  149  *
  150  * If all the lists are filled, the adapter will deliver an RX 'end of
  151  * channel' interrupt when it hits the 0 forward pointer at the end of
  152  * the chain. The RXEOC handler then cleans out the RX chain and resets
  153  * the list head pointer in the ch_parm register and restarts the receiver.
  154  *
  155  * For frame transmission, it is possible to program the ThunderLAN's
  156  * transmit interrupt threshold so that the chip can acknowledge multiple
  157  * lists with only a single TX EOF interrupt. This allows the driver to
  158  * queue several frames in one shot, and only have to handle a total
  159  * two interrupts (one TX EOF and one TX EOC) no matter how many frames
  160  * are transmitted. Frame transmission is done directly out of the
  161  * mbufs passed to the tl_start() routine via the interface send queue.
  162  * The driver simply sets up the fragment descriptors in the transmit
  163  * lists to point to the mbuf data regions and sends a TX GO command.
  164  *
  165  * Note that since the RX and TX lists themselves are always used
  166  * only by the driver, the are malloc()ed once at driver initialization
  167  * time and never free()ed.
  168  *
  169  * Also, in order to remain as platform independent as possible, this
  170  * driver uses memory mapped register access to manipulate the card
  171  * as opposed to programmed I/O. This avoids the use of the inb/outb
  172  * (and related) instructions which are specific to the i386 platform.
  173  *
  174  * Using these techniques, this driver achieves very high performance
  175  * by minimizing the amount of interrupts generated during large
  176  * transfers and by completely avoiding buffer copies. Frame transfer
  177  * to and from the ThunderLAN chip is performed entirely by the chip
  178  * itself thereby reducing the load on the host CPU.
  179  */
  180 
  181 #include <sys/param.h>
  182 #include <sys/systm.h>
  183 #include <sys/sockio.h>
  184 #include <sys/mbuf.h>
  185 #include <sys/malloc.h>
  186 #include <sys/kernel.h>
  187 #include <sys/socket.h>
  188 
  189 #include <net/if.h>
  190 #include <net/if_arp.h>
  191 #include <net/ethernet.h>
  192 #include <net/if_dl.h>
  193 #include <net/if_media.h>
  194 
  195 #include <net/bpf.h>
  196 
  197 #include <vm/vm.h>              /* for vtophys */
  198 #include <vm/pmap.h>            /* for vtophys */
  199 #include <machine/clock.h>      /* for DELAY */
  200 #include <machine/bus_memio.h>
  201 #include <machine/bus_pio.h>
  202 #include <machine/bus.h>
  203 #include <machine/resource.h>
  204 #include <sys/bus.h>
  205 #include <sys/rman.h>
  206 
  207 #include <dev/mii/mii.h>
  208 #include <dev/mii/miivar.h>
  209 
  210 #include <pci/pcireg.h>
  211 #include <pci/pcivar.h>
  212 
  213 /*
  214  * Default to using PIO register access mode to pacify certain
  215  * laptop docking stations with built-in ThunderLAN chips that
  216  * don't seem to handle memory mapped mode properly.
  217  */
  218 #define TL_USEIOSPACE
  219 
  220 #include <pci/if_tlreg.h>
  221 
  222 /* "controller miibus0" required.  See GENERIC if you get errors here. */
  223 #include "miibus_if.h"
  224 
  225 #if !defined(lint)
  226 static const char rcsid[] =
  227   "$FreeBSD$";
  228 #endif
  229 
  230 /*
  231  * Various supported device vendors/types and their names.
  232  */
  233 
  234 static struct tl_type tl_devs[] = {
  235         { TI_VENDORID,  TI_DEVICEID_THUNDERLAN,
  236                 "Texas Instruments ThunderLAN" },
  237         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
  238                 "Compaq Netelligent 10" },
  239         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
  240                 "Compaq Netelligent 10/100" },
  241         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
  242                 "Compaq Netelligent 10/100 Proliant" },
  243         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
  244                 "Compaq Netelligent 10/100 Dual Port" },
  245         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
  246                 "Compaq NetFlex-3/P Integrated" },
  247         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
  248                 "Compaq NetFlex-3/P" },
  249         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
  250                 "Compaq NetFlex 3/P w/ BNC" },
  251         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
  252                 "Compaq Netelligent 10/100 TX Embedded UTP" },
  253         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
  254                 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
  255         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
  256                 "Compaq Netelligent 10/100 TX UTP" },
  257         { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
  258                 "Olicom OC-2183/2185" },
  259         { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
  260                 "Olicom OC-2325" },
  261         { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
  262                 "Olicom OC-2326 10/100 TX UTP" },
  263         { 0, 0, NULL }
  264 };
  265 
  266 static int tl_probe             __P((device_t));
  267 static int tl_attach            __P((device_t));
  268 static int tl_detach            __P((device_t));
  269 static int tl_intvec_rxeoc      __P((void *, u_int32_t));
  270 static int tl_intvec_txeoc      __P((void *, u_int32_t));
  271 static int tl_intvec_txeof      __P((void *, u_int32_t));
  272 static int tl_intvec_rxeof      __P((void *, u_int32_t));
  273 static int tl_intvec_adchk      __P((void *, u_int32_t));
  274 static int tl_intvec_netsts     __P((void *, u_int32_t));
  275 
  276 static int tl_newbuf            __P((struct tl_softc *,
  277                                         struct tl_chain_onefrag *));
  278 static void tl_stats_update     __P((void *));
  279 static int tl_encap             __P((struct tl_softc *, struct tl_chain *,
  280                                                 struct mbuf *));
  281 
  282 static void tl_intr             __P((void *));
  283 static void tl_start            __P((struct ifnet *));
  284 static int tl_ioctl             __P((struct ifnet *, u_long, caddr_t));
  285 static void tl_init             __P((void *));
  286 static void tl_stop             __P((struct tl_softc *));
  287 static void tl_watchdog         __P((struct ifnet *));
  288 static void tl_shutdown         __P((device_t));
  289 static int tl_ifmedia_upd       __P((struct ifnet *));
  290 static void tl_ifmedia_sts      __P((struct ifnet *, struct ifmediareq *));
  291 
  292 static u_int8_t tl_eeprom_putbyte       __P((struct tl_softc *, int));
  293 static u_int8_t tl_eeprom_getbyte       __P((struct tl_softc *,
  294                                                 int, u_int8_t *));
  295 static int tl_read_eeprom       __P((struct tl_softc *, caddr_t, int, int));
  296 
  297 static void tl_mii_sync         __P((struct tl_softc *));
  298 static void tl_mii_send         __P((struct tl_softc *, u_int32_t, int));
  299 static int tl_mii_readreg       __P((struct tl_softc *, struct tl_mii_frame *));
  300 static int tl_mii_writereg      __P((struct tl_softc *, struct tl_mii_frame *));
  301 static int tl_miibus_readreg    __P((device_t, int, int));
  302 static int tl_miibus_writereg   __P((device_t, int, int, int));
  303 static void tl_miibus_statchg   __P((device_t));
  304 
  305 static void tl_setmode          __P((struct tl_softc *, int));
  306 static int tl_calchash          __P((caddr_t));
  307 static void tl_setmulti         __P((struct tl_softc *));
  308 static void tl_setfilt          __P((struct tl_softc *, caddr_t, int));
  309 static void tl_softreset        __P((struct tl_softc *, int));
  310 static void tl_hardreset        __P((device_t));
  311 static int tl_list_rx_init      __P((struct tl_softc *));
  312 static int tl_list_tx_init      __P((struct tl_softc *));
  313 
  314 static u_int8_t tl_dio_read8    __P((struct tl_softc *, int));
  315 static u_int16_t tl_dio_read16  __P((struct tl_softc *, int));
  316 static u_int32_t tl_dio_read32  __P((struct tl_softc *, int));
  317 static void tl_dio_write8       __P((struct tl_softc *, int, int));
  318 static void tl_dio_write16      __P((struct tl_softc *, int, int));
  319 static void tl_dio_write32      __P((struct tl_softc *, int, int));
  320 static void tl_dio_setbit       __P((struct tl_softc *, int, int));
  321 static void tl_dio_clrbit       __P((struct tl_softc *, int, int));
  322 static void tl_dio_setbit16     __P((struct tl_softc *, int, int));
  323 static void tl_dio_clrbit16     __P((struct tl_softc *, int, int));
  324 
  325 #ifdef TL_USEIOSPACE
  326 #define TL_RES          SYS_RES_IOPORT
  327 #define TL_RID          TL_PCI_LOIO
  328 #else
  329 #define TL_RES          SYS_RES_MEMORY
  330 #define TL_RID          TL_PCI_LOMEM
  331 #endif
  332 
  333 static device_method_t tl_methods[] = {
  334         /* Device interface */
  335         DEVMETHOD(device_probe,         tl_probe),
  336         DEVMETHOD(device_attach,        tl_attach),
  337         DEVMETHOD(device_detach,        tl_detach),
  338         DEVMETHOD(device_shutdown,      tl_shutdown),
  339 
  340         /* bus interface */
  341         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  342         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  343 
  344         /* MII interface */
  345         DEVMETHOD(miibus_readreg,       tl_miibus_readreg),
  346         DEVMETHOD(miibus_writereg,      tl_miibus_writereg),
  347         DEVMETHOD(miibus_statchg,       tl_miibus_statchg),
  348 
  349         { 0, 0 }
  350 };
  351 
  352 static driver_t tl_driver = {
  353         "tl",
  354         tl_methods,
  355         sizeof(struct tl_softc)
  356 };
  357 
  358 static devclass_t tl_devclass;
  359 
  360 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0);
  361 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
  362 
  363 static u_int8_t tl_dio_read8(sc, reg)
  364         struct tl_softc         *sc;
  365         int                     reg;
  366 {
  367         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  368         return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
  369 }
  370 
  371 static u_int16_t tl_dio_read16(sc, reg)
  372         struct tl_softc         *sc;
  373         int                     reg;
  374 {
  375         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  376         return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
  377 }
  378 
  379 static u_int32_t tl_dio_read32(sc, reg)
  380         struct tl_softc         *sc;
  381         int                     reg;
  382 {
  383         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  384         return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
  385 }
  386 
  387 static void tl_dio_write8(sc, reg, val)
  388         struct tl_softc         *sc;
  389         int                     reg;
  390         int                     val;
  391 {
  392         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  393         CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
  394         return;
  395 }
  396 
  397 static void tl_dio_write16(sc, reg, val)
  398         struct tl_softc         *sc;
  399         int                     reg;
  400         int                     val;
  401 {
  402         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  403         CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
  404         return;
  405 }
  406 
  407 static void tl_dio_write32(sc, reg, val)
  408         struct tl_softc         *sc;
  409         int                     reg;
  410         int                     val;
  411 {
  412         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  413         CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
  414         return;
  415 }
  416 
  417 static void tl_dio_setbit(sc, reg, bit)
  418         struct tl_softc         *sc;
  419         int                     reg;
  420         int                     bit;
  421 {
  422         u_int8_t                        f;
  423 
  424         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  425         f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
  426         f |= bit;
  427         CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
  428 
  429         return;
  430 }
  431 
  432 static void tl_dio_clrbit(sc, reg, bit)
  433         struct tl_softc         *sc;
  434         int                     reg;
  435         int                     bit;
  436 {
  437         u_int8_t                        f;
  438 
  439         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  440         f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
  441         f &= ~bit;
  442         CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
  443 
  444         return;
  445 }
  446 
  447 static void tl_dio_setbit16(sc, reg, bit)
  448         struct tl_softc         *sc;
  449         int                     reg;
  450         int                     bit;
  451 {
  452         u_int16_t                       f;
  453 
  454         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  455         f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
  456         f |= bit;
  457         CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
  458 
  459         return;
  460 }
  461 
  462 static void tl_dio_clrbit16(sc, reg, bit)
  463         struct tl_softc         *sc;
  464         int                     reg;
  465         int                     bit;
  466 {
  467         u_int16_t                       f;
  468 
  469         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  470         f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
  471         f &= ~bit;
  472         CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
  473 
  474         return;
  475 }
  476 
  477 /*
  478  * Send an instruction or address to the EEPROM, check for ACK.
  479  */
  480 static u_int8_t tl_eeprom_putbyte(sc, byte)
  481         struct tl_softc         *sc;
  482         int                     byte;
  483 {
  484         register int            i, ack = 0;
  485 
  486         /*
  487          * Make sure we're in TX mode.
  488          */
  489         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
  490 
  491         /*
  492          * Feed in each bit and stobe the clock.
  493          */
  494         for (i = 0x80; i; i >>= 1) {
  495                 if (byte & i) {
  496                         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
  497                 } else {
  498                         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
  499                 }
  500                 DELAY(1);
  501                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  502                 DELAY(1);
  503                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  504         }
  505 
  506         /*
  507          * Turn off TX mode.
  508          */
  509         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
  510 
  511         /*
  512          * Check for ack.
  513          */
  514         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  515         ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
  516         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  517 
  518         return(ack);
  519 }
  520 
  521 /*
  522  * Read a byte of data stored in the EEPROM at address 'addr.'
  523  */
  524 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
  525         struct tl_softc         *sc;
  526         int                     addr;
  527         u_int8_t                *dest;
  528 {
  529         register int            i;
  530         u_int8_t                byte = 0;
  531 
  532         tl_dio_write8(sc, TL_NETSIO, 0);
  533 
  534         EEPROM_START;
  535 
  536         /*
  537          * Send write control code to EEPROM.
  538          */
  539         if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
  540                 printf("tl%d: failed to send write command, status: %x\n",
  541                                 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
  542                 return(1);
  543         }
  544 
  545         /*
  546          * Send address of byte we want to read.
  547          */
  548         if (tl_eeprom_putbyte(sc, addr)) {
  549                 printf("tl%d: failed to send address, status: %x\n",
  550                                 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
  551                 return(1);
  552         }
  553 
  554         EEPROM_STOP;
  555         EEPROM_START;
  556         /*
  557          * Send read control code to EEPROM.
  558          */
  559         if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
  560                 printf("tl%d: failed to send write command, status: %x\n",
  561                                 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
  562                 return(1);
  563         }
  564 
  565         /*
  566          * Start reading bits from EEPROM.
  567          */
  568         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
  569         for (i = 0x80; i; i >>= 1) {
  570                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  571                 DELAY(1);
  572                 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
  573                         byte |= i;
  574                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  575                 DELAY(1);
  576         }
  577 
  578         EEPROM_STOP;
  579 
  580         /*
  581          * No ACK generated for read, so just return byte.
  582          */
  583 
  584         *dest = byte;
  585 
  586         return(0);
  587 }
  588 
  589 /*
  590  * Read a sequence of bytes from the EEPROM.
  591  */
  592 static int tl_read_eeprom(sc, dest, off, cnt)
  593         struct tl_softc         *sc;
  594         caddr_t                 dest;
  595         int                     off;
  596         int                     cnt;
  597 {
  598         int                     err = 0, i;
  599         u_int8_t                byte = 0;
  600 
  601         for (i = 0; i < cnt; i++) {
  602                 err = tl_eeprom_getbyte(sc, off + i, &byte);
  603                 if (err)
  604                         break;
  605                 *(dest + i) = byte;
  606         }
  607 
  608         return(err ? 1 : 0);
  609 }
  610 
  611 static void tl_mii_sync(sc)
  612         struct tl_softc         *sc;
  613 {
  614         register int            i;
  615 
  616         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  617 
  618         for (i = 0; i < 32; i++) {
  619                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  620                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  621         }
  622 
  623         return;
  624 }
  625 
  626 static void tl_mii_send(sc, bits, cnt)
  627         struct tl_softc         *sc;
  628         u_int32_t               bits;
  629         int                     cnt;
  630 {
  631         int                     i;
  632 
  633         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  634                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  635                 if (bits & i) {
  636                         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
  637                 } else {
  638                         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
  639                 }
  640                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  641         }
  642 }
  643 
  644 static int tl_mii_readreg(sc, frame)
  645         struct tl_softc         *sc;
  646         struct tl_mii_frame     *frame;
  647         
  648 {
  649         int                     i, ack, s;
  650         int                     minten = 0;
  651 
  652         s = splimp();
  653 
  654         tl_mii_sync(sc);
  655 
  656         /*
  657          * Set up frame for RX.
  658          */
  659         frame->mii_stdelim = TL_MII_STARTDELIM;
  660         frame->mii_opcode = TL_MII_READOP;
  661         frame->mii_turnaround = 0;
  662         frame->mii_data = 0;
  663         
  664         /*
  665          * Turn off MII interrupt by forcing MINTEN low.
  666          */
  667         minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
  668         if (minten) {
  669                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  670         }
  671 
  672         /*
  673          * Turn on data xmit.
  674          */
  675         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  676 
  677         /*
  678          * Send command/address info.
  679          */
  680         tl_mii_send(sc, frame->mii_stdelim, 2);
  681         tl_mii_send(sc, frame->mii_opcode, 2);
  682         tl_mii_send(sc, frame->mii_phyaddr, 5);
  683         tl_mii_send(sc, frame->mii_regaddr, 5);
  684 
  685         /*
  686          * Turn off xmit.
  687          */
  688         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  689 
  690         /* Idle bit */
  691         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  692         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  693 
  694         /* Check for ack */
  695         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  696         ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
  697 
  698         /* Complete the cycle */
  699         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  700 
  701         /*
  702          * Now try reading data bits. If the ack failed, we still
  703          * need to clock through 16 cycles to keep the PHYs in sync.
  704          */
  705         if (ack) {
  706                 for(i = 0; i < 16; i++) {
  707                         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  708                         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  709                 }
  710                 goto fail;
  711         }
  712 
  713         for (i = 0x8000; i; i >>= 1) {
  714                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  715                 if (!ack) {
  716                         if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
  717                                 frame->mii_data |= i;
  718                 }
  719                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  720         }
  721 
  722 fail:
  723 
  724         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  725         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  726 
  727         /* Reenable interrupts */
  728         if (minten) {
  729                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  730         }
  731 
  732         splx(s);
  733 
  734         if (ack)
  735                 return(1);
  736         return(0);
  737 }
  738 
  739 static int tl_mii_writereg(sc, frame)
  740         struct tl_softc         *sc;
  741         struct tl_mii_frame     *frame;
  742         
  743 {
  744         int                     s;
  745         int                     minten;
  746 
  747         tl_mii_sync(sc);
  748 
  749         s = splimp();
  750         /*
  751          * Set up frame for TX.
  752          */
  753 
  754         frame->mii_stdelim = TL_MII_STARTDELIM;
  755         frame->mii_opcode = TL_MII_WRITEOP;
  756         frame->mii_turnaround = TL_MII_TURNAROUND;
  757         
  758         /*
  759          * Turn off MII interrupt by forcing MINTEN low.
  760          */
  761         minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
  762         if (minten) {
  763                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  764         }
  765 
  766         /*
  767          * Turn on data output.
  768          */
  769         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  770 
  771         tl_mii_send(sc, frame->mii_stdelim, 2);
  772         tl_mii_send(sc, frame->mii_opcode, 2);
  773         tl_mii_send(sc, frame->mii_phyaddr, 5);
  774         tl_mii_send(sc, frame->mii_regaddr, 5);
  775         tl_mii_send(sc, frame->mii_turnaround, 2);
  776         tl_mii_send(sc, frame->mii_data, 16);
  777 
  778         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  779         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  780 
  781         /*
  782          * Turn off xmit.
  783          */
  784         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  785 
  786         /* Reenable interrupts */
  787         if (minten)
  788                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  789 
  790         splx(s);
  791 
  792         return(0);
  793 }
  794 
  795 static int tl_miibus_readreg(dev, phy, reg)
  796         device_t                dev;
  797         int                     phy, reg;
  798 {
  799         struct tl_softc         *sc;
  800         struct tl_mii_frame     frame;
  801 
  802         sc = device_get_softc(dev);
  803         bzero((char *)&frame, sizeof(frame));
  804 
  805         frame.mii_phyaddr = phy;
  806         frame.mii_regaddr = reg;
  807         tl_mii_readreg(sc, &frame);
  808 
  809         return(frame.mii_data);
  810 }
  811 
  812 static int tl_miibus_writereg(dev, phy, reg, data)
  813         device_t                dev;
  814         int                     phy, reg, data;
  815 {
  816         struct tl_softc         *sc;
  817         struct tl_mii_frame     frame;
  818 
  819         sc = device_get_softc(dev);
  820         bzero((char *)&frame, sizeof(frame));
  821 
  822         frame.mii_phyaddr = phy;
  823         frame.mii_regaddr = reg;
  824         frame.mii_data = data;
  825 
  826         tl_mii_writereg(sc, &frame);
  827 
  828         return(0);
  829 }
  830 
  831 static void tl_miibus_statchg(dev)
  832         device_t                dev;
  833 {
  834         struct tl_softc         *sc;
  835         struct mii_data         *mii;
  836 
  837         sc = device_get_softc(dev);
  838         mii = device_get_softc(sc->tl_miibus);
  839 
  840         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
  841                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
  842         } else {
  843                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
  844         }
  845 
  846         return;
  847 }
  848 
  849 /*
  850  * Set modes for bitrate devices.
  851  */
  852 static void tl_setmode(sc, media)
  853         struct tl_softc         *sc;
  854         int                     media;
  855 {
  856         if (IFM_SUBTYPE(media) == IFM_10_5)
  857                 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
  858         if (IFM_SUBTYPE(media) == IFM_10_T) {
  859                 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
  860                 if ((media & IFM_GMASK) == IFM_FDX) {
  861                         tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
  862                         tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
  863                 } else {
  864                         tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
  865                         tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
  866                 }
  867         }
  868 
  869         return;
  870 }
  871 
  872 /*
  873  * Calculate the hash of a MAC address for programming the multicast hash
  874  * table.  This hash is simply the address split into 6-bit chunks
  875  * XOR'd, e.g.
  876  * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
  877  * bit:  765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
  878  * Bytes 0-2 and 3-5 are symmetrical, so are folded together.  Then
  879  * the folded 24-bit value is split into 6-bit portions and XOR'd.
  880  */
  881 static int tl_calchash(addr)
  882         caddr_t                 addr;
  883 {
  884         int                     t;
  885 
  886         t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
  887                 (addr[2] ^ addr[5]);
  888         return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
  889 }
  890 
  891 /*
  892  * The ThunderLAN has a perfect MAC address filter in addition to
  893  * the multicast hash filter. The perfect filter can be programmed
  894  * with up to four MAC addresses. The first one is always used to
  895  * hold the station address, which leaves us free to use the other
  896  * three for multicast addresses.
  897  */
  898 static void tl_setfilt(sc, addr, slot)
  899         struct tl_softc         *sc;
  900         caddr_t                 addr;
  901         int                     slot;
  902 {
  903         int                     i;
  904         u_int16_t               regaddr;
  905 
  906         regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
  907 
  908         for (i = 0; i < ETHER_ADDR_LEN; i++)
  909                 tl_dio_write8(sc, regaddr + i, *(addr + i));
  910 
  911         return;
  912 }
  913 
  914 /*
  915  * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
  916  * linked list. This is fine, except addresses are added from the head
  917  * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
  918  * group to always be in the perfect filter, but as more groups are added,
  919  * the 224.0.0.1 entry (which is always added first) gets pushed down
  920  * the list and ends up at the tail. So after 3 or 4 multicast groups
  921  * are added, the all-hosts entry gets pushed out of the perfect filter
  922  * and into the hash table.
  923  *
  924  * Because the multicast list is a doubly-linked list as opposed to a
  925  * circular queue, we don't have the ability to just grab the tail of
  926  * the list and traverse it backwards. Instead, we have to traverse
  927  * the list once to find the tail, then traverse it again backwards to
  928  * update the multicast filter.
  929  */
  930 static void tl_setmulti(sc)
  931         struct tl_softc         *sc;
  932 {
  933         struct ifnet            *ifp;
  934         u_int32_t               hashes[2] = { 0, 0 };
  935         int                     h, i;
  936         struct ifmultiaddr      *ifma;
  937         u_int8_t                dummy[] = { 0, 0, 0, 0, 0 ,0 };
  938         ifp = &sc->arpcom.ac_if;
  939 
  940         /* First, zot all the existing filters. */
  941         for (i = 1; i < 4; i++)
  942                 tl_setfilt(sc, (caddr_t)&dummy, i);
  943         tl_dio_write32(sc, TL_HASH1, 0);
  944         tl_dio_write32(sc, TL_HASH2, 0);
  945 
  946         /* Now program new ones. */
  947         if (ifp->if_flags & IFF_ALLMULTI) {
  948                 hashes[0] = 0xFFFFFFFF;
  949                 hashes[1] = 0xFFFFFFFF;
  950         } else {
  951                 i = 1;
  952                 /* First find the tail of the list. */
  953                 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
  954                                         ifma = ifma->ifma_link.le_next) {
  955                         if (ifma->ifma_link.le_next == NULL)
  956                                 break;
  957                 }
  958                 /* Now traverse the list backwards. */
  959                 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
  960                         ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
  961                         if (ifma->ifma_addr->sa_family != AF_LINK)
  962                                 continue;
  963                         /*
  964                          * Program the first three multicast groups
  965                          * into the perfect filter. For all others,
  966                          * use the hash table.
  967                          */
  968                         if (i < 4) {
  969                                 tl_setfilt(sc,
  970                         LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
  971                                 i++;
  972                                 continue;
  973                         }
  974 
  975                         h = tl_calchash(
  976                                 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  977                         if (h < 32)
  978                                 hashes[0] |= (1 << h);
  979                         else
  980                                 hashes[1] |= (1 << (h - 32));
  981                 }
  982         }
  983 
  984         tl_dio_write32(sc, TL_HASH1, hashes[0]);
  985         tl_dio_write32(sc, TL_HASH2, hashes[1]);
  986 
  987         return;
  988 }
  989 
  990 /*
  991  * This routine is recommended by the ThunderLAN manual to insure that
  992  * the internal PHY is powered up correctly. It also recommends a one
  993  * second pause at the end to 'wait for the clocks to start' but in my
  994  * experience this isn't necessary.
  995  */
  996 static void tl_hardreset(dev)
  997         device_t                dev;
  998 {
  999         struct tl_softc         *sc;
 1000         int                     i;
 1001         u_int16_t               flags;
 1002 
 1003         sc = device_get_softc(dev);
 1004 
 1005         tl_mii_sync(sc);
 1006 
 1007         flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
 1008 
 1009         for (i = 0; i < MII_NPHY; i++)
 1010                 tl_miibus_writereg(dev, i, MII_BMCR, flags);
 1011 
 1012         tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
 1013         DELAY(50000);
 1014         tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
 1015         tl_mii_sync(sc);
 1016         while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
 1017 
 1018         DELAY(50000);
 1019         return;
 1020 }
 1021 
 1022 static void tl_softreset(sc, internal)
 1023         struct tl_softc         *sc;
 1024         int                     internal;
 1025 {
 1026         u_int32_t               cmd, dummy, i;
 1027 
 1028         /* Assert the adapter reset bit. */
 1029         CMD_SET(sc, TL_CMD_ADRST);
 1030 
 1031         /* Turn off interrupts */
 1032         CMD_SET(sc, TL_CMD_INTSOFF);
 1033 
 1034         /* First, clear the stats registers. */
 1035         for (i = 0; i < 5; i++)
 1036                 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
 1037 
 1038         /* Clear Areg and Hash registers */
 1039         for (i = 0; i < 8; i++)
 1040                 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
 1041 
 1042         /*
 1043          * Set up Netconfig register. Enable one channel and
 1044          * one fragment mode.
 1045          */
 1046         tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
 1047         if (internal && !sc->tl_bitrate) {
 1048                 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
 1049         } else {
 1050                 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
 1051         }
 1052 
 1053         /* Handle cards with bitrate devices. */
 1054         if (sc->tl_bitrate)
 1055                 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
 1056 
 1057         /*
 1058          * Load adapter irq pacing timer and tx threshold.
 1059          * We make the transmit threshold 1 initially but we may
 1060          * change that later.
 1061          */
 1062         cmd = CSR_READ_4(sc, TL_HOSTCMD);
 1063         cmd |= TL_CMD_NES;
 1064         cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
 1065         CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
 1066         CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
 1067 
 1068         /* Unreset the MII */
 1069         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
 1070 
 1071         /* Take the adapter out of reset */
 1072         tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
 1073 
 1074         /* Wait for things to settle down a little. */
 1075         DELAY(500);
 1076 
 1077         return;
 1078 }
 1079 
 1080 /*
 1081  * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
 1082  * against our list and return its name if we find a match.
 1083  */
 1084 static int tl_probe(dev)
 1085         device_t                dev;
 1086 {
 1087         struct tl_type          *t;
 1088 
 1089         t = tl_devs;
 1090 
 1091         while(t->tl_name != NULL) {
 1092                 if ((pci_get_vendor(dev) == t->tl_vid) &&
 1093                     (pci_get_device(dev) == t->tl_did)) {
 1094                         device_set_desc(dev, t->tl_name);
 1095                         return(0);
 1096                 }
 1097                 t++;
 1098         }
 1099 
 1100         return(ENXIO);
 1101 }
 1102 
 1103 static int tl_attach(dev)
 1104         device_t                dev;
 1105 {
 1106         int                     s, i;
 1107         u_int32_t               command;
 1108         u_int16_t               did, vid;
 1109         struct tl_type          *t;
 1110         struct ifnet            *ifp;
 1111         struct tl_softc         *sc;
 1112         int                     unit, error = 0, rid;
 1113 
 1114         s = splimp();
 1115 
 1116         vid = pci_get_vendor(dev);
 1117         did = pci_get_device(dev);
 1118         sc = device_get_softc(dev);
 1119         unit = device_get_unit(dev);
 1120         bzero(sc, sizeof(struct tl_softc));
 1121 
 1122         t = tl_devs;
 1123         while(t->tl_name != NULL) {
 1124                 if (vid == t->tl_vid && did == t->tl_did)
 1125                         break;
 1126                 t++;
 1127         }
 1128 
 1129         if (t->tl_name == NULL) {
 1130                 printf("tl%d: unknown device!?\n", unit);
 1131                 goto fail;
 1132         }
 1133 
 1134         /*
 1135          * Map control/status registers.
 1136          */
 1137         command = pci_read_config(dev, PCIR_COMMAND, 4);
 1138         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
 1139         pci_write_config(dev, PCIR_COMMAND, command, 4);
 1140         command = pci_read_config(dev, PCIR_COMMAND, 4);
 1141 
 1142 #ifdef TL_USEIOSPACE
 1143         if (!(command & PCIM_CMD_PORTEN)) {
 1144                 printf("tl%d: failed to enable I/O ports!\n", unit);
 1145                 error = ENXIO;
 1146                 goto fail;
 1147         }
 1148 
 1149         rid = TL_PCI_LOIO;
 1150         sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
 1151                 0, ~0, 1, RF_ACTIVE);
 1152 
 1153         /*
 1154          * Some cards have the I/O and memory mapped address registers
 1155          * reversed. Try both combinations before giving up.
 1156          */
 1157         if (sc->tl_res == NULL) {
 1158                 rid = TL_PCI_LOMEM;
 1159                 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
 1160                     0, ~0, 1, RF_ACTIVE);
 1161         }
 1162 #else
 1163         if (!(command & PCIM_CMD_MEMEN)) {
 1164                 printf("tl%d: failed to enable memory mapping!\n", unit);
 1165                 error = ENXIO;
 1166                 goto fail;
 1167         }
 1168 
 1169         rid = TL_PCI_LOMEM;
 1170         sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
 1171             0, ~0, 1, RF_ACTIVE);
 1172         if (sc->tl_res == NULL) {
 1173                 rid = TL_PCI_LOIO;
 1174                 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
 1175                     0, ~0, 1, RF_ACTIVE);
 1176         }
 1177 #endif
 1178 
 1179         if (sc->tl_res == NULL) {
 1180                 printf("tl%d: couldn't map ports/memory\n", unit);
 1181                 error = ENXIO;
 1182                 goto fail;
 1183         }
 1184 
 1185         sc->tl_btag = rman_get_bustag(sc->tl_res);
 1186         sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
 1187 
 1188 #ifdef notdef
 1189         /*
 1190          * The ThunderLAN manual suggests jacking the PCI latency
 1191          * timer all the way up to its maximum value. I'm not sure
 1192          * if this is really necessary, but what the manual wants,
 1193          * the manual gets.
 1194          */
 1195         command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
 1196         command |= 0x0000FF00;
 1197         pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
 1198 #endif
 1199 
 1200         /* Allocate interrupt */
 1201         rid = 0;
 1202         sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
 1203             RF_SHAREABLE | RF_ACTIVE);
 1204 
 1205         if (sc->tl_irq == NULL) {
 1206                 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
 1207                 printf("tl%d: couldn't map interrupt\n", unit);
 1208                 error = ENXIO;
 1209                 goto fail;
 1210         }
 1211 
 1212         error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET,
 1213             tl_intr, sc, &sc->tl_intrhand);
 1214 
 1215         if (error) {
 1216                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
 1217                 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
 1218                 printf("tl%d: couldn't set up irq\n", unit);
 1219                 goto fail;
 1220         }
 1221 
 1222         /*
 1223          * Now allocate memory for the TX and RX lists.
 1224          */
 1225         sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
 1226             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 1227 
 1228         if (sc->tl_ldata == NULL) {
 1229                 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
 1230                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
 1231                 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
 1232                 printf("tl%d: no memory for list buffers!\n", unit);
 1233                 error = ENXIO;
 1234                 goto fail;
 1235         }
 1236 
 1237         bzero(sc->tl_ldata, sizeof(struct tl_list_data));
 1238 
 1239         sc->tl_unit = unit;
 1240         sc->tl_dinfo = t;
 1241         if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
 1242                 sc->tl_eeaddr = TL_EEPROM_EADDR;
 1243         if (t->tl_vid == OLICOM_VENDORID)
 1244                 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
 1245 
 1246         /* Reset the adapter. */
 1247         tl_softreset(sc, 1);
 1248         tl_hardreset(dev);
 1249         tl_softreset(sc, 1);
 1250 
 1251         /*
 1252          * Get station address from the EEPROM.
 1253          */
 1254         if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
 1255                                 sc->tl_eeaddr, ETHER_ADDR_LEN)) {
 1256                 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
 1257                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
 1258                 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
 1259                 contigfree(sc->tl_ldata,
 1260                     sizeof(struct tl_list_data), M_DEVBUF);
 1261                 printf("tl%d: failed to read station address\n", unit);
 1262                 error = ENXIO;
 1263                 goto fail;
 1264         }
 1265 
 1266         /*
 1267          * XXX Olicom, in its desire to be different from the
 1268          * rest of the world, has done strange things with the
 1269          * encoding of the station address in the EEPROM. First
 1270          * of all, they store the address at offset 0xF8 rather
 1271          * than at 0x83 like the ThunderLAN manual suggests.
 1272          * Second, they store the address in three 16-bit words in
 1273          * network byte order, as opposed to storing it sequentially
 1274          * like all the other ThunderLAN cards. In order to get
 1275          * the station address in a form that matches what the Olicom
 1276          * diagnostic utility specifies, we have to byte-swap each
 1277          * word. To make things even more confusing, neither 00:00:28
 1278          * nor 00:00:24 appear in the IEEE OUI database.
 1279          */
 1280         if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
 1281                 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
 1282                         u_int16_t               *p;
 1283                         p = (u_int16_t *)&sc->arpcom.ac_enaddr[i];
 1284                         *p = ntohs(*p);
 1285                 }
 1286         }
 1287 
 1288         /*
 1289          * A ThunderLAN chip was detected. Inform the world.
 1290          */
 1291         printf("tl%d: Ethernet address: %6D\n", unit,
 1292                                 sc->arpcom.ac_enaddr, ":");
 1293 
 1294         ifp = &sc->arpcom.ac_if;
 1295         ifp->if_softc = sc;
 1296         ifp->if_unit = sc->tl_unit;
 1297         ifp->if_name = "tl";
 1298         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1299         ifp->if_ioctl = tl_ioctl;
 1300         ifp->if_output = ether_output;
 1301         ifp->if_start = tl_start;
 1302         ifp->if_watchdog = tl_watchdog;
 1303         ifp->if_init = tl_init;
 1304         ifp->if_mtu = ETHERMTU;
 1305         ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1;
 1306         callout_handle_init(&sc->tl_stat_ch);
 1307 
 1308         /* Reset the adapter again. */
 1309         tl_softreset(sc, 1);
 1310         tl_hardreset(dev);
 1311         tl_softreset(sc, 1);
 1312 
 1313         /*
 1314          * Do MII setup. If no PHYs are found, then this is a
 1315          * bitrate ThunderLAN chip that only supports 10baseT
 1316          * and AUI/BNC.
 1317          */
 1318         if (mii_phy_probe(dev, &sc->tl_miibus,
 1319             tl_ifmedia_upd, tl_ifmedia_sts)) {
 1320                 struct ifmedia          *ifm;
 1321                 sc->tl_bitrate = 1;
 1322                 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
 1323                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 1324                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
 1325                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
 1326                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
 1327                 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
 1328                 /* Reset again, this time setting bitrate mode. */
 1329                 tl_softreset(sc, 1);
 1330                 ifm = &sc->ifmedia;
 1331                 ifm->ifm_media = ifm->ifm_cur->ifm_media;
 1332                 tl_ifmedia_upd(ifp);
 1333         }
 1334 
 1335         /*
 1336          * Call MI attach routine.
 1337          */
 1338         ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
 1339 
 1340 fail:
 1341         splx(s);
 1342         return(error);
 1343 }
 1344 
 1345 static int tl_detach(dev)
 1346         device_t                dev;
 1347 {
 1348         struct tl_softc         *sc;
 1349         struct ifnet            *ifp;
 1350         int                     s;
 1351 
 1352         s = splimp();
 1353 
 1354         sc = device_get_softc(dev);
 1355         ifp = &sc->arpcom.ac_if;
 1356 
 1357         tl_stop(sc);
 1358         ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
 1359 
 1360         bus_generic_detach(dev);
 1361         device_delete_child(dev, sc->tl_miibus);
 1362 
 1363         contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
 1364         if (sc->tl_bitrate)
 1365                 ifmedia_removeall(&sc->ifmedia);
 1366 
 1367         bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
 1368         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
 1369         bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
 1370 
 1371         splx(s);
 1372 
 1373         return(0);
 1374 }
 1375 
 1376 /*
 1377  * Initialize the transmit lists.
 1378  */
 1379 static int tl_list_tx_init(sc)
 1380         struct tl_softc         *sc;
 1381 {
 1382         struct tl_chain_data    *cd;
 1383         struct tl_list_data     *ld;
 1384         int                     i;
 1385 
 1386         cd = &sc->tl_cdata;
 1387         ld = sc->tl_ldata;
 1388         for (i = 0; i < TL_TX_LIST_CNT; i++) {
 1389                 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
 1390                 if (i == (TL_TX_LIST_CNT - 1))
 1391                         cd->tl_tx_chain[i].tl_next = NULL;
 1392                 else
 1393                         cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
 1394         }
 1395 
 1396         cd->tl_tx_free = &cd->tl_tx_chain[0];
 1397         cd->tl_tx_tail = cd->tl_tx_head = NULL;
 1398         sc->tl_txeoc = 1;
 1399 
 1400         return(0);
 1401 }
 1402 
 1403 /*
 1404  * Initialize the RX lists and allocate mbufs for them.
 1405  */
 1406 static int tl_list_rx_init(sc)
 1407         struct tl_softc         *sc;
 1408 {
 1409         struct tl_chain_data    *cd;
 1410         struct tl_list_data     *ld;
 1411         int                     i;
 1412 
 1413         cd = &sc->tl_cdata;
 1414         ld = sc->tl_ldata;
 1415 
 1416         for (i = 0; i < TL_RX_LIST_CNT; i++) {
 1417                 cd->tl_rx_chain[i].tl_ptr =
 1418                         (struct tl_list_onefrag *)&ld->tl_rx_list[i];
 1419                 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
 1420                         return(ENOBUFS);
 1421                 if (i == (TL_RX_LIST_CNT - 1)) {
 1422                         cd->tl_rx_chain[i].tl_next = NULL;
 1423                         ld->tl_rx_list[i].tlist_fptr = 0;
 1424                 } else {
 1425                         cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
 1426                         ld->tl_rx_list[i].tlist_fptr =
 1427                                         vtophys(&ld->tl_rx_list[i + 1]);
 1428                 }
 1429         }
 1430 
 1431         cd->tl_rx_head = &cd->tl_rx_chain[0];
 1432         cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
 1433 
 1434         return(0);
 1435 }
 1436 
 1437 static int tl_newbuf(sc, c)
 1438         struct tl_softc         *sc;
 1439         struct tl_chain_onefrag *c;
 1440 {
 1441         struct mbuf             *m_new = NULL;
 1442 
 1443         MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1444         if (m_new == NULL)
 1445                 return(ENOBUFS);
 1446 
 1447         MCLGET(m_new, M_DONTWAIT);
 1448         if (!(m_new->m_flags & M_EXT)) {
 1449                 m_freem(m_new);
 1450                 return(ENOBUFS);
 1451         }
 1452 
 1453 #ifdef __alpha__
 1454         m_new->m_data += 2;
 1455 #endif
 1456 
 1457         c->tl_mbuf = m_new;
 1458         c->tl_next = NULL;
 1459         c->tl_ptr->tlist_frsize = MCLBYTES;
 1460         c->tl_ptr->tlist_fptr = 0;
 1461         c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
 1462         c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
 1463         c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
 1464 
 1465         return(0);
 1466 }
 1467 /*
 1468  * Interrupt handler for RX 'end of frame' condition (EOF). This
 1469  * tells us that a full ethernet frame has been captured and we need
 1470  * to handle it.
 1471  *
 1472  * Reception is done using 'lists' which consist of a header and a
 1473  * series of 10 data count/data address pairs that point to buffers.
 1474  * Initially you're supposed to create a list, populate it with pointers
 1475  * to buffers, then load the physical address of the list into the
 1476  * ch_parm register. The adapter is then supposed to DMA the received
 1477  * frame into the buffers for you.
 1478  *
 1479  * To make things as fast as possible, we have the chip DMA directly
 1480  * into mbufs. This saves us from having to do a buffer copy: we can
 1481  * just hand the mbufs directly to ether_input(). Once the frame has
 1482  * been sent on its way, the 'list' structure is assigned a new buffer
 1483  * and moved to the end of the RX chain. As long we we stay ahead of
 1484  * the chip, it will always think it has an endless receive channel.
 1485  *
 1486  * If we happen to fall behind and the chip manages to fill up all of
 1487  * the buffers, it will generate an end of channel interrupt and wait
 1488  * for us to empty the chain and restart the receiver.
 1489  */
 1490 static int tl_intvec_rxeof(xsc, type)
 1491         void                    *xsc;
 1492         u_int32_t               type;
 1493 {
 1494         struct tl_softc         *sc;
 1495         int                     r = 0, total_len = 0;
 1496         struct ether_header     *eh;
 1497         struct mbuf             *m;
 1498         struct ifnet            *ifp;
 1499         struct tl_chain_onefrag *cur_rx;
 1500 
 1501         sc = xsc;
 1502         ifp = &sc->arpcom.ac_if;
 1503 
 1504         while(sc->tl_cdata.tl_rx_head != NULL) {
 1505                 cur_rx = sc->tl_cdata.tl_rx_head;
 1506                 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
 1507                         break;
 1508                 r++;
 1509                 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
 1510                 m = cur_rx->tl_mbuf;
 1511                 total_len = cur_rx->tl_ptr->tlist_frsize;
 1512 
 1513                 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
 1514                         ifp->if_ierrors++;
 1515                         cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
 1516                         cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
 1517                         cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
 1518                         continue;
 1519                 }
 1520 
 1521                 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
 1522                                                 vtophys(cur_rx->tl_ptr);
 1523                 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
 1524                 sc->tl_cdata.tl_rx_tail = cur_rx;
 1525 
 1526                 eh = mtod(m, struct ether_header *);
 1527                 m->m_pkthdr.rcvif = ifp;
 1528 
 1529                 /*
 1530                  * Note: when the ThunderLAN chip is in 'capture all
 1531                  * frames' mode, it will receive its own transmissions.
 1532                  * We drop don't need to process our own transmissions,
 1533                  * so we drop them here and continue.
 1534                  */
 1535                 /*if (ifp->if_flags & IFF_PROMISC && */
 1536                 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
 1537                                                         ETHER_ADDR_LEN)) {
 1538                                 m_freem(m);
 1539                                 continue;
 1540                 }
 1541 
 1542                 /* Remove header from mbuf and pass it on. */
 1543                 m->m_pkthdr.len = m->m_len =
 1544                                 total_len - sizeof(struct ether_header);
 1545                 m->m_data += sizeof(struct ether_header);
 1546                 ether_input(ifp, eh, m);
 1547         }
 1548 
 1549         return(r);
 1550 }
 1551 
 1552 /*
 1553  * The RX-EOC condition hits when the ch_parm address hasn't been
 1554  * initialized or the adapter reached a list with a forward pointer
 1555  * of 0 (which indicates the end of the chain). In our case, this means
 1556  * the card has hit the end of the receive buffer chain and we need to
 1557  * empty out the buffers and shift the pointer back to the beginning again.
 1558  */
 1559 static int tl_intvec_rxeoc(xsc, type)
 1560         void                    *xsc;
 1561         u_int32_t               type;
 1562 {
 1563         struct tl_softc         *sc;
 1564         int                     r;
 1565         struct tl_chain_data    *cd;
 1566 
 1567 
 1568         sc = xsc;
 1569         cd = &sc->tl_cdata;
 1570 
 1571         /* Flush out the receive queue and ack RXEOF interrupts. */
 1572         r = tl_intvec_rxeof(xsc, type);
 1573         CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
 1574         r = 1;
 1575         cd->tl_rx_head = &cd->tl_rx_chain[0];
 1576         cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
 1577         CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
 1578         r |= (TL_CMD_GO|TL_CMD_RT);
 1579         return(r);
 1580 }
 1581 
 1582 static int tl_intvec_txeof(xsc, type)
 1583         void                    *xsc;
 1584         u_int32_t               type;
 1585 {
 1586         struct tl_softc         *sc;
 1587         int                     r = 0;
 1588         struct tl_chain         *cur_tx;
 1589 
 1590         sc = xsc;
 1591 
 1592         /*
 1593          * Go through our tx list and free mbufs for those
 1594          * frames that have been sent.
 1595          */
 1596         while (sc->tl_cdata.tl_tx_head != NULL) {
 1597                 cur_tx = sc->tl_cdata.tl_tx_head;
 1598                 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
 1599                         break;
 1600                 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
 1601 
 1602                 r++;
 1603                 m_freem(cur_tx->tl_mbuf);
 1604                 cur_tx->tl_mbuf = NULL;
 1605 
 1606                 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
 1607                 sc->tl_cdata.tl_tx_free = cur_tx;
 1608                 if (!cur_tx->tl_ptr->tlist_fptr)
 1609                         break;
 1610         }
 1611 
 1612         return(r);
 1613 }
 1614 
 1615 /*
 1616  * The transmit end of channel interrupt. The adapter triggers this
 1617  * interrupt to tell us it hit the end of the current transmit list.
 1618  *
 1619  * A note about this: it's possible for a condition to arise where
 1620  * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
 1621  * You have to avoid this since the chip expects things to go in a
 1622  * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
 1623  * When the TXEOF handler is called, it will free all of the transmitted
 1624  * frames and reset the tx_head pointer to NULL. However, a TXEOC
 1625  * interrupt should be received and acknowledged before any more frames
 1626  * are queued for transmission. If tl_statrt() is called after TXEOF
 1627  * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
 1628  * it could attempt to issue a transmit command prematurely.
 1629  *
 1630  * To guard against this, tl_start() will only issue transmit commands
 1631  * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
 1632  * can set this flag once tl_start() has cleared it.
 1633  */
 1634 static int tl_intvec_txeoc(xsc, type)
 1635         void                    *xsc;
 1636         u_int32_t               type;
 1637 {
 1638         struct tl_softc         *sc;
 1639         struct ifnet            *ifp;
 1640         u_int32_t               cmd;
 1641 
 1642         sc = xsc;
 1643         ifp = &sc->arpcom.ac_if;
 1644 
 1645         /* Clear the timeout timer. */
 1646         ifp->if_timer = 0;
 1647 
 1648         if (sc->tl_cdata.tl_tx_head == NULL) {
 1649                 ifp->if_flags &= ~IFF_OACTIVE;
 1650                 sc->tl_cdata.tl_tx_tail = NULL;
 1651                 sc->tl_txeoc = 1;
 1652         } else {
 1653                 sc->tl_txeoc = 0;
 1654                 /* First we have to ack the EOC interrupt. */
 1655                 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
 1656                 /* Then load the address of the next TX list. */
 1657                 CSR_WRITE_4(sc, TL_CH_PARM,
 1658                     vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
 1659                 /* Restart TX channel. */
 1660                 cmd = CSR_READ_4(sc, TL_HOSTCMD);
 1661                 cmd &= ~TL_CMD_RT;
 1662                 cmd |= TL_CMD_GO|TL_CMD_INTSON;
 1663                 CMD_PUT(sc, cmd);
 1664                 return(0);
 1665         }
 1666 
 1667         return(1);
 1668 }
 1669 
 1670 static int tl_intvec_adchk(xsc, type)
 1671         void                    *xsc;
 1672         u_int32_t               type;
 1673 {
 1674         struct tl_softc         *sc;
 1675 
 1676         sc = xsc;
 1677 
 1678         if (type)
 1679                 printf("tl%d: adapter check: %x\n", sc->tl_unit,
 1680                         (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
 1681 
 1682         tl_softreset(sc, 1);
 1683         tl_stop(sc);
 1684         tl_init(sc);
 1685         CMD_SET(sc, TL_CMD_INTSON);
 1686 
 1687         return(0);
 1688 }
 1689 
 1690 static int tl_intvec_netsts(xsc, type)
 1691         void                    *xsc;
 1692         u_int32_t               type;
 1693 {
 1694         struct tl_softc         *sc;
 1695         u_int16_t               netsts;
 1696 
 1697         sc = xsc;
 1698 
 1699         netsts = tl_dio_read16(sc, TL_NETSTS);
 1700         tl_dio_write16(sc, TL_NETSTS, netsts);
 1701 
 1702         printf("tl%d: network status: %x\n", sc->tl_unit, netsts);
 1703 
 1704         return(1);
 1705 }
 1706 
 1707 static void tl_intr(xsc)
 1708         void                    *xsc;
 1709 {
 1710         struct tl_softc         *sc;
 1711         struct ifnet            *ifp;
 1712         int                     r = 0;
 1713         u_int32_t               type = 0;
 1714         u_int16_t               ints = 0;
 1715         u_int8_t                ivec = 0;
 1716 
 1717         sc = xsc;
 1718 
 1719         /* Disable interrupts */
 1720         ints = CSR_READ_2(sc, TL_HOST_INT);
 1721         CSR_WRITE_2(sc, TL_HOST_INT, ints);
 1722         type = (ints << 16) & 0xFFFF0000;
 1723         ivec = (ints & TL_VEC_MASK) >> 5;
 1724         ints = (ints & TL_INT_MASK) >> 2;
 1725 
 1726         ifp = &sc->arpcom.ac_if;
 1727 
 1728         switch(ints) {
 1729         case (TL_INTR_INVALID):
 1730 #ifdef DIAGNOSTIC
 1731                 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit);
 1732 #endif
 1733                 /* Re-enable interrupts but don't ack this one. */
 1734                 CMD_PUT(sc, type);
 1735                 r = 0;
 1736                 break;
 1737         case (TL_INTR_TXEOF):
 1738                 r = tl_intvec_txeof((void *)sc, type);
 1739                 break;
 1740         case (TL_INTR_TXEOC):
 1741                 r = tl_intvec_txeoc((void *)sc, type);
 1742                 break;
 1743         case (TL_INTR_STATOFLOW):
 1744                 tl_stats_update(sc);
 1745                 r = 1;
 1746                 break;
 1747         case (TL_INTR_RXEOF):
 1748                 r = tl_intvec_rxeof((void *)sc, type);
 1749                 break;
 1750         case (TL_INTR_DUMMY):
 1751                 printf("tl%d: got a dummy interrupt\n", sc->tl_unit);
 1752                 r = 1;
 1753                 break;
 1754         case (TL_INTR_ADCHK):
 1755                 if (ivec)
 1756                         r = tl_intvec_adchk((void *)sc, type);
 1757                 else
 1758                         r = tl_intvec_netsts((void *)sc, type);
 1759                 break;
 1760         case (TL_INTR_RXEOC):
 1761                 r = tl_intvec_rxeoc((void *)sc, type);
 1762                 break;
 1763         default:
 1764                 printf("tl%d: bogus interrupt type\n", ifp->if_unit);
 1765                 break;
 1766         }
 1767 
 1768         /* Re-enable interrupts */
 1769         if (r) {
 1770                 CMD_PUT(sc, TL_CMD_ACK | r | type);
 1771         }
 1772 
 1773         if (ifp->if_snd.ifq_head != NULL)
 1774                 tl_start(ifp);
 1775 
 1776         return;
 1777 }
 1778 
 1779 static void tl_stats_update(xsc)
 1780         void                    *xsc;
 1781 {
 1782         struct tl_softc         *sc;
 1783         struct ifnet            *ifp;
 1784         struct tl_stats         tl_stats;
 1785         struct mii_data         *mii;
 1786         u_int32_t               *p;
 1787         int                     s;
 1788 
 1789         s = splimp();
 1790 
 1791         bzero((char *)&tl_stats, sizeof(struct tl_stats));
 1792 
 1793         sc = xsc;
 1794         ifp = &sc->arpcom.ac_if;
 1795 
 1796         p = (u_int32_t *)&tl_stats;
 1797 
 1798         CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
 1799         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 1800         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 1801         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 1802         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 1803         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 1804 
 1805         ifp->if_opackets += tl_tx_goodframes(tl_stats);
 1806         ifp->if_collisions += tl_stats.tl_tx_single_collision +
 1807                                 tl_stats.tl_tx_multi_collision;
 1808         ifp->if_ipackets += tl_rx_goodframes(tl_stats);
 1809         ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
 1810                             tl_rx_overrun(tl_stats);
 1811         ifp->if_oerrors += tl_tx_underrun(tl_stats);
 1812 
 1813         if (tl_tx_underrun(tl_stats)) {
 1814                 u_int8_t                tx_thresh;
 1815                 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
 1816                 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
 1817                         tx_thresh >>= 4;
 1818                         tx_thresh++;
 1819                         printf("tl%d: tx underrun -- increasing "
 1820                             "tx threshold to %d bytes\n", sc->tl_unit,
 1821                             (64 * (tx_thresh * 4)));
 1822                         tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
 1823                         tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
 1824                 }
 1825         }
 1826 
 1827         sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
 1828 
 1829         if (!sc->tl_bitrate) {
 1830                 mii = device_get_softc(sc->tl_miibus);
 1831                 mii_tick(mii);
 1832         }
 1833 
 1834         splx(s);
 1835 
 1836         return;
 1837 }
 1838 
 1839 /*
 1840  * Encapsulate an mbuf chain in a list by coupling the mbuf data
 1841  * pointers to the fragment pointers.
 1842  */
 1843 static int tl_encap(sc, c, m_head)
 1844         struct tl_softc         *sc;
 1845         struct tl_chain         *c;
 1846         struct mbuf             *m_head;
 1847 {
 1848         int                     frag = 0;
 1849         struct tl_frag          *f = NULL;
 1850         int                     total_len;
 1851         struct mbuf             *m;
 1852 
 1853         /*
 1854          * Start packing the mbufs in this chain into
 1855          * the fragment pointers. Stop when we run out
 1856          * of fragments or hit the end of the mbuf chain.
 1857          */
 1858         m = m_head;
 1859         total_len = 0;
 1860 
 1861         for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
 1862                 if (m->m_len != 0) {
 1863                         if (frag == TL_MAXFRAGS)
 1864                                 break;
 1865                         total_len+= m->m_len;
 1866                         c->tl_ptr->tl_frag[frag].tlist_dadr =
 1867                                 vtophys(mtod(m, vm_offset_t));
 1868                         c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
 1869                         frag++;
 1870                 }
 1871         }
 1872 
 1873         /*
 1874          * Handle special cases.
 1875          * Special case #1: we used up all 10 fragments, but
 1876          * we have more mbufs left in the chain. Copy the
 1877          * data into an mbuf cluster. Note that we don't
 1878          * bother clearing the values in the other fragment
 1879          * pointers/counters; it wouldn't gain us anything,
 1880          * and would waste cycles.
 1881          */
 1882         if (m != NULL) {
 1883                 struct mbuf             *m_new = NULL;
 1884 
 1885                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1886                 if (m_new == NULL) {
 1887                         printf("tl%d: no memory for tx list\n", sc->tl_unit);
 1888                         return(1);
 1889                 }
 1890                 if (m_head->m_pkthdr.len > MHLEN) {
 1891                         MCLGET(m_new, M_DONTWAIT);
 1892                         if (!(m_new->m_flags & M_EXT)) {
 1893                                 m_freem(m_new);
 1894                                 printf("tl%d: no memory for tx list\n",
 1895                                 sc->tl_unit);
 1896                                 return(1);
 1897                         }
 1898                 }
 1899                 m_copydata(m_head, 0, m_head->m_pkthdr.len,     
 1900                                         mtod(m_new, caddr_t));
 1901                 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
 1902                 m_freem(m_head);
 1903                 m_head = m_new;
 1904                 f = &c->tl_ptr->tl_frag[0];
 1905                 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
 1906                 f->tlist_dcnt = total_len = m_new->m_len;
 1907                 frag = 1;
 1908         }
 1909 
 1910         /*
 1911          * Special case #2: the frame is smaller than the minimum
 1912          * frame size. We have to pad it to make the chip happy.
 1913          */
 1914         if (total_len < TL_MIN_FRAMELEN) {
 1915                 if (frag == TL_MAXFRAGS)
 1916                         printf("tl%d: all frags filled but "
 1917                                 "frame still to small!\n", sc->tl_unit);
 1918                 f = &c->tl_ptr->tl_frag[frag];
 1919                 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
 1920                 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
 1921                 total_len += f->tlist_dcnt;
 1922                 frag++;
 1923         }
 1924 
 1925         c->tl_mbuf = m_head;
 1926         c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
 1927         c->tl_ptr->tlist_frsize = total_len;
 1928         c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
 1929         c->tl_ptr->tlist_fptr = 0;
 1930 
 1931         return(0);
 1932 }
 1933 
 1934 /*
 1935  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 1936  * to the mbuf data regions directly in the transmit lists. We also save a
 1937  * copy of the pointers since the transmit list fragment pointers are
 1938  * physical addresses.
 1939  */
 1940 static void tl_start(ifp)
 1941         struct ifnet            *ifp;
 1942 {
 1943         struct tl_softc         *sc;
 1944         struct mbuf             *m_head = NULL;
 1945         u_int32_t               cmd;
 1946         struct tl_chain         *prev = NULL, *cur_tx = NULL, *start_tx;
 1947 
 1948         sc = ifp->if_softc;
 1949 
 1950         /*
 1951          * Check for an available queue slot. If there are none,
 1952          * punt.
 1953          */
 1954         if (sc->tl_cdata.tl_tx_free == NULL) {
 1955                 ifp->if_flags |= IFF_OACTIVE;
 1956                 return;
 1957         }
 1958 
 1959         start_tx = sc->tl_cdata.tl_tx_free;
 1960 
 1961         while(sc->tl_cdata.tl_tx_free != NULL) {
 1962                 IF_DEQUEUE(&ifp->if_snd, m_head);
 1963                 if (m_head == NULL)
 1964                         break;
 1965 
 1966                 /* Pick a chain member off the free list. */
 1967                 cur_tx = sc->tl_cdata.tl_tx_free;
 1968                 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
 1969 
 1970                 cur_tx->tl_next = NULL;
 1971 
 1972                 /* Pack the data into the list. */
 1973                 tl_encap(sc, cur_tx, m_head);
 1974 
 1975                 /* Chain it together */
 1976                 if (prev != NULL) {
 1977                         prev->tl_next = cur_tx;
 1978                         prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
 1979                 }
 1980                 prev = cur_tx;
 1981 
 1982                 /*
 1983                  * If there's a BPF listener, bounce a copy of this frame
 1984                  * to him.
 1985                  */
 1986                 if (ifp->if_bpf)
 1987                         bpf_mtap(ifp, cur_tx->tl_mbuf);
 1988         }
 1989 
 1990         /*
 1991          * If there are no packets queued, bail.
 1992          */
 1993         if (cur_tx == NULL)
 1994                 return;
 1995 
 1996         /*
 1997          * That's all we can stands, we can't stands no more.
 1998          * If there are no other transfers pending, then issue the
 1999          * TX GO command to the adapter to start things moving.
 2000          * Otherwise, just leave the data in the queue and let
 2001          * the EOF/EOC interrupt handler send.
 2002          */
 2003         if (sc->tl_cdata.tl_tx_head == NULL) {
 2004                 sc->tl_cdata.tl_tx_head = start_tx;
 2005                 sc->tl_cdata.tl_tx_tail = cur_tx;
 2006 
 2007                 if (sc->tl_txeoc) {
 2008                         sc->tl_txeoc = 0;
 2009                         CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
 2010                         cmd = CSR_READ_4(sc, TL_HOSTCMD);
 2011                         cmd &= ~TL_CMD_RT;
 2012                         cmd |= TL_CMD_GO|TL_CMD_INTSON;
 2013                         CMD_PUT(sc, cmd);
 2014                 }
 2015         } else {
 2016                 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
 2017                 sc->tl_cdata.tl_tx_tail = cur_tx;
 2018         }
 2019 
 2020         /*
 2021          * Set a timeout in case the chip goes out to lunch.
 2022          */
 2023         ifp->if_timer = 5;
 2024 
 2025         return;
 2026 }
 2027 
 2028 static void tl_init(xsc)
 2029         void                    *xsc;
 2030 {
 2031         struct tl_softc         *sc = xsc;
 2032         struct ifnet            *ifp = &sc->arpcom.ac_if;
 2033         int                     s;
 2034         struct mii_data         *mii;
 2035 
 2036         s = splimp();
 2037 
 2038         ifp = &sc->arpcom.ac_if;
 2039 
 2040         /*
 2041          * Cancel pending I/O.
 2042          */
 2043         tl_stop(sc);
 2044 
 2045         /* Initialize TX FIFO threshold */
 2046         tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
 2047         tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
 2048 
 2049         /* Set PCI burst size */
 2050         tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
 2051 
 2052         /*
 2053          * Set 'capture all frames' bit for promiscuous mode.
 2054          */
 2055         if (ifp->if_flags & IFF_PROMISC)
 2056                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
 2057         else
 2058                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
 2059 
 2060         /*
 2061          * Set capture broadcast bit to capture broadcast frames.
 2062          */
 2063         if (ifp->if_flags & IFF_BROADCAST)
 2064                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
 2065         else
 2066                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
 2067 
 2068         tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
 2069 
 2070         /* Init our MAC address */
 2071         tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
 2072 
 2073         /* Init multicast filter, if needed. */
 2074         tl_setmulti(sc);
 2075 
 2076         /* Init circular RX list. */
 2077         if (tl_list_rx_init(sc) == ENOBUFS) {
 2078                 printf("tl%d: initialization failed: no "
 2079                         "memory for rx buffers\n", sc->tl_unit);
 2080                 tl_stop(sc);
 2081                 return;
 2082         }
 2083 
 2084         /* Init TX pointers. */
 2085         tl_list_tx_init(sc);
 2086 
 2087         /* Enable PCI interrupts. */
 2088         CMD_SET(sc, TL_CMD_INTSON);
 2089 
 2090         /* Load the address of the rx list */
 2091         CMD_SET(sc, TL_CMD_RT);
 2092         CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
 2093 
 2094         if (!sc->tl_bitrate) {
 2095                 if (sc->tl_miibus != NULL) {
 2096                         mii = device_get_softc(sc->tl_miibus);
 2097                         mii_mediachg(mii);
 2098                 }
 2099         }
 2100 
 2101         /* Send the RX go command */
 2102         CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
 2103 
 2104         ifp->if_flags |= IFF_RUNNING;
 2105         ifp->if_flags &= ~IFF_OACTIVE;
 2106 
 2107         (void)splx(s);
 2108 
 2109         /* Start the stats update counter */
 2110         sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
 2111 
 2112         return;
 2113 }
 2114 
 2115 /*
 2116  * Set media options.
 2117  */
 2118 static int tl_ifmedia_upd(ifp)
 2119         struct ifnet            *ifp;
 2120 {
 2121         struct tl_softc         *sc;
 2122         struct mii_data         *mii = NULL;
 2123 
 2124         sc = ifp->if_softc;
 2125 
 2126         if (sc->tl_bitrate)
 2127                 tl_setmode(sc, sc->ifmedia.ifm_media);
 2128         else {
 2129                 mii = device_get_softc(sc->tl_miibus);
 2130                 mii_mediachg(mii);
 2131         }
 2132 
 2133         return(0);
 2134 }
 2135 
 2136 /*
 2137  * Report current media status.
 2138  */
 2139 static void tl_ifmedia_sts(ifp, ifmr)
 2140         struct ifnet            *ifp;
 2141         struct ifmediareq       *ifmr;
 2142 {
 2143         struct tl_softc         *sc;
 2144         struct mii_data         *mii;
 2145 
 2146         sc = ifp->if_softc;
 2147 
 2148         ifmr->ifm_active = IFM_ETHER;
 2149 
 2150         if (sc->tl_bitrate) {
 2151                 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
 2152                         ifmr->ifm_active = IFM_ETHER|IFM_10_5;
 2153                 else
 2154                         ifmr->ifm_active = IFM_ETHER|IFM_10_T;
 2155                 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
 2156                         ifmr->ifm_active |= IFM_HDX;
 2157                 else
 2158                         ifmr->ifm_active |= IFM_FDX;
 2159                 return;
 2160         } else {
 2161                 mii = device_get_softc(sc->tl_miibus);
 2162                 mii_pollstat(mii);
 2163                 ifmr->ifm_active = mii->mii_media_active;
 2164                 ifmr->ifm_status = mii->mii_media_status;
 2165         }
 2166 
 2167         return;
 2168 }
 2169 
 2170 static int tl_ioctl(ifp, command, data)
 2171         struct ifnet            *ifp;
 2172         u_long                  command;
 2173         caddr_t                 data;
 2174 {
 2175         struct tl_softc         *sc = ifp->if_softc;
 2176         struct ifreq            *ifr = (struct ifreq *) data;
 2177         int                     s, error = 0;
 2178 
 2179         s = splimp();
 2180 
 2181         switch(command) {
 2182         case SIOCSIFADDR:
 2183         case SIOCGIFADDR:
 2184         case SIOCSIFMTU:
 2185                 error = ether_ioctl(ifp, command, data);
 2186                 break;
 2187         case SIOCSIFFLAGS:
 2188                 if (ifp->if_flags & IFF_UP) {
 2189                         if (ifp->if_flags & IFF_RUNNING &&
 2190                             ifp->if_flags & IFF_PROMISC &&
 2191                             !(sc->tl_if_flags & IFF_PROMISC)) {
 2192                                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
 2193                                 tl_setmulti(sc);
 2194                         } else if (ifp->if_flags & IFF_RUNNING &&
 2195                             !(ifp->if_flags & IFF_PROMISC) &&
 2196                             sc->tl_if_flags & IFF_PROMISC) {
 2197                                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
 2198                                 tl_setmulti(sc);
 2199                         } else
 2200                                 tl_init(sc);
 2201                 } else {
 2202                         if (ifp->if_flags & IFF_RUNNING) {
 2203                                 tl_stop(sc);
 2204                         }
 2205                 }
 2206                 sc->tl_if_flags = ifp->if_flags;
 2207                 error = 0;
 2208                 break;
 2209         case SIOCADDMULTI:
 2210         case SIOCDELMULTI:
 2211                 tl_setmulti(sc);
 2212                 error = 0;
 2213                 break;
 2214         case SIOCSIFMEDIA:
 2215         case SIOCGIFMEDIA:
 2216                 if (sc->tl_bitrate)
 2217                         error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
 2218                 else {
 2219                         struct mii_data         *mii;
 2220                         mii = device_get_softc(sc->tl_miibus);
 2221                         error = ifmedia_ioctl(ifp, ifr,
 2222                             &mii->mii_media, command);
 2223                 }
 2224                 break;
 2225         default:
 2226                 error = EINVAL;
 2227                 break;
 2228         }
 2229 
 2230         (void)splx(s);
 2231 
 2232         return(error);
 2233 }
 2234 
 2235 static void tl_watchdog(ifp)
 2236         struct ifnet            *ifp;
 2237 {
 2238         struct tl_softc         *sc;
 2239 
 2240         sc = ifp->if_softc;
 2241 
 2242         printf("tl%d: device timeout\n", sc->tl_unit);
 2243 
 2244         ifp->if_oerrors++;
 2245 
 2246         tl_softreset(sc, 1);
 2247         tl_init(sc);
 2248 
 2249         return;
 2250 }
 2251 
 2252 /*
 2253  * Stop the adapter and free any mbufs allocated to the
 2254  * RX and TX lists.
 2255  */
 2256 static void tl_stop(sc)
 2257         struct tl_softc         *sc;
 2258 {
 2259         register int            i;
 2260         struct ifnet            *ifp;
 2261 
 2262         ifp = &sc->arpcom.ac_if;
 2263 
 2264         /* Stop the stats updater. */
 2265         untimeout(tl_stats_update, sc, sc->tl_stat_ch);
 2266 
 2267         /* Stop the transmitter */
 2268         CMD_CLR(sc, TL_CMD_RT);
 2269         CMD_SET(sc, TL_CMD_STOP);
 2270         CSR_WRITE_4(sc, TL_CH_PARM, 0);
 2271 
 2272         /* Stop the receiver */
 2273         CMD_SET(sc, TL_CMD_RT);
 2274         CMD_SET(sc, TL_CMD_STOP);
 2275         CSR_WRITE_4(sc, TL_CH_PARM, 0);
 2276 
 2277         /*
 2278          * Disable host interrupts.
 2279          */
 2280         CMD_SET(sc, TL_CMD_INTSOFF);
 2281 
 2282         /*
 2283          * Clear list pointer.
 2284          */
 2285         CSR_WRITE_4(sc, TL_CH_PARM, 0);
 2286 
 2287         /*
 2288          * Free the RX lists.
 2289          */
 2290         for (i = 0; i < TL_RX_LIST_CNT; i++) {
 2291                 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
 2292                         m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
 2293                         sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
 2294                 }
 2295         }
 2296         bzero((char *)&sc->tl_ldata->tl_rx_list,
 2297                 sizeof(sc->tl_ldata->tl_rx_list));
 2298 
 2299         /*
 2300          * Free the TX list buffers.
 2301          */
 2302         for (i = 0; i < TL_TX_LIST_CNT; i++) {
 2303                 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
 2304                         m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
 2305                         sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
 2306                 }
 2307         }
 2308         bzero((char *)&sc->tl_ldata->tl_tx_list,
 2309                 sizeof(sc->tl_ldata->tl_tx_list));
 2310 
 2311         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 2312 
 2313         return;
 2314 }
 2315 
 2316 /*
 2317  * Stop all chip I/O so that the kernel's probe routines don't
 2318  * get confused by errant DMAs when rebooting.
 2319  */
 2320 static void tl_shutdown(dev)
 2321         device_t                dev;
 2322 {
 2323         struct tl_softc         *sc;
 2324 
 2325         sc = device_get_softc(dev);
 2326 
 2327         tl_stop(sc);
 2328 
 2329         return;
 2330 }

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