FreeBSD/Linux Kernel Cross Reference
sys/pci/if_tl.c
1 /*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
35 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
36 * the National Semiconductor DP83840A physical interface and the
37 * Microchip Technology 24Cxx series serial EEPROM.
38 *
39 * Written using the following four documents:
40 *
41 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
42 * National Semiconductor DP83840A data sheet (www.national.com)
43 * Microchip Technology 24C02C data sheet (www.microchip.com)
44 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
45 *
46 * Written by Bill Paul <wpaul@ctr.columbia.edu>
47 * Electrical Engineering Department
48 * Columbia University, New York City
49 */
50
51 /*
52 * Some notes about the ThunderLAN:
53 *
54 * The ThunderLAN controller is a single chip containing PCI controller
55 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
56 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
57 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
58 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
59 * to act as a complete ethernet interface.
60 *
61 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
62 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
63 * in full or half duplex. Some of the Compaq Deskpro machines use a
64 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
65 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
66 * concert with the ThunderLAN's internal PHY to provide full 10/100
67 * support. This is cheaper than using a standalone external PHY for both
68 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
69 * A serial EEPROM is also attached to the ThunderLAN chip to provide
70 * power-up default register settings and for storing the adapter's
71 * station address. Although not supported by this driver, the ThunderLAN
72 * chip can also be connected to token ring PHYs.
73 *
74 * The ThunderLAN has a set of registers which can be used to issue
75 * commands, acknowledge interrupts, and to manipulate other internal
76 * registers on its DIO bus. The primary registers can be accessed
77 * using either programmed I/O (inb/outb) or via PCI memory mapping,
78 * depending on how the card is configured during the PCI probing
79 * phase. It is even possible to have both PIO and memory mapped
80 * access turned on at the same time.
81 *
82 * Frame reception and transmission with the ThunderLAN chip is done
83 * using frame 'lists.' A list structure looks more or less like this:
84 *
85 * struct tl_frag {
86 * u_int32_t fragment_address;
87 * u_int32_t fragment_size;
88 * };
89 * struct tl_list {
90 * u_int32_t forward_pointer;
91 * u_int16_t cstat;
92 * u_int16_t frame_size;
93 * struct tl_frag fragments[10];
94 * };
95 *
96 * The forward pointer in the list header can be either a 0 or the address
97 * of another list, which allows several lists to be linked together. Each
98 * list contains up to 10 fragment descriptors. This means the chip allows
99 * ethernet frames to be broken up into up to 10 chunks for transfer to
100 * and from the SRAM. Note that the forward pointer and fragment buffer
101 * addresses are physical memory addresses, not virtual. Note also that
102 * a single ethernet frame can not span lists: if the host wants to
103 * transmit a frame and the frame data is split up over more than 10
104 * buffers, the frame has to collapsed before it can be transmitted.
105 *
106 * To receive frames, the driver sets up a number of lists and populates
107 * the fragment descriptors, then it sends an RX GO command to the chip.
108 * When a frame is received, the chip will DMA it into the memory regions
109 * specified by the fragment descriptors and then trigger an RX 'end of
110 * frame interrupt' when done. The driver may choose to use only one
111 * fragment per list; this may result is slighltly less efficient use
112 * of memory in exchange for improving performance.
113 *
114 * To transmit frames, the driver again sets up lists and fragment
115 * descriptors, only this time the buffers contain frame data that
116 * is to be DMA'ed into the chip instead of out of it. Once the chip
117 * has transfered the data into its on-board SRAM, it will trigger a
118 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
119 * interrupt when it reaches the end of the list.
120 */
121
122 /*
123 * Some notes about this driver:
124 *
125 * The ThunderLAN chip provides a couple of different ways to organize
126 * reception, transmission and interrupt handling. The simplest approach
127 * is to use one list each for transmission and reception. In this mode,
128 * the ThunderLAN will generate two interrupts for every received frame
129 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
130 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
131 * performance to have to handle so many interrupts.
132 *
133 * Initially I wanted to create a circular list of receive buffers so
134 * that the ThunderLAN chip would think there was an infinitely long
135 * receive channel and never deliver an RXEOC interrupt. However this
136 * doesn't work correctly under heavy load: while the manual says the
137 * chip will trigger an RXEOF interrupt each time a frame is copied into
138 * memory, you can't count on the chip waiting around for you to acknowledge
139 * the interrupt before it starts trying to DMA the next frame. The result
140 * is that the chip might traverse the entire circular list and then wrap
141 * around before you have a chance to do anything about it. Consequently,
142 * the receive list is terminated (with a 0 in the forward pointer in the
143 * last element). Each time an RXEOF interrupt arrives, the used list
144 * is shifted to the end of the list. This gives the appearance of an
145 * infinitely large RX chain so long as the driver doesn't fall behind
146 * the chip and allow all of the lists to be filled up.
147 *
148 * If all the lists are filled, the adapter will deliver an RX 'end of
149 * channel' interrupt when it hits the 0 forward pointer at the end of
150 * the chain. The RXEOC handler then cleans out the RX chain and resets
151 * the list head pointer in the ch_parm register and restarts the receiver.
152 *
153 * For frame transmission, it is possible to program the ThunderLAN's
154 * transmit interrupt threshold so that the chip can acknowledge multiple
155 * lists with only a single TX EOF interrupt. This allows the driver to
156 * queue several frames in one shot, and only have to handle a total
157 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
158 * are transmitted. Frame transmission is done directly out of the
159 * mbufs passed to the tl_start() routine via the interface send queue.
160 * The driver simply sets up the fragment descriptors in the transmit
161 * lists to point to the mbuf data regions and sends a TX GO command.
162 *
163 * Note that since the RX and TX lists themselves are always used
164 * only by the driver, the are malloc()ed once at driver initialization
165 * time and never free()ed.
166 *
167 * Also, in order to remain as platform independent as possible, this
168 * driver uses memory mapped register access to manipulate the card
169 * as opposed to programmed I/O. This avoids the use of the inb/outb
170 * (and related) instructions which are specific to the i386 platform.
171 *
172 * Using these techniques, this driver achieves very high performance
173 * by minimizing the amount of interrupts generated during large
174 * transfers and by completely avoiding buffer copies. Frame transfer
175 * to and from the ThunderLAN chip is performed entirely by the chip
176 * itself thereby reducing the load on the host CPU.
177 */
178
179 #include <sys/cdefs.h>
180 __FBSDID("$FreeBSD: releng/5.1/sys/pci/if_tl.c 113812 2003-04-21 18:34:04Z imp $");
181
182 #include <sys/param.h>
183 #include <sys/systm.h>
184 #include <sys/sockio.h>
185 #include <sys/mbuf.h>
186 #include <sys/malloc.h>
187 #include <sys/kernel.h>
188 #include <sys/socket.h>
189
190 #include <net/if.h>
191 #include <net/if_arp.h>
192 #include <net/ethernet.h>
193 #include <net/if_dl.h>
194 #include <net/if_media.h>
195
196 #include <net/bpf.h>
197
198 #include <vm/vm.h> /* for vtophys */
199 #include <vm/pmap.h> /* for vtophys */
200 #include <machine/bus_memio.h>
201 #include <machine/bus_pio.h>
202 #include <machine/bus.h>
203 #include <machine/resource.h>
204 #include <sys/bus.h>
205 #include <sys/rman.h>
206
207 #include <dev/mii/mii.h>
208 #include <dev/mii/miivar.h>
209
210 #include <pci/pcireg.h>
211 #include <pci/pcivar.h>
212
213 /*
214 * Default to using PIO register access mode to pacify certain
215 * laptop docking stations with built-in ThunderLAN chips that
216 * don't seem to handle memory mapped mode properly.
217 */
218 #define TL_USEIOSPACE
219
220 #include <pci/if_tlreg.h>
221
222 MODULE_DEPEND(tl, pci, 1, 1, 1);
223 MODULE_DEPEND(tl, ether, 1, 1, 1);
224 MODULE_DEPEND(tl, miibus, 1, 1, 1);
225
226 /* "controller miibus0" required. See GENERIC if you get errors here. */
227 #include "miibus_if.h"
228
229 /*
230 * Various supported device vendors/types and their names.
231 */
232
233 static struct tl_type tl_devs[] = {
234 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
235 "Texas Instruments ThunderLAN" },
236 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
237 "Compaq Netelligent 10" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
239 "Compaq Netelligent 10/100" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
241 "Compaq Netelligent 10/100 Proliant" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
243 "Compaq Netelligent 10/100 Dual Port" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
245 "Compaq NetFlex-3/P Integrated" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
247 "Compaq NetFlex-3/P" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
249 "Compaq NetFlex 3/P w/ BNC" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
251 "Compaq Netelligent 10/100 TX Embedded UTP" },
252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
253 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
254 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
255 "Compaq Netelligent 10/100 TX UTP" },
256 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
257 "Olicom OC-2183/2185" },
258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
259 "Olicom OC-2325" },
260 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
261 "Olicom OC-2326 10/100 TX UTP" },
262 { 0, 0, NULL }
263 };
264
265 static int tl_probe (device_t);
266 static int tl_attach (device_t);
267 static int tl_detach (device_t);
268 static int tl_intvec_rxeoc (void *, u_int32_t);
269 static int tl_intvec_txeoc (void *, u_int32_t);
270 static int tl_intvec_txeof (void *, u_int32_t);
271 static int tl_intvec_rxeof (void *, u_int32_t);
272 static int tl_intvec_adchk (void *, u_int32_t);
273 static int tl_intvec_netsts (void *, u_int32_t);
274
275 static int tl_newbuf (struct tl_softc *, struct tl_chain_onefrag *);
276 static void tl_stats_update (void *);
277 static int tl_encap (struct tl_softc *, struct tl_chain *,
278 struct mbuf *);
279
280 static void tl_intr (void *);
281 static void tl_start (struct ifnet *);
282 static int tl_ioctl (struct ifnet *, u_long, caddr_t);
283 static void tl_init (void *);
284 static void tl_stop (struct tl_softc *);
285 static void tl_watchdog (struct ifnet *);
286 static void tl_shutdown (device_t);
287 static int tl_ifmedia_upd (struct ifnet *);
288 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
289
290 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int);
291 static u_int8_t tl_eeprom_getbyte (struct tl_softc *, int, u_int8_t *);
292 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int);
293
294 static void tl_mii_sync (struct tl_softc *);
295 static void tl_mii_send (struct tl_softc *, u_int32_t, int);
296 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *);
297 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *);
298 static int tl_miibus_readreg (device_t, int, int);
299 static int tl_miibus_writereg (device_t, int, int, int);
300 static void tl_miibus_statchg (device_t);
301
302 static void tl_setmode (struct tl_softc *, int);
303 static int tl_calchash (caddr_t);
304 static void tl_setmulti (struct tl_softc *);
305 static void tl_setfilt (struct tl_softc *, caddr_t, int);
306 static void tl_softreset (struct tl_softc *, int);
307 static void tl_hardreset (device_t);
308 static int tl_list_rx_init (struct tl_softc *);
309 static int tl_list_tx_init (struct tl_softc *);
310
311 static u_int8_t tl_dio_read8 (struct tl_softc *, int);
312 static u_int16_t tl_dio_read16 (struct tl_softc *, int);
313 static u_int32_t tl_dio_read32 (struct tl_softc *, int);
314 static void tl_dio_write8 (struct tl_softc *, int, int);
315 static void tl_dio_write16 (struct tl_softc *, int, int);
316 static void tl_dio_write32 (struct tl_softc *, int, int);
317 static void tl_dio_setbit (struct tl_softc *, int, int);
318 static void tl_dio_clrbit (struct tl_softc *, int, int);
319 static void tl_dio_setbit16 (struct tl_softc *, int, int);
320 static void tl_dio_clrbit16 (struct tl_softc *, int, int);
321
322 #ifdef TL_USEIOSPACE
323 #define TL_RES SYS_RES_IOPORT
324 #define TL_RID TL_PCI_LOIO
325 #else
326 #define TL_RES SYS_RES_MEMORY
327 #define TL_RID TL_PCI_LOMEM
328 #endif
329
330 static device_method_t tl_methods[] = {
331 /* Device interface */
332 DEVMETHOD(device_probe, tl_probe),
333 DEVMETHOD(device_attach, tl_attach),
334 DEVMETHOD(device_detach, tl_detach),
335 DEVMETHOD(device_shutdown, tl_shutdown),
336
337 /* bus interface */
338 DEVMETHOD(bus_print_child, bus_generic_print_child),
339 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
340
341 /* MII interface */
342 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
343 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
344 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
345
346 { 0, 0 }
347 };
348
349 static driver_t tl_driver = {
350 "tl",
351 tl_methods,
352 sizeof(struct tl_softc)
353 };
354
355 static devclass_t tl_devclass;
356
357 DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0);
358 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
359
360 static u_int8_t tl_dio_read8(sc, reg)
361 struct tl_softc *sc;
362 int reg;
363 {
364 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
365 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
366 }
367
368 static u_int16_t tl_dio_read16(sc, reg)
369 struct tl_softc *sc;
370 int reg;
371 {
372 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
373 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
374 }
375
376 static u_int32_t tl_dio_read32(sc, reg)
377 struct tl_softc *sc;
378 int reg;
379 {
380 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
381 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
382 }
383
384 static void tl_dio_write8(sc, reg, val)
385 struct tl_softc *sc;
386 int reg;
387 int val;
388 {
389 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
390 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
391 return;
392 }
393
394 static void tl_dio_write16(sc, reg, val)
395 struct tl_softc *sc;
396 int reg;
397 int val;
398 {
399 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
400 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
401 return;
402 }
403
404 static void tl_dio_write32(sc, reg, val)
405 struct tl_softc *sc;
406 int reg;
407 int val;
408 {
409 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
410 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
411 return;
412 }
413
414 static void
415 tl_dio_setbit(sc, reg, bit)
416 struct tl_softc *sc;
417 int reg;
418 int bit;
419 {
420 u_int8_t f;
421
422 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
423 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
424 f |= bit;
425 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
426
427 return;
428 }
429
430 static void
431 tl_dio_clrbit(sc, reg, bit)
432 struct tl_softc *sc;
433 int reg;
434 int bit;
435 {
436 u_int8_t f;
437
438 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
439 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
440 f &= ~bit;
441 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
442
443 return;
444 }
445
446 static void tl_dio_setbit16(sc, reg, bit)
447 struct tl_softc *sc;
448 int reg;
449 int bit;
450 {
451 u_int16_t f;
452
453 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
454 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
455 f |= bit;
456 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
457
458 return;
459 }
460
461 static void tl_dio_clrbit16(sc, reg, bit)
462 struct tl_softc *sc;
463 int reg;
464 int bit;
465 {
466 u_int16_t f;
467
468 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
469 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
470 f &= ~bit;
471 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
472
473 return;
474 }
475
476 /*
477 * Send an instruction or address to the EEPROM, check for ACK.
478 */
479 static u_int8_t tl_eeprom_putbyte(sc, byte)
480 struct tl_softc *sc;
481 int byte;
482 {
483 register int i, ack = 0;
484
485 /*
486 * Make sure we're in TX mode.
487 */
488 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
489
490 /*
491 * Feed in each bit and stobe the clock.
492 */
493 for (i = 0x80; i; i >>= 1) {
494 if (byte & i) {
495 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
496 } else {
497 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
498 }
499 DELAY(1);
500 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
501 DELAY(1);
502 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
503 }
504
505 /*
506 * Turn off TX mode.
507 */
508 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
509
510 /*
511 * Check for ack.
512 */
513 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
514 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
515 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
516
517 return(ack);
518 }
519
520 /*
521 * Read a byte of data stored in the EEPROM at address 'addr.'
522 */
523 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
524 struct tl_softc *sc;
525 int addr;
526 u_int8_t *dest;
527 {
528 register int i;
529 u_int8_t byte = 0;
530 struct ifnet *ifp = &sc->arpcom.ac_if;
531
532 tl_dio_write8(sc, TL_NETSIO, 0);
533
534 EEPROM_START;
535
536 /*
537 * Send write control code to EEPROM.
538 */
539 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
540 if_printf(ifp, "failed to send write command, status: %x\n",
541 tl_dio_read8(sc, TL_NETSIO));
542 return(1);
543 }
544
545 /*
546 * Send address of byte we want to read.
547 */
548 if (tl_eeprom_putbyte(sc, addr)) {
549 if_printf(ifp, "failed to send address, status: %x\n",
550 tl_dio_read8(sc, TL_NETSIO));
551 return(1);
552 }
553
554 EEPROM_STOP;
555 EEPROM_START;
556 /*
557 * Send read control code to EEPROM.
558 */
559 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
560 if_printf(ifp, "failed to send write command, status: %x\n",
561 tl_dio_read8(sc, TL_NETSIO));
562 return(1);
563 }
564
565 /*
566 * Start reading bits from EEPROM.
567 */
568 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
569 for (i = 0x80; i; i >>= 1) {
570 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
571 DELAY(1);
572 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
573 byte |= i;
574 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
575 DELAY(1);
576 }
577
578 EEPROM_STOP;
579
580 /*
581 * No ACK generated for read, so just return byte.
582 */
583
584 *dest = byte;
585
586 return(0);
587 }
588
589 /*
590 * Read a sequence of bytes from the EEPROM.
591 */
592 static int
593 tl_read_eeprom(sc, dest, off, cnt)
594 struct tl_softc *sc;
595 caddr_t dest;
596 int off;
597 int cnt;
598 {
599 int err = 0, i;
600 u_int8_t byte = 0;
601
602 for (i = 0; i < cnt; i++) {
603 err = tl_eeprom_getbyte(sc, off + i, &byte);
604 if (err)
605 break;
606 *(dest + i) = byte;
607 }
608
609 return(err ? 1 : 0);
610 }
611
612 static void
613 tl_mii_sync(sc)
614 struct tl_softc *sc;
615 {
616 register int i;
617
618 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
619
620 for (i = 0; i < 32; i++) {
621 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
622 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
623 }
624
625 return;
626 }
627
628 static void
629 tl_mii_send(sc, bits, cnt)
630 struct tl_softc *sc;
631 u_int32_t bits;
632 int cnt;
633 {
634 int i;
635
636 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
637 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
638 if (bits & i) {
639 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
640 } else {
641 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
642 }
643 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
644 }
645 }
646
647 static int
648 tl_mii_readreg(sc, frame)
649 struct tl_softc *sc;
650 struct tl_mii_frame *frame;
651
652 {
653 int i, ack;
654 int minten = 0;
655
656 TL_LOCK(sc);
657
658 tl_mii_sync(sc);
659
660 /*
661 * Set up frame for RX.
662 */
663 frame->mii_stdelim = TL_MII_STARTDELIM;
664 frame->mii_opcode = TL_MII_READOP;
665 frame->mii_turnaround = 0;
666 frame->mii_data = 0;
667
668 /*
669 * Turn off MII interrupt by forcing MINTEN low.
670 */
671 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
672 if (minten) {
673 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
674 }
675
676 /*
677 * Turn on data xmit.
678 */
679 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
680
681 /*
682 * Send command/address info.
683 */
684 tl_mii_send(sc, frame->mii_stdelim, 2);
685 tl_mii_send(sc, frame->mii_opcode, 2);
686 tl_mii_send(sc, frame->mii_phyaddr, 5);
687 tl_mii_send(sc, frame->mii_regaddr, 5);
688
689 /*
690 * Turn off xmit.
691 */
692 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
693
694 /* Idle bit */
695 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
696 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
697
698 /* Check for ack */
699 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
700 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
701
702 /* Complete the cycle */
703 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
704
705 /*
706 * Now try reading data bits. If the ack failed, we still
707 * need to clock through 16 cycles to keep the PHYs in sync.
708 */
709 if (ack) {
710 for(i = 0; i < 16; i++) {
711 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
712 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
713 }
714 goto fail;
715 }
716
717 for (i = 0x8000; i; i >>= 1) {
718 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
719 if (!ack) {
720 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
721 frame->mii_data |= i;
722 }
723 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
724 }
725
726 fail:
727
728 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
729 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
730
731 /* Reenable interrupts */
732 if (minten) {
733 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
734 }
735
736 TL_UNLOCK(sc);
737
738 if (ack)
739 return(1);
740 return(0);
741 }
742
743 static int
744 tl_mii_writereg(sc, frame)
745 struct tl_softc *sc;
746 struct tl_mii_frame *frame;
747
748 {
749 int minten;
750
751 TL_LOCK(sc);
752
753 tl_mii_sync(sc);
754
755 /*
756 * Set up frame for TX.
757 */
758
759 frame->mii_stdelim = TL_MII_STARTDELIM;
760 frame->mii_opcode = TL_MII_WRITEOP;
761 frame->mii_turnaround = TL_MII_TURNAROUND;
762
763 /*
764 * Turn off MII interrupt by forcing MINTEN low.
765 */
766 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
767 if (minten) {
768 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
769 }
770
771 /*
772 * Turn on data output.
773 */
774 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
775
776 tl_mii_send(sc, frame->mii_stdelim, 2);
777 tl_mii_send(sc, frame->mii_opcode, 2);
778 tl_mii_send(sc, frame->mii_phyaddr, 5);
779 tl_mii_send(sc, frame->mii_regaddr, 5);
780 tl_mii_send(sc, frame->mii_turnaround, 2);
781 tl_mii_send(sc, frame->mii_data, 16);
782
783 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
784 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
785
786 /*
787 * Turn off xmit.
788 */
789 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
790
791 /* Reenable interrupts */
792 if (minten)
793 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
794
795 TL_UNLOCK(sc);
796
797 return(0);
798 }
799
800 static int
801 tl_miibus_readreg(dev, phy, reg)
802 device_t dev;
803 int phy, reg;
804 {
805 struct tl_softc *sc;
806 struct tl_mii_frame frame;
807
808 sc = device_get_softc(dev);
809 bzero((char *)&frame, sizeof(frame));
810
811 frame.mii_phyaddr = phy;
812 frame.mii_regaddr = reg;
813 tl_mii_readreg(sc, &frame);
814
815 return(frame.mii_data);
816 }
817
818 static int
819 tl_miibus_writereg(dev, phy, reg, data)
820 device_t dev;
821 int phy, reg, data;
822 {
823 struct tl_softc *sc;
824 struct tl_mii_frame frame;
825
826 sc = device_get_softc(dev);
827 bzero((char *)&frame, sizeof(frame));
828
829 frame.mii_phyaddr = phy;
830 frame.mii_regaddr = reg;
831 frame.mii_data = data;
832
833 tl_mii_writereg(sc, &frame);
834
835 return(0);
836 }
837
838 static void
839 tl_miibus_statchg(dev)
840 device_t dev;
841 {
842 struct tl_softc *sc;
843 struct mii_data *mii;
844
845 sc = device_get_softc(dev);
846 TL_LOCK(sc);
847 mii = device_get_softc(sc->tl_miibus);
848
849 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
850 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
851 } else {
852 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
853 }
854 TL_UNLOCK(sc);
855
856 return;
857 }
858
859 /*
860 * Set modes for bitrate devices.
861 */
862 static void
863 tl_setmode(sc, media)
864 struct tl_softc *sc;
865 int media;
866 {
867 if (IFM_SUBTYPE(media) == IFM_10_5)
868 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
869 if (IFM_SUBTYPE(media) == IFM_10_T) {
870 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
871 if ((media & IFM_GMASK) == IFM_FDX) {
872 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
873 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
874 } else {
875 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
876 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
877 }
878 }
879
880 return;
881 }
882
883 /*
884 * Calculate the hash of a MAC address for programming the multicast hash
885 * table. This hash is simply the address split into 6-bit chunks
886 * XOR'd, e.g.
887 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
888 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
889 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
890 * the folded 24-bit value is split into 6-bit portions and XOR'd.
891 */
892 static int
893 tl_calchash(addr)
894 caddr_t addr;
895 {
896 int t;
897
898 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
899 (addr[2] ^ addr[5]);
900 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
901 }
902
903 /*
904 * The ThunderLAN has a perfect MAC address filter in addition to
905 * the multicast hash filter. The perfect filter can be programmed
906 * with up to four MAC addresses. The first one is always used to
907 * hold the station address, which leaves us free to use the other
908 * three for multicast addresses.
909 */
910 static void
911 tl_setfilt(sc, addr, slot)
912 struct tl_softc *sc;
913 caddr_t addr;
914 int slot;
915 {
916 int i;
917 u_int16_t regaddr;
918
919 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
920
921 for (i = 0; i < ETHER_ADDR_LEN; i++)
922 tl_dio_write8(sc, regaddr + i, *(addr + i));
923
924 return;
925 }
926
927 /*
928 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
929 * linked list. This is fine, except addresses are added from the head
930 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
931 * group to always be in the perfect filter, but as more groups are added,
932 * the 224.0.0.1 entry (which is always added first) gets pushed down
933 * the list and ends up at the tail. So after 3 or 4 multicast groups
934 * are added, the all-hosts entry gets pushed out of the perfect filter
935 * and into the hash table.
936 *
937 * Because the multicast list is a doubly-linked list as opposed to a
938 * circular queue, we don't have the ability to just grab the tail of
939 * the list and traverse it backwards. Instead, we have to traverse
940 * the list once to find the tail, then traverse it again backwards to
941 * update the multicast filter.
942 */
943 static void
944 tl_setmulti(sc)
945 struct tl_softc *sc;
946 {
947 struct ifnet *ifp;
948 u_int32_t hashes[2] = { 0, 0 };
949 int h, i;
950 struct ifmultiaddr *ifma;
951 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
952 ifp = &sc->arpcom.ac_if;
953
954 /* First, zot all the existing filters. */
955 for (i = 1; i < 4; i++)
956 tl_setfilt(sc, (caddr_t)&dummy, i);
957 tl_dio_write32(sc, TL_HASH1, 0);
958 tl_dio_write32(sc, TL_HASH2, 0);
959
960 /* Now program new ones. */
961 if (ifp->if_flags & IFF_ALLMULTI) {
962 hashes[0] = 0xFFFFFFFF;
963 hashes[1] = 0xFFFFFFFF;
964 } else {
965 i = 1;
966 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
967 if (ifma->ifma_addr->sa_family != AF_LINK)
968 continue;
969 /*
970 * Program the first three multicast groups
971 * into the perfect filter. For all others,
972 * use the hash table.
973 */
974 if (i < 4) {
975 tl_setfilt(sc,
976 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
977 i++;
978 continue;
979 }
980
981 h = tl_calchash(
982 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
983 if (h < 32)
984 hashes[0] |= (1 << h);
985 else
986 hashes[1] |= (1 << (h - 32));
987 }
988 }
989
990 tl_dio_write32(sc, TL_HASH1, hashes[0]);
991 tl_dio_write32(sc, TL_HASH2, hashes[1]);
992
993 return;
994 }
995
996 /*
997 * This routine is recommended by the ThunderLAN manual to insure that
998 * the internal PHY is powered up correctly. It also recommends a one
999 * second pause at the end to 'wait for the clocks to start' but in my
1000 * experience this isn't necessary.
1001 */
1002 static void
1003 tl_hardreset(dev)
1004 device_t dev;
1005 {
1006 struct tl_softc *sc;
1007 int i;
1008 u_int16_t flags;
1009
1010 sc = device_get_softc(dev);
1011
1012 tl_mii_sync(sc);
1013
1014 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
1015
1016 for (i = 0; i < MII_NPHY; i++)
1017 tl_miibus_writereg(dev, i, MII_BMCR, flags);
1018
1019 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
1020 DELAY(50000);
1021 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
1022 tl_mii_sync(sc);
1023 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
1024
1025 DELAY(50000);
1026 return;
1027 }
1028
1029 static void
1030 tl_softreset(sc, internal)
1031 struct tl_softc *sc;
1032 int internal;
1033 {
1034 u_int32_t cmd, dummy, i;
1035
1036 /* Assert the adapter reset bit. */
1037 CMD_SET(sc, TL_CMD_ADRST);
1038
1039 /* Turn off interrupts */
1040 CMD_SET(sc, TL_CMD_INTSOFF);
1041
1042 /* First, clear the stats registers. */
1043 for (i = 0; i < 5; i++)
1044 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
1045
1046 /* Clear Areg and Hash registers */
1047 for (i = 0; i < 8; i++)
1048 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
1049
1050 /*
1051 * Set up Netconfig register. Enable one channel and
1052 * one fragment mode.
1053 */
1054 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
1055 if (internal && !sc->tl_bitrate) {
1056 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1057 } else {
1058 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1059 }
1060
1061 /* Handle cards with bitrate devices. */
1062 if (sc->tl_bitrate)
1063 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1064
1065 /*
1066 * Load adapter irq pacing timer and tx threshold.
1067 * We make the transmit threshold 1 initially but we may
1068 * change that later.
1069 */
1070 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1071 cmd |= TL_CMD_NES;
1072 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1073 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1074 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1075
1076 /* Unreset the MII */
1077 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1078
1079 /* Take the adapter out of reset */
1080 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1081
1082 /* Wait for things to settle down a little. */
1083 DELAY(500);
1084
1085 return;
1086 }
1087
1088 /*
1089 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1090 * against our list and return its name if we find a match.
1091 */
1092 static int
1093 tl_probe(dev)
1094 device_t dev;
1095 {
1096 struct tl_type *t;
1097
1098 t = tl_devs;
1099
1100 while(t->tl_name != NULL) {
1101 if ((pci_get_vendor(dev) == t->tl_vid) &&
1102 (pci_get_device(dev) == t->tl_did)) {
1103 device_set_desc(dev, t->tl_name);
1104 return(0);
1105 }
1106 t++;
1107 }
1108
1109 return(ENXIO);
1110 }
1111
1112 static int
1113 tl_attach(dev)
1114 device_t dev;
1115 {
1116 int i;
1117 u_int16_t did, vid;
1118 struct tl_type *t;
1119 struct ifnet *ifp;
1120 struct tl_softc *sc;
1121 int unit, error = 0, rid;
1122
1123 vid = pci_get_vendor(dev);
1124 did = pci_get_device(dev);
1125 sc = device_get_softc(dev);
1126 unit = device_get_unit(dev);
1127
1128 t = tl_devs;
1129 while(t->tl_name != NULL) {
1130 if (vid == t->tl_vid && did == t->tl_did)
1131 break;
1132 t++;
1133 }
1134
1135 if (t->tl_name == NULL) {
1136 device_printf(dev, "unknown device!?\n");
1137 return (ENXIO);
1138 }
1139
1140 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1141 MTX_DEF | MTX_RECURSE);
1142
1143 /*
1144 * Map control/status registers.
1145 */
1146 pci_enable_busmaster(dev);
1147
1148 #ifdef TL_USEIOSPACE
1149
1150 rid = TL_PCI_LOIO;
1151 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1152 0, ~0, 1, RF_ACTIVE);
1153
1154 /*
1155 * Some cards have the I/O and memory mapped address registers
1156 * reversed. Try both combinations before giving up.
1157 */
1158 if (sc->tl_res == NULL) {
1159 rid = TL_PCI_LOMEM;
1160 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1161 0, ~0, 1, RF_ACTIVE);
1162 }
1163 #else
1164 rid = TL_PCI_LOMEM;
1165 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1166 0, ~0, 1, RF_ACTIVE);
1167 if (sc->tl_res == NULL) {
1168 rid = TL_PCI_LOIO;
1169 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1170 0, ~0, 1, RF_ACTIVE);
1171 }
1172 #endif
1173
1174 if (sc->tl_res == NULL) {
1175 device_printf(dev, "couldn't map ports/memory\n");
1176 error = ENXIO;
1177 goto fail;
1178 }
1179
1180 sc->tl_btag = rman_get_bustag(sc->tl_res);
1181 sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
1182
1183 #ifdef notdef
1184 /*
1185 * The ThunderLAN manual suggests jacking the PCI latency
1186 * timer all the way up to its maximum value. I'm not sure
1187 * if this is really necessary, but what the manual wants,
1188 * the manual gets.
1189 */
1190 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1191 command |= 0x0000FF00;
1192 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1193 #endif
1194
1195 /* Allocate interrupt */
1196 rid = 0;
1197 sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1198 RF_SHAREABLE | RF_ACTIVE);
1199
1200 if (sc->tl_irq == NULL) {
1201 device_printf(dev, "couldn't map interrupt\n");
1202 error = ENXIO;
1203 goto fail;
1204 }
1205
1206 /*
1207 * Now allocate memory for the TX and RX lists.
1208 */
1209 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1210 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1211
1212 if (sc->tl_ldata == NULL) {
1213 device_printf(dev, "no memory for list buffers!\n");
1214 error = ENXIO;
1215 goto fail;
1216 }
1217
1218 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1219
1220 sc->tl_dinfo = t;
1221 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1222 sc->tl_eeaddr = TL_EEPROM_EADDR;
1223 if (t->tl_vid == OLICOM_VENDORID)
1224 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1225
1226 /* Reset the adapter. */
1227 tl_softreset(sc, 1);
1228 tl_hardreset(dev);
1229 tl_softreset(sc, 1);
1230
1231 /*
1232 * Get station address from the EEPROM.
1233 */
1234 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1235 sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1236 device_printf(dev, "failed to read station address\n");
1237 error = ENXIO;
1238 goto fail;
1239 }
1240
1241 /*
1242 * XXX Olicom, in its desire to be different from the
1243 * rest of the world, has done strange things with the
1244 * encoding of the station address in the EEPROM. First
1245 * of all, they store the address at offset 0xF8 rather
1246 * than at 0x83 like the ThunderLAN manual suggests.
1247 * Second, they store the address in three 16-bit words in
1248 * network byte order, as opposed to storing it sequentially
1249 * like all the other ThunderLAN cards. In order to get
1250 * the station address in a form that matches what the Olicom
1251 * diagnostic utility specifies, we have to byte-swap each
1252 * word. To make things even more confusing, neither 00:00:28
1253 * nor 00:00:24 appear in the IEEE OUI database.
1254 */
1255 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1256 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1257 u_int16_t *p;
1258 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i];
1259 *p = ntohs(*p);
1260 }
1261 }
1262
1263 /*
1264 * A ThunderLAN chip was detected. Inform the world.
1265 */
1266 device_printf(dev, "Ethernet address: %6D\n",
1267 sc->arpcom.ac_enaddr, ":");
1268
1269 ifp = &sc->arpcom.ac_if;
1270 ifp->if_softc = sc;
1271 ifp->if_unit = unit;
1272 ifp->if_name = "tl";
1273 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1274 ifp->if_ioctl = tl_ioctl;
1275 ifp->if_output = ether_output;
1276 ifp->if_start = tl_start;
1277 ifp->if_watchdog = tl_watchdog;
1278 ifp->if_init = tl_init;
1279 ifp->if_mtu = ETHERMTU;
1280 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1;
1281 callout_handle_init(&sc->tl_stat_ch);
1282
1283 /* Reset the adapter again. */
1284 tl_softreset(sc, 1);
1285 tl_hardreset(dev);
1286 tl_softreset(sc, 1);
1287
1288 /*
1289 * Do MII setup. If no PHYs are found, then this is a
1290 * bitrate ThunderLAN chip that only supports 10baseT
1291 * and AUI/BNC.
1292 */
1293 if (mii_phy_probe(dev, &sc->tl_miibus,
1294 tl_ifmedia_upd, tl_ifmedia_sts)) {
1295 struct ifmedia *ifm;
1296 sc->tl_bitrate = 1;
1297 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1298 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1299 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1300 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1301 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1302 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1303 /* Reset again, this time setting bitrate mode. */
1304 tl_softreset(sc, 1);
1305 ifm = &sc->ifmedia;
1306 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1307 tl_ifmedia_upd(ifp);
1308 }
1309
1310 /*
1311 * Call MI attach routine.
1312 */
1313 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1314
1315 /* Hook interrupt last to avoid having to lock softc */
1316 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET,
1317 tl_intr, sc, &sc->tl_intrhand);
1318
1319 if (error) {
1320 device_printf(dev, "couldn't set up irq\n");
1321 ether_ifdetach(ifp);
1322 goto fail;
1323 }
1324
1325 fail:
1326 if (error)
1327 tl_detach(dev);
1328
1329 return(error);
1330 }
1331
1332 /*
1333 * Shutdown hardware and free up resources. This can be called any
1334 * time after the mutex has been initialized. It is called in both
1335 * the error case in attach and the normal detach case so it needs
1336 * to be careful about only freeing resources that have actually been
1337 * allocated.
1338 */
1339 static int
1340 tl_detach(dev)
1341 device_t dev;
1342 {
1343 struct tl_softc *sc;
1344 struct ifnet *ifp;
1345
1346 sc = device_get_softc(dev);
1347 KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized"));
1348 TL_LOCK(sc);
1349 ifp = &sc->arpcom.ac_if;
1350
1351 /* These should only be active if attach succeeded */
1352 if (device_is_attached(dev)) {
1353 tl_stop(sc);
1354 ether_ifdetach(ifp);
1355 }
1356 if (sc->tl_miibus)
1357 device_delete_child(dev, sc->tl_miibus);
1358 bus_generic_detach(dev);
1359
1360 if (sc->tl_ldata)
1361 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1362 if (sc->tl_bitrate)
1363 ifmedia_removeall(&sc->ifmedia);
1364
1365 if (sc->tl_intrhand)
1366 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1367 if (sc->tl_irq)
1368 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1369 if (sc->tl_res)
1370 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1371
1372 TL_UNLOCK(sc);
1373 mtx_destroy(&sc->tl_mtx);
1374
1375 return(0);
1376 }
1377
1378 /*
1379 * Initialize the transmit lists.
1380 */
1381 static int
1382 tl_list_tx_init(sc)
1383 struct tl_softc *sc;
1384 {
1385 struct tl_chain_data *cd;
1386 struct tl_list_data *ld;
1387 int i;
1388
1389 cd = &sc->tl_cdata;
1390 ld = sc->tl_ldata;
1391 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1392 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1393 if (i == (TL_TX_LIST_CNT - 1))
1394 cd->tl_tx_chain[i].tl_next = NULL;
1395 else
1396 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1397 }
1398
1399 cd->tl_tx_free = &cd->tl_tx_chain[0];
1400 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1401 sc->tl_txeoc = 1;
1402
1403 return(0);
1404 }
1405
1406 /*
1407 * Initialize the RX lists and allocate mbufs for them.
1408 */
1409 static int
1410 tl_list_rx_init(sc)
1411 struct tl_softc *sc;
1412 {
1413 struct tl_chain_data *cd;
1414 struct tl_list_data *ld;
1415 int i;
1416
1417 cd = &sc->tl_cdata;
1418 ld = sc->tl_ldata;
1419
1420 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1421 cd->tl_rx_chain[i].tl_ptr =
1422 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1423 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1424 return(ENOBUFS);
1425 if (i == (TL_RX_LIST_CNT - 1)) {
1426 cd->tl_rx_chain[i].tl_next = NULL;
1427 ld->tl_rx_list[i].tlist_fptr = 0;
1428 } else {
1429 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1430 ld->tl_rx_list[i].tlist_fptr =
1431 vtophys(&ld->tl_rx_list[i + 1]);
1432 }
1433 }
1434
1435 cd->tl_rx_head = &cd->tl_rx_chain[0];
1436 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1437
1438 return(0);
1439 }
1440
1441 static int
1442 tl_newbuf(sc, c)
1443 struct tl_softc *sc;
1444 struct tl_chain_onefrag *c;
1445 {
1446 struct mbuf *m_new = NULL;
1447
1448 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1449 if (m_new == NULL)
1450 return(ENOBUFS);
1451
1452 MCLGET(m_new, M_DONTWAIT);
1453 if (!(m_new->m_flags & M_EXT)) {
1454 m_freem(m_new);
1455 return(ENOBUFS);
1456 }
1457
1458 #ifdef __alpha__
1459 m_new->m_data += 2;
1460 #endif
1461
1462 c->tl_mbuf = m_new;
1463 c->tl_next = NULL;
1464 c->tl_ptr->tlist_frsize = MCLBYTES;
1465 c->tl_ptr->tlist_fptr = 0;
1466 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1467 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1468 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1469
1470 return(0);
1471 }
1472 /*
1473 * Interrupt handler for RX 'end of frame' condition (EOF). This
1474 * tells us that a full ethernet frame has been captured and we need
1475 * to handle it.
1476 *
1477 * Reception is done using 'lists' which consist of a header and a
1478 * series of 10 data count/data address pairs that point to buffers.
1479 * Initially you're supposed to create a list, populate it with pointers
1480 * to buffers, then load the physical address of the list into the
1481 * ch_parm register. The adapter is then supposed to DMA the received
1482 * frame into the buffers for you.
1483 *
1484 * To make things as fast as possible, we have the chip DMA directly
1485 * into mbufs. This saves us from having to do a buffer copy: we can
1486 * just hand the mbufs directly to ether_input(). Once the frame has
1487 * been sent on its way, the 'list' structure is assigned a new buffer
1488 * and moved to the end of the RX chain. As long we we stay ahead of
1489 * the chip, it will always think it has an endless receive channel.
1490 *
1491 * If we happen to fall behind and the chip manages to fill up all of
1492 * the buffers, it will generate an end of channel interrupt and wait
1493 * for us to empty the chain and restart the receiver.
1494 */
1495 static int
1496 tl_intvec_rxeof(xsc, type)
1497 void *xsc;
1498 u_int32_t type;
1499 {
1500 struct tl_softc *sc;
1501 int r = 0, total_len = 0;
1502 struct ether_header *eh;
1503 struct mbuf *m;
1504 struct ifnet *ifp;
1505 struct tl_chain_onefrag *cur_rx;
1506
1507 sc = xsc;
1508 ifp = &sc->arpcom.ac_if;
1509
1510 while(sc->tl_cdata.tl_rx_head != NULL) {
1511 cur_rx = sc->tl_cdata.tl_rx_head;
1512 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1513 break;
1514 r++;
1515 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1516 m = cur_rx->tl_mbuf;
1517 total_len = cur_rx->tl_ptr->tlist_frsize;
1518
1519 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1520 ifp->if_ierrors++;
1521 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1522 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1523 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1524 continue;
1525 }
1526
1527 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1528 vtophys(cur_rx->tl_ptr);
1529 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1530 sc->tl_cdata.tl_rx_tail = cur_rx;
1531
1532 /*
1533 * Note: when the ThunderLAN chip is in 'capture all
1534 * frames' mode, it will receive its own transmissions.
1535 * We drop don't need to process our own transmissions,
1536 * so we drop them here and continue.
1537 */
1538 eh = mtod(m, struct ether_header *);
1539 /*if (ifp->if_flags & IFF_PROMISC && */
1540 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1541 ETHER_ADDR_LEN)) {
1542 m_freem(m);
1543 continue;
1544 }
1545
1546 m->m_pkthdr.rcvif = ifp;
1547 m->m_pkthdr.len = m->m_len = total_len;
1548
1549 (*ifp->if_input)(ifp, m);
1550 }
1551
1552 return(r);
1553 }
1554
1555 /*
1556 * The RX-EOC condition hits when the ch_parm address hasn't been
1557 * initialized or the adapter reached a list with a forward pointer
1558 * of 0 (which indicates the end of the chain). In our case, this means
1559 * the card has hit the end of the receive buffer chain and we need to
1560 * empty out the buffers and shift the pointer back to the beginning again.
1561 */
1562 static int
1563 tl_intvec_rxeoc(xsc, type)
1564 void *xsc;
1565 u_int32_t type;
1566 {
1567 struct tl_softc *sc;
1568 int r;
1569 struct tl_chain_data *cd;
1570
1571
1572 sc = xsc;
1573 cd = &sc->tl_cdata;
1574
1575 /* Flush out the receive queue and ack RXEOF interrupts. */
1576 r = tl_intvec_rxeof(xsc, type);
1577 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1578 r = 1;
1579 cd->tl_rx_head = &cd->tl_rx_chain[0];
1580 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1581 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1582 r |= (TL_CMD_GO|TL_CMD_RT);
1583 return(r);
1584 }
1585
1586 static int
1587 tl_intvec_txeof(xsc, type)
1588 void *xsc;
1589 u_int32_t type;
1590 {
1591 struct tl_softc *sc;
1592 int r = 0;
1593 struct tl_chain *cur_tx;
1594
1595 sc = xsc;
1596
1597 /*
1598 * Go through our tx list and free mbufs for those
1599 * frames that have been sent.
1600 */
1601 while (sc->tl_cdata.tl_tx_head != NULL) {
1602 cur_tx = sc->tl_cdata.tl_tx_head;
1603 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1604 break;
1605 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1606
1607 r++;
1608 m_freem(cur_tx->tl_mbuf);
1609 cur_tx->tl_mbuf = NULL;
1610
1611 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1612 sc->tl_cdata.tl_tx_free = cur_tx;
1613 if (!cur_tx->tl_ptr->tlist_fptr)
1614 break;
1615 }
1616
1617 return(r);
1618 }
1619
1620 /*
1621 * The transmit end of channel interrupt. The adapter triggers this
1622 * interrupt to tell us it hit the end of the current transmit list.
1623 *
1624 * A note about this: it's possible for a condition to arise where
1625 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1626 * You have to avoid this since the chip expects things to go in a
1627 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1628 * When the TXEOF handler is called, it will free all of the transmitted
1629 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1630 * interrupt should be received and acknowledged before any more frames
1631 * are queued for transmission. If tl_statrt() is called after TXEOF
1632 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1633 * it could attempt to issue a transmit command prematurely.
1634 *
1635 * To guard against this, tl_start() will only issue transmit commands
1636 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1637 * can set this flag once tl_start() has cleared it.
1638 */
1639 static int
1640 tl_intvec_txeoc(xsc, type)
1641 void *xsc;
1642 u_int32_t type;
1643 {
1644 struct tl_softc *sc;
1645 struct ifnet *ifp;
1646 u_int32_t cmd;
1647
1648 sc = xsc;
1649 ifp = &sc->arpcom.ac_if;
1650
1651 /* Clear the timeout timer. */
1652 ifp->if_timer = 0;
1653
1654 if (sc->tl_cdata.tl_tx_head == NULL) {
1655 ifp->if_flags &= ~IFF_OACTIVE;
1656 sc->tl_cdata.tl_tx_tail = NULL;
1657 sc->tl_txeoc = 1;
1658 } else {
1659 sc->tl_txeoc = 0;
1660 /* First we have to ack the EOC interrupt. */
1661 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1662 /* Then load the address of the next TX list. */
1663 CSR_WRITE_4(sc, TL_CH_PARM,
1664 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1665 /* Restart TX channel. */
1666 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1667 cmd &= ~TL_CMD_RT;
1668 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1669 CMD_PUT(sc, cmd);
1670 return(0);
1671 }
1672
1673 return(1);
1674 }
1675
1676 static int
1677 tl_intvec_adchk(xsc, type)
1678 void *xsc;
1679 u_int32_t type;
1680 {
1681 struct tl_softc *sc;
1682
1683 sc = xsc;
1684
1685 if (type)
1686 if_printf(&sc->arpcom.ac_if, "adapter check: %x\n",
1687 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1688
1689 tl_softreset(sc, 1);
1690 tl_stop(sc);
1691 tl_init(sc);
1692 CMD_SET(sc, TL_CMD_INTSON);
1693
1694 return(0);
1695 }
1696
1697 static int
1698 tl_intvec_netsts(xsc, type)
1699 void *xsc;
1700 u_int32_t type;
1701 {
1702 struct tl_softc *sc;
1703 u_int16_t netsts;
1704
1705 sc = xsc;
1706
1707 netsts = tl_dio_read16(sc, TL_NETSTS);
1708 tl_dio_write16(sc, TL_NETSTS, netsts);
1709
1710 if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts);
1711
1712 return(1);
1713 }
1714
1715 static void
1716 tl_intr(xsc)
1717 void *xsc;
1718 {
1719 struct tl_softc *sc;
1720 struct ifnet *ifp;
1721 int r = 0;
1722 u_int32_t type = 0;
1723 u_int16_t ints = 0;
1724 u_int8_t ivec = 0;
1725
1726 sc = xsc;
1727 TL_LOCK(sc);
1728
1729 /* Disable interrupts */
1730 ints = CSR_READ_2(sc, TL_HOST_INT);
1731 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1732 type = (ints << 16) & 0xFFFF0000;
1733 ivec = (ints & TL_VEC_MASK) >> 5;
1734 ints = (ints & TL_INT_MASK) >> 2;
1735
1736 ifp = &sc->arpcom.ac_if;
1737
1738 switch(ints) {
1739 case (TL_INTR_INVALID):
1740 #ifdef DIAGNOSTIC
1741 if_printf(ifp, "got an invalid interrupt!\n");
1742 #endif
1743 /* Re-enable interrupts but don't ack this one. */
1744 CMD_PUT(sc, type);
1745 r = 0;
1746 break;
1747 case (TL_INTR_TXEOF):
1748 r = tl_intvec_txeof((void *)sc, type);
1749 break;
1750 case (TL_INTR_TXEOC):
1751 r = tl_intvec_txeoc((void *)sc, type);
1752 break;
1753 case (TL_INTR_STATOFLOW):
1754 tl_stats_update(sc);
1755 r = 1;
1756 break;
1757 case (TL_INTR_RXEOF):
1758 r = tl_intvec_rxeof((void *)sc, type);
1759 break;
1760 case (TL_INTR_DUMMY):
1761 if_printf(ifp, "got a dummy interrupt\n");
1762 r = 1;
1763 break;
1764 case (TL_INTR_ADCHK):
1765 if (ivec)
1766 r = tl_intvec_adchk((void *)sc, type);
1767 else
1768 r = tl_intvec_netsts((void *)sc, type);
1769 break;
1770 case (TL_INTR_RXEOC):
1771 r = tl_intvec_rxeoc((void *)sc, type);
1772 break;
1773 default:
1774 if_printf(ifp, "bogus interrupt type\n");
1775 break;
1776 }
1777
1778 /* Re-enable interrupts */
1779 if (r) {
1780 CMD_PUT(sc, TL_CMD_ACK | r | type);
1781 }
1782
1783 if (ifp->if_snd.ifq_head != NULL)
1784 tl_start(ifp);
1785
1786 TL_UNLOCK(sc);
1787
1788 return;
1789 }
1790
1791 static void
1792 tl_stats_update(xsc)
1793 void *xsc;
1794 {
1795 struct tl_softc *sc;
1796 struct ifnet *ifp;
1797 struct tl_stats tl_stats;
1798 struct mii_data *mii;
1799 u_int32_t *p;
1800
1801 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1802
1803 sc = xsc;
1804 TL_LOCK(sc);
1805 ifp = &sc->arpcom.ac_if;
1806
1807 p = (u_int32_t *)&tl_stats;
1808
1809 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1810 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1811 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1812 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1813 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1814 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1815
1816 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1817 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1818 tl_stats.tl_tx_multi_collision;
1819 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1820 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1821 tl_rx_overrun(tl_stats);
1822 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1823
1824 if (tl_tx_underrun(tl_stats)) {
1825 u_int8_t tx_thresh;
1826 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1827 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1828 tx_thresh >>= 4;
1829 tx_thresh++;
1830 if_printf(ifp, "tx underrun -- increasing "
1831 "tx threshold to %d bytes\n",
1832 (64 * (tx_thresh * 4)));
1833 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1834 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1835 }
1836 }
1837
1838 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
1839
1840 if (!sc->tl_bitrate) {
1841 mii = device_get_softc(sc->tl_miibus);
1842 mii_tick(mii);
1843 }
1844
1845 TL_UNLOCK(sc);
1846
1847 return;
1848 }
1849
1850 /*
1851 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1852 * pointers to the fragment pointers.
1853 */
1854 static int
1855 tl_encap(sc, c, m_head)
1856 struct tl_softc *sc;
1857 struct tl_chain *c;
1858 struct mbuf *m_head;
1859 {
1860 int frag = 0;
1861 struct tl_frag *f = NULL;
1862 int total_len;
1863 struct mbuf *m;
1864 struct ifnet *ifp = &sc->arpcom.ac_if;
1865
1866 /*
1867 * Start packing the mbufs in this chain into
1868 * the fragment pointers. Stop when we run out
1869 * of fragments or hit the end of the mbuf chain.
1870 */
1871 m = m_head;
1872 total_len = 0;
1873
1874 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1875 if (m->m_len != 0) {
1876 if (frag == TL_MAXFRAGS)
1877 break;
1878 total_len+= m->m_len;
1879 c->tl_ptr->tl_frag[frag].tlist_dadr =
1880 vtophys(mtod(m, vm_offset_t));
1881 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1882 frag++;
1883 }
1884 }
1885
1886 /*
1887 * Handle special cases.
1888 * Special case #1: we used up all 10 fragments, but
1889 * we have more mbufs left in the chain. Copy the
1890 * data into an mbuf cluster. Note that we don't
1891 * bother clearing the values in the other fragment
1892 * pointers/counters; it wouldn't gain us anything,
1893 * and would waste cycles.
1894 */
1895 if (m != NULL) {
1896 struct mbuf *m_new = NULL;
1897
1898 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1899 if (m_new == NULL) {
1900 if_printf(ifp, "no memory for tx list\n");
1901 return(1);
1902 }
1903 if (m_head->m_pkthdr.len > MHLEN) {
1904 MCLGET(m_new, M_DONTWAIT);
1905 if (!(m_new->m_flags & M_EXT)) {
1906 m_freem(m_new);
1907 if_printf(ifp, "no memory for tx list\n");
1908 return(1);
1909 }
1910 }
1911 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1912 mtod(m_new, caddr_t));
1913 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1914 m_freem(m_head);
1915 m_head = m_new;
1916 f = &c->tl_ptr->tl_frag[0];
1917 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1918 f->tlist_dcnt = total_len = m_new->m_len;
1919 frag = 1;
1920 }
1921
1922 /*
1923 * Special case #2: the frame is smaller than the minimum
1924 * frame size. We have to pad it to make the chip happy.
1925 */
1926 if (total_len < TL_MIN_FRAMELEN) {
1927 if (frag == TL_MAXFRAGS)
1928 if_printf(ifp,
1929 "all frags filled but frame still to small!\n");
1930 f = &c->tl_ptr->tl_frag[frag];
1931 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1932 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1933 total_len += f->tlist_dcnt;
1934 frag++;
1935 }
1936
1937 c->tl_mbuf = m_head;
1938 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1939 c->tl_ptr->tlist_frsize = total_len;
1940 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1941 c->tl_ptr->tlist_fptr = 0;
1942
1943 return(0);
1944 }
1945
1946 /*
1947 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1948 * to the mbuf data regions directly in the transmit lists. We also save a
1949 * copy of the pointers since the transmit list fragment pointers are
1950 * physical addresses.
1951 */
1952 static void
1953 tl_start(ifp)
1954 struct ifnet *ifp;
1955 {
1956 struct tl_softc *sc;
1957 struct mbuf *m_head = NULL;
1958 u_int32_t cmd;
1959 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1960
1961 sc = ifp->if_softc;
1962 TL_LOCK(sc);
1963
1964 /*
1965 * Check for an available queue slot. If there are none,
1966 * punt.
1967 */
1968 if (sc->tl_cdata.tl_tx_free == NULL) {
1969 ifp->if_flags |= IFF_OACTIVE;
1970 TL_UNLOCK(sc);
1971 return;
1972 }
1973
1974 start_tx = sc->tl_cdata.tl_tx_free;
1975
1976 while(sc->tl_cdata.tl_tx_free != NULL) {
1977 IF_DEQUEUE(&ifp->if_snd, m_head);
1978 if (m_head == NULL)
1979 break;
1980
1981 /* Pick a chain member off the free list. */
1982 cur_tx = sc->tl_cdata.tl_tx_free;
1983 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1984
1985 cur_tx->tl_next = NULL;
1986
1987 /* Pack the data into the list. */
1988 tl_encap(sc, cur_tx, m_head);
1989
1990 /* Chain it together */
1991 if (prev != NULL) {
1992 prev->tl_next = cur_tx;
1993 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1994 }
1995 prev = cur_tx;
1996
1997 /*
1998 * If there's a BPF listener, bounce a copy of this frame
1999 * to him.
2000 */
2001 BPF_MTAP(ifp, cur_tx->tl_mbuf);
2002 }
2003
2004 /*
2005 * If there are no packets queued, bail.
2006 */
2007 if (cur_tx == NULL) {
2008 TL_UNLOCK(sc);
2009 return;
2010 }
2011
2012 /*
2013 * That's all we can stands, we can't stands no more.
2014 * If there are no other transfers pending, then issue the
2015 * TX GO command to the adapter to start things moving.
2016 * Otherwise, just leave the data in the queue and let
2017 * the EOF/EOC interrupt handler send.
2018 */
2019 if (sc->tl_cdata.tl_tx_head == NULL) {
2020 sc->tl_cdata.tl_tx_head = start_tx;
2021 sc->tl_cdata.tl_tx_tail = cur_tx;
2022
2023 if (sc->tl_txeoc) {
2024 sc->tl_txeoc = 0;
2025 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
2026 cmd = CSR_READ_4(sc, TL_HOSTCMD);
2027 cmd &= ~TL_CMD_RT;
2028 cmd |= TL_CMD_GO|TL_CMD_INTSON;
2029 CMD_PUT(sc, cmd);
2030 }
2031 } else {
2032 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
2033 sc->tl_cdata.tl_tx_tail = cur_tx;
2034 }
2035
2036 /*
2037 * Set a timeout in case the chip goes out to lunch.
2038 */
2039 ifp->if_timer = 5;
2040 TL_UNLOCK(sc);
2041
2042 return;
2043 }
2044
2045 static void
2046 tl_init(xsc)
2047 void *xsc;
2048 {
2049 struct tl_softc *sc = xsc;
2050 struct ifnet *ifp = &sc->arpcom.ac_if;
2051 struct mii_data *mii;
2052
2053 TL_LOCK(sc);
2054
2055 ifp = &sc->arpcom.ac_if;
2056
2057 /*
2058 * Cancel pending I/O.
2059 */
2060 tl_stop(sc);
2061
2062 /* Initialize TX FIFO threshold */
2063 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
2064 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
2065
2066 /* Set PCI burst size */
2067 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
2068
2069 /*
2070 * Set 'capture all frames' bit for promiscuous mode.
2071 */
2072 if (ifp->if_flags & IFF_PROMISC)
2073 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2074 else
2075 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2076
2077 /*
2078 * Set capture broadcast bit to capture broadcast frames.
2079 */
2080 if (ifp->if_flags & IFF_BROADCAST)
2081 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2082 else
2083 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2084
2085 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
2086
2087 /* Init our MAC address */
2088 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
2089
2090 /* Init multicast filter, if needed. */
2091 tl_setmulti(sc);
2092
2093 /* Init circular RX list. */
2094 if (tl_list_rx_init(sc) == ENOBUFS) {
2095 if_printf(ifp,
2096 "initialization failed: no memory for rx buffers\n");
2097 tl_stop(sc);
2098 TL_UNLOCK(sc);
2099 return;
2100 }
2101
2102 /* Init TX pointers. */
2103 tl_list_tx_init(sc);
2104
2105 /* Enable PCI interrupts. */
2106 CMD_SET(sc, TL_CMD_INTSON);
2107
2108 /* Load the address of the rx list */
2109 CMD_SET(sc, TL_CMD_RT);
2110 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2111
2112 if (!sc->tl_bitrate) {
2113 if (sc->tl_miibus != NULL) {
2114 mii = device_get_softc(sc->tl_miibus);
2115 mii_mediachg(mii);
2116 }
2117 } else {
2118 tl_ifmedia_upd(ifp);
2119 }
2120
2121 /* Send the RX go command */
2122 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2123
2124 ifp->if_flags |= IFF_RUNNING;
2125 ifp->if_flags &= ~IFF_OACTIVE;
2126
2127 /* Start the stats update counter */
2128 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
2129 TL_UNLOCK(sc);
2130
2131 return;
2132 }
2133
2134 /*
2135 * Set media options.
2136 */
2137 static int
2138 tl_ifmedia_upd(ifp)
2139 struct ifnet *ifp;
2140 {
2141 struct tl_softc *sc;
2142 struct mii_data *mii = NULL;
2143
2144 sc = ifp->if_softc;
2145
2146 if (sc->tl_bitrate)
2147 tl_setmode(sc, sc->ifmedia.ifm_media);
2148 else {
2149 mii = device_get_softc(sc->tl_miibus);
2150 mii_mediachg(mii);
2151 }
2152
2153 return(0);
2154 }
2155
2156 /*
2157 * Report current media status.
2158 */
2159 static void
2160 tl_ifmedia_sts(ifp, ifmr)
2161 struct ifnet *ifp;
2162 struct ifmediareq *ifmr;
2163 {
2164 struct tl_softc *sc;
2165 struct mii_data *mii;
2166
2167 sc = ifp->if_softc;
2168
2169 ifmr->ifm_active = IFM_ETHER;
2170
2171 if (sc->tl_bitrate) {
2172 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2173 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2174 else
2175 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2176 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2177 ifmr->ifm_active |= IFM_HDX;
2178 else
2179 ifmr->ifm_active |= IFM_FDX;
2180 return;
2181 } else {
2182 mii = device_get_softc(sc->tl_miibus);
2183 mii_pollstat(mii);
2184 ifmr->ifm_active = mii->mii_media_active;
2185 ifmr->ifm_status = mii->mii_media_status;
2186 }
2187
2188 return;
2189 }
2190
2191 static int
2192 tl_ioctl(ifp, command, data)
2193 struct ifnet *ifp;
2194 u_long command;
2195 caddr_t data;
2196 {
2197 struct tl_softc *sc = ifp->if_softc;
2198 struct ifreq *ifr = (struct ifreq *) data;
2199 int s, error = 0;
2200
2201 s = splimp();
2202
2203 switch(command) {
2204 case SIOCSIFFLAGS:
2205 if (ifp->if_flags & IFF_UP) {
2206 if (ifp->if_flags & IFF_RUNNING &&
2207 ifp->if_flags & IFF_PROMISC &&
2208 !(sc->tl_if_flags & IFF_PROMISC)) {
2209 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2210 tl_setmulti(sc);
2211 } else if (ifp->if_flags & IFF_RUNNING &&
2212 !(ifp->if_flags & IFF_PROMISC) &&
2213 sc->tl_if_flags & IFF_PROMISC) {
2214 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2215 tl_setmulti(sc);
2216 } else
2217 tl_init(sc);
2218 } else {
2219 if (ifp->if_flags & IFF_RUNNING) {
2220 tl_stop(sc);
2221 }
2222 }
2223 sc->tl_if_flags = ifp->if_flags;
2224 error = 0;
2225 break;
2226 case SIOCADDMULTI:
2227 case SIOCDELMULTI:
2228 tl_setmulti(sc);
2229 error = 0;
2230 break;
2231 case SIOCSIFMEDIA:
2232 case SIOCGIFMEDIA:
2233 if (sc->tl_bitrate)
2234 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2235 else {
2236 struct mii_data *mii;
2237 mii = device_get_softc(sc->tl_miibus);
2238 error = ifmedia_ioctl(ifp, ifr,
2239 &mii->mii_media, command);
2240 }
2241 break;
2242 default:
2243 error = ether_ioctl(ifp, command, data);
2244 break;
2245 }
2246
2247 (void)splx(s);
2248
2249 return(error);
2250 }
2251
2252 static void
2253 tl_watchdog(ifp)
2254 struct ifnet *ifp;
2255 {
2256 struct tl_softc *sc;
2257
2258 sc = ifp->if_softc;
2259
2260 if_printf(ifp, "device timeout\n");
2261
2262 ifp->if_oerrors++;
2263
2264 tl_softreset(sc, 1);
2265 tl_init(sc);
2266
2267 return;
2268 }
2269
2270 /*
2271 * Stop the adapter and free any mbufs allocated to the
2272 * RX and TX lists.
2273 */
2274 static void
2275 tl_stop(sc)
2276 struct tl_softc *sc;
2277 {
2278 register int i;
2279 struct ifnet *ifp;
2280
2281 TL_LOCK(sc);
2282
2283 ifp = &sc->arpcom.ac_if;
2284
2285 /* Stop the stats updater. */
2286 untimeout(tl_stats_update, sc, sc->tl_stat_ch);
2287
2288 /* Stop the transmitter */
2289 CMD_CLR(sc, TL_CMD_RT);
2290 CMD_SET(sc, TL_CMD_STOP);
2291 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2292
2293 /* Stop the receiver */
2294 CMD_SET(sc, TL_CMD_RT);
2295 CMD_SET(sc, TL_CMD_STOP);
2296 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2297
2298 /*
2299 * Disable host interrupts.
2300 */
2301 CMD_SET(sc, TL_CMD_INTSOFF);
2302
2303 /*
2304 * Clear list pointer.
2305 */
2306 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2307
2308 /*
2309 * Free the RX lists.
2310 */
2311 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2312 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2313 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2314 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2315 }
2316 }
2317 bzero((char *)&sc->tl_ldata->tl_rx_list,
2318 sizeof(sc->tl_ldata->tl_rx_list));
2319
2320 /*
2321 * Free the TX list buffers.
2322 */
2323 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2324 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2325 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2326 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2327 }
2328 }
2329 bzero((char *)&sc->tl_ldata->tl_tx_list,
2330 sizeof(sc->tl_ldata->tl_tx_list));
2331
2332 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2333 TL_UNLOCK(sc);
2334
2335 return;
2336 }
2337
2338 /*
2339 * Stop all chip I/O so that the kernel's probe routines don't
2340 * get confused by errant DMAs when rebooting.
2341 */
2342 static void
2343 tl_shutdown(dev)
2344 device_t dev;
2345 {
2346 struct tl_softc *sc;
2347
2348 sc = device_get_softc(dev);
2349
2350 tl_stop(sc);
2351
2352 return;
2353 }
Cache object: 90f0c00ada0dff0c5fb0d6d31fcccab4
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