Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_tl.c
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1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/5.3/sys/pci/if_tl.c 134658 2004-09-02 20:57:40Z rwatson $"); 35 36 /* 37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 39 * the National Semiconductor DP83840A physical interface and the 40 * Microchip Technology 24Cxx series serial EEPROM. 41 * 42 * Written using the following four documents: 43 * 44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 45 * National Semiconductor DP83840A data sheet (www.national.com) 46 * Microchip Technology 24C02C data sheet (www.microchip.com) 47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 48 * 49 * Written by Bill Paul <wpaul@ctr.columbia.edu> 50 * Electrical Engineering Department 51 * Columbia University, New York City 52 */ 53 /* 54 * Some notes about the ThunderLAN: 55 * 56 * The ThunderLAN controller is a single chip containing PCI controller 57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 61 * to act as a complete ethernet interface. 62 * 63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 65 * in full or half duplex. Some of the Compaq Deskpro machines use a 66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 68 * concert with the ThunderLAN's internal PHY to provide full 10/100 69 * support. This is cheaper than using a standalone external PHY for both 70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 71 * A serial EEPROM is also attached to the ThunderLAN chip to provide 72 * power-up default register settings and for storing the adapter's 73 * station address. Although not supported by this driver, the ThunderLAN 74 * chip can also be connected to token ring PHYs. 75 * 76 * The ThunderLAN has a set of registers which can be used to issue 77 * commands, acknowledge interrupts, and to manipulate other internal 78 * registers on its DIO bus. The primary registers can be accessed 79 * using either programmed I/O (inb/outb) or via PCI memory mapping, 80 * depending on how the card is configured during the PCI probing 81 * phase. It is even possible to have both PIO and memory mapped 82 * access turned on at the same time. 83 * 84 * Frame reception and transmission with the ThunderLAN chip is done 85 * using frame 'lists.' A list structure looks more or less like this: 86 * 87 * struct tl_frag { 88 * u_int32_t fragment_address; 89 * u_int32_t fragment_size; 90 * }; 91 * struct tl_list { 92 * u_int32_t forward_pointer; 93 * u_int16_t cstat; 94 * u_int16_t frame_size; 95 * struct tl_frag fragments[10]; 96 * }; 97 * 98 * The forward pointer in the list header can be either a 0 or the address 99 * of another list, which allows several lists to be linked together. Each 100 * list contains up to 10 fragment descriptors. This means the chip allows 101 * ethernet frames to be broken up into up to 10 chunks for transfer to 102 * and from the SRAM. Note that the forward pointer and fragment buffer 103 * addresses are physical memory addresses, not virtual. Note also that 104 * a single ethernet frame can not span lists: if the host wants to 105 * transmit a frame and the frame data is split up over more than 10 106 * buffers, the frame has to collapsed before it can be transmitted. 107 * 108 * To receive frames, the driver sets up a number of lists and populates 109 * the fragment descriptors, then it sends an RX GO command to the chip. 110 * When a frame is received, the chip will DMA it into the memory regions 111 * specified by the fragment descriptors and then trigger an RX 'end of 112 * frame interrupt' when done. The driver may choose to use only one 113 * fragment per list; this may result is slighltly less efficient use 114 * of memory in exchange for improving performance. 115 * 116 * To transmit frames, the driver again sets up lists and fragment 117 * descriptors, only this time the buffers contain frame data that 118 * is to be DMA'ed into the chip instead of out of it. Once the chip 119 * has transfered the data into its on-board SRAM, it will trigger a 120 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 121 * interrupt when it reaches the end of the list. 122 */ 123 /* 124 * Some notes about this driver: 125 * 126 * The ThunderLAN chip provides a couple of different ways to organize 127 * reception, transmission and interrupt handling. The simplest approach 128 * is to use one list each for transmission and reception. In this mode, 129 * the ThunderLAN will generate two interrupts for every received frame 130 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 131 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 132 * performance to have to handle so many interrupts. 133 * 134 * Initially I wanted to create a circular list of receive buffers so 135 * that the ThunderLAN chip would think there was an infinitely long 136 * receive channel and never deliver an RXEOC interrupt. However this 137 * doesn't work correctly under heavy load: while the manual says the 138 * chip will trigger an RXEOF interrupt each time a frame is copied into 139 * memory, you can't count on the chip waiting around for you to acknowledge 140 * the interrupt before it starts trying to DMA the next frame. The result 141 * is that the chip might traverse the entire circular list and then wrap 142 * around before you have a chance to do anything about it. Consequently, 143 * the receive list is terminated (with a 0 in the forward pointer in the 144 * last element). Each time an RXEOF interrupt arrives, the used list 145 * is shifted to the end of the list. This gives the appearance of an 146 * infinitely large RX chain so long as the driver doesn't fall behind 147 * the chip and allow all of the lists to be filled up. 148 * 149 * If all the lists are filled, the adapter will deliver an RX 'end of 150 * channel' interrupt when it hits the 0 forward pointer at the end of 151 * the chain. The RXEOC handler then cleans out the RX chain and resets 152 * the list head pointer in the ch_parm register and restarts the receiver. 153 * 154 * For frame transmission, it is possible to program the ThunderLAN's 155 * transmit interrupt threshold so that the chip can acknowledge multiple 156 * lists with only a single TX EOF interrupt. This allows the driver to 157 * queue several frames in one shot, and only have to handle a total 158 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 159 * are transmitted. Frame transmission is done directly out of the 160 * mbufs passed to the tl_start() routine via the interface send queue. 161 * The driver simply sets up the fragment descriptors in the transmit 162 * lists to point to the mbuf data regions and sends a TX GO command. 163 * 164 * Note that since the RX and TX lists themselves are always used 165 * only by the driver, the are malloc()ed once at driver initialization 166 * time and never free()ed. 167 * 168 * Also, in order to remain as platform independent as possible, this 169 * driver uses memory mapped register access to manipulate the card 170 * as opposed to programmed I/O. This avoids the use of the inb/outb 171 * (and related) instructions which are specific to the i386 platform. 172 * 173 * Using these techniques, this driver achieves very high performance 174 * by minimizing the amount of interrupts generated during large 175 * transfers and by completely avoiding buffer copies. Frame transfer 176 * to and from the ThunderLAN chip is performed entirely by the chip 177 * itself thereby reducing the load on the host CPU. 178 */ 179 180 #include <sys/param.h> 181 #include <sys/systm.h> 182 #include <sys/sockio.h> 183 #include <sys/mbuf.h> 184 #include <sys/malloc.h> 185 #include <sys/kernel.h> 186 #include <sys/module.h> 187 #include <sys/socket.h> 188 189 #include <net/if.h> 190 #include <net/if_arp.h> 191 #include <net/ethernet.h> 192 #include <net/if_dl.h> 193 #include <net/if_media.h> 194 195 #include <net/bpf.h> 196 197 #include <vm/vm.h> /* for vtophys */ 198 #include <vm/pmap.h> /* for vtophys */ 199 #include <machine/bus_memio.h> 200 #include <machine/bus_pio.h> 201 #include <machine/bus.h> 202 #include <machine/resource.h> 203 #include <sys/bus.h> 204 #include <sys/rman.h> 205 206 #include <dev/mii/mii.h> 207 #include <dev/mii/miivar.h> 208 209 #include <dev/pci/pcireg.h> 210 #include <dev/pci/pcivar.h> 211 212 /* 213 * Default to using PIO register access mode to pacify certain 214 * laptop docking stations with built-in ThunderLAN chips that 215 * don't seem to handle memory mapped mode properly. 216 */ 217 #define TL_USEIOSPACE 218 219 #include <pci/if_tlreg.h> 220 221 MODULE_DEPEND(tl, pci, 1, 1, 1); 222 MODULE_DEPEND(tl, ether, 1, 1, 1); 223 MODULE_DEPEND(tl, miibus, 1, 1, 1); 224 225 /* "controller miibus0" required. See GENERIC if you get errors here. */ 226 #include "miibus_if.h" 227 228 /* 229 * Various supported device vendors/types and their names. 230 */ 231 232 static struct tl_type tl_devs[] = { 233 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 234 "Texas Instruments ThunderLAN" }, 235 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 236 "Compaq Netelligent 10" }, 237 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 238 "Compaq Netelligent 10/100" }, 239 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 240 "Compaq Netelligent 10/100 Proliant" }, 241 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 242 "Compaq Netelligent 10/100 Dual Port" }, 243 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 244 "Compaq NetFlex-3/P Integrated" }, 245 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 246 "Compaq NetFlex-3/P" }, 247 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 248 "Compaq NetFlex 3/P w/ BNC" }, 249 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 250 "Compaq Netelligent 10/100 TX Embedded UTP" }, 251 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 252 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 253 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 254 "Compaq Netelligent 10/100 TX UTP" }, 255 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 256 "Olicom OC-2183/2185" }, 257 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 258 "Olicom OC-2325" }, 259 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 260 "Olicom OC-2326 10/100 TX UTP" }, 261 { 0, 0, NULL } 262 }; 263 264 static int tl_probe (device_t); 265 static int tl_attach (device_t); 266 static int tl_detach (device_t); 267 static int tl_intvec_rxeoc (void *, u_int32_t); 268 static int tl_intvec_txeoc (void *, u_int32_t); 269 static int tl_intvec_txeof (void *, u_int32_t); 270 static int tl_intvec_rxeof (void *, u_int32_t); 271 static int tl_intvec_adchk (void *, u_int32_t); 272 static int tl_intvec_netsts (void *, u_int32_t); 273 274 static int tl_newbuf (struct tl_softc *, struct tl_chain_onefrag *); 275 static void tl_stats_update (void *); 276 static int tl_encap (struct tl_softc *, struct tl_chain *, 277 struct mbuf *); 278 279 static void tl_intr (void *); 280 static void tl_start (struct ifnet *); 281 static int tl_ioctl (struct ifnet *, u_long, caddr_t); 282 static void tl_init (void *); 283 static void tl_stop (struct tl_softc *); 284 static void tl_watchdog (struct ifnet *); 285 static void tl_shutdown (device_t); 286 static int tl_ifmedia_upd (struct ifnet *); 287 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 288 289 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int); 290 static u_int8_t tl_eeprom_getbyte (struct tl_softc *, int, u_int8_t *); 291 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int); 292 293 static void tl_mii_sync (struct tl_softc *); 294 static void tl_mii_send (struct tl_softc *, u_int32_t, int); 295 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *); 296 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *); 297 static int tl_miibus_readreg (device_t, int, int); 298 static int tl_miibus_writereg (device_t, int, int, int); 299 static void tl_miibus_statchg (device_t); 300 301 static void tl_setmode (struct tl_softc *, int); 302 static uint32_t tl_mchash (const uint8_t *); 303 static void tl_setmulti (struct tl_softc *); 304 static void tl_setfilt (struct tl_softc *, caddr_t, int); 305 static void tl_softreset (struct tl_softc *, int); 306 static void tl_hardreset (device_t); 307 static int tl_list_rx_init (struct tl_softc *); 308 static int tl_list_tx_init (struct tl_softc *); 309 310 static u_int8_t tl_dio_read8 (struct tl_softc *, int); 311 static u_int16_t tl_dio_read16 (struct tl_softc *, int); 312 static u_int32_t tl_dio_read32 (struct tl_softc *, int); 313 static void tl_dio_write8 (struct tl_softc *, int, int); 314 static void tl_dio_write16 (struct tl_softc *, int, int); 315 static void tl_dio_write32 (struct tl_softc *, int, int); 316 static void tl_dio_setbit (struct tl_softc *, int, int); 317 static void tl_dio_clrbit (struct tl_softc *, int, int); 318 static void tl_dio_setbit16 (struct tl_softc *, int, int); 319 static void tl_dio_clrbit16 (struct tl_softc *, int, int); 320 321 #ifdef TL_USEIOSPACE 322 #define TL_RES SYS_RES_IOPORT 323 #define TL_RID TL_PCI_LOIO 324 #else 325 #define TL_RES SYS_RES_MEMORY 326 #define TL_RID TL_PCI_LOMEM 327 #endif 328 329 static device_method_t tl_methods[] = { 330 /* Device interface */ 331 DEVMETHOD(device_probe, tl_probe), 332 DEVMETHOD(device_attach, tl_attach), 333 DEVMETHOD(device_detach, tl_detach), 334 DEVMETHOD(device_shutdown, tl_shutdown), 335 336 /* bus interface */ 337 DEVMETHOD(bus_print_child, bus_generic_print_child), 338 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 339 340 /* MII interface */ 341 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 342 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 343 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 344 345 { 0, 0 } 346 }; 347 348 static driver_t tl_driver = { 349 "tl", 350 tl_methods, 351 sizeof(struct tl_softc) 352 }; 353 354 static devclass_t tl_devclass; 355 356 DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0); 357 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 358 359 static u_int8_t tl_dio_read8(sc, reg) 360 struct tl_softc *sc; 361 int reg; 362 { 363 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 364 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 365 } 366 367 static u_int16_t tl_dio_read16(sc, reg) 368 struct tl_softc *sc; 369 int reg; 370 { 371 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 372 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 373 } 374 375 static u_int32_t tl_dio_read32(sc, reg) 376 struct tl_softc *sc; 377 int reg; 378 { 379 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 380 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 381 } 382 383 static void tl_dio_write8(sc, reg, val) 384 struct tl_softc *sc; 385 int reg; 386 int val; 387 { 388 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 389 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 390 return; 391 } 392 393 static void tl_dio_write16(sc, reg, val) 394 struct tl_softc *sc; 395 int reg; 396 int val; 397 { 398 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 399 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 400 return; 401 } 402 403 static void tl_dio_write32(sc, reg, val) 404 struct tl_softc *sc; 405 int reg; 406 int val; 407 { 408 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 409 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 410 return; 411 } 412 413 static void 414 tl_dio_setbit(sc, reg, bit) 415 struct tl_softc *sc; 416 int reg; 417 int bit; 418 { 419 u_int8_t f; 420 421 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 422 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 423 f |= bit; 424 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 425 426 return; 427 } 428 429 static void 430 tl_dio_clrbit(sc, reg, bit) 431 struct tl_softc *sc; 432 int reg; 433 int bit; 434 { 435 u_int8_t f; 436 437 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 438 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 439 f &= ~bit; 440 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 441 442 return; 443 } 444 445 static void tl_dio_setbit16(sc, reg, bit) 446 struct tl_softc *sc; 447 int reg; 448 int bit; 449 { 450 u_int16_t f; 451 452 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 453 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 454 f |= bit; 455 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 456 457 return; 458 } 459 460 static void tl_dio_clrbit16(sc, reg, bit) 461 struct tl_softc *sc; 462 int reg; 463 int bit; 464 { 465 u_int16_t f; 466 467 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 468 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 469 f &= ~bit; 470 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 471 472 return; 473 } 474 475 /* 476 * Send an instruction or address to the EEPROM, check for ACK. 477 */ 478 static u_int8_t tl_eeprom_putbyte(sc, byte) 479 struct tl_softc *sc; 480 int byte; 481 { 482 register int i, ack = 0; 483 484 /* 485 * Make sure we're in TX mode. 486 */ 487 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 488 489 /* 490 * Feed in each bit and stobe the clock. 491 */ 492 for (i = 0x80; i; i >>= 1) { 493 if (byte & i) { 494 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 495 } else { 496 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 497 } 498 DELAY(1); 499 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 500 DELAY(1); 501 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 502 } 503 504 /* 505 * Turn off TX mode. 506 */ 507 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 508 509 /* 510 * Check for ack. 511 */ 512 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 513 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 514 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 515 516 return(ack); 517 } 518 519 /* 520 * Read a byte of data stored in the EEPROM at address 'addr.' 521 */ 522 static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 523 struct tl_softc *sc; 524 int addr; 525 u_int8_t *dest; 526 { 527 register int i; 528 u_int8_t byte = 0; 529 struct ifnet *ifp = &sc->arpcom.ac_if; 530 531 tl_dio_write8(sc, TL_NETSIO, 0); 532 533 EEPROM_START; 534 535 /* 536 * Send write control code to EEPROM. 537 */ 538 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 539 if_printf(ifp, "failed to send write command, status: %x\n", 540 tl_dio_read8(sc, TL_NETSIO)); 541 return(1); 542 } 543 544 /* 545 * Send address of byte we want to read. 546 */ 547 if (tl_eeprom_putbyte(sc, addr)) { 548 if_printf(ifp, "failed to send address, status: %x\n", 549 tl_dio_read8(sc, TL_NETSIO)); 550 return(1); 551 } 552 553 EEPROM_STOP; 554 EEPROM_START; 555 /* 556 * Send read control code to EEPROM. 557 */ 558 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 559 if_printf(ifp, "failed to send write command, status: %x\n", 560 tl_dio_read8(sc, TL_NETSIO)); 561 return(1); 562 } 563 564 /* 565 * Start reading bits from EEPROM. 566 */ 567 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 568 for (i = 0x80; i; i >>= 1) { 569 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 570 DELAY(1); 571 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 572 byte |= i; 573 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 574 DELAY(1); 575 } 576 577 EEPROM_STOP; 578 579 /* 580 * No ACK generated for read, so just return byte. 581 */ 582 583 *dest = byte; 584 585 return(0); 586 } 587 588 /* 589 * Read a sequence of bytes from the EEPROM. 590 */ 591 static int 592 tl_read_eeprom(sc, dest, off, cnt) 593 struct tl_softc *sc; 594 caddr_t dest; 595 int off; 596 int cnt; 597 { 598 int err = 0, i; 599 u_int8_t byte = 0; 600 601 for (i = 0; i < cnt; i++) { 602 err = tl_eeprom_getbyte(sc, off + i, &byte); 603 if (err) 604 break; 605 *(dest + i) = byte; 606 } 607 608 return(err ? 1 : 0); 609 } 610 611 static void 612 tl_mii_sync(sc) 613 struct tl_softc *sc; 614 { 615 register int i; 616 617 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 618 619 for (i = 0; i < 32; i++) { 620 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 621 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 622 } 623 624 return; 625 } 626 627 static void 628 tl_mii_send(sc, bits, cnt) 629 struct tl_softc *sc; 630 u_int32_t bits; 631 int cnt; 632 { 633 int i; 634 635 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 636 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 637 if (bits & i) { 638 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 639 } else { 640 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 641 } 642 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 643 } 644 } 645 646 static int 647 tl_mii_readreg(sc, frame) 648 struct tl_softc *sc; 649 struct tl_mii_frame *frame; 650 651 { 652 int i, ack; 653 int minten = 0; 654 655 TL_LOCK(sc); 656 657 tl_mii_sync(sc); 658 659 /* 660 * Set up frame for RX. 661 */ 662 frame->mii_stdelim = TL_MII_STARTDELIM; 663 frame->mii_opcode = TL_MII_READOP; 664 frame->mii_turnaround = 0; 665 frame->mii_data = 0; 666 667 /* 668 * Turn off MII interrupt by forcing MINTEN low. 669 */ 670 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 671 if (minten) { 672 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 673 } 674 675 /* 676 * Turn on data xmit. 677 */ 678 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 679 680 /* 681 * Send command/address info. 682 */ 683 tl_mii_send(sc, frame->mii_stdelim, 2); 684 tl_mii_send(sc, frame->mii_opcode, 2); 685 tl_mii_send(sc, frame->mii_phyaddr, 5); 686 tl_mii_send(sc, frame->mii_regaddr, 5); 687 688 /* 689 * Turn off xmit. 690 */ 691 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 692 693 /* Idle bit */ 694 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 695 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 696 697 /* Check for ack */ 698 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 699 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 700 701 /* Complete the cycle */ 702 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 703 704 /* 705 * Now try reading data bits. If the ack failed, we still 706 * need to clock through 16 cycles to keep the PHYs in sync. 707 */ 708 if (ack) { 709 for(i = 0; i < 16; i++) { 710 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 711 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 712 } 713 goto fail; 714 } 715 716 for (i = 0x8000; i; i >>= 1) { 717 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 718 if (!ack) { 719 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 720 frame->mii_data |= i; 721 } 722 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 723 } 724 725 fail: 726 727 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 728 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 729 730 /* Reenable interrupts */ 731 if (minten) { 732 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 733 } 734 735 TL_UNLOCK(sc); 736 737 if (ack) 738 return(1); 739 return(0); 740 } 741 742 static int 743 tl_mii_writereg(sc, frame) 744 struct tl_softc *sc; 745 struct tl_mii_frame *frame; 746 747 { 748 int minten; 749 750 TL_LOCK(sc); 751 752 tl_mii_sync(sc); 753 754 /* 755 * Set up frame for TX. 756 */ 757 758 frame->mii_stdelim = TL_MII_STARTDELIM; 759 frame->mii_opcode = TL_MII_WRITEOP; 760 frame->mii_turnaround = TL_MII_TURNAROUND; 761 762 /* 763 * Turn off MII interrupt by forcing MINTEN low. 764 */ 765 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 766 if (minten) { 767 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 768 } 769 770 /* 771 * Turn on data output. 772 */ 773 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 774 775 tl_mii_send(sc, frame->mii_stdelim, 2); 776 tl_mii_send(sc, frame->mii_opcode, 2); 777 tl_mii_send(sc, frame->mii_phyaddr, 5); 778 tl_mii_send(sc, frame->mii_regaddr, 5); 779 tl_mii_send(sc, frame->mii_turnaround, 2); 780 tl_mii_send(sc, frame->mii_data, 16); 781 782 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 783 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 784 785 /* 786 * Turn off xmit. 787 */ 788 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 789 790 /* Reenable interrupts */ 791 if (minten) 792 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 793 794 TL_UNLOCK(sc); 795 796 return(0); 797 } 798 799 static int 800 tl_miibus_readreg(dev, phy, reg) 801 device_t dev; 802 int phy, reg; 803 { 804 struct tl_softc *sc; 805 struct tl_mii_frame frame; 806 807 sc = device_get_softc(dev); 808 bzero((char *)&frame, sizeof(frame)); 809 810 frame.mii_phyaddr = phy; 811 frame.mii_regaddr = reg; 812 tl_mii_readreg(sc, &frame); 813 814 return(frame.mii_data); 815 } 816 817 static int 818 tl_miibus_writereg(dev, phy, reg, data) 819 device_t dev; 820 int phy, reg, data; 821 { 822 struct tl_softc *sc; 823 struct tl_mii_frame frame; 824 825 sc = device_get_softc(dev); 826 bzero((char *)&frame, sizeof(frame)); 827 828 frame.mii_phyaddr = phy; 829 frame.mii_regaddr = reg; 830 frame.mii_data = data; 831 832 tl_mii_writereg(sc, &frame); 833 834 return(0); 835 } 836 837 static void 838 tl_miibus_statchg(dev) 839 device_t dev; 840 { 841 struct tl_softc *sc; 842 struct mii_data *mii; 843 844 sc = device_get_softc(dev); 845 TL_LOCK(sc); 846 mii = device_get_softc(sc->tl_miibus); 847 848 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 849 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 850 } else { 851 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 852 } 853 TL_UNLOCK(sc); 854 855 return; 856 } 857 858 /* 859 * Set modes for bitrate devices. 860 */ 861 static void 862 tl_setmode(sc, media) 863 struct tl_softc *sc; 864 int media; 865 { 866 if (IFM_SUBTYPE(media) == IFM_10_5) 867 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 868 if (IFM_SUBTYPE(media) == IFM_10_T) { 869 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 870 if ((media & IFM_GMASK) == IFM_FDX) { 871 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 872 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 873 } else { 874 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 875 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 876 } 877 } 878 879 return; 880 } 881 882 /* 883 * Calculate the hash of a MAC address for programming the multicast hash 884 * table. This hash is simply the address split into 6-bit chunks 885 * XOR'd, e.g. 886 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 887 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 888 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 889 * the folded 24-bit value is split into 6-bit portions and XOR'd. 890 */ 891 static uint32_t 892 tl_mchash(addr) 893 const uint8_t *addr; 894 { 895 int t; 896 897 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 898 (addr[2] ^ addr[5]); 899 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 900 } 901 902 /* 903 * The ThunderLAN has a perfect MAC address filter in addition to 904 * the multicast hash filter. The perfect filter can be programmed 905 * with up to four MAC addresses. The first one is always used to 906 * hold the station address, which leaves us free to use the other 907 * three for multicast addresses. 908 */ 909 static void 910 tl_setfilt(sc, addr, slot) 911 struct tl_softc *sc; 912 caddr_t addr; 913 int slot; 914 { 915 int i; 916 u_int16_t regaddr; 917 918 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 919 920 for (i = 0; i < ETHER_ADDR_LEN; i++) 921 tl_dio_write8(sc, regaddr + i, *(addr + i)); 922 923 return; 924 } 925 926 /* 927 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 928 * linked list. This is fine, except addresses are added from the head 929 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 930 * group to always be in the perfect filter, but as more groups are added, 931 * the 224.0.0.1 entry (which is always added first) gets pushed down 932 * the list and ends up at the tail. So after 3 or 4 multicast groups 933 * are added, the all-hosts entry gets pushed out of the perfect filter 934 * and into the hash table. 935 * 936 * Because the multicast list is a doubly-linked list as opposed to a 937 * circular queue, we don't have the ability to just grab the tail of 938 * the list and traverse it backwards. Instead, we have to traverse 939 * the list once to find the tail, then traverse it again backwards to 940 * update the multicast filter. 941 */ 942 static void 943 tl_setmulti(sc) 944 struct tl_softc *sc; 945 { 946 struct ifnet *ifp; 947 u_int32_t hashes[2] = { 0, 0 }; 948 int h, i; 949 struct ifmultiaddr *ifma; 950 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 951 ifp = &sc->arpcom.ac_if; 952 953 /* First, zot all the existing filters. */ 954 for (i = 1; i < 4; i++) 955 tl_setfilt(sc, (caddr_t)&dummy, i); 956 tl_dio_write32(sc, TL_HASH1, 0); 957 tl_dio_write32(sc, TL_HASH2, 0); 958 959 /* Now program new ones. */ 960 if (ifp->if_flags & IFF_ALLMULTI) { 961 hashes[0] = 0xFFFFFFFF; 962 hashes[1] = 0xFFFFFFFF; 963 } else { 964 i = 1; 965 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 966 if (ifma->ifma_addr->sa_family != AF_LINK) 967 continue; 968 /* 969 * Program the first three multicast groups 970 * into the perfect filter. For all others, 971 * use the hash table. 972 */ 973 if (i < 4) { 974 tl_setfilt(sc, 975 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 976 i++; 977 continue; 978 } 979 980 h = tl_mchash( 981 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 982 if (h < 32) 983 hashes[0] |= (1 << h); 984 else 985 hashes[1] |= (1 << (h - 32)); 986 } 987 } 988 989 tl_dio_write32(sc, TL_HASH1, hashes[0]); 990 tl_dio_write32(sc, TL_HASH2, hashes[1]); 991 992 return; 993 } 994 995 /* 996 * This routine is recommended by the ThunderLAN manual to insure that 997 * the internal PHY is powered up correctly. It also recommends a one 998 * second pause at the end to 'wait for the clocks to start' but in my 999 * experience this isn't necessary. 1000 */ 1001 static void 1002 tl_hardreset(dev) 1003 device_t dev; 1004 { 1005 struct tl_softc *sc; 1006 int i; 1007 u_int16_t flags; 1008 1009 sc = device_get_softc(dev); 1010 1011 tl_mii_sync(sc); 1012 1013 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 1014 1015 for (i = 0; i < MII_NPHY; i++) 1016 tl_miibus_writereg(dev, i, MII_BMCR, flags); 1017 1018 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 1019 DELAY(50000); 1020 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 1021 tl_mii_sync(sc); 1022 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 1023 1024 DELAY(50000); 1025 return; 1026 } 1027 1028 static void 1029 tl_softreset(sc, internal) 1030 struct tl_softc *sc; 1031 int internal; 1032 { 1033 u_int32_t cmd, dummy, i; 1034 1035 /* Assert the adapter reset bit. */ 1036 CMD_SET(sc, TL_CMD_ADRST); 1037 1038 /* Turn off interrupts */ 1039 CMD_SET(sc, TL_CMD_INTSOFF); 1040 1041 /* First, clear the stats registers. */ 1042 for (i = 0; i < 5; i++) 1043 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1044 1045 /* Clear Areg and Hash registers */ 1046 for (i = 0; i < 8; i++) 1047 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1048 1049 /* 1050 * Set up Netconfig register. Enable one channel and 1051 * one fragment mode. 1052 */ 1053 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1054 if (internal && !sc->tl_bitrate) { 1055 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1056 } else { 1057 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1058 } 1059 1060 /* Handle cards with bitrate devices. */ 1061 if (sc->tl_bitrate) 1062 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1063 1064 /* 1065 * Load adapter irq pacing timer and tx threshold. 1066 * We make the transmit threshold 1 initially but we may 1067 * change that later. 1068 */ 1069 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1070 cmd |= TL_CMD_NES; 1071 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1072 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1073 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1074 1075 /* Unreset the MII */ 1076 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1077 1078 /* Take the adapter out of reset */ 1079 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1080 1081 /* Wait for things to settle down a little. */ 1082 DELAY(500); 1083 1084 return; 1085 } 1086 1087 /* 1088 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1089 * against our list and return its name if we find a match. 1090 */ 1091 static int 1092 tl_probe(dev) 1093 device_t dev; 1094 { 1095 struct tl_type *t; 1096 1097 t = tl_devs; 1098 1099 while(t->tl_name != NULL) { 1100 if ((pci_get_vendor(dev) == t->tl_vid) && 1101 (pci_get_device(dev) == t->tl_did)) { 1102 device_set_desc(dev, t->tl_name); 1103 return(0); 1104 } 1105 t++; 1106 } 1107 1108 return(ENXIO); 1109 } 1110 1111 static int 1112 tl_attach(dev) 1113 device_t dev; 1114 { 1115 int i; 1116 u_int16_t did, vid; 1117 struct tl_type *t; 1118 struct ifnet *ifp; 1119 struct tl_softc *sc; 1120 int unit, error = 0, rid; 1121 1122 vid = pci_get_vendor(dev); 1123 did = pci_get_device(dev); 1124 sc = device_get_softc(dev); 1125 unit = device_get_unit(dev); 1126 1127 t = tl_devs; 1128 while(t->tl_name != NULL) { 1129 if (vid == t->tl_vid && did == t->tl_did) 1130 break; 1131 t++; 1132 } 1133 1134 if (t->tl_name == NULL) { 1135 device_printf(dev, "unknown device!?\n"); 1136 return (ENXIO); 1137 } 1138 1139 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1140 MTX_DEF | MTX_RECURSE); 1141 1142 /* 1143 * Map control/status registers. 1144 */ 1145 pci_enable_busmaster(dev); 1146 1147 #ifdef TL_USEIOSPACE 1148 1149 rid = TL_PCI_LOIO; 1150 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1151 RF_ACTIVE); 1152 1153 /* 1154 * Some cards have the I/O and memory mapped address registers 1155 * reversed. Try both combinations before giving up. 1156 */ 1157 if (sc->tl_res == NULL) { 1158 rid = TL_PCI_LOMEM; 1159 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1160 RF_ACTIVE); 1161 } 1162 #else 1163 rid = TL_PCI_LOMEM; 1164 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1165 RF_ACTIVE); 1166 if (sc->tl_res == NULL) { 1167 rid = TL_PCI_LOIO; 1168 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1169 RF_ACTIVE); 1170 } 1171 #endif 1172 1173 if (sc->tl_res == NULL) { 1174 device_printf(dev, "couldn't map ports/memory\n"); 1175 error = ENXIO; 1176 goto fail; 1177 } 1178 1179 sc->tl_btag = rman_get_bustag(sc->tl_res); 1180 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1181 1182 #ifdef notdef 1183 /* 1184 * The ThunderLAN manual suggests jacking the PCI latency 1185 * timer all the way up to its maximum value. I'm not sure 1186 * if this is really necessary, but what the manual wants, 1187 * the manual gets. 1188 */ 1189 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1190 command |= 0x0000FF00; 1191 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1192 #endif 1193 1194 /* Allocate interrupt */ 1195 rid = 0; 1196 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1197 RF_SHAREABLE | RF_ACTIVE); 1198 1199 if (sc->tl_irq == NULL) { 1200 device_printf(dev, "couldn't map interrupt\n"); 1201 error = ENXIO; 1202 goto fail; 1203 } 1204 1205 /* 1206 * Now allocate memory for the TX and RX lists. 1207 */ 1208 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1209 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1210 1211 if (sc->tl_ldata == NULL) { 1212 device_printf(dev, "no memory for list buffers!\n"); 1213 error = ENXIO; 1214 goto fail; 1215 } 1216 1217 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1218 1219 sc->tl_dinfo = t; 1220 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1221 sc->tl_eeaddr = TL_EEPROM_EADDR; 1222 if (t->tl_vid == OLICOM_VENDORID) 1223 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1224 1225 /* Reset the adapter. */ 1226 tl_softreset(sc, 1); 1227 tl_hardreset(dev); 1228 tl_softreset(sc, 1); 1229 1230 /* 1231 * Get station address from the EEPROM. 1232 */ 1233 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1234 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1235 device_printf(dev, "failed to read station address\n"); 1236 error = ENXIO; 1237 goto fail; 1238 } 1239 1240 /* 1241 * XXX Olicom, in its desire to be different from the 1242 * rest of the world, has done strange things with the 1243 * encoding of the station address in the EEPROM. First 1244 * of all, they store the address at offset 0xF8 rather 1245 * than at 0x83 like the ThunderLAN manual suggests. 1246 * Second, they store the address in three 16-bit words in 1247 * network byte order, as opposed to storing it sequentially 1248 * like all the other ThunderLAN cards. In order to get 1249 * the station address in a form that matches what the Olicom 1250 * diagnostic utility specifies, we have to byte-swap each 1251 * word. To make things even more confusing, neither 00:00:28 1252 * nor 00:00:24 appear in the IEEE OUI database. 1253 */ 1254 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1255 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1256 u_int16_t *p; 1257 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1258 *p = ntohs(*p); 1259 } 1260 } 1261 1262 ifp = &sc->arpcom.ac_if; 1263 ifp->if_softc = sc; 1264 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 1266 IFF_NEEDSGIANT; 1267 ifp->if_ioctl = tl_ioctl; 1268 ifp->if_start = tl_start; 1269 ifp->if_watchdog = tl_watchdog; 1270 ifp->if_init = tl_init; 1271 ifp->if_mtu = ETHERMTU; 1272 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 1273 callout_handle_init(&sc->tl_stat_ch); 1274 1275 /* Reset the adapter again. */ 1276 tl_softreset(sc, 1); 1277 tl_hardreset(dev); 1278 tl_softreset(sc, 1); 1279 1280 /* 1281 * Do MII setup. If no PHYs are found, then this is a 1282 * bitrate ThunderLAN chip that only supports 10baseT 1283 * and AUI/BNC. 1284 */ 1285 if (mii_phy_probe(dev, &sc->tl_miibus, 1286 tl_ifmedia_upd, tl_ifmedia_sts)) { 1287 struct ifmedia *ifm; 1288 sc->tl_bitrate = 1; 1289 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1290 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1291 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1292 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1293 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1294 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1295 /* Reset again, this time setting bitrate mode. */ 1296 tl_softreset(sc, 1); 1297 ifm = &sc->ifmedia; 1298 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1299 tl_ifmedia_upd(ifp); 1300 } 1301 1302 /* 1303 * Call MI attach routine. 1304 */ 1305 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1306 1307 /* Hook interrupt last to avoid having to lock softc */ 1308 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1309 tl_intr, sc, &sc->tl_intrhand); 1310 1311 if (error) { 1312 device_printf(dev, "couldn't set up irq\n"); 1313 ether_ifdetach(ifp); 1314 goto fail; 1315 } 1316 1317 fail: 1318 if (error) 1319 tl_detach(dev); 1320 1321 return(error); 1322 } 1323 1324 /* 1325 * Shutdown hardware and free up resources. This can be called any 1326 * time after the mutex has been initialized. It is called in both 1327 * the error case in attach and the normal detach case so it needs 1328 * to be careful about only freeing resources that have actually been 1329 * allocated. 1330 */ 1331 static int 1332 tl_detach(dev) 1333 device_t dev; 1334 { 1335 struct tl_softc *sc; 1336 struct ifnet *ifp; 1337 1338 sc = device_get_softc(dev); 1339 KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized")); 1340 TL_LOCK(sc); 1341 ifp = &sc->arpcom.ac_if; 1342 1343 /* These should only be active if attach succeeded */ 1344 if (device_is_attached(dev)) { 1345 tl_stop(sc); 1346 ether_ifdetach(ifp); 1347 } 1348 if (sc->tl_miibus) 1349 device_delete_child(dev, sc->tl_miibus); 1350 bus_generic_detach(dev); 1351 1352 if (sc->tl_ldata) 1353 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1354 if (sc->tl_bitrate) 1355 ifmedia_removeall(&sc->ifmedia); 1356 1357 if (sc->tl_intrhand) 1358 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1359 if (sc->tl_irq) 1360 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1361 if (sc->tl_res) 1362 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1363 1364 TL_UNLOCK(sc); 1365 mtx_destroy(&sc->tl_mtx); 1366 1367 return(0); 1368 } 1369 1370 /* 1371 * Initialize the transmit lists. 1372 */ 1373 static int 1374 tl_list_tx_init(sc) 1375 struct tl_softc *sc; 1376 { 1377 struct tl_chain_data *cd; 1378 struct tl_list_data *ld; 1379 int i; 1380 1381 cd = &sc->tl_cdata; 1382 ld = sc->tl_ldata; 1383 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1384 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1385 if (i == (TL_TX_LIST_CNT - 1)) 1386 cd->tl_tx_chain[i].tl_next = NULL; 1387 else 1388 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1389 } 1390 1391 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1392 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1393 sc->tl_txeoc = 1; 1394 1395 return(0); 1396 } 1397 1398 /* 1399 * Initialize the RX lists and allocate mbufs for them. 1400 */ 1401 static int 1402 tl_list_rx_init(sc) 1403 struct tl_softc *sc; 1404 { 1405 struct tl_chain_data *cd; 1406 struct tl_list_data *ld; 1407 int i; 1408 1409 cd = &sc->tl_cdata; 1410 ld = sc->tl_ldata; 1411 1412 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1413 cd->tl_rx_chain[i].tl_ptr = 1414 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1415 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1416 return(ENOBUFS); 1417 if (i == (TL_RX_LIST_CNT - 1)) { 1418 cd->tl_rx_chain[i].tl_next = NULL; 1419 ld->tl_rx_list[i].tlist_fptr = 0; 1420 } else { 1421 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1422 ld->tl_rx_list[i].tlist_fptr = 1423 vtophys(&ld->tl_rx_list[i + 1]); 1424 } 1425 } 1426 1427 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1428 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1429 1430 return(0); 1431 } 1432 1433 static int 1434 tl_newbuf(sc, c) 1435 struct tl_softc *sc; 1436 struct tl_chain_onefrag *c; 1437 { 1438 struct mbuf *m_new = NULL; 1439 1440 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1441 if (m_new == NULL) 1442 return(ENOBUFS); 1443 1444 MCLGET(m_new, M_DONTWAIT); 1445 if (!(m_new->m_flags & M_EXT)) { 1446 m_freem(m_new); 1447 return(ENOBUFS); 1448 } 1449 1450 #ifdef __alpha__ 1451 m_new->m_data += 2; 1452 #endif 1453 1454 c->tl_mbuf = m_new; 1455 c->tl_next = NULL; 1456 c->tl_ptr->tlist_frsize = MCLBYTES; 1457 c->tl_ptr->tlist_fptr = 0; 1458 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1459 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1460 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1461 1462 return(0); 1463 } 1464 /* 1465 * Interrupt handler for RX 'end of frame' condition (EOF). This 1466 * tells us that a full ethernet frame has been captured and we need 1467 * to handle it. 1468 * 1469 * Reception is done using 'lists' which consist of a header and a 1470 * series of 10 data count/data address pairs that point to buffers. 1471 * Initially you're supposed to create a list, populate it with pointers 1472 * to buffers, then load the physical address of the list into the 1473 * ch_parm register. The adapter is then supposed to DMA the received 1474 * frame into the buffers for you. 1475 * 1476 * To make things as fast as possible, we have the chip DMA directly 1477 * into mbufs. This saves us from having to do a buffer copy: we can 1478 * just hand the mbufs directly to ether_input(). Once the frame has 1479 * been sent on its way, the 'list' structure is assigned a new buffer 1480 * and moved to the end of the RX chain. As long we we stay ahead of 1481 * the chip, it will always think it has an endless receive channel. 1482 * 1483 * If we happen to fall behind and the chip manages to fill up all of 1484 * the buffers, it will generate an end of channel interrupt and wait 1485 * for us to empty the chain and restart the receiver. 1486 */ 1487 static int 1488 tl_intvec_rxeof(xsc, type) 1489 void *xsc; 1490 u_int32_t type; 1491 { 1492 struct tl_softc *sc; 1493 int r = 0, total_len = 0; 1494 struct ether_header *eh; 1495 struct mbuf *m; 1496 struct ifnet *ifp; 1497 struct tl_chain_onefrag *cur_rx; 1498 1499 sc = xsc; 1500 ifp = &sc->arpcom.ac_if; 1501 1502 TL_LOCK_ASSERT(sc); 1503 1504 while(sc->tl_cdata.tl_rx_head != NULL) { 1505 cur_rx = sc->tl_cdata.tl_rx_head; 1506 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1507 break; 1508 r++; 1509 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1510 m = cur_rx->tl_mbuf; 1511 total_len = cur_rx->tl_ptr->tlist_frsize; 1512 1513 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1514 ifp->if_ierrors++; 1515 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1516 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1517 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1518 continue; 1519 } 1520 1521 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1522 vtophys(cur_rx->tl_ptr); 1523 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1524 sc->tl_cdata.tl_rx_tail = cur_rx; 1525 1526 /* 1527 * Note: when the ThunderLAN chip is in 'capture all 1528 * frames' mode, it will receive its own transmissions. 1529 * We drop don't need to process our own transmissions, 1530 * so we drop them here and continue. 1531 */ 1532 eh = mtod(m, struct ether_header *); 1533 /*if (ifp->if_flags & IFF_PROMISC && */ 1534 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1535 ETHER_ADDR_LEN)) { 1536 m_freem(m); 1537 continue; 1538 } 1539 1540 m->m_pkthdr.rcvif = ifp; 1541 m->m_pkthdr.len = m->m_len = total_len; 1542 1543 TL_UNLOCK(sc); 1544 (*ifp->if_input)(ifp, m); 1545 TL_LOCK(sc); 1546 } 1547 1548 return(r); 1549 } 1550 1551 /* 1552 * The RX-EOC condition hits when the ch_parm address hasn't been 1553 * initialized or the adapter reached a list with a forward pointer 1554 * of 0 (which indicates the end of the chain). In our case, this means 1555 * the card has hit the end of the receive buffer chain and we need to 1556 * empty out the buffers and shift the pointer back to the beginning again. 1557 */ 1558 static int 1559 tl_intvec_rxeoc(xsc, type) 1560 void *xsc; 1561 u_int32_t type; 1562 { 1563 struct tl_softc *sc; 1564 int r; 1565 struct tl_chain_data *cd; 1566 1567 1568 sc = xsc; 1569 cd = &sc->tl_cdata; 1570 1571 /* Flush out the receive queue and ack RXEOF interrupts. */ 1572 r = tl_intvec_rxeof(xsc, type); 1573 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1574 r = 1; 1575 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1576 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1577 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1578 r |= (TL_CMD_GO|TL_CMD_RT); 1579 return(r); 1580 } 1581 1582 static int 1583 tl_intvec_txeof(xsc, type) 1584 void *xsc; 1585 u_int32_t type; 1586 { 1587 struct tl_softc *sc; 1588 int r = 0; 1589 struct tl_chain *cur_tx; 1590 1591 sc = xsc; 1592 1593 /* 1594 * Go through our tx list and free mbufs for those 1595 * frames that have been sent. 1596 */ 1597 while (sc->tl_cdata.tl_tx_head != NULL) { 1598 cur_tx = sc->tl_cdata.tl_tx_head; 1599 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1600 break; 1601 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1602 1603 r++; 1604 m_freem(cur_tx->tl_mbuf); 1605 cur_tx->tl_mbuf = NULL; 1606 1607 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1608 sc->tl_cdata.tl_tx_free = cur_tx; 1609 if (!cur_tx->tl_ptr->tlist_fptr) 1610 break; 1611 } 1612 1613 return(r); 1614 } 1615 1616 /* 1617 * The transmit end of channel interrupt. The adapter triggers this 1618 * interrupt to tell us it hit the end of the current transmit list. 1619 * 1620 * A note about this: it's possible for a condition to arise where 1621 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1622 * You have to avoid this since the chip expects things to go in a 1623 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1624 * When the TXEOF handler is called, it will free all of the transmitted 1625 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1626 * interrupt should be received and acknowledged before any more frames 1627 * are queued for transmission. If tl_statrt() is called after TXEOF 1628 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1629 * it could attempt to issue a transmit command prematurely. 1630 * 1631 * To guard against this, tl_start() will only issue transmit commands 1632 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1633 * can set this flag once tl_start() has cleared it. 1634 */ 1635 static int 1636 tl_intvec_txeoc(xsc, type) 1637 void *xsc; 1638 u_int32_t type; 1639 { 1640 struct tl_softc *sc; 1641 struct ifnet *ifp; 1642 u_int32_t cmd; 1643 1644 sc = xsc; 1645 ifp = &sc->arpcom.ac_if; 1646 1647 /* Clear the timeout timer. */ 1648 ifp->if_timer = 0; 1649 1650 if (sc->tl_cdata.tl_tx_head == NULL) { 1651 ifp->if_flags &= ~IFF_OACTIVE; 1652 sc->tl_cdata.tl_tx_tail = NULL; 1653 sc->tl_txeoc = 1; 1654 } else { 1655 sc->tl_txeoc = 0; 1656 /* First we have to ack the EOC interrupt. */ 1657 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1658 /* Then load the address of the next TX list. */ 1659 CSR_WRITE_4(sc, TL_CH_PARM, 1660 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1661 /* Restart TX channel. */ 1662 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1663 cmd &= ~TL_CMD_RT; 1664 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1665 CMD_PUT(sc, cmd); 1666 return(0); 1667 } 1668 1669 return(1); 1670 } 1671 1672 static int 1673 tl_intvec_adchk(xsc, type) 1674 void *xsc; 1675 u_int32_t type; 1676 { 1677 struct tl_softc *sc; 1678 1679 sc = xsc; 1680 1681 if (type) 1682 if_printf(&sc->arpcom.ac_if, "adapter check: %x\n", 1683 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1684 1685 tl_softreset(sc, 1); 1686 tl_stop(sc); 1687 tl_init(sc); 1688 CMD_SET(sc, TL_CMD_INTSON); 1689 1690 return(0); 1691 } 1692 1693 static int 1694 tl_intvec_netsts(xsc, type) 1695 void *xsc; 1696 u_int32_t type; 1697 { 1698 struct tl_softc *sc; 1699 u_int16_t netsts; 1700 1701 sc = xsc; 1702 1703 netsts = tl_dio_read16(sc, TL_NETSTS); 1704 tl_dio_write16(sc, TL_NETSTS, netsts); 1705 1706 if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts); 1707 1708 return(1); 1709 } 1710 1711 static void 1712 tl_intr(xsc) 1713 void *xsc; 1714 { 1715 struct tl_softc *sc; 1716 struct ifnet *ifp; 1717 int r = 0; 1718 u_int32_t type = 0; 1719 u_int16_t ints = 0; 1720 u_int8_t ivec = 0; 1721 1722 sc = xsc; 1723 TL_LOCK(sc); 1724 1725 /* Disable interrupts */ 1726 ints = CSR_READ_2(sc, TL_HOST_INT); 1727 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1728 type = (ints << 16) & 0xFFFF0000; 1729 ivec = (ints & TL_VEC_MASK) >> 5; 1730 ints = (ints & TL_INT_MASK) >> 2; 1731 1732 ifp = &sc->arpcom.ac_if; 1733 1734 switch(ints) { 1735 case (TL_INTR_INVALID): 1736 #ifdef DIAGNOSTIC 1737 if_printf(ifp, "got an invalid interrupt!\n"); 1738 #endif 1739 /* Re-enable interrupts but don't ack this one. */ 1740 CMD_PUT(sc, type); 1741 r = 0; 1742 break; 1743 case (TL_INTR_TXEOF): 1744 r = tl_intvec_txeof((void *)sc, type); 1745 break; 1746 case (TL_INTR_TXEOC): 1747 r = tl_intvec_txeoc((void *)sc, type); 1748 break; 1749 case (TL_INTR_STATOFLOW): 1750 tl_stats_update(sc); 1751 r = 1; 1752 break; 1753 case (TL_INTR_RXEOF): 1754 r = tl_intvec_rxeof((void *)sc, type); 1755 break; 1756 case (TL_INTR_DUMMY): 1757 if_printf(ifp, "got a dummy interrupt\n"); 1758 r = 1; 1759 break; 1760 case (TL_INTR_ADCHK): 1761 if (ivec) 1762 r = tl_intvec_adchk((void *)sc, type); 1763 else 1764 r = tl_intvec_netsts((void *)sc, type); 1765 break; 1766 case (TL_INTR_RXEOC): 1767 r = tl_intvec_rxeoc((void *)sc, type); 1768 break; 1769 default: 1770 if_printf(ifp, "bogus interrupt type\n"); 1771 break; 1772 } 1773 1774 /* Re-enable interrupts */ 1775 if (r) { 1776 CMD_PUT(sc, TL_CMD_ACK | r | type); 1777 } 1778 1779 if (ifp->if_snd.ifq_head != NULL) 1780 tl_start(ifp); 1781 1782 TL_UNLOCK(sc); 1783 1784 return; 1785 } 1786 1787 static void 1788 tl_stats_update(xsc) 1789 void *xsc; 1790 { 1791 struct tl_softc *sc; 1792 struct ifnet *ifp; 1793 struct tl_stats tl_stats; 1794 struct mii_data *mii; 1795 u_int32_t *p; 1796 1797 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1798 1799 sc = xsc; 1800 TL_LOCK(sc); 1801 ifp = &sc->arpcom.ac_if; 1802 1803 p = (u_int32_t *)&tl_stats; 1804 1805 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1806 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1807 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1808 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1809 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1810 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1811 1812 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1813 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1814 tl_stats.tl_tx_multi_collision; 1815 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1816 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1817 tl_rx_overrun(tl_stats); 1818 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1819 1820 if (tl_tx_underrun(tl_stats)) { 1821 u_int8_t tx_thresh; 1822 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1823 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1824 tx_thresh >>= 4; 1825 tx_thresh++; 1826 if_printf(ifp, "tx underrun -- increasing " 1827 "tx threshold to %d bytes\n", 1828 (64 * (tx_thresh * 4))); 1829 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1830 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1831 } 1832 } 1833 1834 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 1835 1836 if (!sc->tl_bitrate) { 1837 mii = device_get_softc(sc->tl_miibus); 1838 mii_tick(mii); 1839 } 1840 1841 TL_UNLOCK(sc); 1842 1843 return; 1844 } 1845 1846 /* 1847 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1848 * pointers to the fragment pointers. 1849 */ 1850 static int 1851 tl_encap(sc, c, m_head) 1852 struct tl_softc *sc; 1853 struct tl_chain *c; 1854 struct mbuf *m_head; 1855 { 1856 int frag = 0; 1857 struct tl_frag *f = NULL; 1858 int total_len; 1859 struct mbuf *m; 1860 struct ifnet *ifp = &sc->arpcom.ac_if; 1861 1862 /* 1863 * Start packing the mbufs in this chain into 1864 * the fragment pointers. Stop when we run out 1865 * of fragments or hit the end of the mbuf chain. 1866 */ 1867 m = m_head; 1868 total_len = 0; 1869 1870 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1871 if (m->m_len != 0) { 1872 if (frag == TL_MAXFRAGS) 1873 break; 1874 total_len+= m->m_len; 1875 c->tl_ptr->tl_frag[frag].tlist_dadr = 1876 vtophys(mtod(m, vm_offset_t)); 1877 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1878 frag++; 1879 } 1880 } 1881 1882 /* 1883 * Handle special cases. 1884 * Special case #1: we used up all 10 fragments, but 1885 * we have more mbufs left in the chain. Copy the 1886 * data into an mbuf cluster. Note that we don't 1887 * bother clearing the values in the other fragment 1888 * pointers/counters; it wouldn't gain us anything, 1889 * and would waste cycles. 1890 */ 1891 if (m != NULL) { 1892 struct mbuf *m_new = NULL; 1893 1894 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1895 if (m_new == NULL) { 1896 if_printf(ifp, "no memory for tx list\n"); 1897 return(1); 1898 } 1899 if (m_head->m_pkthdr.len > MHLEN) { 1900 MCLGET(m_new, M_DONTWAIT); 1901 if (!(m_new->m_flags & M_EXT)) { 1902 m_freem(m_new); 1903 if_printf(ifp, "no memory for tx list\n"); 1904 return(1); 1905 } 1906 } 1907 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1908 mtod(m_new, caddr_t)); 1909 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1910 m_freem(m_head); 1911 m_head = m_new; 1912 f = &c->tl_ptr->tl_frag[0]; 1913 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1914 f->tlist_dcnt = total_len = m_new->m_len; 1915 frag = 1; 1916 } 1917 1918 /* 1919 * Special case #2: the frame is smaller than the minimum 1920 * frame size. We have to pad it to make the chip happy. 1921 */ 1922 if (total_len < TL_MIN_FRAMELEN) { 1923 if (frag == TL_MAXFRAGS) 1924 if_printf(ifp, 1925 "all frags filled but frame still to small!\n"); 1926 f = &c->tl_ptr->tl_frag[frag]; 1927 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1928 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1929 total_len += f->tlist_dcnt; 1930 frag++; 1931 } 1932 1933 c->tl_mbuf = m_head; 1934 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1935 c->tl_ptr->tlist_frsize = total_len; 1936 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1937 c->tl_ptr->tlist_fptr = 0; 1938 1939 return(0); 1940 } 1941 1942 /* 1943 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1944 * to the mbuf data regions directly in the transmit lists. We also save a 1945 * copy of the pointers since the transmit list fragment pointers are 1946 * physical addresses. 1947 */ 1948 static void 1949 tl_start(ifp) 1950 struct ifnet *ifp; 1951 { 1952 struct tl_softc *sc; 1953 struct mbuf *m_head = NULL; 1954 u_int32_t cmd; 1955 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1956 1957 sc = ifp->if_softc; 1958 TL_LOCK(sc); 1959 1960 /* 1961 * Check for an available queue slot. If there are none, 1962 * punt. 1963 */ 1964 if (sc->tl_cdata.tl_tx_free == NULL) { 1965 ifp->if_flags |= IFF_OACTIVE; 1966 TL_UNLOCK(sc); 1967 return; 1968 } 1969 1970 start_tx = sc->tl_cdata.tl_tx_free; 1971 1972 while(sc->tl_cdata.tl_tx_free != NULL) { 1973 IF_DEQUEUE(&ifp->if_snd, m_head); 1974 if (m_head == NULL) 1975 break; 1976 1977 /* Pick a chain member off the free list. */ 1978 cur_tx = sc->tl_cdata.tl_tx_free; 1979 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1980 1981 cur_tx->tl_next = NULL; 1982 1983 /* Pack the data into the list. */ 1984 tl_encap(sc, cur_tx, m_head); 1985 1986 /* Chain it together */ 1987 if (prev != NULL) { 1988 prev->tl_next = cur_tx; 1989 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 1990 } 1991 prev = cur_tx; 1992 1993 /* 1994 * If there's a BPF listener, bounce a copy of this frame 1995 * to him. 1996 */ 1997 BPF_MTAP(ifp, cur_tx->tl_mbuf); 1998 } 1999 2000 /* 2001 * If there are no packets queued, bail. 2002 */ 2003 if (cur_tx == NULL) { 2004 TL_UNLOCK(sc); 2005 return; 2006 } 2007 2008 /* 2009 * That's all we can stands, we can't stands no more. 2010 * If there are no other transfers pending, then issue the 2011 * TX GO command to the adapter to start things moving. 2012 * Otherwise, just leave the data in the queue and let 2013 * the EOF/EOC interrupt handler send. 2014 */ 2015 if (sc->tl_cdata.tl_tx_head == NULL) { 2016 sc->tl_cdata.tl_tx_head = start_tx; 2017 sc->tl_cdata.tl_tx_tail = cur_tx; 2018 2019 if (sc->tl_txeoc) { 2020 sc->tl_txeoc = 0; 2021 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 2022 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2023 cmd &= ~TL_CMD_RT; 2024 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2025 CMD_PUT(sc, cmd); 2026 } 2027 } else { 2028 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2029 sc->tl_cdata.tl_tx_tail = cur_tx; 2030 } 2031 2032 /* 2033 * Set a timeout in case the chip goes out to lunch. 2034 */ 2035 ifp->if_timer = 5; 2036 TL_UNLOCK(sc); 2037 2038 return; 2039 } 2040 2041 static void 2042 tl_init(xsc) 2043 void *xsc; 2044 { 2045 struct tl_softc *sc = xsc; 2046 struct ifnet *ifp = &sc->arpcom.ac_if; 2047 struct mii_data *mii; 2048 2049 TL_LOCK(sc); 2050 2051 ifp = &sc->arpcom.ac_if; 2052 2053 /* 2054 * Cancel pending I/O. 2055 */ 2056 tl_stop(sc); 2057 2058 /* Initialize TX FIFO threshold */ 2059 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 2060 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 2061 2062 /* Set PCI burst size */ 2063 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 2064 2065 /* 2066 * Set 'capture all frames' bit for promiscuous mode. 2067 */ 2068 if (ifp->if_flags & IFF_PROMISC) 2069 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2070 else 2071 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2072 2073 /* 2074 * Set capture broadcast bit to capture broadcast frames. 2075 */ 2076 if (ifp->if_flags & IFF_BROADCAST) 2077 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2078 else 2079 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2080 2081 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2082 2083 /* Init our MAC address */ 2084 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 2085 2086 /* Init multicast filter, if needed. */ 2087 tl_setmulti(sc); 2088 2089 /* Init circular RX list. */ 2090 if (tl_list_rx_init(sc) == ENOBUFS) { 2091 if_printf(ifp, 2092 "initialization failed: no memory for rx buffers\n"); 2093 tl_stop(sc); 2094 TL_UNLOCK(sc); 2095 return; 2096 } 2097 2098 /* Init TX pointers. */ 2099 tl_list_tx_init(sc); 2100 2101 /* Enable PCI interrupts. */ 2102 CMD_SET(sc, TL_CMD_INTSON); 2103 2104 /* Load the address of the rx list */ 2105 CMD_SET(sc, TL_CMD_RT); 2106 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2107 2108 if (!sc->tl_bitrate) { 2109 if (sc->tl_miibus != NULL) { 2110 mii = device_get_softc(sc->tl_miibus); 2111 mii_mediachg(mii); 2112 } 2113 } else { 2114 tl_ifmedia_upd(ifp); 2115 } 2116 2117 /* Send the RX go command */ 2118 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2119 2120 ifp->if_flags |= IFF_RUNNING; 2121 ifp->if_flags &= ~IFF_OACTIVE; 2122 2123 /* Start the stats update counter */ 2124 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2125 TL_UNLOCK(sc); 2126 2127 return; 2128 } 2129 2130 /* 2131 * Set media options. 2132 */ 2133 static int 2134 tl_ifmedia_upd(ifp) 2135 struct ifnet *ifp; 2136 { 2137 struct tl_softc *sc; 2138 struct mii_data *mii = NULL; 2139 2140 sc = ifp->if_softc; 2141 2142 if (sc->tl_bitrate) 2143 tl_setmode(sc, sc->ifmedia.ifm_media); 2144 else { 2145 mii = device_get_softc(sc->tl_miibus); 2146 mii_mediachg(mii); 2147 } 2148 2149 return(0); 2150 } 2151 2152 /* 2153 * Report current media status. 2154 */ 2155 static void 2156 tl_ifmedia_sts(ifp, ifmr) 2157 struct ifnet *ifp; 2158 struct ifmediareq *ifmr; 2159 { 2160 struct tl_softc *sc; 2161 struct mii_data *mii; 2162 2163 sc = ifp->if_softc; 2164 2165 ifmr->ifm_active = IFM_ETHER; 2166 2167 if (sc->tl_bitrate) { 2168 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2169 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2170 else 2171 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2172 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2173 ifmr->ifm_active |= IFM_HDX; 2174 else 2175 ifmr->ifm_active |= IFM_FDX; 2176 return; 2177 } else { 2178 mii = device_get_softc(sc->tl_miibus); 2179 mii_pollstat(mii); 2180 ifmr->ifm_active = mii->mii_media_active; 2181 ifmr->ifm_status = mii->mii_media_status; 2182 } 2183 2184 return; 2185 } 2186 2187 static int 2188 tl_ioctl(ifp, command, data) 2189 struct ifnet *ifp; 2190 u_long command; 2191 caddr_t data; 2192 { 2193 struct tl_softc *sc = ifp->if_softc; 2194 struct ifreq *ifr = (struct ifreq *) data; 2195 int s, error = 0; 2196 2197 s = splimp(); 2198 2199 switch(command) { 2200 case SIOCSIFFLAGS: 2201 if (ifp->if_flags & IFF_UP) { 2202 if (ifp->if_flags & IFF_RUNNING && 2203 ifp->if_flags & IFF_PROMISC && 2204 !(sc->tl_if_flags & IFF_PROMISC)) { 2205 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2206 tl_setmulti(sc); 2207 } else if (ifp->if_flags & IFF_RUNNING && 2208 !(ifp->if_flags & IFF_PROMISC) && 2209 sc->tl_if_flags & IFF_PROMISC) { 2210 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2211 tl_setmulti(sc); 2212 } else 2213 tl_init(sc); 2214 } else { 2215 if (ifp->if_flags & IFF_RUNNING) { 2216 tl_stop(sc); 2217 } 2218 } 2219 sc->tl_if_flags = ifp->if_flags; 2220 error = 0; 2221 break; 2222 case SIOCADDMULTI: 2223 case SIOCDELMULTI: 2224 tl_setmulti(sc); 2225 error = 0; 2226 break; 2227 case SIOCSIFMEDIA: 2228 case SIOCGIFMEDIA: 2229 if (sc->tl_bitrate) 2230 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2231 else { 2232 struct mii_data *mii; 2233 mii = device_get_softc(sc->tl_miibus); 2234 error = ifmedia_ioctl(ifp, ifr, 2235 &mii->mii_media, command); 2236 } 2237 break; 2238 default: 2239 error = ether_ioctl(ifp, command, data); 2240 break; 2241 } 2242 2243 (void)splx(s); 2244 2245 return(error); 2246 } 2247 2248 static void 2249 tl_watchdog(ifp) 2250 struct ifnet *ifp; 2251 { 2252 struct tl_softc *sc; 2253 2254 sc = ifp->if_softc; 2255 2256 if_printf(ifp, "device timeout\n"); 2257 2258 ifp->if_oerrors++; 2259 2260 tl_softreset(sc, 1); 2261 tl_init(sc); 2262 2263 return; 2264 } 2265 2266 /* 2267 * Stop the adapter and free any mbufs allocated to the 2268 * RX and TX lists. 2269 */ 2270 static void 2271 tl_stop(sc) 2272 struct tl_softc *sc; 2273 { 2274 register int i; 2275 struct ifnet *ifp; 2276 2277 TL_LOCK(sc); 2278 2279 ifp = &sc->arpcom.ac_if; 2280 2281 /* Stop the stats updater. */ 2282 untimeout(tl_stats_update, sc, sc->tl_stat_ch); 2283 2284 /* Stop the transmitter */ 2285 CMD_CLR(sc, TL_CMD_RT); 2286 CMD_SET(sc, TL_CMD_STOP); 2287 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2288 2289 /* Stop the receiver */ 2290 CMD_SET(sc, TL_CMD_RT); 2291 CMD_SET(sc, TL_CMD_STOP); 2292 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2293 2294 /* 2295 * Disable host interrupts. 2296 */ 2297 CMD_SET(sc, TL_CMD_INTSOFF); 2298 2299 /* 2300 * Clear list pointer. 2301 */ 2302 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2303 2304 /* 2305 * Free the RX lists. 2306 */ 2307 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2308 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2309 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2310 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2311 } 2312 } 2313 bzero((char *)&sc->tl_ldata->tl_rx_list, 2314 sizeof(sc->tl_ldata->tl_rx_list)); 2315 2316 /* 2317 * Free the TX list buffers. 2318 */ 2319 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2320 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2321 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2322 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2323 } 2324 } 2325 bzero((char *)&sc->tl_ldata->tl_tx_list, 2326 sizeof(sc->tl_ldata->tl_tx_list)); 2327 2328 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2329 TL_UNLOCK(sc); 2330 2331 return; 2332 } 2333 2334 /* 2335 * Stop all chip I/O so that the kernel's probe routines don't 2336 * get confused by errant DMAs when rebooting. 2337 */ 2338 static void 2339 tl_shutdown(dev) 2340 device_t dev; 2341 { 2342 struct tl_softc *sc; 2343 2344 sc = device_get_softc(dev); 2345 2346 tl_stop(sc); 2347 2348 return; 2349 }
Cache object: 67c488c779fb0734bf568fe0cad1be56
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