The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_tl.c

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    1 /*-
    2  * Copyright (c) 1997, 1998
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: src/sys/pci/if_tl.c,v 1.93.2.4 2006/01/29 15:39:09 emaste Exp $");
   35 
   36 /*
   37  * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
   38  * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
   39  * the National Semiconductor DP83840A physical interface and the
   40  * Microchip Technology 24Cxx series serial EEPROM.
   41  *
   42  * Written using the following four documents:
   43  *
   44  * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
   45  * National Semiconductor DP83840A data sheet (www.national.com)
   46  * Microchip Technology 24C02C data sheet (www.microchip.com)
   47  * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
   48  * 
   49  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   50  * Electrical Engineering Department
   51  * Columbia University, New York City
   52  */
   53 /*
   54  * Some notes about the ThunderLAN:
   55  *
   56  * The ThunderLAN controller is a single chip containing PCI controller
   57  * logic, approximately 3K of on-board SRAM, a LAN controller, and media
   58  * independent interface (MII) bus. The MII allows the ThunderLAN chip to
   59  * control up to 32 different physical interfaces (PHYs). The ThunderLAN
   60  * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
   61  * to act as a complete ethernet interface.
   62  *
   63  * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
   64  * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
   65  * in full or half duplex. Some of the Compaq Deskpro machines use a
   66  * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
   67  * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
   68  * concert with the ThunderLAN's internal PHY to provide full 10/100
   69  * support. This is cheaper than using a standalone external PHY for both
   70  * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
   71  * A serial EEPROM is also attached to the ThunderLAN chip to provide
   72  * power-up default register settings and for storing the adapter's
   73  * station address. Although not supported by this driver, the ThunderLAN
   74  * chip can also be connected to token ring PHYs.
   75  *
   76  * The ThunderLAN has a set of registers which can be used to issue
   77  * commands, acknowledge interrupts, and to manipulate other internal
   78  * registers on its DIO bus. The primary registers can be accessed
   79  * using either programmed I/O (inb/outb) or via PCI memory mapping,
   80  * depending on how the card is configured during the PCI probing
   81  * phase. It is even possible to have both PIO and memory mapped
   82  * access turned on at the same time.
   83  * 
   84  * Frame reception and transmission with the ThunderLAN chip is done
   85  * using frame 'lists.' A list structure looks more or less like this:
   86  *
   87  * struct tl_frag {
   88  *      u_int32_t               fragment_address;
   89  *      u_int32_t               fragment_size;
   90  * };
   91  * struct tl_list {
   92  *      u_int32_t               forward_pointer;
   93  *      u_int16_t               cstat;
   94  *      u_int16_t               frame_size;
   95  *      struct tl_frag          fragments[10];
   96  * };
   97  *
   98  * The forward pointer in the list header can be either a 0 or the address
   99  * of another list, which allows several lists to be linked together. Each
  100  * list contains up to 10 fragment descriptors. This means the chip allows
  101  * ethernet frames to be broken up into up to 10 chunks for transfer to
  102  * and from the SRAM. Note that the forward pointer and fragment buffer
  103  * addresses are physical memory addresses, not virtual. Note also that
  104  * a single ethernet frame can not span lists: if the host wants to
  105  * transmit a frame and the frame data is split up over more than 10
  106  * buffers, the frame has to collapsed before it can be transmitted.
  107  *
  108  * To receive frames, the driver sets up a number of lists and populates
  109  * the fragment descriptors, then it sends an RX GO command to the chip.
  110  * When a frame is received, the chip will DMA it into the memory regions
  111  * specified by the fragment descriptors and then trigger an RX 'end of
  112  * frame interrupt' when done. The driver may choose to use only one
  113  * fragment per list; this may result is slighltly less efficient use
  114  * of memory in exchange for improving performance.
  115  *
  116  * To transmit frames, the driver again sets up lists and fragment
  117  * descriptors, only this time the buffers contain frame data that
  118  * is to be DMA'ed into the chip instead of out of it. Once the chip
  119  * has transfered the data into its on-board SRAM, it will trigger a
  120  * TX 'end of frame' interrupt. It will also generate an 'end of channel'
  121  * interrupt when it reaches the end of the list.
  122  */
  123 /*
  124  * Some notes about this driver:
  125  *
  126  * The ThunderLAN chip provides a couple of different ways to organize
  127  * reception, transmission and interrupt handling. The simplest approach
  128  * is to use one list each for transmission and reception. In this mode,
  129  * the ThunderLAN will generate two interrupts for every received frame
  130  * (one RX EOF and one RX EOC) and two for each transmitted frame (one
  131  * TX EOF and one TX EOC). This may make the driver simpler but it hurts
  132  * performance to have to handle so many interrupts.
  133  *
  134  * Initially I wanted to create a circular list of receive buffers so
  135  * that the ThunderLAN chip would think there was an infinitely long
  136  * receive channel and never deliver an RXEOC interrupt. However this
  137  * doesn't work correctly under heavy load: while the manual says the
  138  * chip will trigger an RXEOF interrupt each time a frame is copied into
  139  * memory, you can't count on the chip waiting around for you to acknowledge
  140  * the interrupt before it starts trying to DMA the next frame. The result
  141  * is that the chip might traverse the entire circular list and then wrap
  142  * around before you have a chance to do anything about it. Consequently,
  143  * the receive list is terminated (with a 0 in the forward pointer in the
  144  * last element). Each time an RXEOF interrupt arrives, the used list
  145  * is shifted to the end of the list. This gives the appearance of an
  146  * infinitely large RX chain so long as the driver doesn't fall behind
  147  * the chip and allow all of the lists to be filled up.
  148  *
  149  * If all the lists are filled, the adapter will deliver an RX 'end of
  150  * channel' interrupt when it hits the 0 forward pointer at the end of
  151  * the chain. The RXEOC handler then cleans out the RX chain and resets
  152  * the list head pointer in the ch_parm register and restarts the receiver.
  153  *
  154  * For frame transmission, it is possible to program the ThunderLAN's
  155  * transmit interrupt threshold so that the chip can acknowledge multiple
  156  * lists with only a single TX EOF interrupt. This allows the driver to
  157  * queue several frames in one shot, and only have to handle a total
  158  * two interrupts (one TX EOF and one TX EOC) no matter how many frames
  159  * are transmitted. Frame transmission is done directly out of the
  160  * mbufs passed to the tl_start() routine via the interface send queue.
  161  * The driver simply sets up the fragment descriptors in the transmit
  162  * lists to point to the mbuf data regions and sends a TX GO command.
  163  *
  164  * Note that since the RX and TX lists themselves are always used
  165  * only by the driver, the are malloc()ed once at driver initialization
  166  * time and never free()ed.
  167  *
  168  * Also, in order to remain as platform independent as possible, this
  169  * driver uses memory mapped register access to manipulate the card
  170  * as opposed to programmed I/O. This avoids the use of the inb/outb
  171  * (and related) instructions which are specific to the i386 platform.
  172  *
  173  * Using these techniques, this driver achieves very high performance
  174  * by minimizing the amount of interrupts generated during large
  175  * transfers and by completely avoiding buffer copies. Frame transfer
  176  * to and from the ThunderLAN chip is performed entirely by the chip
  177  * itself thereby reducing the load on the host CPU.
  178  */
  179 
  180 #include <sys/param.h>
  181 #include <sys/systm.h>
  182 #include <sys/sockio.h>
  183 #include <sys/mbuf.h>
  184 #include <sys/malloc.h>
  185 #include <sys/kernel.h>
  186 #include <sys/module.h>
  187 #include <sys/socket.h>
  188 
  189 #include <net/if.h>
  190 #include <net/if_arp.h>
  191 #include <net/ethernet.h>
  192 #include <net/if_dl.h>
  193 #include <net/if_media.h>
  194 
  195 #include <net/bpf.h>
  196 
  197 #include <vm/vm.h>              /* for vtophys */
  198 #include <vm/pmap.h>            /* for vtophys */
  199 #include <machine/bus_memio.h>
  200 #include <machine/bus_pio.h>
  201 #include <machine/bus.h>
  202 #include <machine/resource.h>
  203 #include <sys/bus.h>
  204 #include <sys/rman.h>
  205 
  206 #include <dev/mii/mii.h>
  207 #include <dev/mii/miivar.h>
  208 
  209 #include <dev/pci/pcireg.h>
  210 #include <dev/pci/pcivar.h>
  211 
  212 /*
  213  * Default to using PIO register access mode to pacify certain
  214  * laptop docking stations with built-in ThunderLAN chips that
  215  * don't seem to handle memory mapped mode properly.
  216  */
  217 #define TL_USEIOSPACE
  218 
  219 #include <pci/if_tlreg.h>
  220 
  221 MODULE_DEPEND(tl, pci, 1, 1, 1);
  222 MODULE_DEPEND(tl, ether, 1, 1, 1);
  223 MODULE_DEPEND(tl, miibus, 1, 1, 1);
  224 
  225 /* "controller miibus0" required.  See GENERIC if you get errors here. */
  226 #include "miibus_if.h"
  227 
  228 /*
  229  * Various supported device vendors/types and their names.
  230  */
  231 
  232 static struct tl_type tl_devs[] = {
  233         { TI_VENDORID,  TI_DEVICEID_THUNDERLAN,
  234                 "Texas Instruments ThunderLAN" },
  235         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
  236                 "Compaq Netelligent 10" },
  237         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
  238                 "Compaq Netelligent 10/100" },
  239         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
  240                 "Compaq Netelligent 10/100 Proliant" },
  241         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
  242                 "Compaq Netelligent 10/100 Dual Port" },
  243         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
  244                 "Compaq NetFlex-3/P Integrated" },
  245         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
  246                 "Compaq NetFlex-3/P" },
  247         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
  248                 "Compaq NetFlex 3/P w/ BNC" },
  249         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
  250                 "Compaq Netelligent 10/100 TX Embedded UTP" },
  251         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
  252                 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
  253         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
  254                 "Compaq Netelligent 10/100 TX UTP" },
  255         { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
  256                 "Olicom OC-2183/2185" },
  257         { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
  258                 "Olicom OC-2325" },
  259         { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
  260                 "Olicom OC-2326 10/100 TX UTP" },
  261         { 0, 0, NULL }
  262 };
  263 
  264 static int tl_probe(device_t);
  265 static int tl_attach(device_t);
  266 static int tl_detach(device_t);
  267 static int tl_intvec_rxeoc(void *, u_int32_t);
  268 static int tl_intvec_txeoc(void *, u_int32_t);
  269 static int tl_intvec_txeof(void *, u_int32_t);
  270 static int tl_intvec_rxeof(void *, u_int32_t);
  271 static int tl_intvec_adchk(void *, u_int32_t);
  272 static int tl_intvec_netsts(void *, u_int32_t);
  273 
  274 static int tl_newbuf(struct tl_softc *, struct tl_chain_onefrag *);
  275 static void tl_stats_update(void *);
  276 static int tl_encap(struct tl_softc *, struct tl_chain *, struct mbuf *);
  277 
  278 static void tl_intr(void *);
  279 static void tl_start(struct ifnet *);
  280 static int tl_ioctl(struct ifnet *, u_long, caddr_t);
  281 static void tl_init(void *);
  282 static void tl_stop(struct tl_softc *);
  283 static void tl_watchdog(struct ifnet *);
  284 static void tl_shutdown(device_t);
  285 static int tl_ifmedia_upd(struct ifnet *);
  286 static void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  287 
  288 static u_int8_t tl_eeprom_putbyte(struct tl_softc *, int);
  289 static u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *);
  290 static int tl_read_eeprom(struct tl_softc *, caddr_t, int, int);
  291 
  292 static void tl_mii_sync(struct tl_softc *);
  293 static void tl_mii_send(struct tl_softc *, u_int32_t, int);
  294 static int tl_mii_readreg(struct tl_softc *, struct tl_mii_frame *);
  295 static int tl_mii_writereg(struct tl_softc *, struct tl_mii_frame *);
  296 static int tl_miibus_readreg(device_t, int, int);
  297 static int tl_miibus_writereg(device_t, int, int, int);
  298 static void tl_miibus_statchg(device_t);
  299 
  300 static void tl_setmode(struct tl_softc *, int);
  301 static uint32_t tl_mchash(const uint8_t *);
  302 static void tl_setmulti(struct tl_softc *);
  303 static void tl_setfilt(struct tl_softc *, caddr_t, int);
  304 static void tl_softreset(struct tl_softc *, int);
  305 static void tl_hardreset(device_t);
  306 static int tl_list_rx_init(struct tl_softc *);
  307 static int tl_list_tx_init(struct tl_softc *);
  308 
  309 static u_int8_t tl_dio_read8(struct tl_softc *, int);
  310 static u_int16_t tl_dio_read16(struct tl_softc *, int);
  311 static u_int32_t tl_dio_read32(struct tl_softc *, int);
  312 static void tl_dio_write8(struct tl_softc *, int, int);
  313 static void tl_dio_write16(struct tl_softc *, int, int);
  314 static void tl_dio_write32(struct tl_softc *, int, int);
  315 static void tl_dio_setbit(struct tl_softc *, int, int);
  316 static void tl_dio_clrbit(struct tl_softc *, int, int);
  317 static void tl_dio_setbit16(struct tl_softc *, int, int);
  318 static void tl_dio_clrbit16(struct tl_softc *, int, int);
  319 
  320 #ifdef TL_USEIOSPACE
  321 #define TL_RES          SYS_RES_IOPORT
  322 #define TL_RID          TL_PCI_LOIO
  323 #else
  324 #define TL_RES          SYS_RES_MEMORY
  325 #define TL_RID          TL_PCI_LOMEM
  326 #endif
  327 
  328 static device_method_t tl_methods[] = {
  329         /* Device interface */
  330         DEVMETHOD(device_probe,         tl_probe),
  331         DEVMETHOD(device_attach,        tl_attach),
  332         DEVMETHOD(device_detach,        tl_detach),
  333         DEVMETHOD(device_shutdown,      tl_shutdown),
  334 
  335         /* bus interface */
  336         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  337         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  338 
  339         /* MII interface */
  340         DEVMETHOD(miibus_readreg,       tl_miibus_readreg),
  341         DEVMETHOD(miibus_writereg,      tl_miibus_writereg),
  342         DEVMETHOD(miibus_statchg,       tl_miibus_statchg),
  343 
  344         { 0, 0 }
  345 };
  346 
  347 static driver_t tl_driver = {
  348         "tl",
  349         tl_methods,
  350         sizeof(struct tl_softc)
  351 };
  352 
  353 static devclass_t tl_devclass;
  354 
  355 DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0);
  356 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
  357 
  358 static u_int8_t tl_dio_read8(sc, reg)
  359         struct tl_softc         *sc;
  360         int                     reg;
  361 {
  362         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  363         return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
  364 }
  365 
  366 static u_int16_t tl_dio_read16(sc, reg)
  367         struct tl_softc         *sc;
  368         int                     reg;
  369 {
  370         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  371         return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
  372 }
  373 
  374 static u_int32_t tl_dio_read32(sc, reg)
  375         struct tl_softc         *sc;
  376         int                     reg;
  377 {
  378         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  379         return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
  380 }
  381 
  382 static void tl_dio_write8(sc, reg, val)
  383         struct tl_softc         *sc;
  384         int                     reg;
  385         int                     val;
  386 {
  387         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  388         CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
  389         return;
  390 }
  391 
  392 static void tl_dio_write16(sc, reg, val)
  393         struct tl_softc         *sc;
  394         int                     reg;
  395         int                     val;
  396 {
  397         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  398         CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
  399         return;
  400 }
  401 
  402 static void tl_dio_write32(sc, reg, val)
  403         struct tl_softc         *sc;
  404         int                     reg;
  405         int                     val;
  406 {
  407         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  408         CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
  409         return;
  410 }
  411 
  412 static void
  413 tl_dio_setbit(sc, reg, bit)
  414         struct tl_softc         *sc;
  415         int                     reg;
  416         int                     bit;
  417 {
  418         u_int8_t                        f;
  419 
  420         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  421         f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
  422         f |= bit;
  423         CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
  424 
  425         return;
  426 }
  427 
  428 static void
  429 tl_dio_clrbit(sc, reg, bit)
  430         struct tl_softc         *sc;
  431         int                     reg;
  432         int                     bit;
  433 {
  434         u_int8_t                        f;
  435 
  436         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  437         f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
  438         f &= ~bit;
  439         CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
  440 
  441         return;
  442 }
  443 
  444 static void tl_dio_setbit16(sc, reg, bit)
  445         struct tl_softc         *sc;
  446         int                     reg;
  447         int                     bit;
  448 {
  449         u_int16_t                       f;
  450 
  451         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  452         f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
  453         f |= bit;
  454         CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
  455 
  456         return;
  457 }
  458 
  459 static void tl_dio_clrbit16(sc, reg, bit)
  460         struct tl_softc         *sc;
  461         int                     reg;
  462         int                     bit;
  463 {
  464         u_int16_t                       f;
  465 
  466         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  467         f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
  468         f &= ~bit;
  469         CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
  470 
  471         return;
  472 }
  473 
  474 /*
  475  * Send an instruction or address to the EEPROM, check for ACK.
  476  */
  477 static u_int8_t tl_eeprom_putbyte(sc, byte)
  478         struct tl_softc         *sc;
  479         int                     byte;
  480 {
  481         register int            i, ack = 0;
  482 
  483         /*
  484          * Make sure we're in TX mode.
  485          */
  486         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
  487 
  488         /*
  489          * Feed in each bit and stobe the clock.
  490          */
  491         for (i = 0x80; i; i >>= 1) {
  492                 if (byte & i) {
  493                         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
  494                 } else {
  495                         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
  496                 }
  497                 DELAY(1);
  498                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  499                 DELAY(1);
  500                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  501         }
  502 
  503         /*
  504          * Turn off TX mode.
  505          */
  506         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
  507 
  508         /*
  509          * Check for ack.
  510          */
  511         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  512         ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
  513         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  514 
  515         return(ack);
  516 }
  517 
  518 /*
  519  * Read a byte of data stored in the EEPROM at address 'addr.'
  520  */
  521 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
  522         struct tl_softc         *sc;
  523         int                     addr;
  524         u_int8_t                *dest;
  525 {
  526         register int            i;
  527         u_int8_t                byte = 0;
  528         struct ifnet            *ifp = &sc->arpcom.ac_if;
  529 
  530         tl_dio_write8(sc, TL_NETSIO, 0);
  531 
  532         EEPROM_START;
  533 
  534         /*
  535          * Send write control code to EEPROM.
  536          */
  537         if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
  538                 if_printf(ifp, "failed to send write command, status: %x\n",
  539                     tl_dio_read8(sc, TL_NETSIO));
  540                 return(1);
  541         }
  542 
  543         /*
  544          * Send address of byte we want to read.
  545          */
  546         if (tl_eeprom_putbyte(sc, addr)) {
  547                 if_printf(ifp, "failed to send address, status: %x\n",
  548                     tl_dio_read8(sc, TL_NETSIO));
  549                 return(1);
  550         }
  551 
  552         EEPROM_STOP;
  553         EEPROM_START;
  554         /*
  555          * Send read control code to EEPROM.
  556          */
  557         if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
  558                 if_printf(ifp, "failed to send write command, status: %x\n",
  559                     tl_dio_read8(sc, TL_NETSIO));
  560                 return(1);
  561         }
  562 
  563         /*
  564          * Start reading bits from EEPROM.
  565          */
  566         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
  567         for (i = 0x80; i; i >>= 1) {
  568                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  569                 DELAY(1);
  570                 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
  571                         byte |= i;
  572                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  573                 DELAY(1);
  574         }
  575 
  576         EEPROM_STOP;
  577 
  578         /*
  579          * No ACK generated for read, so just return byte.
  580          */
  581 
  582         *dest = byte;
  583 
  584         return(0);
  585 }
  586 
  587 /*
  588  * Read a sequence of bytes from the EEPROM.
  589  */
  590 static int
  591 tl_read_eeprom(sc, dest, off, cnt)
  592         struct tl_softc         *sc;
  593         caddr_t                 dest;
  594         int                     off;
  595         int                     cnt;
  596 {
  597         int                     err = 0, i;
  598         u_int8_t                byte = 0;
  599 
  600         for (i = 0; i < cnt; i++) {
  601                 err = tl_eeprom_getbyte(sc, off + i, &byte);
  602                 if (err)
  603                         break;
  604                 *(dest + i) = byte;
  605         }
  606 
  607         return(err ? 1 : 0);
  608 }
  609 
  610 static void
  611 tl_mii_sync(sc)
  612         struct tl_softc         *sc;
  613 {
  614         register int            i;
  615 
  616         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  617 
  618         for (i = 0; i < 32; i++) {
  619                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  620                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  621         }
  622 
  623         return;
  624 }
  625 
  626 static void
  627 tl_mii_send(sc, bits, cnt)
  628         struct tl_softc         *sc;
  629         u_int32_t               bits;
  630         int                     cnt;
  631 {
  632         int                     i;
  633 
  634         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  635                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  636                 if (bits & i) {
  637                         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
  638                 } else {
  639                         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
  640                 }
  641                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  642         }
  643 }
  644 
  645 static int
  646 tl_mii_readreg(sc, frame)
  647         struct tl_softc         *sc;
  648         struct tl_mii_frame     *frame;
  649         
  650 {
  651         int                     i, ack;
  652         int                     minten = 0;
  653 
  654         TL_LOCK(sc);
  655 
  656         tl_mii_sync(sc);
  657 
  658         /*
  659          * Set up frame for RX.
  660          */
  661         frame->mii_stdelim = TL_MII_STARTDELIM;
  662         frame->mii_opcode = TL_MII_READOP;
  663         frame->mii_turnaround = 0;
  664         frame->mii_data = 0;
  665         
  666         /*
  667          * Turn off MII interrupt by forcing MINTEN low.
  668          */
  669         minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
  670         if (minten) {
  671                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  672         }
  673 
  674         /*
  675          * Turn on data xmit.
  676          */
  677         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  678 
  679         /*
  680          * Send command/address info.
  681          */
  682         tl_mii_send(sc, frame->mii_stdelim, 2);
  683         tl_mii_send(sc, frame->mii_opcode, 2);
  684         tl_mii_send(sc, frame->mii_phyaddr, 5);
  685         tl_mii_send(sc, frame->mii_regaddr, 5);
  686 
  687         /*
  688          * Turn off xmit.
  689          */
  690         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  691 
  692         /* Idle bit */
  693         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  694         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  695 
  696         /* Check for ack */
  697         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  698         ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
  699 
  700         /* Complete the cycle */
  701         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  702 
  703         /*
  704          * Now try reading data bits. If the ack failed, we still
  705          * need to clock through 16 cycles to keep the PHYs in sync.
  706          */
  707         if (ack) {
  708                 for(i = 0; i < 16; i++) {
  709                         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  710                         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  711                 }
  712                 goto fail;
  713         }
  714 
  715         for (i = 0x8000; i; i >>= 1) {
  716                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  717                 if (!ack) {
  718                         if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
  719                                 frame->mii_data |= i;
  720                 }
  721                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  722         }
  723 
  724 fail:
  725 
  726         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  727         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  728 
  729         /* Reenable interrupts */
  730         if (minten) {
  731                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  732         }
  733 
  734         TL_UNLOCK(sc);
  735 
  736         if (ack)
  737                 return(1);
  738         return(0);
  739 }
  740 
  741 static int
  742 tl_mii_writereg(sc, frame)
  743         struct tl_softc         *sc;
  744         struct tl_mii_frame     *frame;
  745         
  746 {
  747         int                     minten;
  748 
  749         TL_LOCK(sc);
  750 
  751         tl_mii_sync(sc);
  752 
  753         /*
  754          * Set up frame for TX.
  755          */
  756 
  757         frame->mii_stdelim = TL_MII_STARTDELIM;
  758         frame->mii_opcode = TL_MII_WRITEOP;
  759         frame->mii_turnaround = TL_MII_TURNAROUND;
  760         
  761         /*
  762          * Turn off MII interrupt by forcing MINTEN low.
  763          */
  764         minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
  765         if (minten) {
  766                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  767         }
  768 
  769         /*
  770          * Turn on data output.
  771          */
  772         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  773 
  774         tl_mii_send(sc, frame->mii_stdelim, 2);
  775         tl_mii_send(sc, frame->mii_opcode, 2);
  776         tl_mii_send(sc, frame->mii_phyaddr, 5);
  777         tl_mii_send(sc, frame->mii_regaddr, 5);
  778         tl_mii_send(sc, frame->mii_turnaround, 2);
  779         tl_mii_send(sc, frame->mii_data, 16);
  780 
  781         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  782         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  783 
  784         /*
  785          * Turn off xmit.
  786          */
  787         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  788 
  789         /* Reenable interrupts */
  790         if (minten)
  791                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  792 
  793         TL_UNLOCK(sc);
  794 
  795         return(0);
  796 }
  797 
  798 static int
  799 tl_miibus_readreg(dev, phy, reg)
  800         device_t                dev;
  801         int                     phy, reg;
  802 {
  803         struct tl_softc         *sc;
  804         struct tl_mii_frame     frame;
  805 
  806         sc = device_get_softc(dev);
  807         bzero((char *)&frame, sizeof(frame));
  808 
  809         frame.mii_phyaddr = phy;
  810         frame.mii_regaddr = reg;
  811         tl_mii_readreg(sc, &frame);
  812 
  813         return(frame.mii_data);
  814 }
  815 
  816 static int
  817 tl_miibus_writereg(dev, phy, reg, data)
  818         device_t                dev;
  819         int                     phy, reg, data;
  820 {
  821         struct tl_softc         *sc;
  822         struct tl_mii_frame     frame;
  823 
  824         sc = device_get_softc(dev);
  825         bzero((char *)&frame, sizeof(frame));
  826 
  827         frame.mii_phyaddr = phy;
  828         frame.mii_regaddr = reg;
  829         frame.mii_data = data;
  830 
  831         tl_mii_writereg(sc, &frame);
  832 
  833         return(0);
  834 }
  835 
  836 static void
  837 tl_miibus_statchg(dev)
  838         device_t                dev;
  839 {
  840         struct tl_softc         *sc;
  841         struct mii_data         *mii;
  842 
  843         sc = device_get_softc(dev);
  844         TL_LOCK(sc);
  845         mii = device_get_softc(sc->tl_miibus);
  846 
  847         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
  848                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
  849         } else {
  850                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
  851         }
  852         TL_UNLOCK(sc);
  853 
  854         return;
  855 }
  856 
  857 /*
  858  * Set modes for bitrate devices.
  859  */
  860 static void
  861 tl_setmode(sc, media)
  862         struct tl_softc         *sc;
  863         int                     media;
  864 {
  865         if (IFM_SUBTYPE(media) == IFM_10_5)
  866                 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
  867         if (IFM_SUBTYPE(media) == IFM_10_T) {
  868                 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
  869                 if ((media & IFM_GMASK) == IFM_FDX) {
  870                         tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
  871                         tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
  872                 } else {
  873                         tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
  874                         tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
  875                 }
  876         }
  877 
  878         return;
  879 }
  880 
  881 /*
  882  * Calculate the hash of a MAC address for programming the multicast hash
  883  * table.  This hash is simply the address split into 6-bit chunks
  884  * XOR'd, e.g.
  885  * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
  886  * bit:  765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
  887  * Bytes 0-2 and 3-5 are symmetrical, so are folded together.  Then
  888  * the folded 24-bit value is split into 6-bit portions and XOR'd.
  889  */
  890 static uint32_t
  891 tl_mchash(addr)
  892         const uint8_t *addr;
  893 {
  894         int t;
  895 
  896         t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
  897                 (addr[2] ^ addr[5]);
  898         return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
  899 }
  900 
  901 /*
  902  * The ThunderLAN has a perfect MAC address filter in addition to
  903  * the multicast hash filter. The perfect filter can be programmed
  904  * with up to four MAC addresses. The first one is always used to
  905  * hold the station address, which leaves us free to use the other
  906  * three for multicast addresses.
  907  */
  908 static void
  909 tl_setfilt(sc, addr, slot)
  910         struct tl_softc         *sc;
  911         caddr_t                 addr;
  912         int                     slot;
  913 {
  914         int                     i;
  915         u_int16_t               regaddr;
  916 
  917         regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
  918 
  919         for (i = 0; i < ETHER_ADDR_LEN; i++)
  920                 tl_dio_write8(sc, regaddr + i, *(addr + i));
  921 
  922         return;
  923 }
  924 
  925 /*
  926  * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
  927  * linked list. This is fine, except addresses are added from the head
  928  * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
  929  * group to always be in the perfect filter, but as more groups are added,
  930  * the 224.0.0.1 entry (which is always added first) gets pushed down
  931  * the list and ends up at the tail. So after 3 or 4 multicast groups
  932  * are added, the all-hosts entry gets pushed out of the perfect filter
  933  * and into the hash table.
  934  *
  935  * Because the multicast list is a doubly-linked list as opposed to a
  936  * circular queue, we don't have the ability to just grab the tail of
  937  * the list and traverse it backwards. Instead, we have to traverse
  938  * the list once to find the tail, then traverse it again backwards to
  939  * update the multicast filter.
  940  */
  941 static void
  942 tl_setmulti(sc)
  943         struct tl_softc         *sc;
  944 {
  945         struct ifnet            *ifp;
  946         u_int32_t               hashes[2] = { 0, 0 };
  947         int                     h, i;
  948         struct ifmultiaddr      *ifma;
  949         u_int8_t                dummy[] = { 0, 0, 0, 0, 0 ,0 };
  950         ifp = &sc->arpcom.ac_if;
  951 
  952         /* First, zot all the existing filters. */
  953         for (i = 1; i < 4; i++)
  954                 tl_setfilt(sc, (caddr_t)&dummy, i);
  955         tl_dio_write32(sc, TL_HASH1, 0);
  956         tl_dio_write32(sc, TL_HASH2, 0);
  957 
  958         /* Now program new ones. */
  959         if (ifp->if_flags & IFF_ALLMULTI) {
  960                 hashes[0] = 0xFFFFFFFF;
  961                 hashes[1] = 0xFFFFFFFF;
  962         } else {
  963                 i = 1;
  964                 IF_ADDR_LOCK(ifp);
  965                 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
  966                         if (ifma->ifma_addr->sa_family != AF_LINK)
  967                                 continue;
  968                         /*
  969                          * Program the first three multicast groups
  970                          * into the perfect filter. For all others,
  971                          * use the hash table.
  972                          */
  973                         if (i < 4) {
  974                                 tl_setfilt(sc,
  975                         LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
  976                                 i++;
  977                                 continue;
  978                         }
  979 
  980                         h = tl_mchash(
  981                                 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  982                         if (h < 32)
  983                                 hashes[0] |= (1 << h);
  984                         else
  985                                 hashes[1] |= (1 << (h - 32));
  986                 }
  987                 IF_ADDR_UNLOCK(ifp);
  988         }
  989 
  990         tl_dio_write32(sc, TL_HASH1, hashes[0]);
  991         tl_dio_write32(sc, TL_HASH2, hashes[1]);
  992 
  993         return;
  994 }
  995 
  996 /*
  997  * This routine is recommended by the ThunderLAN manual to insure that
  998  * the internal PHY is powered up correctly. It also recommends a one
  999  * second pause at the end to 'wait for the clocks to start' but in my
 1000  * experience this isn't necessary.
 1001  */
 1002 static void
 1003 tl_hardreset(dev)
 1004         device_t                dev;
 1005 {
 1006         struct tl_softc         *sc;
 1007         int                     i;
 1008         u_int16_t               flags;
 1009 
 1010         sc = device_get_softc(dev);
 1011 
 1012         tl_mii_sync(sc);
 1013 
 1014         flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
 1015 
 1016         for (i = 0; i < MII_NPHY; i++)
 1017                 tl_miibus_writereg(dev, i, MII_BMCR, flags);
 1018 
 1019         tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
 1020         DELAY(50000);
 1021         tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
 1022         tl_mii_sync(sc);
 1023         while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
 1024 
 1025         DELAY(50000);
 1026         return;
 1027 }
 1028 
 1029 static void
 1030 tl_softreset(sc, internal)
 1031         struct tl_softc         *sc;
 1032         int                     internal;
 1033 {
 1034         u_int32_t               cmd, dummy, i;
 1035 
 1036         /* Assert the adapter reset bit. */
 1037         CMD_SET(sc, TL_CMD_ADRST);
 1038 
 1039         /* Turn off interrupts */
 1040         CMD_SET(sc, TL_CMD_INTSOFF);
 1041 
 1042         /* First, clear the stats registers. */
 1043         for (i = 0; i < 5; i++)
 1044                 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
 1045 
 1046         /* Clear Areg and Hash registers */
 1047         for (i = 0; i < 8; i++)
 1048                 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
 1049 
 1050         /*
 1051          * Set up Netconfig register. Enable one channel and
 1052          * one fragment mode.
 1053          */
 1054         tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
 1055         if (internal && !sc->tl_bitrate) {
 1056                 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
 1057         } else {
 1058                 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
 1059         }
 1060 
 1061         /* Handle cards with bitrate devices. */
 1062         if (sc->tl_bitrate)
 1063                 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
 1064 
 1065         /*
 1066          * Load adapter irq pacing timer and tx threshold.
 1067          * We make the transmit threshold 1 initially but we may
 1068          * change that later.
 1069          */
 1070         cmd = CSR_READ_4(sc, TL_HOSTCMD);
 1071         cmd |= TL_CMD_NES;
 1072         cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
 1073         CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
 1074         CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
 1075 
 1076         /* Unreset the MII */
 1077         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
 1078 
 1079         /* Take the adapter out of reset */
 1080         tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
 1081 
 1082         /* Wait for things to settle down a little. */
 1083         DELAY(500);
 1084 
 1085         return;
 1086 }
 1087 
 1088 /*
 1089  * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
 1090  * against our list and return its name if we find a match.
 1091  */
 1092 static int
 1093 tl_probe(dev)
 1094         device_t                dev;
 1095 {
 1096         struct tl_type          *t;
 1097 
 1098         t = tl_devs;
 1099 
 1100         while(t->tl_name != NULL) {
 1101                 if ((pci_get_vendor(dev) == t->tl_vid) &&
 1102                     (pci_get_device(dev) == t->tl_did)) {
 1103                         device_set_desc(dev, t->tl_name);
 1104                         return (BUS_PROBE_DEFAULT);
 1105                 }
 1106                 t++;
 1107         }
 1108 
 1109         return(ENXIO);
 1110 }
 1111 
 1112 static int
 1113 tl_attach(dev)
 1114         device_t                dev;
 1115 {
 1116         int                     i;
 1117         u_int16_t               did, vid;
 1118         struct tl_type          *t;
 1119         struct ifnet            *ifp;
 1120         struct tl_softc         *sc;
 1121         int                     unit, error = 0, rid;
 1122 
 1123         vid = pci_get_vendor(dev);
 1124         did = pci_get_device(dev);
 1125         sc = device_get_softc(dev);
 1126         unit = device_get_unit(dev);
 1127 
 1128         t = tl_devs;
 1129         while(t->tl_name != NULL) {
 1130                 if (vid == t->tl_vid && did == t->tl_did)
 1131                         break;
 1132                 t++;
 1133         }
 1134 
 1135         if (t->tl_name == NULL) {
 1136                 device_printf(dev, "unknown device!?\n");
 1137                 return (ENXIO);
 1138         }
 1139 
 1140         mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 1141             MTX_DEF | MTX_RECURSE);
 1142 
 1143         /*
 1144          * Map control/status registers.
 1145          */
 1146         pci_enable_busmaster(dev);
 1147 
 1148 #ifdef TL_USEIOSPACE
 1149 
 1150         rid = TL_PCI_LOIO;
 1151         sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
 1152                 RF_ACTIVE);
 1153 
 1154         /*
 1155          * Some cards have the I/O and memory mapped address registers
 1156          * reversed. Try both combinations before giving up.
 1157          */
 1158         if (sc->tl_res == NULL) {
 1159                 rid = TL_PCI_LOMEM;
 1160                 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
 1161                     RF_ACTIVE);
 1162         }
 1163 #else
 1164         rid = TL_PCI_LOMEM;
 1165         sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 1166             RF_ACTIVE);
 1167         if (sc->tl_res == NULL) {
 1168                 rid = TL_PCI_LOIO;
 1169                 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 1170                     RF_ACTIVE);
 1171         }
 1172 #endif
 1173 
 1174         if (sc->tl_res == NULL) {
 1175                 device_printf(dev, "couldn't map ports/memory\n");
 1176                 error = ENXIO;
 1177                 goto fail;
 1178         }
 1179 
 1180         sc->tl_btag = rman_get_bustag(sc->tl_res);
 1181         sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
 1182 
 1183 #ifdef notdef
 1184         /*
 1185          * The ThunderLAN manual suggests jacking the PCI latency
 1186          * timer all the way up to its maximum value. I'm not sure
 1187          * if this is really necessary, but what the manual wants,
 1188          * the manual gets.
 1189          */
 1190         command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
 1191         command |= 0x0000FF00;
 1192         pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
 1193 #endif
 1194 
 1195         /* Allocate interrupt */
 1196         rid = 0;
 1197         sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 1198             RF_SHAREABLE | RF_ACTIVE);
 1199 
 1200         if (sc->tl_irq == NULL) {
 1201                 device_printf(dev, "couldn't map interrupt\n");
 1202                 error = ENXIO;
 1203                 goto fail;
 1204         }
 1205 
 1206         /*
 1207          * Now allocate memory for the TX and RX lists.
 1208          */
 1209         sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
 1210             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 1211 
 1212         if (sc->tl_ldata == NULL) {
 1213                 device_printf(dev, "no memory for list buffers!\n");
 1214                 error = ENXIO;
 1215                 goto fail;
 1216         }
 1217 
 1218         bzero(sc->tl_ldata, sizeof(struct tl_list_data));
 1219 
 1220         sc->tl_dinfo = t;
 1221         if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
 1222                 sc->tl_eeaddr = TL_EEPROM_EADDR;
 1223         if (t->tl_vid == OLICOM_VENDORID)
 1224                 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
 1225 
 1226         /* Reset the adapter. */
 1227         tl_softreset(sc, 1);
 1228         tl_hardreset(dev);
 1229         tl_softreset(sc, 1);
 1230 
 1231         /*
 1232          * Get station address from the EEPROM.
 1233          */
 1234         if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
 1235                                 sc->tl_eeaddr, ETHER_ADDR_LEN)) {
 1236                 device_printf(dev, "failed to read station address\n");
 1237                 error = ENXIO;
 1238                 goto fail;
 1239         }
 1240 
 1241         /*
 1242          * XXX Olicom, in its desire to be different from the
 1243          * rest of the world, has done strange things with the
 1244          * encoding of the station address in the EEPROM. First
 1245          * of all, they store the address at offset 0xF8 rather
 1246          * than at 0x83 like the ThunderLAN manual suggests.
 1247          * Second, they store the address in three 16-bit words in
 1248          * network byte order, as opposed to storing it sequentially
 1249          * like all the other ThunderLAN cards. In order to get
 1250          * the station address in a form that matches what the Olicom
 1251          * diagnostic utility specifies, we have to byte-swap each
 1252          * word. To make things even more confusing, neither 00:00:28
 1253          * nor 00:00:24 appear in the IEEE OUI database.
 1254          */
 1255         if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
 1256                 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
 1257                         u_int16_t               *p;
 1258                         p = (u_int16_t *)&sc->arpcom.ac_enaddr[i];
 1259                         *p = ntohs(*p);
 1260                 }
 1261         }
 1262 
 1263         ifp = &sc->arpcom.ac_if;
 1264         ifp->if_softc = sc;
 1265         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 1266         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
 1267             IFF_NEEDSGIANT;
 1268         ifp->if_ioctl = tl_ioctl;
 1269         ifp->if_start = tl_start;
 1270         ifp->if_watchdog = tl_watchdog;
 1271         ifp->if_init = tl_init;
 1272         ifp->if_mtu = ETHERMTU;
 1273         ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1;
 1274         callout_handle_init(&sc->tl_stat_ch);
 1275 
 1276         /* Reset the adapter again. */
 1277         tl_softreset(sc, 1);
 1278         tl_hardreset(dev);
 1279         tl_softreset(sc, 1);
 1280 
 1281         /*
 1282          * Do MII setup. If no PHYs are found, then this is a
 1283          * bitrate ThunderLAN chip that only supports 10baseT
 1284          * and AUI/BNC.
 1285          */
 1286         if (mii_phy_probe(dev, &sc->tl_miibus,
 1287             tl_ifmedia_upd, tl_ifmedia_sts)) {
 1288                 struct ifmedia          *ifm;
 1289                 sc->tl_bitrate = 1;
 1290                 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
 1291                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 1292                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
 1293                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
 1294                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
 1295                 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
 1296                 /* Reset again, this time setting bitrate mode. */
 1297                 tl_softreset(sc, 1);
 1298                 ifm = &sc->ifmedia;
 1299                 ifm->ifm_media = ifm->ifm_cur->ifm_media;
 1300                 tl_ifmedia_upd(ifp);
 1301         }
 1302 
 1303         /*
 1304          * Call MI attach routine.
 1305          */
 1306         ether_ifattach(ifp, sc->arpcom.ac_enaddr);
 1307 
 1308         /* Hook interrupt last to avoid having to lock softc */
 1309         error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET,
 1310             tl_intr, sc, &sc->tl_intrhand);
 1311 
 1312         if (error) {
 1313                 device_printf(dev, "couldn't set up irq\n");
 1314                 ether_ifdetach(ifp);
 1315                 goto fail;
 1316         }
 1317 
 1318 fail:
 1319         if (error)
 1320                 tl_detach(dev);
 1321 
 1322         return(error);
 1323 }
 1324 
 1325 /*
 1326  * Shutdown hardware and free up resources. This can be called any
 1327  * time after the mutex has been initialized. It is called in both
 1328  * the error case in attach and the normal detach case so it needs
 1329  * to be careful about only freeing resources that have actually been
 1330  * allocated.
 1331  */
 1332 static int
 1333 tl_detach(dev)
 1334         device_t                dev;
 1335 {
 1336         struct tl_softc         *sc;
 1337         struct ifnet            *ifp;
 1338 
 1339         sc = device_get_softc(dev);
 1340         KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized"));
 1341         TL_LOCK(sc);
 1342         ifp = &sc->arpcom.ac_if;
 1343 
 1344         /* These should only be active if attach succeeded */
 1345         if (device_is_attached(dev)) {
 1346                 tl_stop(sc);
 1347                 ether_ifdetach(ifp);
 1348         }
 1349         if (sc->tl_miibus)
 1350                 device_delete_child(dev, sc->tl_miibus);
 1351         bus_generic_detach(dev);
 1352 
 1353         if (sc->tl_ldata)
 1354                 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
 1355         if (sc->tl_bitrate)
 1356                 ifmedia_removeall(&sc->ifmedia);
 1357 
 1358         if (sc->tl_intrhand)
 1359                 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
 1360         if (sc->tl_irq)
 1361                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
 1362         if (sc->tl_res)
 1363                 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
 1364 
 1365         TL_UNLOCK(sc);
 1366         mtx_destroy(&sc->tl_mtx);
 1367 
 1368         return(0);
 1369 }
 1370 
 1371 /*
 1372  * Initialize the transmit lists.
 1373  */
 1374 static int
 1375 tl_list_tx_init(sc)
 1376         struct tl_softc         *sc;
 1377 {
 1378         struct tl_chain_data    *cd;
 1379         struct tl_list_data     *ld;
 1380         int                     i;
 1381 
 1382         cd = &sc->tl_cdata;
 1383         ld = sc->tl_ldata;
 1384         for (i = 0; i < TL_TX_LIST_CNT; i++) {
 1385                 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
 1386                 if (i == (TL_TX_LIST_CNT - 1))
 1387                         cd->tl_tx_chain[i].tl_next = NULL;
 1388                 else
 1389                         cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
 1390         }
 1391 
 1392         cd->tl_tx_free = &cd->tl_tx_chain[0];
 1393         cd->tl_tx_tail = cd->tl_tx_head = NULL;
 1394         sc->tl_txeoc = 1;
 1395 
 1396         return(0);
 1397 }
 1398 
 1399 /*
 1400  * Initialize the RX lists and allocate mbufs for them.
 1401  */
 1402 static int
 1403 tl_list_rx_init(sc)
 1404         struct tl_softc         *sc;
 1405 {
 1406         struct tl_chain_data    *cd;
 1407         struct tl_list_data     *ld;
 1408         int                     i;
 1409 
 1410         cd = &sc->tl_cdata;
 1411         ld = sc->tl_ldata;
 1412 
 1413         for (i = 0; i < TL_RX_LIST_CNT; i++) {
 1414                 cd->tl_rx_chain[i].tl_ptr =
 1415                         (struct tl_list_onefrag *)&ld->tl_rx_list[i];
 1416                 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
 1417                         return(ENOBUFS);
 1418                 if (i == (TL_RX_LIST_CNT - 1)) {
 1419                         cd->tl_rx_chain[i].tl_next = NULL;
 1420                         ld->tl_rx_list[i].tlist_fptr = 0;
 1421                 } else {
 1422                         cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
 1423                         ld->tl_rx_list[i].tlist_fptr =
 1424                                         vtophys(&ld->tl_rx_list[i + 1]);
 1425                 }
 1426         }
 1427 
 1428         cd->tl_rx_head = &cd->tl_rx_chain[0];
 1429         cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
 1430 
 1431         return(0);
 1432 }
 1433 
 1434 static int
 1435 tl_newbuf(sc, c)
 1436         struct tl_softc         *sc;
 1437         struct tl_chain_onefrag *c;
 1438 {
 1439         struct mbuf             *m_new = NULL;
 1440 
 1441         MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1442         if (m_new == NULL)
 1443                 return(ENOBUFS);
 1444 
 1445         MCLGET(m_new, M_DONTWAIT);
 1446         if (!(m_new->m_flags & M_EXT)) {
 1447                 m_freem(m_new);
 1448                 return(ENOBUFS);
 1449         }
 1450 
 1451 #ifdef __alpha__
 1452         m_new->m_data += 2;
 1453 #endif
 1454 
 1455         c->tl_mbuf = m_new;
 1456         c->tl_next = NULL;
 1457         c->tl_ptr->tlist_frsize = MCLBYTES;
 1458         c->tl_ptr->tlist_fptr = 0;
 1459         c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
 1460         c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
 1461         c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
 1462 
 1463         return(0);
 1464 }
 1465 /*
 1466  * Interrupt handler for RX 'end of frame' condition (EOF). This
 1467  * tells us that a full ethernet frame has been captured and we need
 1468  * to handle it.
 1469  *
 1470  * Reception is done using 'lists' which consist of a header and a
 1471  * series of 10 data count/data address pairs that point to buffers.
 1472  * Initially you're supposed to create a list, populate it with pointers
 1473  * to buffers, then load the physical address of the list into the
 1474  * ch_parm register. The adapter is then supposed to DMA the received
 1475  * frame into the buffers for you.
 1476  *
 1477  * To make things as fast as possible, we have the chip DMA directly
 1478  * into mbufs. This saves us from having to do a buffer copy: we can
 1479  * just hand the mbufs directly to ether_input(). Once the frame has
 1480  * been sent on its way, the 'list' structure is assigned a new buffer
 1481  * and moved to the end of the RX chain. As long we we stay ahead of
 1482  * the chip, it will always think it has an endless receive channel.
 1483  *
 1484  * If we happen to fall behind and the chip manages to fill up all of
 1485  * the buffers, it will generate an end of channel interrupt and wait
 1486  * for us to empty the chain and restart the receiver.
 1487  */
 1488 static int
 1489 tl_intvec_rxeof(xsc, type)
 1490         void                    *xsc;
 1491         u_int32_t               type;
 1492 {
 1493         struct tl_softc         *sc;
 1494         int                     r = 0, total_len = 0;
 1495         struct ether_header     *eh;
 1496         struct mbuf             *m;
 1497         struct ifnet            *ifp;
 1498         struct tl_chain_onefrag *cur_rx;
 1499 
 1500         sc = xsc;
 1501         ifp = &sc->arpcom.ac_if;
 1502 
 1503         TL_LOCK_ASSERT(sc);
 1504 
 1505         while(sc->tl_cdata.tl_rx_head != NULL) {
 1506                 cur_rx = sc->tl_cdata.tl_rx_head;
 1507                 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
 1508                         break;
 1509                 r++;
 1510                 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
 1511                 m = cur_rx->tl_mbuf;
 1512                 total_len = cur_rx->tl_ptr->tlist_frsize;
 1513 
 1514                 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
 1515                         ifp->if_ierrors++;
 1516                         cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
 1517                         cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
 1518                         cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
 1519                         continue;
 1520                 }
 1521 
 1522                 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
 1523                                                 vtophys(cur_rx->tl_ptr);
 1524                 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
 1525                 sc->tl_cdata.tl_rx_tail = cur_rx;
 1526 
 1527                 /*
 1528                  * Note: when the ThunderLAN chip is in 'capture all
 1529                  * frames' mode, it will receive its own transmissions.
 1530                  * We drop don't need to process our own transmissions,
 1531                  * so we drop them here and continue.
 1532                  */
 1533                 eh = mtod(m, struct ether_header *);
 1534                 /*if (ifp->if_flags & IFF_PROMISC && */
 1535                 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
 1536                                                         ETHER_ADDR_LEN)) {
 1537                                 m_freem(m);
 1538                                 continue;
 1539                 }
 1540 
 1541                 m->m_pkthdr.rcvif = ifp;
 1542                 m->m_pkthdr.len = m->m_len = total_len;
 1543 
 1544                 TL_UNLOCK(sc);
 1545                 (*ifp->if_input)(ifp, m);
 1546                 TL_LOCK(sc);
 1547         }
 1548 
 1549         return(r);
 1550 }
 1551 
 1552 /*
 1553  * The RX-EOC condition hits when the ch_parm address hasn't been
 1554  * initialized or the adapter reached a list with a forward pointer
 1555  * of 0 (which indicates the end of the chain). In our case, this means
 1556  * the card has hit the end of the receive buffer chain and we need to
 1557  * empty out the buffers and shift the pointer back to the beginning again.
 1558  */
 1559 static int
 1560 tl_intvec_rxeoc(xsc, type)
 1561         void                    *xsc;
 1562         u_int32_t               type;
 1563 {
 1564         struct tl_softc         *sc;
 1565         int                     r;
 1566         struct tl_chain_data    *cd;
 1567 
 1568 
 1569         sc = xsc;
 1570         cd = &sc->tl_cdata;
 1571 
 1572         /* Flush out the receive queue and ack RXEOF interrupts. */
 1573         r = tl_intvec_rxeof(xsc, type);
 1574         CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
 1575         r = 1;
 1576         cd->tl_rx_head = &cd->tl_rx_chain[0];
 1577         cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
 1578         CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
 1579         r |= (TL_CMD_GO|TL_CMD_RT);
 1580         return(r);
 1581 }
 1582 
 1583 static int
 1584 tl_intvec_txeof(xsc, type)
 1585         void                    *xsc;
 1586         u_int32_t               type;
 1587 {
 1588         struct tl_softc         *sc;
 1589         int                     r = 0;
 1590         struct tl_chain         *cur_tx;
 1591 
 1592         sc = xsc;
 1593 
 1594         /*
 1595          * Go through our tx list and free mbufs for those
 1596          * frames that have been sent.
 1597          */
 1598         while (sc->tl_cdata.tl_tx_head != NULL) {
 1599                 cur_tx = sc->tl_cdata.tl_tx_head;
 1600                 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
 1601                         break;
 1602                 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
 1603 
 1604                 r++;
 1605                 m_freem(cur_tx->tl_mbuf);
 1606                 cur_tx->tl_mbuf = NULL;
 1607 
 1608                 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
 1609                 sc->tl_cdata.tl_tx_free = cur_tx;
 1610                 if (!cur_tx->tl_ptr->tlist_fptr)
 1611                         break;
 1612         }
 1613 
 1614         return(r);
 1615 }
 1616 
 1617 /*
 1618  * The transmit end of channel interrupt. The adapter triggers this
 1619  * interrupt to tell us it hit the end of the current transmit list.
 1620  *
 1621  * A note about this: it's possible for a condition to arise where
 1622  * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
 1623  * You have to avoid this since the chip expects things to go in a
 1624  * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
 1625  * When the TXEOF handler is called, it will free all of the transmitted
 1626  * frames and reset the tx_head pointer to NULL. However, a TXEOC
 1627  * interrupt should be received and acknowledged before any more frames
 1628  * are queued for transmission. If tl_statrt() is called after TXEOF
 1629  * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
 1630  * it could attempt to issue a transmit command prematurely.
 1631  *
 1632  * To guard against this, tl_start() will only issue transmit commands
 1633  * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
 1634  * can set this flag once tl_start() has cleared it.
 1635  */
 1636 static int
 1637 tl_intvec_txeoc(xsc, type)
 1638         void                    *xsc;
 1639         u_int32_t               type;
 1640 {
 1641         struct tl_softc         *sc;
 1642         struct ifnet            *ifp;
 1643         u_int32_t               cmd;
 1644 
 1645         sc = xsc;
 1646         ifp = &sc->arpcom.ac_if;
 1647 
 1648         /* Clear the timeout timer. */
 1649         ifp->if_timer = 0;
 1650 
 1651         if (sc->tl_cdata.tl_tx_head == NULL) {
 1652                 ifp->if_flags &= ~IFF_OACTIVE;
 1653                 sc->tl_cdata.tl_tx_tail = NULL;
 1654                 sc->tl_txeoc = 1;
 1655         } else {
 1656                 sc->tl_txeoc = 0;
 1657                 /* First we have to ack the EOC interrupt. */
 1658                 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
 1659                 /* Then load the address of the next TX list. */
 1660                 CSR_WRITE_4(sc, TL_CH_PARM,
 1661                     vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
 1662                 /* Restart TX channel. */
 1663                 cmd = CSR_READ_4(sc, TL_HOSTCMD);
 1664                 cmd &= ~TL_CMD_RT;
 1665                 cmd |= TL_CMD_GO|TL_CMD_INTSON;
 1666                 CMD_PUT(sc, cmd);
 1667                 return(0);
 1668         }
 1669 
 1670         return(1);
 1671 }
 1672 
 1673 static int
 1674 tl_intvec_adchk(xsc, type)
 1675         void                    *xsc;
 1676         u_int32_t               type;
 1677 {
 1678         struct tl_softc         *sc;
 1679 
 1680         sc = xsc;
 1681 
 1682         if (type)
 1683                 if_printf(&sc->arpcom.ac_if, "adapter check: %x\n",
 1684                         (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
 1685 
 1686         tl_softreset(sc, 1);
 1687         tl_stop(sc);
 1688         tl_init(sc);
 1689         CMD_SET(sc, TL_CMD_INTSON);
 1690 
 1691         return(0);
 1692 }
 1693 
 1694 static int
 1695 tl_intvec_netsts(xsc, type)
 1696         void                    *xsc;
 1697         u_int32_t               type;
 1698 {
 1699         struct tl_softc         *sc;
 1700         u_int16_t               netsts;
 1701 
 1702         sc = xsc;
 1703 
 1704         netsts = tl_dio_read16(sc, TL_NETSTS);
 1705         tl_dio_write16(sc, TL_NETSTS, netsts);
 1706 
 1707         if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts);
 1708 
 1709         return(1);
 1710 }
 1711 
 1712 static void
 1713 tl_intr(xsc)
 1714         void                    *xsc;
 1715 {
 1716         struct tl_softc         *sc;
 1717         struct ifnet            *ifp;
 1718         int                     r = 0;
 1719         u_int32_t               type = 0;
 1720         u_int16_t               ints = 0;
 1721         u_int8_t                ivec = 0;
 1722 
 1723         sc = xsc;
 1724         TL_LOCK(sc);
 1725 
 1726         /* Disable interrupts */
 1727         ints = CSR_READ_2(sc, TL_HOST_INT);
 1728         CSR_WRITE_2(sc, TL_HOST_INT, ints);
 1729         type = (ints << 16) & 0xFFFF0000;
 1730         ivec = (ints & TL_VEC_MASK) >> 5;
 1731         ints = (ints & TL_INT_MASK) >> 2;
 1732 
 1733         ifp = &sc->arpcom.ac_if;
 1734 
 1735         switch(ints) {
 1736         case (TL_INTR_INVALID):
 1737 #ifdef DIAGNOSTIC
 1738                 if_printf(ifp, "got an invalid interrupt!\n");
 1739 #endif
 1740                 /* Re-enable interrupts but don't ack this one. */
 1741                 CMD_PUT(sc, type);
 1742                 r = 0;
 1743                 break;
 1744         case (TL_INTR_TXEOF):
 1745                 r = tl_intvec_txeof((void *)sc, type);
 1746                 break;
 1747         case (TL_INTR_TXEOC):
 1748                 r = tl_intvec_txeoc((void *)sc, type);
 1749                 break;
 1750         case (TL_INTR_STATOFLOW):
 1751                 tl_stats_update(sc);
 1752                 r = 1;
 1753                 break;
 1754         case (TL_INTR_RXEOF):
 1755                 r = tl_intvec_rxeof((void *)sc, type);
 1756                 break;
 1757         case (TL_INTR_DUMMY):
 1758                 if_printf(ifp, "got a dummy interrupt\n");
 1759                 r = 1;
 1760                 break;
 1761         case (TL_INTR_ADCHK):
 1762                 if (ivec)
 1763                         r = tl_intvec_adchk((void *)sc, type);
 1764                 else
 1765                         r = tl_intvec_netsts((void *)sc, type);
 1766                 break;
 1767         case (TL_INTR_RXEOC):
 1768                 r = tl_intvec_rxeoc((void *)sc, type);
 1769                 break;
 1770         default:
 1771                 if_printf(ifp, "bogus interrupt type\n");
 1772                 break;
 1773         }
 1774 
 1775         /* Re-enable interrupts */
 1776         if (r) {
 1777                 CMD_PUT(sc, TL_CMD_ACK | r | type);
 1778         }
 1779 
 1780         if (ifp->if_snd.ifq_head != NULL)
 1781                 tl_start(ifp);
 1782 
 1783         TL_UNLOCK(sc);
 1784 
 1785         return;
 1786 }
 1787 
 1788 static void
 1789 tl_stats_update(xsc)
 1790         void                    *xsc;
 1791 {
 1792         struct tl_softc         *sc;
 1793         struct ifnet            *ifp;
 1794         struct tl_stats         tl_stats;
 1795         struct mii_data         *mii;
 1796         u_int32_t               *p;
 1797 
 1798         bzero((char *)&tl_stats, sizeof(struct tl_stats));
 1799 
 1800         sc = xsc;
 1801         TL_LOCK(sc);
 1802         ifp = &sc->arpcom.ac_if;
 1803 
 1804         p = (u_int32_t *)&tl_stats;
 1805 
 1806         CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
 1807         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 1808         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 1809         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 1810         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 1811         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 1812 
 1813         ifp->if_opackets += tl_tx_goodframes(tl_stats);
 1814         ifp->if_collisions += tl_stats.tl_tx_single_collision +
 1815                                 tl_stats.tl_tx_multi_collision;
 1816         ifp->if_ipackets += tl_rx_goodframes(tl_stats);
 1817         ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
 1818                             tl_rx_overrun(tl_stats);
 1819         ifp->if_oerrors += tl_tx_underrun(tl_stats);
 1820 
 1821         if (tl_tx_underrun(tl_stats)) {
 1822                 u_int8_t                tx_thresh;
 1823                 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
 1824                 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
 1825                         tx_thresh >>= 4;
 1826                         tx_thresh++;
 1827                         if_printf(ifp, "tx underrun -- increasing "
 1828                             "tx threshold to %d bytes\n",
 1829                             (64 * (tx_thresh * 4)));
 1830                         tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
 1831                         tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
 1832                 }
 1833         }
 1834 
 1835         sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
 1836 
 1837         if (!sc->tl_bitrate) {
 1838                 mii = device_get_softc(sc->tl_miibus);
 1839                 mii_tick(mii);
 1840         }
 1841 
 1842         TL_UNLOCK(sc);
 1843 
 1844         return;
 1845 }
 1846 
 1847 /*
 1848  * Encapsulate an mbuf chain in a list by coupling the mbuf data
 1849  * pointers to the fragment pointers.
 1850  */
 1851 static int
 1852 tl_encap(sc, c, m_head)
 1853         struct tl_softc         *sc;
 1854         struct tl_chain         *c;
 1855         struct mbuf             *m_head;
 1856 {
 1857         int                     frag = 0;
 1858         struct tl_frag          *f = NULL;
 1859         int                     total_len;
 1860         struct mbuf             *m;
 1861         struct ifnet            *ifp = &sc->arpcom.ac_if;
 1862 
 1863         /*
 1864          * Start packing the mbufs in this chain into
 1865          * the fragment pointers. Stop when we run out
 1866          * of fragments or hit the end of the mbuf chain.
 1867          */
 1868         m = m_head;
 1869         total_len = 0;
 1870 
 1871         for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
 1872                 if (m->m_len != 0) {
 1873                         if (frag == TL_MAXFRAGS)
 1874                                 break;
 1875                         total_len+= m->m_len;
 1876                         c->tl_ptr->tl_frag[frag].tlist_dadr =
 1877                                 vtophys(mtod(m, vm_offset_t));
 1878                         c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
 1879                         frag++;
 1880                 }
 1881         }
 1882 
 1883         /*
 1884          * Handle special cases.
 1885          * Special case #1: we used up all 10 fragments, but
 1886          * we have more mbufs left in the chain. Copy the
 1887          * data into an mbuf cluster. Note that we don't
 1888          * bother clearing the values in the other fragment
 1889          * pointers/counters; it wouldn't gain us anything,
 1890          * and would waste cycles.
 1891          */
 1892         if (m != NULL) {
 1893                 struct mbuf             *m_new = NULL;
 1894 
 1895                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1896                 if (m_new == NULL) {
 1897                         if_printf(ifp, "no memory for tx list\n");
 1898                         return(1);
 1899                 }
 1900                 if (m_head->m_pkthdr.len > MHLEN) {
 1901                         MCLGET(m_new, M_DONTWAIT);
 1902                         if (!(m_new->m_flags & M_EXT)) {
 1903                                 m_freem(m_new);
 1904                                 if_printf(ifp, "no memory for tx list\n");
 1905                                 return(1);
 1906                         }
 1907                 }
 1908                 m_copydata(m_head, 0, m_head->m_pkthdr.len,     
 1909                                         mtod(m_new, caddr_t));
 1910                 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
 1911                 m_freem(m_head);
 1912                 m_head = m_new;
 1913                 f = &c->tl_ptr->tl_frag[0];
 1914                 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
 1915                 f->tlist_dcnt = total_len = m_new->m_len;
 1916                 frag = 1;
 1917         }
 1918 
 1919         /*
 1920          * Special case #2: the frame is smaller than the minimum
 1921          * frame size. We have to pad it to make the chip happy.
 1922          */
 1923         if (total_len < TL_MIN_FRAMELEN) {
 1924                 if (frag == TL_MAXFRAGS)
 1925                         if_printf(ifp,
 1926                             "all frags filled but frame still to small!\n");
 1927                 f = &c->tl_ptr->tl_frag[frag];
 1928                 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
 1929                 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
 1930                 total_len += f->tlist_dcnt;
 1931                 frag++;
 1932         }
 1933 
 1934         c->tl_mbuf = m_head;
 1935         c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
 1936         c->tl_ptr->tlist_frsize = total_len;
 1937         c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
 1938         c->tl_ptr->tlist_fptr = 0;
 1939 
 1940         return(0);
 1941 }
 1942 
 1943 /*
 1944  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 1945  * to the mbuf data regions directly in the transmit lists. We also save a
 1946  * copy of the pointers since the transmit list fragment pointers are
 1947  * physical addresses.
 1948  */
 1949 static void
 1950 tl_start(ifp)
 1951         struct ifnet            *ifp;
 1952 {
 1953         struct tl_softc         *sc;
 1954         struct mbuf             *m_head = NULL;
 1955         u_int32_t               cmd;
 1956         struct tl_chain         *prev = NULL, *cur_tx = NULL, *start_tx;
 1957 
 1958         sc = ifp->if_softc;
 1959         TL_LOCK(sc);
 1960 
 1961         /*
 1962          * Check for an available queue slot. If there are none,
 1963          * punt.
 1964          */
 1965         if (sc->tl_cdata.tl_tx_free == NULL) {
 1966                 ifp->if_flags |= IFF_OACTIVE;
 1967                 TL_UNLOCK(sc);
 1968                 return;
 1969         }
 1970 
 1971         start_tx = sc->tl_cdata.tl_tx_free;
 1972 
 1973         while(sc->tl_cdata.tl_tx_free != NULL) {
 1974                 IF_DEQUEUE(&ifp->if_snd, m_head);
 1975                 if (m_head == NULL)
 1976                         break;
 1977 
 1978                 /* Pick a chain member off the free list. */
 1979                 cur_tx = sc->tl_cdata.tl_tx_free;
 1980                 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
 1981 
 1982                 cur_tx->tl_next = NULL;
 1983 
 1984                 /* Pack the data into the list. */
 1985                 tl_encap(sc, cur_tx, m_head);
 1986 
 1987                 /* Chain it together */
 1988                 if (prev != NULL) {
 1989                         prev->tl_next = cur_tx;
 1990                         prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
 1991                 }
 1992                 prev = cur_tx;
 1993 
 1994                 /*
 1995                  * If there's a BPF listener, bounce a copy of this frame
 1996                  * to him.
 1997                  */
 1998                 BPF_MTAP(ifp, cur_tx->tl_mbuf);
 1999         }
 2000 
 2001         /*
 2002          * If there are no packets queued, bail.
 2003          */
 2004         if (cur_tx == NULL) {
 2005                 TL_UNLOCK(sc);
 2006                 return;
 2007         }
 2008 
 2009         /*
 2010          * That's all we can stands, we can't stands no more.
 2011          * If there are no other transfers pending, then issue the
 2012          * TX GO command to the adapter to start things moving.
 2013          * Otherwise, just leave the data in the queue and let
 2014          * the EOF/EOC interrupt handler send.
 2015          */
 2016         if (sc->tl_cdata.tl_tx_head == NULL) {
 2017                 sc->tl_cdata.tl_tx_head = start_tx;
 2018                 sc->tl_cdata.tl_tx_tail = cur_tx;
 2019 
 2020                 if (sc->tl_txeoc) {
 2021                         sc->tl_txeoc = 0;
 2022                         CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
 2023                         cmd = CSR_READ_4(sc, TL_HOSTCMD);
 2024                         cmd &= ~TL_CMD_RT;
 2025                         cmd |= TL_CMD_GO|TL_CMD_INTSON;
 2026                         CMD_PUT(sc, cmd);
 2027                 }
 2028         } else {
 2029                 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
 2030                 sc->tl_cdata.tl_tx_tail = cur_tx;
 2031         }
 2032 
 2033         /*
 2034          * Set a timeout in case the chip goes out to lunch.
 2035          */
 2036         ifp->if_timer = 5;
 2037         TL_UNLOCK(sc);
 2038 
 2039         return;
 2040 }
 2041 
 2042 static void
 2043 tl_init(xsc)
 2044         void                    *xsc;
 2045 {
 2046         struct tl_softc         *sc = xsc;
 2047         struct ifnet            *ifp = &sc->arpcom.ac_if;
 2048         struct mii_data         *mii;
 2049 
 2050         TL_LOCK(sc);
 2051 
 2052         ifp = &sc->arpcom.ac_if;
 2053 
 2054         /*
 2055          * Cancel pending I/O.
 2056          */
 2057         tl_stop(sc);
 2058 
 2059         /* Initialize TX FIFO threshold */
 2060         tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
 2061         tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
 2062 
 2063         /* Set PCI burst size */
 2064         tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
 2065 
 2066         /*
 2067          * Set 'capture all frames' bit for promiscuous mode.
 2068          */
 2069         if (ifp->if_flags & IFF_PROMISC)
 2070                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
 2071         else
 2072                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
 2073 
 2074         /*
 2075          * Set capture broadcast bit to capture broadcast frames.
 2076          */
 2077         if (ifp->if_flags & IFF_BROADCAST)
 2078                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
 2079         else
 2080                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
 2081 
 2082         tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
 2083 
 2084         /* Init our MAC address */
 2085         tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
 2086 
 2087         /* Init multicast filter, if needed. */
 2088         tl_setmulti(sc);
 2089 
 2090         /* Init circular RX list. */
 2091         if (tl_list_rx_init(sc) == ENOBUFS) {
 2092                 if_printf(ifp,
 2093                     "initialization failed: no memory for rx buffers\n");
 2094                 tl_stop(sc);
 2095                 TL_UNLOCK(sc);
 2096                 return;
 2097         }
 2098 
 2099         /* Init TX pointers. */
 2100         tl_list_tx_init(sc);
 2101 
 2102         /* Enable PCI interrupts. */
 2103         CMD_SET(sc, TL_CMD_INTSON);
 2104 
 2105         /* Load the address of the rx list */
 2106         CMD_SET(sc, TL_CMD_RT);
 2107         CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
 2108 
 2109         if (!sc->tl_bitrate) {
 2110                 if (sc->tl_miibus != NULL) {
 2111                         mii = device_get_softc(sc->tl_miibus);
 2112                         mii_mediachg(mii);
 2113                 }
 2114         } else {
 2115                 tl_ifmedia_upd(ifp);
 2116         }
 2117 
 2118         /* Send the RX go command */
 2119         CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
 2120 
 2121         ifp->if_flags |= IFF_RUNNING;
 2122         ifp->if_flags &= ~IFF_OACTIVE;
 2123 
 2124         /* Start the stats update counter */
 2125         sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
 2126         TL_UNLOCK(sc);
 2127 
 2128         return;
 2129 }
 2130 
 2131 /*
 2132  * Set media options.
 2133  */
 2134 static int
 2135 tl_ifmedia_upd(ifp)
 2136         struct ifnet            *ifp;
 2137 {
 2138         struct tl_softc         *sc;
 2139         struct mii_data         *mii = NULL;
 2140 
 2141         sc = ifp->if_softc;
 2142 
 2143         if (sc->tl_bitrate)
 2144                 tl_setmode(sc, sc->ifmedia.ifm_media);
 2145         else {
 2146                 mii = device_get_softc(sc->tl_miibus);
 2147                 mii_mediachg(mii);
 2148         }
 2149 
 2150         return(0);
 2151 }
 2152 
 2153 /*
 2154  * Report current media status.
 2155  */
 2156 static void
 2157 tl_ifmedia_sts(ifp, ifmr)
 2158         struct ifnet            *ifp;
 2159         struct ifmediareq       *ifmr;
 2160 {
 2161         struct tl_softc         *sc;
 2162         struct mii_data         *mii;
 2163 
 2164         sc = ifp->if_softc;
 2165 
 2166         ifmr->ifm_active = IFM_ETHER;
 2167 
 2168         if (sc->tl_bitrate) {
 2169                 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
 2170                         ifmr->ifm_active = IFM_ETHER|IFM_10_5;
 2171                 else
 2172                         ifmr->ifm_active = IFM_ETHER|IFM_10_T;
 2173                 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
 2174                         ifmr->ifm_active |= IFM_HDX;
 2175                 else
 2176                         ifmr->ifm_active |= IFM_FDX;
 2177                 return;
 2178         } else {
 2179                 mii = device_get_softc(sc->tl_miibus);
 2180                 mii_pollstat(mii);
 2181                 ifmr->ifm_active = mii->mii_media_active;
 2182                 ifmr->ifm_status = mii->mii_media_status;
 2183         }
 2184 
 2185         return;
 2186 }
 2187 
 2188 static int
 2189 tl_ioctl(ifp, command, data)
 2190         struct ifnet            *ifp;
 2191         u_long                  command;
 2192         caddr_t                 data;
 2193 {
 2194         struct tl_softc         *sc = ifp->if_softc;
 2195         struct ifreq            *ifr = (struct ifreq *) data;
 2196         int                     s, error = 0;
 2197 
 2198         s = splimp();
 2199 
 2200         switch(command) {
 2201         case SIOCSIFFLAGS:
 2202                 if (ifp->if_flags & IFF_UP) {
 2203                         if (ifp->if_flags & IFF_RUNNING &&
 2204                             ifp->if_flags & IFF_PROMISC &&
 2205                             !(sc->tl_if_flags & IFF_PROMISC)) {
 2206                                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
 2207                                 tl_setmulti(sc);
 2208                         } else if (ifp->if_flags & IFF_RUNNING &&
 2209                             !(ifp->if_flags & IFF_PROMISC) &&
 2210                             sc->tl_if_flags & IFF_PROMISC) {
 2211                                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
 2212                                 tl_setmulti(sc);
 2213                         } else
 2214                                 tl_init(sc);
 2215                 } else {
 2216                         if (ifp->if_flags & IFF_RUNNING) {
 2217                                 tl_stop(sc);
 2218                         }
 2219                 }
 2220                 sc->tl_if_flags = ifp->if_flags;
 2221                 error = 0;
 2222                 break;
 2223         case SIOCADDMULTI:
 2224         case SIOCDELMULTI:
 2225                 tl_setmulti(sc);
 2226                 error = 0;
 2227                 break;
 2228         case SIOCSIFMEDIA:
 2229         case SIOCGIFMEDIA:
 2230                 if (sc->tl_bitrate)
 2231                         error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
 2232                 else {
 2233                         struct mii_data         *mii;
 2234                         mii = device_get_softc(sc->tl_miibus);
 2235                         error = ifmedia_ioctl(ifp, ifr,
 2236                             &mii->mii_media, command);
 2237                 }
 2238                 break;
 2239         default:
 2240                 error = ether_ioctl(ifp, command, data);
 2241                 break;
 2242         }
 2243 
 2244         (void)splx(s);
 2245 
 2246         return(error);
 2247 }
 2248 
 2249 static void
 2250 tl_watchdog(ifp)
 2251         struct ifnet            *ifp;
 2252 {
 2253         struct tl_softc         *sc;
 2254 
 2255         sc = ifp->if_softc;
 2256 
 2257         if_printf(ifp, "device timeout\n");
 2258 
 2259         ifp->if_oerrors++;
 2260 
 2261         tl_softreset(sc, 1);
 2262         tl_init(sc);
 2263 
 2264         return;
 2265 }
 2266 
 2267 /*
 2268  * Stop the adapter and free any mbufs allocated to the
 2269  * RX and TX lists.
 2270  */
 2271 static void
 2272 tl_stop(sc)
 2273         struct tl_softc         *sc;
 2274 {
 2275         register int            i;
 2276         struct ifnet            *ifp;
 2277 
 2278         TL_LOCK(sc);
 2279 
 2280         ifp = &sc->arpcom.ac_if;
 2281 
 2282         /* Stop the stats updater. */
 2283         untimeout(tl_stats_update, sc, sc->tl_stat_ch);
 2284 
 2285         /* Stop the transmitter */
 2286         CMD_CLR(sc, TL_CMD_RT);
 2287         CMD_SET(sc, TL_CMD_STOP);
 2288         CSR_WRITE_4(sc, TL_CH_PARM, 0);
 2289 
 2290         /* Stop the receiver */
 2291         CMD_SET(sc, TL_CMD_RT);
 2292         CMD_SET(sc, TL_CMD_STOP);
 2293         CSR_WRITE_4(sc, TL_CH_PARM, 0);
 2294 
 2295         /*
 2296          * Disable host interrupts.
 2297          */
 2298         CMD_SET(sc, TL_CMD_INTSOFF);
 2299 
 2300         /*
 2301          * Clear list pointer.
 2302          */
 2303         CSR_WRITE_4(sc, TL_CH_PARM, 0);
 2304 
 2305         /*
 2306          * Free the RX lists.
 2307          */
 2308         for (i = 0; i < TL_RX_LIST_CNT; i++) {
 2309                 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
 2310                         m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
 2311                         sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
 2312                 }
 2313         }
 2314         bzero((char *)&sc->tl_ldata->tl_rx_list,
 2315                 sizeof(sc->tl_ldata->tl_rx_list));
 2316 
 2317         /*
 2318          * Free the TX list buffers.
 2319          */
 2320         for (i = 0; i < TL_TX_LIST_CNT; i++) {
 2321                 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
 2322                         m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
 2323                         sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
 2324                 }
 2325         }
 2326         bzero((char *)&sc->tl_ldata->tl_tx_list,
 2327                 sizeof(sc->tl_ldata->tl_tx_list));
 2328 
 2329         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 2330         TL_UNLOCK(sc);
 2331 
 2332         return;
 2333 }
 2334 
 2335 /*
 2336  * Stop all chip I/O so that the kernel's probe routines don't
 2337  * get confused by errant DMAs when rebooting.
 2338  */
 2339 static void
 2340 tl_shutdown(dev)
 2341         device_t                dev;
 2342 {
 2343         struct tl_softc         *sc;
 2344 
 2345         sc = device_get_softc(dev);
 2346 
 2347         tl_stop(sc);
 2348 
 2349         return;
 2350 }

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