The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_tl.c

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    1 /*
    2  * Copyright (c) 1997, 1998
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: src/sys/pci/if_tl.c,v 1.16.2.10 1999/09/05 08:21:10 peter Exp $
   33  */
   34 
   35 /*
   36  * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
   37  * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
   38  * the National Semiconductor DP83840A physical interface and the
   39  * Microchip Technology 24Cxx series serial EEPROM.
   40  *
   41  * Written using the following four documents:
   42  *
   43  * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
   44  * National Semiconductor DP83840A data sheet (www.national.com)
   45  * Microchip Technology 24C02C data sheet (www.microchip.com)
   46  * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
   47  * 
   48  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   49  * Electrical Engineering Department
   50  * Columbia University, New York City
   51  */
   52 
   53 /*
   54  * Some notes about the ThunderLAN:
   55  *
   56  * The ThunderLAN controller is a single chip containing PCI controller
   57  * logic, approximately 3K of on-board SRAM, a LAN controller, and media
   58  * independent interface (MII) bus. The MII allows the ThunderLAN chip to
   59  * control up to 32 different physical interfaces (PHYs). The ThunderLAN
   60  * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
   61  * to act as a complete ethernet interface.
   62  *
   63  * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
   64  * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
   65  * in full or half duplex. Some of the Compaq Deskpro machines use a
   66  * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
   67  * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
   68  * concert with the ThunderLAN's internal PHY to provide full 10/100
   69  * support. This is cheaper than using a standalone external PHY for both
   70  * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
   71  * A serial EEPROM is also attached to the ThunderLAN chip to provide
   72  * power-up default register settings and for storing the adapter's
   73  * station address. Although not supported by this driver, the ThunderLAN
   74  * chip can also be connected to token ring PHYs.
   75  *
   76  * The ThunderLAN has a set of registers which can be used to issue
   77  * commands, acknowledge interrupts, and to manipulate other internal
   78  * registers on its DIO bus. The primary registers can be accessed
   79  * using either programmed I/O (inb/outb) or via PCI memory mapping,
   80  * depending on how the card is configured during the PCI probing
   81  * phase. It is even possible to have both PIO and memory mapped
   82  * access turned on at the same time.
   83  * 
   84  * Frame reception and transmission with the ThunderLAN chip is done
   85  * using frame 'lists.' A list structure looks more or less like this:
   86  *
   87  * struct tl_frag {
   88  *      u_int32_t               fragment_address;
   89  *      u_int32_t               fragment_size;
   90  * };
   91  * struct tl_list {
   92  *      u_int32_t               forward_pointer;
   93  *      u_int16_t               cstat;
   94  *      u_int16_t               frame_size;
   95  *      struct tl_frag          fragments[10];
   96  * };
   97  *
   98  * The forward pointer in the list header can be either a 0 or the address
   99  * of another list, which allows several lists to be linked together. Each
  100  * list contains up to 10 fragment descriptors. This means the chip allows
  101  * ethernet frames to be broken up into up to 10 chunks for transfer to
  102  * and from the SRAM. Note that the forward pointer and fragment buffer
  103  * addresses are physical memory addresses, not virtual. Note also that
  104  * a single ethernet frame can not span lists: if the host wants to
  105  * transmit a frame and the frame data is split up over more than 10
  106  * buffers, the frame has to collapsed before it can be transmitted.
  107  *
  108  * To receive frames, the driver sets up a number of lists and populates
  109  * the fragment descriptors, then it sends an RX GO command to the chip.
  110  * When a frame is received, the chip will DMA it into the memory regions
  111  * specified by the fragment descriptors and then trigger an RX 'end of
  112  * frame interrupt' when done. The driver may choose to use only one
  113  * fragment per list; this may result is slighltly less efficient use
  114  * of memory in exchange for improving performance.
  115  *
  116  * To transmit frames, the driver again sets up lists and fragment
  117  * descriptors, only this time the buffers contain frame data that
  118  * is to be DMA'ed into the chip instead of out of it. Once the chip
  119  * has transfered the data into its on-board SRAM, it will trigger a
  120  * TX 'end of frame' interrupt. It will also generate an 'end of channel'
  121  * interrupt when it reaches the end of the list.
  122  */
  123 
  124 /*
  125  * Some notes about this driver:
  126  *
  127  * The ThunderLAN chip provides a couple of different ways to organize
  128  * reception, transmission and interrupt handling. The simplest approach
  129  * is to use one list each for transmission and reception. In this mode,
  130  * the ThunderLAN will generate two interrupts for every received frame
  131  * (one RX EOF and one RX EOC) and two for each transmitted frame (one
  132  * TX EOF and one TX EOC). This may make the driver simpler but it hurts
  133  * performance to have to handle so many interrupts.
  134  *
  135  * Initially I wanted to create a circular list of receive buffers so
  136  * that the ThunderLAN chip would think there was an infinitely long
  137  * receive channel and never deliver an RXEOC interrupt. However this
  138  * doesn't work correctly under heavy load: while the manual says the
  139  * chip will trigger an RXEOF interrupt each time a frame is copied into
  140  * memory, you can't count on the chip waiting around for you to acknowledge
  141  * the interrupt before it starts trying to DMA the next frame. The result
  142  * is that the chip might traverse the entire circular list and then wrap
  143  * around before you have a chance to do anything about it. Consequently,
  144  * the receive list is terminated (with a 0 in the forward pointer in the
  145  * last element). Each time an RXEOF interrupt arrives, the used list
  146  * is shifted to the end of the list. This gives the appearance of an
  147  * infinitely large RX chain so long as the driver doesn't fall behind
  148  * the chip and allow all of the lists to be filled up.
  149  *
  150  * If all the lists are filled, the adapter will deliver an RX 'end of
  151  * channel' interrupt when it hits the 0 forward pointer at the end of
  152  * the chain. The RXEOC handler then cleans out the RX chain and resets
  153  * the list head pointer in the ch_parm register and restarts the receiver.
  154  *
  155  * For frame transmission, it is possible to program the ThunderLAN's
  156  * transmit interrupt threshold so that the chip can acknowledge multiple
  157  * lists with only a single TX EOF interrupt. This allows the driver to
  158  * queue several frames in one shot, and only have to handle a total
  159  * two interrupts (one TX EOF and one TX EOC) no matter how many frames
  160  * are transmitted. Frame transmission is done directly out of the
  161  * mbufs passed to the tl_start() routine via the interface send queue.
  162  * The driver simply sets up the fragment descriptors in the transmit
  163  * lists to point to the mbuf data regions and sends a TX GO command.
  164  *
  165  * Note that since the RX and TX lists themselves are always used
  166  * only by the driver, the are malloc()ed once at driver initialization
  167  * time and never free()ed.
  168  *
  169  * Also, in order to remain as platform independent as possible, this
  170  * driver uses memory mapped register access to manipulate the card
  171  * as opposed to programmed I/O. This avoids the use of the inb/outb
  172  * (and related) instructions which are specific to the i386 platform.
  173  *
  174  * Using these techniques, this driver achieves very high performance
  175  * by minimizing the amount of interrupts generated during large
  176  * transfers and by completely avoiding buffer copies. Frame transfer
  177  * to and from the ThunderLAN chip is performed entirely by the chip
  178  * itself thereby reducing the load on the host CPU.
  179  */
  180 
  181 #include "bpfilter.h"
  182 
  183 #include <sys/param.h>
  184 #include <sys/systm.h>
  185 #include <sys/sockio.h>
  186 #include <sys/mbuf.h>
  187 #include <sys/malloc.h>
  188 #include <sys/kernel.h>
  189 #include <sys/socket.h>
  190 #include <sys/syslog.h>
  191 
  192 #include <net/if.h>
  193 #include <net/if_arp.h>
  194 #include <net/ethernet.h>
  195 #include <net/if_dl.h>
  196 #include <net/if_mib.h>
  197 #include <net/if_media.h>
  198 #include <net/if_types.h>
  199 
  200 #ifdef INET
  201 #include <netinet/in.h>
  202 #include <netinet/in_systm.h>
  203 #include <netinet/in_var.h>
  204 #include <netinet/ip.h>
  205 #include <netinet/if_ether.h>
  206 #endif
  207 
  208 #ifdef IPX
  209 #include <netipx/ipx.h>
  210 #include <netipx/ipx_if.h>
  211 #endif
  212 
  213 #ifdef NS
  214 #include <netns/ns.h>
  215 #include <netns/ns_if.h>
  216 #endif
  217 
  218 #if NBPFILTER > 0
  219 #include <net/bpf.h>
  220 #include <net/bpfdesc.h>
  221 #endif
  222 
  223 #include <vm/vm.h>              /* for vtophys */
  224 #include <vm/vm_param.h>        /* for vtophys */
  225 #include <vm/pmap.h>            /* for vtophys */
  226 #include <machine/clock.h>      /* for DELAY */
  227 
  228 #include <pci/pcireg.h>
  229 #include <pci/pcivar.h>
  230 
  231 /*
  232  * Default to using PIO register access mode to pacify certain
  233  * laptop docking stations with built-in ThunderLAN chips that
  234  * don't seem to handle memory mapped mode properly.
  235  */
  236 #define TL_USEIOSPACE
  237 
  238 /* #define TL_BACKGROUND_AUTONEG */
  239 
  240 #include <pci/if_tlreg.h>
  241 
  242 #if !defined(lint)
  243 static const char rcsid[] =
  244   "$FreeBSD: src/sys/pci/if_tl.c,v 1.16.2.10 1999/09/05 08:21:10 peter Exp $";
  245 #endif
  246 
  247 #ifdef TL_DEBUG
  248 #define EV_TXEOC 2
  249 #define EV_TXEOF 3
  250 #define EV_RXEOC 4
  251 #define EV_RXEOF 5
  252 #define EV_START_TX 6
  253 #define EV_START_Q 7
  254 #define EV_SETMODE 8
  255 #define EV_AUTONEG_XMIT 9
  256 #define EV_AUTONEG_FIN 10
  257 #define EV_START_TX_REAL 11
  258 #define EV_WATCHDOG 12
  259 #define EV_INIT 13
  260 
  261 static void evset(sc, e)
  262         struct tl_softc         *sc;
  263         int                     e;
  264 {
  265         int                     i;
  266 
  267         for (i = 19; i > 0; i--)
  268                 sc->tl_event[i] = sc->tl_event[i - 1];
  269         sc->tl_event[0] = e;
  270 
  271         return;
  272 }
  273 
  274 static void evshow(sc)
  275         struct tl_softc         *sc;
  276 {
  277         int                     i;
  278 
  279         printf("tl%d: events: ", sc->tl_unit);
  280         for (i = 0; i < 20; i++)
  281                 printf(" %d", sc->tl_event[i]);
  282         printf("\n");
  283 
  284         return;
  285 }
  286 #endif
  287 
  288 /*
  289  * Various supported device vendors/types and their names.
  290  */
  291 
  292 static struct tl_type tl_devs[] = {
  293         { TI_VENDORID,  TI_DEVICEID_THUNDERLAN,
  294                 "Texas Instruments ThunderLAN" },
  295         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
  296                 "Compaq Netelligent 10" },
  297         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
  298                 "Compaq Netelligent 10/100" },
  299         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
  300                 "Compaq Netelligent 10/100 Proliant" },
  301         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
  302                 "Compaq Netelligent 10/100 Dual Port" },
  303         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
  304                 "Compaq NetFlex-3/P Integrated" },
  305         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
  306                 "Compaq NetFlex-3/P" },
  307         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
  308                 "Compaq NetFlex 3/P w/ BNC" },
  309         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
  310                 "Compaq Netelligent 10/100 TX Embedded UTP" },
  311         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
  312                 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
  313         { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
  314                 "Compaq Netelligent 10/100 TX UTP" },
  315         { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
  316                 "Olicom OC-2183/2185" },
  317         { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
  318                 "Olicom OC-2325" },
  319         { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
  320                 "Olicom OC-2326 10/100 TX UTP" },
  321         { 0, 0, NULL }
  322 };
  323 
  324 /*
  325  * Various supported PHY vendors/types and their names. Note that
  326  * this driver will work with pretty much any MII-compliant PHY,
  327  * so failure to positively identify the chip is not a fatal error.
  328  */
  329 
  330 static struct tl_type tl_phys[] = {
  331         { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
  332         { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
  333         { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
  334         { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 
  335         { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
  336         { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
  337         { 0, 0, "<MII-compliant physical interface>" }
  338 };
  339 
  340 static unsigned long            tl_count;
  341 
  342 static char *tl_probe           __P((pcici_t, pcidi_t));
  343 static void tl_attach           __P((pcici_t, int));
  344 static int tl_attach_phy        __P((struct tl_softc *));
  345 static int tl_intvec_rxeoc      __P((void *, u_int32_t));
  346 static int tl_intvec_txeoc      __P((void *, u_int32_t));
  347 static int tl_intvec_txeof      __P((void *, u_int32_t));
  348 static int tl_intvec_rxeof      __P((void *, u_int32_t));
  349 static int tl_intvec_adchk      __P((void *, u_int32_t));
  350 static int tl_intvec_netsts     __P((void *, u_int32_t));
  351 
  352 static int tl_newbuf            __P((struct tl_softc *,
  353                                         struct tl_chain_onefrag *));
  354 static void tl_stats_update     __P((void *));
  355 static int tl_encap             __P((struct tl_softc *, struct tl_chain *,
  356                                                 struct mbuf *));
  357 
  358 static void tl_intr             __P((void *));
  359 static void tl_start            __P((struct ifnet *));
  360 static int tl_ioctl             __P((struct ifnet *, int, caddr_t));
  361 static void tl_init             __P((void *));
  362 static void tl_stop             __P((struct tl_softc *));
  363 static void tl_watchdog         __P((struct ifnet *));
  364 static void tl_shutdown         __P((int, void *));
  365 static int tl_ifmedia_upd       __P((struct ifnet *));
  366 static void tl_ifmedia_sts      __P((struct ifnet *, struct ifmediareq *));
  367 
  368 static u_int8_t tl_eeprom_putbyte       __P((struct tl_softc *, int));
  369 static u_int8_t tl_eeprom_getbyte       __P((struct tl_softc *,
  370                                                 int, u_int8_t *));
  371 static int tl_read_eeprom       __P((struct tl_softc *, caddr_t, int, int));
  372 
  373 static void tl_mii_sync         __P((struct tl_softc *));
  374 static void tl_mii_send         __P((struct tl_softc *, u_int32_t, int));
  375 static int tl_mii_readreg       __P((struct tl_softc *, struct tl_mii_frame *));
  376 static int tl_mii_writereg      __P((struct tl_softc *, struct tl_mii_frame *));
  377 static u_int16_t tl_phy_readreg __P((struct tl_softc *, int));
  378 static void tl_phy_writereg     __P((struct tl_softc *, int, int));
  379 
  380 static void tl_autoneg          __P((struct tl_softc *, int, int));
  381 static void tl_setmode          __P((struct tl_softc *, int));
  382 static int tl_calchash          __P((caddr_t));
  383 static void tl_setmulti         __P((struct tl_softc *));
  384 static void tl_setfilt          __P((struct tl_softc *, caddr_t, int));
  385 static void tl_softreset        __P((struct tl_softc *, int));
  386 static void tl_hardreset        __P((struct tl_softc *));
  387 static int tl_list_rx_init      __P((struct tl_softc *));
  388 static int tl_list_tx_init      __P((struct tl_softc *));
  389 
  390 static u_int8_t tl_dio_read8    __P((struct tl_softc *, int));
  391 static u_int16_t tl_dio_read16  __P((struct tl_softc *, int));
  392 static u_int32_t tl_dio_read32  __P((struct tl_softc *, int));
  393 static void tl_dio_write8       __P((struct tl_softc *, int, int));
  394 static void tl_dio_write16      __P((struct tl_softc *, int, int));
  395 static void tl_dio_write32      __P((struct tl_softc *, int, int));
  396 static void tl_dio_setbit       __P((struct tl_softc *, int, int));
  397 static void tl_dio_clrbit       __P((struct tl_softc *, int, int));
  398 static void tl_dio_setbit16     __P((struct tl_softc *, int, int));
  399 static void tl_dio_clrbit16     __P((struct tl_softc *, int, int));
  400 
  401 static u_int8_t tl_dio_read8(sc, reg)
  402         struct tl_softc         *sc;
  403         int                     reg;
  404 {
  405         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  406         return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
  407 }
  408 
  409 static u_int16_t tl_dio_read16(sc, reg)
  410         struct tl_softc         *sc;
  411         int                     reg;
  412 {
  413         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  414         return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
  415 }
  416 
  417 static u_int32_t tl_dio_read32(sc, reg)
  418         struct tl_softc         *sc;
  419         int                     reg;
  420 {
  421         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  422         return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
  423 }
  424 
  425 static void tl_dio_write8(sc, reg, val)
  426         struct tl_softc         *sc;
  427         int                     reg;
  428         int                     val;
  429 {
  430         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  431         CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
  432         return;
  433 }
  434 
  435 static void tl_dio_write16(sc, reg, val)
  436         struct tl_softc         *sc;
  437         int                     reg;
  438         int                     val;
  439 {
  440         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  441         CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
  442         return;
  443 }
  444 
  445 static void tl_dio_write32(sc, reg, val)
  446         struct tl_softc         *sc;
  447         int                     reg;
  448         int                     val;
  449 {
  450         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  451         CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
  452         return;
  453 }
  454 
  455 static void tl_dio_setbit(sc, reg, bit)
  456         struct tl_softc         *sc;
  457         int                     reg;
  458         int                     bit;
  459 {
  460         u_int8_t                        f;
  461 
  462         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  463         f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
  464         f |= bit;
  465         CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
  466 
  467         return;
  468 }
  469 
  470 static void tl_dio_clrbit(sc, reg, bit)
  471         struct tl_softc         *sc;
  472         int                     reg;
  473         int                     bit;
  474 {
  475         u_int8_t                        f;
  476 
  477         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  478         f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
  479         f &= ~bit;
  480         CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
  481 
  482         return;
  483 }
  484 
  485 static void tl_dio_setbit16(sc, reg, bit)
  486         struct tl_softc         *sc;
  487         int                     reg;
  488         int                     bit;
  489 {
  490         u_int16_t                       f;
  491 
  492         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  493         f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
  494         f |= bit;
  495         CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
  496 
  497         return;
  498 }
  499 
  500 static void tl_dio_clrbit16(sc, reg, bit)
  501         struct tl_softc         *sc;
  502         int                     reg;
  503         int                     bit;
  504 {
  505         u_int16_t                       f;
  506 
  507         CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
  508         f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
  509         f &= ~bit;
  510         CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
  511 
  512         return;
  513 }
  514 
  515 /*
  516  * Send an instruction or address to the EEPROM, check for ACK.
  517  */
  518 static u_int8_t tl_eeprom_putbyte(sc, byte)
  519         struct tl_softc         *sc;
  520         int                     byte;
  521 {
  522         register int            i, ack = 0;
  523 
  524         /*
  525          * Make sure we're in TX mode.
  526          */
  527         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
  528 
  529         /*
  530          * Feed in each bit and stobe the clock.
  531          */
  532         for (i = 0x80; i; i >>= 1) {
  533                 if (byte & i) {
  534                         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
  535                 } else {
  536                         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
  537                 }
  538                 DELAY(1);
  539                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  540                 DELAY(1);
  541                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  542         }
  543 
  544         /*
  545          * Turn off TX mode.
  546          */
  547         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
  548 
  549         /*
  550          * Check for ack.
  551          */
  552         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  553         ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
  554         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  555 
  556         return(ack);
  557 }
  558 
  559 /*
  560  * Read a byte of data stored in the EEPROM at address 'addr.'
  561  */
  562 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
  563         struct tl_softc         *sc;
  564         int                     addr;
  565         u_int8_t                *dest;
  566 {
  567         register int            i;
  568         u_int8_t                byte = 0;
  569 
  570         tl_dio_write8(sc, TL_NETSIO, 0);
  571 
  572         EEPROM_START;
  573 
  574         /*
  575          * Send write control code to EEPROM.
  576          */
  577         if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
  578                 printf("tl%d: failed to send write command, status: %x\n",
  579                                 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
  580                 return(1);
  581         }
  582 
  583         /*
  584          * Send address of byte we want to read.
  585          */
  586         if (tl_eeprom_putbyte(sc, addr)) {
  587                 printf("tl%d: failed to send address, status: %x\n",
  588                                 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
  589                 return(1);
  590         }
  591 
  592         EEPROM_STOP;
  593         EEPROM_START;
  594         /*
  595          * Send read control code to EEPROM.
  596          */
  597         if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
  598                 printf("tl%d: failed to send write command, status: %x\n",
  599                                 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
  600                 return(1);
  601         }
  602 
  603         /*
  604          * Start reading bits from EEPROM.
  605          */
  606         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
  607         for (i = 0x80; i; i >>= 1) {
  608                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  609                 DELAY(1);
  610                 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
  611                         byte |= i;
  612                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
  613                 DELAY(1);
  614         }
  615 
  616         EEPROM_STOP;
  617 
  618         /*
  619          * No ACK generated for read, so just return byte.
  620          */
  621 
  622         *dest = byte;
  623 
  624         return(0);
  625 }
  626 
  627 /*
  628  * Read a sequence of bytes from the EEPROM.
  629  */
  630 static int tl_read_eeprom(sc, dest, off, cnt)
  631         struct tl_softc         *sc;
  632         caddr_t                 dest;
  633         int                     off;
  634         int                     cnt;
  635 {
  636         int                     err = 0, i;
  637         u_int8_t                byte = 0;
  638 
  639         for (i = 0; i < cnt; i++) {
  640                 err = tl_eeprom_getbyte(sc, off + i, &byte);
  641                 if (err)
  642                         break;
  643                 *(dest + i) = byte;
  644         }
  645 
  646         return(err ? 1 : 0);
  647 }
  648 
  649 static void tl_mii_sync(sc)
  650         struct tl_softc         *sc;
  651 {
  652         register int            i;
  653 
  654         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  655 
  656         for (i = 0; i < 32; i++) {
  657                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  658                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  659         }
  660 
  661         return;
  662 }
  663 
  664 static void tl_mii_send(sc, bits, cnt)
  665         struct tl_softc         *sc;
  666         u_int32_t               bits;
  667         int                     cnt;
  668 {
  669         int                     i;
  670 
  671         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  672                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  673                 if (bits & i) {
  674                         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
  675                 } else {
  676                         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
  677                 }
  678                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  679         }
  680 }
  681 
  682 static int tl_mii_readreg(sc, frame)
  683         struct tl_softc         *sc;
  684         struct tl_mii_frame     *frame;
  685         
  686 {
  687         int                     i, ack, s;
  688         int                     minten = 0;
  689 
  690         s = splimp();
  691 
  692         tl_mii_sync(sc);
  693 
  694         /*
  695          * Set up frame for RX.
  696          */
  697         frame->mii_stdelim = TL_MII_STARTDELIM;
  698         frame->mii_opcode = TL_MII_READOP;
  699         frame->mii_turnaround = 0;
  700         frame->mii_data = 0;
  701         
  702         /*
  703          * Turn off MII interrupt by forcing MINTEN low.
  704          */
  705         minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
  706         if (minten) {
  707                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  708         }
  709 
  710         /*
  711          * Turn on data xmit.
  712          */
  713         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  714 
  715         /*
  716          * Send command/address info.
  717          */
  718         tl_mii_send(sc, frame->mii_stdelim, 2);
  719         tl_mii_send(sc, frame->mii_opcode, 2);
  720         tl_mii_send(sc, frame->mii_phyaddr, 5);
  721         tl_mii_send(sc, frame->mii_regaddr, 5);
  722 
  723         /*
  724          * Turn off xmit.
  725          */
  726         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  727 
  728         /* Idle bit */
  729         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  730         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  731 
  732         /* Check for ack */
  733         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  734         ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
  735 
  736         /* Complete the cycle */
  737         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  738 
  739         /*
  740          * Now try reading data bits. If the ack failed, we still
  741          * need to clock through 16 cycles to keep the PHYs in sync.
  742          */
  743         if (ack) {
  744                 for(i = 0; i < 16; i++) {
  745                         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  746                         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  747                 }
  748                 goto fail;
  749         }
  750 
  751         for (i = 0x8000; i; i >>= 1) {
  752                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  753                 if (!ack) {
  754                         if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
  755                                 frame->mii_data |= i;
  756                 }
  757                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  758         }
  759 
  760 fail:
  761 
  762         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  763         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  764 
  765         /* Reenable interrupts */
  766         if (minten) {
  767                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  768         }
  769 
  770         splx(s);
  771 
  772         if (ack)
  773                 return(1);
  774         return(0);
  775 }
  776 
  777 static int tl_mii_writereg(sc, frame)
  778         struct tl_softc         *sc;
  779         struct tl_mii_frame     *frame;
  780         
  781 {
  782         int                     s;
  783         int                     minten;
  784 
  785         tl_mii_sync(sc);
  786 
  787         s = splimp();
  788         /*
  789          * Set up frame for TX.
  790          */
  791 
  792         frame->mii_stdelim = TL_MII_STARTDELIM;
  793         frame->mii_opcode = TL_MII_WRITEOP;
  794         frame->mii_turnaround = TL_MII_TURNAROUND;
  795         
  796         /*
  797          * Turn off MII interrupt by forcing MINTEN low.
  798          */
  799         minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
  800         if (minten) {
  801                 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  802         }
  803 
  804         /*
  805          * Turn on data output.
  806          */
  807         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  808 
  809         tl_mii_send(sc, frame->mii_stdelim, 2);
  810         tl_mii_send(sc, frame->mii_opcode, 2);
  811         tl_mii_send(sc, frame->mii_phyaddr, 5);
  812         tl_mii_send(sc, frame->mii_regaddr, 5);
  813         tl_mii_send(sc, frame->mii_turnaround, 2);
  814         tl_mii_send(sc, frame->mii_data, 16);
  815 
  816         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
  817         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
  818 
  819         /*
  820          * Turn off xmit.
  821          */
  822         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
  823 
  824         /* Reenable interrupts */
  825         if (minten)
  826                 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  827 
  828         splx(s);
  829 
  830         return(0);
  831 }
  832 
  833 static u_int16_t tl_phy_readreg(sc, reg)
  834         struct tl_softc         *sc;
  835         int                     reg;
  836 {
  837         struct tl_mii_frame     frame;
  838 
  839         bzero((char *)&frame, sizeof(frame));
  840 
  841         frame.mii_phyaddr = sc->tl_phy_addr;
  842         frame.mii_regaddr = reg;
  843         tl_mii_readreg(sc, &frame);
  844 
  845         /* Reenable MII interrupts, just in case. */
  846         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  847 
  848         return(frame.mii_data);
  849 }
  850 
  851 static void tl_phy_writereg(sc, reg, data)
  852         struct tl_softc         *sc;
  853         int                     reg;
  854         int                     data;
  855 {
  856         struct tl_mii_frame     frame;
  857 
  858         bzero((char *)&frame, sizeof(frame));
  859 
  860         frame.mii_phyaddr = sc->tl_phy_addr;
  861         frame.mii_regaddr = reg;
  862         frame.mii_data = data;
  863 
  864         tl_mii_writereg(sc, &frame);
  865 
  866         /* Reenable MII interrupts, just in case. */
  867         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
  868 
  869         return;
  870 }
  871 
  872 /*
  873  * Initiate autonegotiation with a link partner.
  874  *
  875  * Note that the Texas Instruments ThunderLAN programmer's guide
  876  * fails to mention one very important point about autonegotiation.
  877  * Autonegotiation is done largely by the PHY, independent of the
  878  * ThunderLAN chip itself: the PHY sets the flags in the BMCR
  879  * register to indicate what modes were selected and if link status
  880  * is good. In fact, the PHY does pretty much all of the work itself,
  881  * except for one small detail.
  882  *
  883  * The PHY may negotiate a full-duplex of half-duplex link, and set
  884  * the PHY_BMCR_DUPLEX bit accordingly, but the ThunderLAN's 'NetCommand'
  885  * register _also_ has a half-duplex/full-duplex bit, and you MUST ALSO
  886  * SET THIS BIT MANUALLY TO CORRESPOND TO THE MODE SELECTED FOR THE PHY!
  887  * In other words, both the ThunderLAN chip and the PHY have to be
  888  * programmed for full-duplex mode in order for full-duplex to actually
  889  * work. So in order for autonegotiation to really work right, we have
  890  * to wait for the link to come up, check the BMCR register, then set
  891  * the ThunderLAN for full or half-duplex as needed.
  892  *
  893  * I struggled for two days to figure this out, so I'm making a point
  894  * of drawing attention to this fact. I think it's very strange that
  895  * the ThunderLAN doesn't automagically track the duplex state of the
  896  * PHY, but there you have it.
  897  *
  898  * Also when, using a National Semiconductor DP83840A PHY, we have to
  899  * allow a full three seconds for autonegotiation to complete. So what
  900  * we do is flip the autonegotiation restart bit, then set a timeout
  901  * to wake us up in three seconds to check the link state.
  902  *
  903  * Note that there are some versions of the Olicom 2326 that use a
  904  * Micro Linear ML6692 100BaseTX PHY. This particular PHY is designed
  905  * to provide 100BaseTX support only, but can be used with a controller
  906  * that supports an internal 10Mbps PHY to provide a complete
  907  * 10/100Mbps solution. However, the ML6692 does not have vendor and
  908  * device ID registers, and hence always shows up with a vendor/device
  909  * ID of 0.
  910  *
  911  * We detect this configuration by checking the phy vendor ID in the
  912  * softc structure. If it's a zero, and we're negotiating a high-speed
  913  * mode, then we turn off the internal PHY. If it's a zero and we've
  914  * negotiated a high-speed mode, we turn on the internal PHY. Note
  915  * that to make things even more fun, we have to make extra sure that
  916  * the loopback bit in the internal PHY's control register is turned
  917  * off.
  918  */
  919 static void tl_autoneg(sc, flag, verbose)
  920         struct tl_softc         *sc;
  921         int                     flag;
  922         int                     verbose;
  923 {
  924         u_int16_t               phy_sts = 0, media = 0, advert, ability;
  925         struct ifnet            *ifp;
  926         struct ifmedia          *ifm;
  927 
  928         ifm = &sc->ifmedia;
  929         ifp = &sc->arpcom.ac_if;
  930 
  931         /*
  932          * First, see if autoneg is supported. If not, there's
  933          * no point in continuing.
  934          */
  935         phy_sts = tl_phy_readreg(sc, PHY_BMSR);
  936         if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
  937                 if (verbose)
  938                         printf("tl%d: autonegotiation not supported\n",
  939                                                         sc->tl_unit);
  940                 return;
  941         }
  942 
  943         switch (flag) {
  944         case TL_FLAG_FORCEDELAY:
  945                 /*
  946                  * XXX Never use this option anywhere but in the probe
  947                  * routine: making the kernel stop dead in its tracks
  948                  * for three whole seconds after we've gone multi-user
  949                  * is really bad manners.
  950                  */
  951                 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
  952                 DELAY(500);
  953                 phy_sts = tl_phy_readreg(sc, PHY_BMCR);
  954                 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
  955                 tl_phy_writereg(sc, PHY_BMCR, phy_sts);
  956                 DELAY(5000000);
  957                 break;
  958         case TL_FLAG_SCHEDDELAY:
  959 #ifdef TL_DEBUG
  960                 evset(sc, EV_AUTONEG_XMIT);
  961 #endif
  962                 /*
  963                  * Wait for the transmitter to go idle before starting
  964                  * an autoneg session, otherwise tl_start() may clobber
  965                  * our timeout, and we don't want to allow transmission
  966                  * during an autoneg session since that can screw it up.
  967                  */
  968                 if (!sc->tl_txeoc) {
  969                         sc->tl_want_auto = 1;
  970                         return;
  971                 }
  972                 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
  973                 DELAY(500);
  974                 phy_sts = tl_phy_readreg(sc, PHY_BMCR);
  975                 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
  976                 tl_phy_writereg(sc, PHY_BMCR, phy_sts);
  977                 ifp->if_timer = 5;
  978                 sc->tl_autoneg = 1;
  979                 sc->tl_want_auto = 0;
  980                 return;
  981         case TL_FLAG_DELAYTIMEO:
  982 #ifdef TL_DEBUG
  983                 evset(sc, EV_AUTONEG_FIN);
  984 #endif
  985                 ifp->if_timer = 0;
  986                 sc->tl_autoneg = 0;
  987                 break;
  988         default:
  989                 printf("tl%d: invalid autoneg flag: %d\n", sc->tl_unit, flag);
  990                 return;
  991         }
  992 
  993         /*
  994          * Read the BMSR register twice: the LINKSTAT bit is a
  995          * latching bit.
  996          */
  997         tl_phy_readreg(sc, PHY_BMSR);
  998         phy_sts = tl_phy_readreg(sc, PHY_BMSR);
  999         if (phy_sts & PHY_BMSR_AUTONEGCOMP) {
 1000                 if (verbose)
 1001                         printf("tl%d: autoneg complete, ", sc->tl_unit);
 1002                 phy_sts = tl_phy_readreg(sc, PHY_BMSR);
 1003         } else {
 1004                 if (verbose)
 1005                         printf("tl%d: autoneg not complete, ", sc->tl_unit);
 1006         }
 1007 
 1008         /* Link is good. Report modes and set duplex mode. */
 1009         if (phy_sts & PHY_BMSR_LINKSTAT) {
 1010                 if (verbose)
 1011                         printf("link status good ");
 1012 
 1013                 advert = tl_phy_readreg(sc, TL_PHY_ANAR);
 1014                 ability = tl_phy_readreg(sc, TL_PHY_LPAR);
 1015                 media = tl_phy_readreg(sc, PHY_BMCR);
 1016 
 1017                 /*
 1018                  * Be sure to turn off the ISOLATE and
 1019                  * LOOPBACK bits in the control register,
 1020                  * otherwise we may not be able to communicate.
 1021                  */
 1022                 media &= ~(PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE);
 1023                 /* Set the DUPLEX bit in the NetCmd register accordingly. */
 1024                 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
 1025                         ifm->ifm_media = IFM_ETHER|IFM_100_T4;
 1026                         media |= PHY_BMCR_SPEEDSEL;
 1027                         media &= ~PHY_BMCR_DUPLEX;
 1028                         if (verbose)
 1029                                 printf("(100baseT4)\n");
 1030                 } else if (advert & PHY_ANAR_100BTXFULL &&
 1031                         ability & PHY_ANAR_100BTXFULL) {
 1032                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
 1033                         media |= PHY_BMCR_SPEEDSEL;
 1034                         media |= PHY_BMCR_DUPLEX;
 1035                         if (verbose)
 1036                                 printf("(full-duplex, 100Mbps)\n");
 1037                 } else if (advert & PHY_ANAR_100BTXHALF &&
 1038                         ability & PHY_ANAR_100BTXHALF) {
 1039                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
 1040                         media |= PHY_BMCR_SPEEDSEL;
 1041                         media &= ~PHY_BMCR_DUPLEX;
 1042                         if (verbose)
 1043                                 printf("(half-duplex, 100Mbps)\n");
 1044                 } else if (advert & PHY_ANAR_10BTFULL &&
 1045                         ability & PHY_ANAR_10BTFULL) {
 1046                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
 1047                         media &= ~PHY_BMCR_SPEEDSEL;
 1048                         media |= PHY_BMCR_DUPLEX;
 1049                         if (verbose)
 1050                                 printf("(full-duplex, 10Mbps)\n");
 1051                 } else {
 1052                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
 1053                         media &= ~PHY_BMCR_SPEEDSEL;
 1054                         media &= ~PHY_BMCR_DUPLEX;
 1055                         if (verbose)
 1056                                 printf("(half-duplex, 10Mbps)\n");
 1057                 }
 1058 
 1059                 if (media & PHY_BMCR_DUPLEX)
 1060                         tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
 1061                 else
 1062                         tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
 1063 
 1064                 media &= ~PHY_BMCR_AUTONEGENBL;
 1065                 tl_phy_writereg(sc, PHY_BMCR, media);
 1066         } else {
 1067                 if (verbose)
 1068                         printf("no carrier\n");
 1069         }
 1070 
 1071         tl_init(sc);
 1072 
 1073         if (sc->tl_tx_pend) {
 1074                 sc->tl_autoneg = 0;
 1075                 sc->tl_tx_pend = 0;
 1076                 tl_start(ifp);
 1077         }
 1078 
 1079         return;
 1080 }
 1081 
 1082 /*
 1083  * Set speed and duplex mode. Also program autoneg advertisements
 1084  * accordingly.
 1085  */
 1086 static void tl_setmode(sc, media)
 1087         struct tl_softc         *sc;
 1088         int                     media;
 1089 {
 1090         u_int16_t               bmcr;
 1091 
 1092         bmcr = tl_phy_readreg(sc, PHY_BMCR);
 1093 
 1094         bmcr &= ~(PHY_BMCR_SPEEDSEL|PHY_BMCR_DUPLEX|PHY_BMCR_AUTONEGENBL|
 1095                   PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE);
 1096 
 1097         if (IFM_SUBTYPE(media) == IFM_LOOP)
 1098                 bmcr |= PHY_BMCR_LOOPBK;
 1099 
 1100         if (IFM_SUBTYPE(media) == IFM_AUTO)
 1101                 bmcr |= PHY_BMCR_AUTONEGENBL;
 1102 
 1103         /*
 1104          * The ThunderLAN's internal PHY has an AUI transceiver
 1105          * that can be selected. This is usually attached to a
 1106          * 10base2/BNC port. In order to activate this port, we
 1107          * have to set the AUISEL bit in the internal PHY's
 1108          * special control register.
 1109          */
 1110         if (IFM_SUBTYPE(media) == IFM_10_5) {
 1111                 u_int16_t               addr, ctl;
 1112                 addr = sc->tl_phy_addr;
 1113                 sc->tl_phy_addr = TL_PHYADDR_MAX;
 1114                 ctl = tl_phy_readreg(sc, TL_PHY_CTL);
 1115                 ctl |= PHY_CTL_AUISEL;
 1116                 tl_phy_writereg(sc, TL_PHY_CTL, ctl);
 1117                 tl_phy_writereg(sc, PHY_BMCR, bmcr);
 1118                 sc->tl_phy_addr = addr;
 1119                 bmcr |= PHY_BMCR_ISOLATE;
 1120         } else {
 1121                 u_int16_t               addr, ctl;
 1122                 addr = sc->tl_phy_addr;
 1123                 sc->tl_phy_addr = TL_PHYADDR_MAX;
 1124                 ctl = tl_phy_readreg(sc, TL_PHY_CTL);
 1125                 ctl &= ~PHY_CTL_AUISEL;
 1126                 tl_phy_writereg(sc, TL_PHY_CTL, ctl);
 1127                 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE);
 1128                 sc->tl_phy_addr = addr;
 1129                 bmcr &= ~PHY_BMCR_ISOLATE;
 1130         }
 1131 
 1132         if (IFM_SUBTYPE(media) == IFM_100_TX) {
 1133                 bmcr |= PHY_BMCR_SPEEDSEL;
 1134                 if ((media & IFM_GMASK) == IFM_FDX) {
 1135                         bmcr |= PHY_BMCR_DUPLEX;
 1136                         tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
 1137                 } else {
 1138                         bmcr &= ~PHY_BMCR_DUPLEX;
 1139                         tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
 1140                 }
 1141         }
 1142 
 1143         if (IFM_SUBTYPE(media) == IFM_10_T) {
 1144                 bmcr &= ~PHY_BMCR_SPEEDSEL;
 1145                 if ((media & IFM_GMASK) == IFM_FDX) {
 1146                         bmcr |= PHY_BMCR_DUPLEX;
 1147                         tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
 1148                 } else {
 1149                         bmcr &= ~PHY_BMCR_DUPLEX;
 1150                         tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
 1151                 }
 1152         }
 1153 
 1154         tl_phy_writereg(sc, PHY_BMCR, bmcr);
 1155 
 1156         tl_init(sc);
 1157 
 1158         return;
 1159 }
 1160 
 1161 /*
 1162  * Calculate the hash of a MAC address for programming the multicast hash
 1163  * table.  This hash is simply the address split into 6-bit chunks
 1164  * XOR'd, e.g.
 1165  * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
 1166  * bit:  765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
 1167  * Bytes 0-2 and 3-5 are symmetrical, so are folded together.  Then
 1168  * the folded 24-bit value is split into 6-bit portions and XOR'd.
 1169  */
 1170 static int tl_calchash(addr)
 1171         caddr_t                 addr;
 1172 {
 1173         int                     t;
 1174 
 1175         t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
 1176                 (addr[2] ^ addr[5]);
 1177         return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
 1178 }
 1179 
 1180 /*
 1181  * The ThunderLAN has a perfect MAC address filter in addition to
 1182  * the multicast hash filter. The perfect filter can be programmed
 1183  * with up to four MAC addresses. The first one is always used to
 1184  * hold the station address, which leaves us free to use the other
 1185  * three for multicast addresses.
 1186  */
 1187 static void tl_setfilt(sc, addr, slot)
 1188         struct tl_softc         *sc;
 1189         caddr_t                 addr;
 1190         int                     slot;
 1191 {
 1192         int                     i;
 1193         u_int16_t               regaddr;
 1194 
 1195         regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
 1196 
 1197         for (i = 0; i < ETHER_ADDR_LEN; i++)
 1198                 tl_dio_write8(sc, regaddr + i, *(addr + i));
 1199 
 1200         return;
 1201 }
 1202 
 1203 static void tl_setmulti(sc)
 1204         struct tl_softc         *sc;
 1205 {
 1206         struct ifnet            *ifp;
 1207         u_int32_t               hashes[2] = { 0, 0 };
 1208         int                     h, i;
 1209         struct ether_multi      *enm;
 1210         struct ether_multistep  step;
 1211         u_int8_t                dummy[] = { 0, 0, 0, 0, 0, 0 };
 1212 
 1213         ifp = &sc->arpcom.ac_if;
 1214 
 1215         /* First, zot all the existing filters. */
 1216         for (i = 1; i < 4; i++)
 1217                 tl_setfilt(sc, (caddr_t)&dummy, i);
 1218         tl_dio_write32(sc, TL_HASH1, 0);
 1219         tl_dio_write32(sc, TL_HASH2, 0);
 1220 
 1221         /* Now program new ones. */
 1222         if (ifp->if_flags & IFF_ALLMULTI) {
 1223                 hashes[0] = 0xFFFFFFFF;
 1224                 hashes[1] = 0xFFFFFFFF;
 1225         } else {
 1226                 i = 1;
 1227                 ETHER_FIRST_MULTI(step, &sc->arpcom, enm);
 1228                 while(enm != NULL) {
 1229                         if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
 1230                                                 ETHER_ADDR_LEN)) {
 1231                                 hashes[0] = 0xFFFFFFFF;
 1232                                 hashes[1] = 0xFFFFFFFF;
 1233                                 break;
 1234                         } else {
 1235                                 /*
 1236                                  * Program the first three multicast groups
 1237                                  * into the perfect filter. For all others,
 1238                                  * use the hash table.
 1239                                  */
 1240                                 if (i < 4) {
 1241                                         tl_setfilt(sc, enm->enm_addrlo, i);
 1242                                         i++;
 1243                                         ETHER_NEXT_MULTI(step, enm);
 1244                                         continue;
 1245                                 }
 1246 
 1247                                 h = tl_calchash(enm->enm_addrlo);
 1248                                 if (h < 32)
 1249                                         hashes[0] |= (1 << h);
 1250                                 else
 1251                                         hashes[1] |= (1 << (h - 32));
 1252                         }
 1253                         ETHER_NEXT_MULTI(step, enm);
 1254                 }
 1255         }
 1256 
 1257         tl_dio_write32(sc, TL_HASH1, hashes[0]);
 1258         tl_dio_write32(sc, TL_HASH2, hashes[1]);
 1259 
 1260         return;
 1261 }
 1262 
 1263 /*
 1264  * This routine is recommended by the ThunderLAN manual to insure that
 1265  * the internal PHY is powered up correctly. It also recommends a one
 1266  * second pause at the end to 'wait for the clocks to start' but in my
 1267  * experience this isn't necessary.
 1268  */
 1269 static void tl_hardreset(sc)
 1270         struct tl_softc         *sc;
 1271 {
 1272         int                     i;
 1273         u_int16_t               old_addr, flags;
 1274 
 1275         old_addr = sc->tl_phy_addr;
 1276 
 1277         for (i = 0; i < TL_PHYADDR_MAX + 1; i++) {
 1278                 sc->tl_phy_addr = i;
 1279                 tl_mii_sync(sc);
 1280         }
 1281 
 1282         flags = PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE|PHY_BMCR_PWRDOWN;
 1283 
 1284         for (i = 0; i < TL_PHYADDR_MAX + 1; i++) {
 1285                 sc->tl_phy_addr = i;
 1286                 tl_phy_writereg(sc, PHY_BMCR, flags);
 1287         }
 1288 
 1289         sc->tl_phy_addr = TL_PHYADDR_MAX;
 1290         tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE);
 1291 
 1292         DELAY(50000);
 1293 
 1294         tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE);
 1295 
 1296         tl_mii_sync(sc);
 1297 
 1298         while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
 1299 
 1300         sc->tl_phy_addr = old_addr;
 1301 
 1302         return;
 1303 }
 1304 
 1305 static void tl_softreset(sc, internal)
 1306         struct tl_softc         *sc;
 1307         int                     internal;
 1308 {
 1309         u_int32_t               cmd, dummy, i;
 1310 
 1311         /* Assert the adapter reset bit. */
 1312         CMD_SET(sc, TL_CMD_ADRST);
 1313         /* Turn off interrupts */
 1314         CMD_SET(sc, TL_CMD_INTSOFF);
 1315 
 1316         /* First, clear the stats registers. */
 1317         for (i = 0; i < 5; i++)
 1318                 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
 1319 
 1320         /* Clear Areg and Hash registers */
 1321         for (i = 0; i < 8; i++)
 1322                 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
 1323 
 1324         /*
 1325          * Set up Netconfig register. Enable one channel and
 1326          * one fragment mode.
 1327          */
 1328         tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
 1329         if (internal) {
 1330                 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
 1331         } else {
 1332                 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
 1333         }
 1334 
 1335         /* Set PCI burst size */
 1336         tl_dio_write8(sc, TL_BSIZEREG, 0x33);
 1337 
 1338         /*
 1339          * Load adapter irq pacing timer and tx threshold.
 1340          * We make the transmit threshold 1 initially but we may
 1341          * change that later.
 1342          */
 1343         cmd = CSR_READ_4(sc, TL_HOSTCMD);
 1344         cmd |= TL_CMD_NES;
 1345         cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
 1346         CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
 1347         CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
 1348 
 1349         /* Unreset the MII */
 1350         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
 1351 
 1352         /* Clear status register */
 1353         tl_dio_setbit16(sc, TL_NETSTS, TL_STS_MIRQ);
 1354         tl_dio_setbit16(sc, TL_NETSTS, TL_STS_HBEAT);
 1355         tl_dio_setbit16(sc, TL_NETSTS, TL_STS_TXSTOP);
 1356         tl_dio_setbit16(sc, TL_NETSTS, TL_STS_RXSTOP);
 1357 
 1358         /* Enable network status interrupts for everything. */
 1359         tl_dio_setbit(sc, TL_NETMASK, TL_MASK_MASK7|TL_MASK_MASK6|
 1360                         TL_MASK_MASK5|TL_MASK_MASK4);
 1361 
 1362         /* Take the adapter out of reset */
 1363         tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
 1364 
 1365         /* Wait for things to settle down a little. */
 1366         DELAY(500);
 1367 
 1368         return;
 1369 }
 1370 
 1371 /*
 1372  * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
 1373  * against our list and return its name if we find a match.
 1374  */
 1375 static char *
 1376 tl_probe(config_id, device_id)
 1377         pcici_t                 config_id;
 1378         pcidi_t                 device_id;
 1379 {
 1380         struct tl_type          *t;
 1381 
 1382         t = tl_devs;
 1383 
 1384         while(t->tl_name != NULL) {
 1385                 if ((device_id & 0xFFFF) == t->tl_vid &&
 1386                     ((device_id >> 16) & 0xFFFF) == t->tl_did)
 1387                         return(t->tl_name);
 1388                 t++;
 1389         }
 1390 
 1391         return(NULL);
 1392 }
 1393 
 1394 /*
 1395  * Do the interface setup and attach for a PHY on a particular
 1396  * ThunderLAN chip. Also also set up interrupt vectors.
 1397  */ 
 1398 static int tl_attach_phy(sc)
 1399         struct tl_softc         *sc;
 1400 {
 1401         int                     phy_ctl;
 1402         struct tl_type          *p = tl_phys;
 1403         int                     media = IFM_ETHER|IFM_100_TX|IFM_FDX;
 1404         struct ifnet            *ifp;
 1405 
 1406         ifp = &sc->arpcom.ac_if;
 1407 
 1408         sc->tl_phy_did = tl_phy_readreg(sc, TL_PHY_DEVID);
 1409         sc->tl_phy_vid = tl_phy_readreg(sc, TL_PHY_VENID);
 1410         sc->tl_phy_sts = tl_phy_readreg(sc, TL_PHY_GENSTS);
 1411         phy_ctl = tl_phy_readreg(sc, TL_PHY_GENCTL);
 1412 
 1413         /*
 1414          * PHY revision numbers tend to vary a bit. Our algorithm here
 1415          * is to check everything but the 8 least significant bits.
 1416          */
 1417         while(p->tl_vid) {
 1418                 if (sc->tl_phy_vid  == p->tl_vid &&
 1419                         (sc->tl_phy_did | 0x000F) == p->tl_did) {
 1420                         sc->tl_pinfo = p;
 1421                         break;
 1422                 }
 1423                 p++;
 1424         }
 1425         if (sc->tl_pinfo == NULL) {
 1426                 sc->tl_pinfo = &tl_phys[PHY_UNKNOWN];
 1427         }
 1428 
 1429         if (sc->tl_phy_sts & PHY_BMSR_100BT4 ||
 1430                 sc->tl_phy_sts & PHY_BMSR_100BTXFULL ||
 1431                 sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
 1432                 ifp->if_baudrate = 100000000;
 1433         else
 1434                 ifp->if_baudrate = 10000000;
 1435 
 1436         if (bootverbose) {
 1437                 printf("tl%d: phy at mii address %d\n", sc->tl_unit,
 1438                                                         sc->tl_phy_addr);
 1439 
 1440                 printf("tl%d: %s ", sc->tl_unit, sc->tl_pinfo->tl_name);
 1441         }
 1442 
 1443         if (sc->tl_phy_sts & PHY_BMSR_100BT4 ||
 1444                 sc->tl_phy_sts & PHY_BMSR_100BTXHALF ||
 1445                 sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
 1446                 if (bootverbose)
 1447                         printf("10/100Mbps ");
 1448         else {
 1449                 media &= ~IFM_100_TX;
 1450                 media |= IFM_10_T;
 1451                 if (bootverbose)
 1452                         printf("10Mbps ");
 1453         }
 1454 
 1455         if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL ||
 1456                 sc->tl_phy_sts & PHY_BMSR_10BTFULL)
 1457                 if (bootverbose)
 1458                         printf("full duplex ");
 1459         else {
 1460                 if (bootverbose)
 1461                         printf("half duplex ");
 1462                 media &= ~IFM_FDX;
 1463         }
 1464 
 1465         if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) {
 1466                 media = IFM_ETHER|IFM_AUTO;
 1467                 if (bootverbose)
 1468                         printf("autonegotiating\n");
 1469         } else
 1470                 if (bootverbose)
 1471                         printf("\n");
 1472 
 1473         /* If this isn't a known PHY, print the PHY indentifier info. */
 1474         if (sc->tl_pinfo->tl_vid == 0 && bootverbose)
 1475                 printf("tl%d: vendor id: %04x product id: %04x\n",
 1476                         sc->tl_unit, sc->tl_phy_vid, sc->tl_phy_did);
 1477 
 1478         /* Set up ifmedia data and callbacks. */
 1479         ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
 1480 
 1481         /*
 1482          * All ThunderLANs support at least 10baseT half duplex.
 1483          * They also support AUI selection if used in 10Mb/s modes.
 1484          */
 1485         ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
 1486         ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 1487         ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
 1488 
 1489         /* Some ThunderLAN PHYs support autonegotiation. */
 1490         if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG)
 1491                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 1492 
 1493         /* Some support 10baseT full duplex. */
 1494         if (sc->tl_phy_sts & PHY_BMSR_10BTFULL)
 1495                 ifmedia_add(&sc->ifmedia,
 1496                         IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
 1497 
 1498         /* Some support 100BaseTX half duplex. */
 1499         if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
 1500                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
 1501         if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
 1502                 ifmedia_add(&sc->ifmedia,
 1503                         IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
 1504 
 1505         /* Some support 100BaseTX full duplex. */
 1506         if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL)
 1507                 ifmedia_add(&sc->ifmedia,
 1508                         IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
 1509 
 1510         /* Some also support 100BaseT4. */
 1511         if (sc->tl_phy_sts & PHY_BMSR_100BT4)
 1512                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
 1513 
 1514         /* Set default media. */
 1515         ifmedia_set(&sc->ifmedia, media);
 1516 
 1517         /*
 1518          * Kick off an autonegotiation session if this PHY supports it.
 1519          * This is necessary to make sure the chip's duplex mode matches
 1520          * the PHY's duplex mode. It may not: once enabled, the PHY may
 1521          * autonegotiate full-duplex mode with its link partner, but the
 1522          * ThunderLAN chip defaults to half-duplex and stays there unless
 1523          * told otherwise.
 1524          */
 1525         if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) {
 1526                 tl_init(sc);
 1527 #ifdef TL_BACKGROUND_AUTONEG
 1528                 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
 1529 #else
 1530                 tl_autoneg(sc, TL_FLAG_FORCEDELAY, 1);
 1531 #endif
 1532         }
 1533 
 1534         return(0);
 1535 }
 1536 
 1537 static void
 1538 tl_attach(config_id, unit)
 1539         pcici_t                 config_id;
 1540         int                     unit;
 1541 {
 1542         int                     s, i, phys = 0;
 1543 #ifndef TL_USEIOSPACE
 1544         vm_offset_t             pbase, vbase;
 1545 #endif
 1546         u_int32_t               command;
 1547         u_int16_t               did, vid;
 1548         struct tl_type          *t;
 1549         struct ifnet            *ifp;
 1550         struct tl_softc         *sc;
 1551         unsigned int            round;
 1552         caddr_t                 roundptr;
 1553 
 1554         s = splimp();
 1555 
 1556         vid = pci_conf_read(config_id, PCI_ID_REG) & 0xFFFF;
 1557         did = (pci_conf_read(config_id, PCI_ID_REG) >> 16) & 0xFFFF;
 1558 
 1559         t = tl_devs;
 1560         while(t->tl_name != NULL) {
 1561                 if (vid == t->tl_vid && did == t->tl_did)
 1562                         break;
 1563                 t++;
 1564         }
 1565 
 1566         if (t->tl_name == NULL) {
 1567                 printf("tl%d: unknown device!?\n", unit);
 1568                 goto fail;
 1569         }
 1570 
 1571         /* First, allocate memory for the softc struct. */
 1572         sc = malloc(sizeof(struct tl_softc), M_DEVBUF, M_NOWAIT);
 1573         if (sc == NULL) {
 1574                 printf("tl%d: no memory for softc struct!\n", unit);
 1575                 goto fail;
 1576         }
 1577 
 1578         bzero(sc, sizeof(struct tl_softc));
 1579 
 1580         /*
 1581          * Map control/status registers.
 1582          */
 1583         command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
 1584         command |= (PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE|
 1585                         PCI_COMMAND_MASTER_ENABLE);
 1586         pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
 1587         command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
 1588 
 1589 #ifdef TL_USEIOSPACE
 1590         if (!(command & PCI_COMMAND_IO_ENABLE)) {
 1591                 printf("tl%d: failed to enable I/O ports!\n", unit);
 1592                 free(sc, M_DEVBUF);
 1593                 goto fail;
 1594         }
 1595 
 1596         sc->iobase = pci_conf_read(config_id, TL_PCI_LOIO) & 0xFFFFFFFC;
 1597 #else
 1598         if (!(command & PCI_COMMAND_MEM_ENABLE)) {
 1599                 printf("tl%d: failed to enable memory mapping!\n", unit);
 1600                 goto fail;
 1601         }
 1602 
 1603         if (!pci_map_mem(config_id, TL_PCI_LOMEM, &vbase, &pbase)) {
 1604                 printf ("tl%d: couldn't map memory\n", unit);
 1605                 goto fail;
 1606         }
 1607 
 1608         sc->csr = (volatile caddr_t)vbase;
 1609 #endif
 1610 
 1611 #ifdef notdef
 1612         /*
 1613          * The ThunderLAN manual suggests jacking the PCI latency
 1614          * timer all the way up to its maximum value. I'm not sure
 1615          * if this is really necessary, but what the manual wants,
 1616          * the manual gets.
 1617          */
 1618         command = pci_conf_read(config_id, TL_PCI_LATENCY_TIMER);
 1619         command |= 0x0000FF00;
 1620         pci_conf_write(config_id, TL_PCI_LATENCY_TIMER, command);
 1621 #endif
 1622 
 1623         /* Allocate interrupt */
 1624         if (!pci_map_int(config_id, tl_intr, sc, &net_imask)) {
 1625                 printf("tl%d: couldn't map interrupt\n", unit);
 1626                 goto fail;
 1627         }
 1628 
 1629         /*
 1630          * Now allocate memory for the TX and RX lists. Note that
 1631          * we actually allocate 8 bytes more than we really need:
 1632          * this is because we need to adjust the final address to
 1633          * be aligned on a quadword (64-bit) boundary in order to
 1634          * make the chip happy. If the list structures aren't properly
 1635          * aligned, DMA fails and the chip generates an adapter check
 1636          * interrupt and has to be reset. If you set up the softc struct
 1637          * just right you can sort of obtain proper alignment 'by chance.'
 1638          * But I don't want to depend on this, so instead the alignment
 1639          * is forced here.
 1640          */
 1641         sc->tl_ldata_ptr = malloc(sizeof(struct tl_list_data) + 8,
 1642                                 M_DEVBUF, M_NOWAIT);
 1643 
 1644         if (sc->tl_ldata_ptr == NULL) {
 1645                 free(sc, M_DEVBUF);
 1646                 printf("tl%d: no memory for list buffers!\n", unit);
 1647                 goto fail;
 1648         }
 1649 
 1650         /*
 1651          * Convoluted but satisfies my ANSI sensibilities. GCC lets
 1652          * you do casts on the LHS of an assignment, but ANSI doesn't
 1653          * allow that.
 1654          */
 1655         sc->tl_ldata = (struct tl_list_data *)sc->tl_ldata_ptr;
 1656         round = (unsigned int)sc->tl_ldata_ptr & 0xF;
 1657         roundptr = sc->tl_ldata_ptr;
 1658         for (i = 0; i < 8; i++) {
 1659                 if (round % 8) {
 1660                         round++;
 1661                         roundptr++;
 1662                 } else
 1663                         break;
 1664         }
 1665         sc->tl_ldata = (struct tl_list_data *)roundptr;
 1666 
 1667         bzero(sc->tl_ldata, sizeof(struct tl_list_data));
 1668 
 1669         sc->tl_unit = unit;
 1670         sc->tl_dinfo = t;
 1671         if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
 1672                 sc->tl_eeaddr = TL_EEPROM_EADDR;
 1673         if (t->tl_vid == OLICOM_VENDORID)
 1674                 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
 1675 
 1676         /* Reset the adapter. */
 1677         tl_softreset(sc, 1);
 1678         tl_hardreset(sc);
 1679         tl_softreset(sc, 1);
 1680 
 1681         /*
 1682          * Get station address from the EEPROM.
 1683          */
 1684         if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
 1685                                 sc->tl_eeaddr, ETHER_ADDR_LEN)) {
 1686                 printf("tl%d: failed to read station address\n", unit);
 1687                 goto fail;
 1688         }
 1689 
 1690         /*
 1691          * XXX Olicom, in its desire to be different from the
 1692          * rest of the world, has done strange things with the
 1693          * encoding of the station address in the EEPROM. First
 1694          * of all, they store the address at offset 0xF8 rather
 1695          * than at 0x83 like the ThunderLAN manual suggests.
 1696          * Second, they store the address in three 16-bit words in
 1697          * network byte order, as opposed to storing it sequentially
 1698          * like all the other ThunderLAN cards. In order to get
 1699          * the station address in a form that matches what the Olicom
 1700          * diagnostic utility specifies, we have to byte-swap each
 1701          * word. To make things even more confusing, neither 00:00:28
 1702          * nor 00:00:24 appear in the IEEE OUI database.
 1703          */
 1704         if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
 1705                 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
 1706                         u_int16_t               *p;
 1707                         p = (u_int16_t *)&sc->arpcom.ac_enaddr[i];
 1708                         *p = ntohs(*p);
 1709                 }
 1710         }
 1711 
 1712         /*
 1713          * A ThunderLAN chip was detected. Inform the world.
 1714          */
 1715         printf("tl%d: Ethernet address: %6D\n", unit,
 1716                                 sc->arpcom.ac_enaddr, ":");
 1717 
 1718         ifp = &sc->arpcom.ac_if;
 1719         ifp->if_softc = sc;
 1720         ifp->if_unit = sc->tl_unit;
 1721         ifp->if_name = "tl";
 1722         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1723         ifp->if_ioctl = tl_ioctl;
 1724         ifp->if_output = ether_output;
 1725         ifp->if_start = tl_start;
 1726         ifp->if_watchdog = tl_watchdog;
 1727         ifp->if_init = tl_init;
 1728         ifp->if_mtu = ETHERMTU;
 1729 
 1730         /* Reset the adapter again. */
 1731         tl_softreset(sc, 1);
 1732         tl_hardreset(sc);
 1733         tl_softreset(sc, 1);
 1734 
 1735         /*
 1736          * Now attach the ThunderLAN's PHYs. There will always
 1737          * be at least one PHY; if the PHY address is 0x1F, then
 1738          * it's the internal one.
 1739          */
 1740 
 1741         for (i = TL_PHYADDR_MIN; i < TL_PHYADDR_MAX + 1; i++) {
 1742                 sc->tl_phy_addr = i;
 1743                 if (bootverbose)
 1744                         printf("tl%d: looking for phy at addr %x\n", unit, i);
 1745                 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
 1746                 DELAY(500);
 1747                 while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
 1748                 sc->tl_phy_sts = tl_phy_readreg(sc, PHY_BMSR);
 1749                 if (bootverbose)
 1750                         printf("tl%d: status: %x\n", unit, sc->tl_phy_sts);
 1751                 if (!sc->tl_phy_sts)
 1752                         continue;
 1753                 if (tl_attach_phy(sc)) {
 1754                         printf("tl%d: failed to attach a phy %d\n", unit, i);
 1755                         goto fail;
 1756                 }
 1757                 phys++;
 1758                 if (phys && i != TL_PHYADDR_MAX)
 1759                         break;
 1760         }
 1761 
 1762         if (!phys) {
 1763                 printf("tl%d: no physical interfaces attached!\n", unit);
 1764                 goto fail;
 1765         }
 1766 
 1767         tl_intvec_adchk((void *)sc, 0);
 1768         tl_stop(sc);
 1769 
 1770         /*
 1771          * Attempt to clear any stray interrupts
 1772          * that may be lurking.
 1773          */
 1774         tl_intr((void *)sc);
 1775 
 1776         /*
 1777          * Call MI attach routines.
 1778          */
 1779         if_attach(ifp);
 1780         ether_ifattach(ifp);
 1781 
 1782 #if NBPFILTER > 0
 1783         bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
 1784 #endif
 1785 
 1786         at_shutdown(tl_shutdown, sc, SHUTDOWN_POST_SYNC);
 1787 
 1788 fail:
 1789         splx(s);
 1790         return;
 1791 }
 1792 
 1793 /*
 1794  * Initialize the transmit lists.
 1795  */
 1796 static int tl_list_tx_init(sc)
 1797         struct tl_softc         *sc;
 1798 {
 1799         struct tl_chain_data    *cd;
 1800         struct tl_list_data     *ld;
 1801         int                     i;
 1802 
 1803         cd = &sc->tl_cdata;
 1804         ld = sc->tl_ldata;
 1805         for (i = 0; i < TL_TX_LIST_CNT; i++) {
 1806                 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
 1807                 if (i == (TL_TX_LIST_CNT - 1))
 1808                         cd->tl_tx_chain[i].tl_next = NULL;
 1809                 else
 1810                         cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
 1811         }
 1812 
 1813         cd->tl_tx_free = &cd->tl_tx_chain[0];
 1814         cd->tl_tx_tail = cd->tl_tx_head = NULL;
 1815         sc->tl_txeoc = 1;
 1816 
 1817         return(0);
 1818 }
 1819 
 1820 /*
 1821  * Initialize the RX lists and allocate mbufs for them.
 1822  */
 1823 static int tl_list_rx_init(sc)
 1824         struct tl_softc         *sc;
 1825 {
 1826         struct tl_chain_data    *cd;
 1827         struct tl_list_data     *ld;
 1828         int                     i;
 1829 
 1830         cd = &sc->tl_cdata;
 1831         ld = sc->tl_ldata;
 1832 
 1833         for (i = 0; i < TL_RX_LIST_CNT; i++) {
 1834                 cd->tl_rx_chain[i].tl_ptr =
 1835                         (struct tl_list_onefrag *)&ld->tl_rx_list[i];
 1836                 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
 1837                         return(ENOBUFS);
 1838                 if (i == (TL_RX_LIST_CNT - 1)) {
 1839                         cd->tl_rx_chain[i].tl_next = NULL;
 1840                         ld->tl_rx_list[i].tlist_fptr = 0;
 1841                 } else {
 1842                         cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
 1843                         ld->tl_rx_list[i].tlist_fptr =
 1844                                         vtophys(&ld->tl_rx_list[i + 1]);
 1845                 }
 1846         }
 1847 
 1848         cd->tl_rx_head = &cd->tl_rx_chain[0];
 1849         cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
 1850 
 1851         return(0);
 1852 }
 1853 
 1854 static int tl_newbuf(sc, c)
 1855         struct tl_softc         *sc;
 1856         struct tl_chain_onefrag *c;
 1857 {
 1858         struct mbuf             *m_new = NULL;
 1859 
 1860         MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1861         if (m_new == NULL) {
 1862                 printf("tl%d: no memory for rx list -- packet dropped!",
 1863                                 sc->tl_unit);
 1864                 return(ENOBUFS);
 1865         }
 1866 
 1867         MCLGET(m_new, M_DONTWAIT);
 1868         if (!(m_new->m_flags & M_EXT)) {
 1869                 printf("tl%d: no memory for rx list -- packet dropped!",
 1870                                  sc->tl_unit);
 1871                 m_freem(m_new);
 1872                 return(ENOBUFS);
 1873         }
 1874 
 1875         c->tl_mbuf = m_new;
 1876         c->tl_next = NULL;
 1877         c->tl_ptr->tlist_frsize = MCLBYTES;
 1878         c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
 1879         c->tl_ptr->tlist_fptr = 0;
 1880         c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
 1881         c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
 1882 
 1883         return(0);
 1884 }
 1885 /*
 1886  * Interrupt handler for RX 'end of frame' condition (EOF). This
 1887  * tells us that a full ethernet frame has been captured and we need
 1888  * to handle it.
 1889  *
 1890  * Reception is done using 'lists' which consist of a header and a
 1891  * series of 10 data count/data address pairs that point to buffers.
 1892  * Initially you're supposed to create a list, populate it with pointers
 1893  * to buffers, then load the physical address of the list into the
 1894  * ch_parm register. The adapter is then supposed to DMA the received
 1895  * frame into the buffers for you.
 1896  *
 1897  * To make things as fast as possible, we have the chip DMA directly
 1898  * into mbufs. This saves us from having to do a buffer copy: we can
 1899  * just hand the mbufs directly to ether_input(). Once the frame has
 1900  * been sent on its way, the 'list' structure is assigned a new buffer
 1901  * and moved to the end of the RX chain. As long we we stay ahead of
 1902  * the chip, it will always think it has an endless receive channel.
 1903  *
 1904  * If we happen to fall behind and the chip manages to fill up all of
 1905  * the buffers, it will generate an end of channel interrupt and wait
 1906  * for us to empty the chain and restart the receiver.
 1907  */
 1908 static int tl_intvec_rxeof(xsc, type)
 1909         void                    *xsc;
 1910         u_int32_t               type;
 1911 {
 1912         struct tl_softc         *sc;
 1913         int                     r = 0, total_len = 0;
 1914         struct ether_header     *eh;
 1915         struct mbuf             *m;
 1916         struct ifnet            *ifp;
 1917         struct tl_chain_onefrag *cur_rx;
 1918 
 1919         sc = xsc;
 1920         ifp = &sc->arpcom.ac_if;
 1921 
 1922 #ifdef TL_DEBUG
 1923         evset(sc, EV_RXEOF);
 1924 #endif
 1925 
 1926         while(sc->tl_cdata.tl_rx_head->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP){
 1927                 r++;
 1928                 cur_rx = sc->tl_cdata.tl_rx_head;
 1929                 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
 1930                 m = cur_rx->tl_mbuf;
 1931                 total_len = cur_rx->tl_ptr->tlist_frsize;
 1932 
 1933                 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
 1934                         ifp->if_ierrors++;
 1935                         cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
 1936                         cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
 1937                         cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
 1938                         continue;
 1939                 }
 1940 
 1941                 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
 1942                                                 vtophys(cur_rx->tl_ptr);
 1943                 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
 1944                 sc->tl_cdata.tl_rx_tail = cur_rx;
 1945 
 1946                 eh = mtod(m, struct ether_header *);
 1947                 m->m_pkthdr.rcvif = ifp;
 1948 
 1949                 /*
 1950                  * Note: when the ThunderLAN chip is in 'capture all
 1951                  * frames' mode, it will receive its own transmissions.
 1952                  * We drop don't need to process our own transmissions,
 1953                  * so we drop them here and continue.
 1954                  */
 1955                 /*if (ifp->if_flags & IFF_PROMISC && */
 1956                 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
 1957                                                         ETHER_ADDR_LEN)) {
 1958                                 m_freem(m);
 1959                                 continue;
 1960                 }
 1961 
 1962 #if NBPFILTER > 0
 1963                 /*
 1964                  * Handle BPF listeners. Let the BPF user see the packet, but
 1965                  * don't pass it up to the ether_input() layer unless it's
 1966                  * a broadcast packet, multicast packet, matches our ethernet
 1967                  * address or the interface is in promiscuous mode. If we don't
 1968                  * want the packet, just forget it. We leave the mbuf in place
 1969                  * since it can be used again later.
 1970                  */
 1971                 if (ifp->if_bpf) {
 1972                         m->m_pkthdr.len = m->m_len = total_len;
 1973                         bpf_mtap(ifp, m);
 1974                         if (ifp->if_flags & IFF_PROMISC &&
 1975                                 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
 1976                                                 ETHER_ADDR_LEN) &&
 1977                                         (eh->ether_dhost[0] & 1) == 0)) {
 1978                                 m_freem(m);
 1979                                 continue;
 1980                         }
 1981                 }
 1982 #endif
 1983                 /* Remove header from mbuf and pass it on. */
 1984                 m->m_pkthdr.len = m->m_len =
 1985                                 total_len - sizeof(struct ether_header);
 1986                 m->m_data += sizeof(struct ether_header);
 1987                 ether_input(ifp, eh, m);
 1988         }
 1989 
 1990         return(r);
 1991 }
 1992 
 1993 /*
 1994  * The RX-EOC condition hits when the ch_parm address hasn't been
 1995  * initialized or the adapter reached a list with a forward pointer
 1996  * of 0 (which indicates the end of the chain). In our case, this means
 1997  * the card has hit the end of the receive buffer chain and we need to
 1998  * empty out the buffers and shift the pointer back to the beginning again.
 1999  */
 2000 static int tl_intvec_rxeoc(xsc, type)
 2001         void                    *xsc;
 2002         u_int32_t               type;
 2003 {
 2004         struct tl_softc         *sc;
 2005         int                     r;
 2006 
 2007         sc = xsc;
 2008 
 2009 #ifdef TL_DEBUG
 2010         evset(sc, EV_RXEOC);
 2011 #endif
 2012 
 2013         /* Flush out the receive queue and ack RXEOF interrupts. */
 2014         r = tl_intvec_rxeof(xsc, type);
 2015         CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
 2016         r = 1;
 2017         CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
 2018         r |= (TL_CMD_GO|TL_CMD_RT);
 2019         return(r);
 2020 }
 2021 
 2022 static int tl_intvec_txeof(xsc, type)
 2023         void                    *xsc;
 2024         u_int32_t               type;
 2025 {
 2026         struct tl_softc         *sc;
 2027         int                     r = 0;
 2028         struct tl_chain         *cur_tx;
 2029 
 2030         sc = xsc;
 2031 
 2032 #ifdef TL_DEBUG
 2033         evset(sc, EV_TXEOF);
 2034 #endif
 2035 
 2036         /*
 2037          * Go through our tx list and free mbufs for those
 2038          * frames that have been sent.
 2039          */
 2040         while (sc->tl_cdata.tl_tx_head != NULL) {
 2041                 cur_tx = sc->tl_cdata.tl_tx_head;
 2042                 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
 2043                         break;
 2044                 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
 2045 
 2046                 r++;
 2047                 m_freem(cur_tx->tl_mbuf);
 2048                 cur_tx->tl_mbuf = NULL;
 2049 
 2050                 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
 2051                 sc->tl_cdata.tl_tx_free = cur_tx;
 2052                 if (!cur_tx->tl_ptr->tlist_fptr)
 2053                         break;
 2054         }
 2055 
 2056         return(r);
 2057 }
 2058 
 2059 /*
 2060  * The transmit end of channel interrupt. The adapter triggers this
 2061  * interrupt to tell us it hit the end of the current transmit list.
 2062  *
 2063  * A note about this: it's possible for a condition to arise where
 2064  * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
 2065  * You have to avoid this since the chip expects things to go in a
 2066  * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
 2067  * When the TXEOF handler is called, it will free all of the transmitted
 2068  * frames and reset the tx_head pointer to NULL. However, a TXEOC
 2069  * interrupt should be received and acknowledged before any more frames
 2070  * are queued for transmission. If tl_statrt() is called after TXEOF
 2071  * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
 2072  * it could attempt to issue a transmit command prematurely.
 2073  *
 2074  * To guard against this, tl_start() will only issue transmit commands
 2075  * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
 2076  * can set this flag once tl_start() has cleared it.
 2077  */
 2078 static int tl_intvec_txeoc(xsc, type)
 2079         void                    *xsc;
 2080         u_int32_t               type;
 2081 {
 2082         struct tl_softc         *sc;
 2083         struct ifnet            *ifp;
 2084         u_int32_t               cmd;
 2085 
 2086         sc = xsc;
 2087         ifp = &sc->arpcom.ac_if;
 2088 
 2089         /* Clear the timeout timer. */
 2090         ifp->if_timer = 0;
 2091 
 2092 #ifdef TL_DEBUG
 2093         evset(sc, EV_TXEOC);
 2094 #endif
 2095 
 2096         if (sc->tl_cdata.tl_tx_head == NULL) {
 2097                 ifp->if_flags &= ~IFF_OACTIVE;
 2098                 sc->tl_cdata.tl_tx_tail = NULL;
 2099                 sc->tl_txeoc = 1;
 2100                 /*
 2101                  * If we just drained the TX queue and
 2102                  * there's an autoneg request waiting, set
 2103                  * it in motion. This will block the transmitter
 2104                  * until the autoneg session completes which will
 2105                  * no doubt piss off any processes waiting to
 2106                  * transmit, but that's the way the ball bounces.
 2107                  */
 2108                 if (sc->tl_want_auto)
 2109                         tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
 2110         } else {
 2111                 sc->tl_txeoc = 0;
 2112                 /* First we have to ack the EOC interrupt. */
 2113                 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
 2114                 /* Then load the address of the next TX list. */
 2115                 CSR_WRITE_4(sc, TL_CH_PARM,
 2116                                 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
 2117                 /* Restart TX channel. */
 2118                 cmd = CSR_READ_4(sc, TL_HOSTCMD);
 2119                 cmd &= ~TL_CMD_RT;
 2120                 cmd |= TL_CMD_GO|TL_CMD_INTSON;
 2121                 CMD_PUT(sc, cmd);
 2122                 return(0);
 2123         }
 2124 
 2125         return(1);
 2126 }
 2127 
 2128 static int tl_intvec_adchk(xsc, type)
 2129         void                    *xsc;
 2130         u_int32_t               type;
 2131 {
 2132         struct tl_softc         *sc;
 2133         u_int16_t               bmcr, ctl;
 2134 
 2135         sc = xsc;
 2136 
 2137         if (type)
 2138                 printf("tl%d: adapter check: %x\n", sc->tl_unit,
 2139                         (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
 2140 #ifdef TL_DEBUG
 2141         evshow(sc);
 2142 #endif
 2143 
 2144         /*
 2145          * Before resetting the adapter, try reading the PHY
 2146          * settings so we can put them back later. This is
 2147          * necessary to keep the chip operating at the same
 2148          * speed and duplex settings after the reset completes.
 2149          */
 2150         bmcr = tl_phy_readreg(sc, PHY_BMCR);
 2151         ctl = tl_phy_readreg(sc, TL_PHY_CTL);
 2152         tl_softreset(sc, 1);
 2153         tl_phy_writereg(sc, PHY_BMCR, bmcr);
 2154         tl_phy_writereg(sc, TL_PHY_CTL, ctl);
 2155         if (bmcr & PHY_BMCR_DUPLEX) {
 2156                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
 2157         } else {
 2158                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
 2159         }
 2160         tl_stop(sc);
 2161         tl_init(sc);
 2162         CMD_SET(sc, TL_CMD_INTSON);
 2163 
 2164         return(0);
 2165 }
 2166 
 2167 static int tl_intvec_netsts(xsc, type)
 2168         void                    *xsc;
 2169         u_int32_t               type;
 2170 {
 2171         struct tl_softc         *sc;
 2172         u_int16_t               netsts;
 2173 
 2174         sc = xsc;
 2175 
 2176         netsts = tl_dio_read16(sc, TL_NETSTS);
 2177         tl_dio_write16(sc, TL_NETSTS, netsts);
 2178 
 2179         printf("tl%d: network status: %x\n", sc->tl_unit, netsts);
 2180 
 2181         return(1);
 2182 }
 2183 
 2184 static void tl_intr(xsc)
 2185         void                    *xsc;
 2186 {
 2187         struct tl_softc         *sc;
 2188         struct ifnet            *ifp;
 2189         int                     r = 0;
 2190         u_int32_t               type = 0;
 2191         u_int16_t               ints = 0;
 2192         u_int8_t                ivec = 0;
 2193 
 2194         sc = xsc;
 2195 
 2196         /* Disable interrupts */
 2197         ints = CSR_READ_2(sc, TL_HOST_INT);
 2198         CSR_WRITE_2(sc, TL_HOST_INT, ints);
 2199         type = (ints << 16) & 0xFFFF0000;
 2200         ivec = (ints & TL_VEC_MASK) >> 5;
 2201         ints = (ints & TL_INT_MASK) >> 2;
 2202 
 2203         ifp = &sc->arpcom.ac_if;
 2204 
 2205         switch(ints) {
 2206         case (TL_INTR_INVALID):
 2207 #ifdef DIAGNOSTIC
 2208                 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit);
 2209 #endif
 2210                 /* Re-enable interrupts but don't ack this one. */
 2211                 CMD_PUT(sc, type);
 2212                 r = 0;
 2213                 break;
 2214         case (TL_INTR_TXEOF):
 2215                 r = tl_intvec_txeof((void *)sc, type);
 2216                 break;
 2217         case (TL_INTR_TXEOC):
 2218                 r = tl_intvec_txeoc((void *)sc, type);
 2219                 break;
 2220         case (TL_INTR_STATOFLOW):
 2221                 tl_stats_update(sc);
 2222                 r = 1;
 2223                 break;
 2224         case (TL_INTR_RXEOF):
 2225                 r = tl_intvec_rxeof((void *)sc, type);
 2226                 break;
 2227         case (TL_INTR_DUMMY):
 2228                 printf("tl%d: got a dummy interrupt\n", sc->tl_unit);
 2229                 r = 1;
 2230                 break;
 2231         case (TL_INTR_ADCHK):
 2232                 if (ivec)
 2233                         r = tl_intvec_adchk((void *)sc, type);
 2234                 else
 2235                         r = tl_intvec_netsts((void *)sc, type);
 2236                 break;
 2237         case (TL_INTR_RXEOC):
 2238                 r = tl_intvec_rxeoc((void *)sc, type);
 2239                 break;
 2240         default:
 2241                 printf("tl%d: bogus interrupt type\n", ifp->if_unit);
 2242                 break;
 2243         }
 2244 
 2245         /* Re-enable interrupts */
 2246         if (r) {
 2247                 CMD_PUT(sc, TL_CMD_ACK | r | type);
 2248         }
 2249 
 2250         if (ifp->if_snd.ifq_head != NULL)
 2251                 tl_start(ifp);
 2252 
 2253         return;
 2254 }
 2255 
 2256 static void tl_stats_update(xsc)
 2257         void                    *xsc;
 2258 {
 2259         struct tl_softc         *sc;
 2260         struct ifnet            *ifp;
 2261         struct tl_stats         tl_stats;
 2262         u_int32_t               *p;
 2263 
 2264         bzero((char *)&tl_stats, sizeof(struct tl_stats));
 2265 
 2266         sc = xsc;
 2267         ifp = &sc->arpcom.ac_if;
 2268 
 2269         p = (u_int32_t *)&tl_stats;
 2270 
 2271         CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
 2272         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 2273         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 2274         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 2275         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 2276         *p++ = CSR_READ_4(sc, TL_DIO_DATA);
 2277 
 2278         ifp->if_opackets += tl_tx_goodframes(tl_stats);
 2279         ifp->if_collisions += tl_stats.tl_tx_single_collision +
 2280                                 tl_stats.tl_tx_multi_collision;
 2281         ifp->if_ipackets += tl_rx_goodframes(tl_stats);
 2282         ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
 2283                             tl_rx_overrun(tl_stats);
 2284         ifp->if_oerrors += tl_tx_underrun(tl_stats);
 2285 
 2286         timeout(tl_stats_update, sc, hz);
 2287 }
 2288 
 2289 /*
 2290  * Encapsulate an mbuf chain in a list by coupling the mbuf data
 2291  * pointers to the fragment pointers.
 2292  */
 2293 static int tl_encap(sc, c, m_head)
 2294         struct tl_softc         *sc;
 2295         struct tl_chain         *c;
 2296         struct mbuf             *m_head;
 2297 {
 2298         int                     frag = 0;
 2299         struct tl_frag          *f = NULL;
 2300         int                     total_len;
 2301         struct mbuf             *m;
 2302 
 2303         /*
 2304          * Start packing the mbufs in this chain into
 2305          * the fragment pointers. Stop when we run out
 2306          * of fragments or hit the end of the mbuf chain.
 2307          */
 2308         m = m_head;
 2309         total_len = 0;
 2310 
 2311         for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
 2312                 if (m->m_len != 0) {
 2313                         if (frag == TL_MAXFRAGS)
 2314                                 break;
 2315                         total_len+= m->m_len;
 2316                         c->tl_ptr->tl_frag[frag].tlist_dadr =
 2317                                 vtophys(mtod(m, vm_offset_t));
 2318                         c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
 2319                         frag++;
 2320                 }
 2321         }
 2322 
 2323         /*
 2324          * Handle special cases.
 2325          * Special case #1: we used up all 10 fragments, but
 2326          * we have more mbufs left in the chain. Copy the
 2327          * data into an mbuf cluster. Note that we don't
 2328          * bother clearing the values in the other fragment
 2329          * pointers/counters; it wouldn't gain us anything,
 2330          * and would waste cycles.
 2331          */
 2332         if (m != NULL) {
 2333                 struct mbuf             *m_new = NULL;
 2334 
 2335                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 2336                 if (m_new == NULL) {
 2337                         printf("tl%d: no memory for tx list", sc->tl_unit);
 2338                         return(1);
 2339                 }
 2340                 if (m_head->m_pkthdr.len > MHLEN) {
 2341                         MCLGET(m_new, M_DONTWAIT);
 2342                         if (!(m_new->m_flags & M_EXT)) {
 2343                                 m_freem(m_new);
 2344                                 printf("tl%d: no memory for tx list",
 2345                                 sc->tl_unit);
 2346                                 return(1);
 2347                         }
 2348                 }
 2349                 m_copydata(m_head, 0, m_head->m_pkthdr.len,     
 2350                                         mtod(m_new, caddr_t));
 2351                 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
 2352                 m_freem(m_head);
 2353                 m_head = m_new;
 2354                 f = &c->tl_ptr->tl_frag[0];
 2355                 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
 2356                 f->tlist_dcnt = total_len = m_new->m_len;
 2357                 frag = 1;
 2358         }
 2359 
 2360         /*
 2361          * Special case #2: the frame is smaller than the minimum
 2362          * frame size. We have to pad it to make the chip happy.
 2363          */
 2364         if (total_len < TL_MIN_FRAMELEN) {
 2365                 if (frag == TL_MAXFRAGS)
 2366                         printf("tl%d: all frags filled but "
 2367                                 "frame still to small!\n", sc->tl_unit);
 2368                 f = &c->tl_ptr->tl_frag[frag];
 2369                 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
 2370                 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
 2371                 total_len += f->tlist_dcnt;
 2372                 frag++;
 2373         }
 2374 
 2375         c->tl_mbuf = m_head;
 2376         c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
 2377         c->tl_ptr->tlist_frsize = total_len;
 2378         c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
 2379         c->tl_ptr->tlist_fptr = 0;
 2380 
 2381         return(0);
 2382 }
 2383 
 2384 /*
 2385  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 2386  * to the mbuf data regions directly in the transmit lists. We also save a
 2387  * copy of the pointers since the transmit list fragment pointers are
 2388  * physical addresses.
 2389  */
 2390 static void tl_start(ifp)
 2391         struct ifnet            *ifp;
 2392 {
 2393         struct tl_softc         *sc;
 2394         struct mbuf             *m_head = NULL;
 2395         u_int32_t               cmd;
 2396         struct tl_chain         *prev = NULL, *cur_tx = NULL, *start_tx;
 2397 
 2398         sc = ifp->if_softc;
 2399 
 2400         if (sc->tl_autoneg) {
 2401                 sc->tl_tx_pend = 1;
 2402                 return;
 2403         }
 2404 
 2405         /*
 2406          * Check for an available queue slot. If there are none,
 2407          * punt.
 2408          */
 2409         if (sc->tl_cdata.tl_tx_free == NULL) {
 2410                 ifp->if_flags |= IFF_OACTIVE;
 2411                 return;
 2412         }
 2413 
 2414         start_tx = sc->tl_cdata.tl_tx_free;
 2415 
 2416         while(sc->tl_cdata.tl_tx_free != NULL) {
 2417                 IF_DEQUEUE(&ifp->if_snd, m_head);
 2418                 if (m_head == NULL)
 2419                         break;
 2420 
 2421                 /* Pick a chain member off the free list. */
 2422                 cur_tx = sc->tl_cdata.tl_tx_free;
 2423                 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
 2424 
 2425                 cur_tx->tl_next = NULL;
 2426 
 2427                 /* Pack the data into the list. */
 2428                 tl_encap(sc, cur_tx, m_head);
 2429 
 2430                 /* Chain it together */
 2431                 if (prev != NULL) {
 2432                         prev->tl_next = cur_tx;
 2433                         prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
 2434                 }
 2435                 prev = cur_tx;
 2436 
 2437                 /*
 2438                  * If there's a BPF listener, bounce a copy of this frame
 2439                  * to him.
 2440                  */
 2441 #if NBPFILTER > 0
 2442                 if (ifp->if_bpf)
 2443                         bpf_mtap(ifp, cur_tx->tl_mbuf);
 2444 #endif
 2445         }
 2446 
 2447         /*
 2448          * If there are no packets queued, bail.
 2449          */
 2450         if (cur_tx == NULL)
 2451                 return;
 2452 
 2453         /*
 2454          * That's all we can stands, we can't stands no more.
 2455          * If there are no other transfers pending, then issue the
 2456          * TX GO command to the adapter to start things moving.
 2457          * Otherwise, just leave the data in the queue and let
 2458          * the EOF/EOC interrupt handler send.
 2459          */
 2460         if (sc->tl_cdata.tl_tx_head == NULL) {
 2461                 sc->tl_cdata.tl_tx_head = start_tx;
 2462                 sc->tl_cdata.tl_tx_tail = cur_tx;
 2463 #ifdef TL_DEBUG
 2464                 evset(sc, EV_START_TX);
 2465 #endif
 2466 
 2467                 if (sc->tl_txeoc) {
 2468 #ifdef TL_DEBUG
 2469                         evset(sc, EV_START_TX_REAL);
 2470 #endif
 2471                         sc->tl_txeoc = 0;
 2472                         CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
 2473                         cmd = CSR_READ_4(sc, TL_HOSTCMD);
 2474                         cmd &= ~TL_CMD_RT;
 2475                         cmd |= TL_CMD_GO|TL_CMD_INTSON;
 2476                         CMD_PUT(sc, cmd);
 2477                 }
 2478         } else {
 2479 #ifdef TL_DEBUG
 2480                 evset(sc, EV_START_Q);
 2481 #endif
 2482                 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
 2483                 sc->tl_cdata.tl_tx_tail = cur_tx;
 2484         }
 2485 
 2486         /*
 2487          * Set a timeout in case the chip goes out to lunch.
 2488          */
 2489         ifp->if_timer = 5;
 2490 
 2491         return;
 2492 }
 2493 
 2494 static void tl_init(xsc)
 2495         void                    *xsc;
 2496 {
 2497         struct tl_softc         *sc = xsc;
 2498         struct ifnet            *ifp = &sc->arpcom.ac_if;
 2499         int                     s;
 2500         u_int16_t               phy_sts;
 2501 
 2502         if (sc->tl_autoneg)
 2503                 return;
 2504 
 2505         s = splimp();
 2506 
 2507         ifp = &sc->arpcom.ac_if;
 2508 
 2509 #ifdef TL_DEBUG
 2510         evset(sc, EV_INIT);
 2511 #endif
 2512 
 2513         /*
 2514          * Cancel pending I/O.
 2515          */
 2516         tl_stop(sc);
 2517 
 2518         /*
 2519          * Set 'capture all frames' bit for promiscuous mode.
 2520          */
 2521         if (ifp->if_flags & IFF_PROMISC)
 2522                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
 2523         else
 2524                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
 2525 
 2526         /*
 2527          * Set capture broadcast bit to capture broadcast frames.
 2528          */
 2529         if (ifp->if_flags & IFF_BROADCAST)
 2530                 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
 2531         else
 2532                 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
 2533 
 2534         /* Init our MAC address */
 2535         tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
 2536 
 2537         /* Init multicast filter, if needed. */
 2538         tl_setmulti(sc);
 2539 
 2540         /* Init circular RX list. */
 2541         if (tl_list_rx_init(sc) == ENOBUFS) {
 2542                 printf("tl%d: initialization failed: no "
 2543                         "memory for rx buffers\n", sc->tl_unit);
 2544                 tl_stop(sc);
 2545                 return;
 2546         }
 2547 
 2548         /* Init TX pointers. */
 2549         tl_list_tx_init(sc);
 2550 
 2551         /*
 2552          * Enable PHY interrupts.
 2553          */
 2554         phy_sts = tl_phy_readreg(sc, TL_PHY_CTL);
 2555         phy_sts |= PHY_CTL_INTEN;
 2556         tl_phy_writereg(sc, TL_PHY_CTL, phy_sts);
 2557 
 2558         /* Enable MII interrupts. */
 2559         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
 2560 
 2561         /* Enable PCI interrupts. */
 2562         CMD_SET(sc, TL_CMD_INTSON);
 2563 
 2564         /* Load the address of the rx list */
 2565         CMD_SET(sc, TL_CMD_RT);
 2566         CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
 2567 
 2568         /*
 2569          * XXX This is a kludge to handle adapters with the Micro Linear
 2570          * ML6692 100BaseTX PHY, which only supports 100Mbps modes and
 2571          * relies on the controller's internal 10Mbps PHY to provide
 2572          * 10Mbps modes. The ML6692 always shows up with a vendor/device ID
 2573          * of 0 (it doesn't actually have vendor/device ID registers)
 2574          * so we use that property to detect it. In theory there ought to
 2575          * be a better way to 'spot the looney' but I can't find one.
 2576          */
 2577         if (!sc->tl_phy_vid) {
 2578                 u_int8_t                        addr = 0;
 2579                 u_int16_t                       bmcr;
 2580 
 2581                 bmcr = tl_phy_readreg(sc, PHY_BMCR);
 2582                 addr = sc->tl_phy_addr;
 2583                 sc->tl_phy_addr = TL_PHYADDR_MAX;
 2584                 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
 2585                 if (bmcr & PHY_BMCR_SPEEDSEL)
 2586                         tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE);
 2587                 else
 2588                         tl_phy_writereg(sc, PHY_BMCR, bmcr);
 2589                 sc->tl_phy_addr = addr;
 2590         }
 2591 
 2592         /* Send the RX go command */
 2593         CMD_SET(sc, TL_CMD_GO|TL_CMD_RT);
 2594 
 2595         ifp->if_flags |= IFF_RUNNING;
 2596         ifp->if_flags &= ~IFF_OACTIVE;
 2597 
 2598         (void)splx(s);
 2599 
 2600         /* Start the stats update counter */
 2601         timeout(tl_stats_update, sc, hz);
 2602 
 2603         return;
 2604 }
 2605 
 2606 /*
 2607  * Set media options.
 2608  */
 2609 static int tl_ifmedia_upd(ifp)
 2610         struct ifnet            *ifp;
 2611 {
 2612         struct tl_softc         *sc;
 2613         struct ifmedia          *ifm;
 2614 
 2615         sc = ifp->if_softc;
 2616         ifm = &sc->ifmedia;
 2617 
 2618         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 2619                 return(EINVAL);
 2620 
 2621         if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
 2622                 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
 2623         else
 2624                 tl_setmode(sc, ifm->ifm_media);
 2625 
 2626         return(0);
 2627 }
 2628 
 2629 /*
 2630  * Report current media status.
 2631  */
 2632 static void tl_ifmedia_sts(ifp, ifmr)
 2633         struct ifnet            *ifp;
 2634         struct ifmediareq       *ifmr;
 2635 {
 2636         u_int16_t               phy_ctl;
 2637         u_int16_t               phy_sts;
 2638         struct tl_softc         *sc;
 2639 
 2640         sc = ifp->if_softc;
 2641 
 2642         ifmr->ifm_active = IFM_ETHER;
 2643 
 2644         phy_ctl = tl_phy_readreg(sc, PHY_BMCR);
 2645         phy_sts = tl_phy_readreg(sc, TL_PHY_CTL);
 2646 
 2647         if (phy_sts & PHY_CTL_AUISEL)
 2648                 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
 2649 
 2650         if (phy_ctl & PHY_BMCR_LOOPBK)
 2651                 ifmr->ifm_active = IFM_ETHER|IFM_LOOP;
 2652 
 2653         if (phy_ctl & PHY_BMCR_SPEEDSEL)
 2654                 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
 2655         else
 2656                 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
 2657 
 2658         if (phy_ctl & PHY_BMCR_DUPLEX) {
 2659                 ifmr->ifm_active |= IFM_FDX;
 2660                 ifmr->ifm_active &= ~IFM_HDX;
 2661         } else {
 2662                 ifmr->ifm_active &= ~IFM_FDX;
 2663                 ifmr->ifm_active |= IFM_HDX;
 2664         }
 2665 
 2666         return;
 2667 }
 2668 
 2669 static int tl_ioctl(ifp, command, data)
 2670         struct ifnet            *ifp;
 2671         int                     command;
 2672         caddr_t                 data;
 2673 {
 2674         struct tl_softc         *sc = ifp->if_softc;
 2675         struct ifreq            *ifr = (struct ifreq *) data;
 2676         int                     s, error = 0;
 2677 
 2678         s = splimp();
 2679 
 2680         switch(command) {
 2681         case SIOCSIFADDR:
 2682         case SIOCGIFADDR:
 2683         case SIOCSIFMTU:
 2684                 error = ether_ioctl(ifp, command, data);
 2685                 break;
 2686         case SIOCSIFFLAGS:
 2687                 if (ifp->if_flags & IFF_UP) {
 2688                         tl_init(sc);
 2689                 } else {
 2690                         if (ifp->if_flags & IFF_RUNNING) {
 2691                                 tl_stop(sc);
 2692                         }
 2693                 }
 2694                 error = 0;
 2695                 break;
 2696         case SIOCADDMULTI:
 2697         case SIOCDELMULTI:
 2698                 if (command == SIOCADDMULTI)
 2699                         error = ether_addmulti(ifr, &sc->arpcom);
 2700                 else
 2701                         error = ether_delmulti(ifr, &sc->arpcom);
 2702                 if (error == ENETRESET) {
 2703                         tl_setmulti(sc);
 2704                         error = 0;
 2705                 }
 2706                 break;
 2707         case SIOCSIFMEDIA:
 2708         case SIOCGIFMEDIA:
 2709                 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
 2710                 break;
 2711         default:
 2712                 error = EINVAL;
 2713                 break;
 2714         }
 2715 
 2716         (void)splx(s);
 2717 
 2718         return(error);
 2719 }
 2720 
 2721 static void tl_watchdog(ifp)
 2722         struct ifnet            *ifp;
 2723 {
 2724         struct tl_softc         *sc;
 2725         u_int16_t               bmsr;
 2726 
 2727         sc = ifp->if_softc;
 2728 
 2729 #ifdef TL_DEBUG
 2730         evset(sc, EV_WATCHDOG);
 2731 #endif
 2732 
 2733         if (sc->tl_autoneg) {
 2734                 tl_autoneg(sc, TL_FLAG_DELAYTIMEO, 1);
 2735                 return;
 2736         }
 2737 
 2738         /* Check that we're still connected. */
 2739         tl_phy_readreg(sc, PHY_BMSR);
 2740         bmsr = tl_phy_readreg(sc, PHY_BMSR);
 2741         if (!(bmsr & PHY_BMSR_LINKSTAT)) {
 2742                 printf("tl%d: no carrier\n", sc->tl_unit);
 2743                 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
 2744         } else
 2745                 printf("tl%d: device timeout\n", sc->tl_unit);
 2746 
 2747         ifp->if_oerrors++;
 2748 
 2749         tl_init(sc);
 2750 
 2751         return;
 2752 }
 2753 
 2754 /*
 2755  * Stop the adapter and free any mbufs allocated to the
 2756  * RX and TX lists.
 2757  */
 2758 static void tl_stop(sc)
 2759         struct tl_softc         *sc;
 2760 {
 2761         register int            i;
 2762         struct ifnet            *ifp;
 2763 
 2764         ifp = &sc->arpcom.ac_if;
 2765 
 2766         /* Stop the stats updater. */
 2767         untimeout(tl_stats_update, sc);
 2768 
 2769         /* Stop the transmitter */
 2770         CMD_CLR(sc, TL_CMD_RT);
 2771         CMD_SET(sc, TL_CMD_STOP);
 2772         CSR_WRITE_4(sc, TL_CH_PARM, 0);
 2773 
 2774         /* Stop the receiver */
 2775         CMD_SET(sc, TL_CMD_RT);
 2776         CMD_SET(sc, TL_CMD_STOP);
 2777         CSR_WRITE_4(sc, TL_CH_PARM, 0);
 2778 
 2779         /*
 2780          * Disable host interrupts.
 2781          */
 2782         CMD_SET(sc, TL_CMD_INTSOFF);
 2783 
 2784         /*
 2785          * Disable MII interrupts.
 2786          */
 2787         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
 2788 
 2789         /*
 2790          * Clear list pointer.
 2791          */
 2792         CSR_WRITE_4(sc, TL_CH_PARM, 0);
 2793 
 2794         /*
 2795          * Free the RX lists.
 2796          */
 2797         for (i = 0; i < TL_RX_LIST_CNT; i++) {
 2798                 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
 2799                         m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
 2800                         sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
 2801                 }
 2802         }
 2803         bzero((char *)&sc->tl_ldata->tl_rx_list,
 2804                 sizeof(sc->tl_ldata->tl_rx_list));
 2805 
 2806         /*
 2807          * Free the TX list buffers.
 2808          */
 2809         for (i = 0; i < TL_TX_LIST_CNT; i++) {
 2810                 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
 2811                         m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
 2812                         sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
 2813                 }
 2814         }
 2815         bzero((char *)&sc->tl_ldata->tl_tx_list,
 2816                 sizeof(sc->tl_ldata->tl_tx_list));
 2817 
 2818         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 2819 
 2820         return;
 2821 }
 2822 
 2823 /*
 2824  * Stop all chip I/O so that the kernel's probe routines don't
 2825  * get confused by errant DMAs when rebooting.
 2826  */
 2827 static void tl_shutdown(howto, xsc)
 2828         int                     howto;
 2829         void                    *xsc;
 2830 {
 2831         struct tl_softc         *sc;
 2832 
 2833         sc = xsc;
 2834 
 2835         tl_stop(sc);
 2836 
 2837         return;
 2838 }
 2839 
 2840 
 2841 static struct pci_device tl_device = {
 2842         "tl",
 2843         tl_probe,
 2844         tl_attach,
 2845         &tl_count,
 2846         NULL
 2847 };
 2848 DATA_SET(pcidevice_set, tl_device);

Cache object: a9ce47ce342d81fd022c83f44dfc9285


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