Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_tlreg.h
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1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 36 struct tl_type { 37 u_int16_t tl_vid; 38 u_int16_t tl_did; 39 char *tl_name; 40 }; 41 42 /* 43 * ThunderLAN TX/RX list format. The TX and RX lists are pretty much 44 * identical: the list begins with a 32-bit forward pointer which points 45 * at the next list in the chain, followed by 16 bits for the total 46 * frame size, and a 16 bit status field. This is followed by a series 47 * of 10 32-bit data count/data address pairs that point to the fragments 48 * that make up the complete frame. 49 */ 50 51 #define TL_MAXFRAGS 10 52 #define TL_RX_LIST_CNT 20 53 #define TL_TX_LIST_CNT 20 54 #define TL_MIN_FRAMELEN 64 55 56 struct tl_frag { 57 u_int32_t tlist_dcnt; 58 u_int32_t tlist_dadr; 59 }; 60 61 struct tl_list { 62 u_int32_t tlist_fptr; /* phys address of next list */ 63 u_int16_t tlist_cstat; /* status word */ 64 u_int16_t tlist_frsize; /* size of data in frame */ 65 struct tl_frag tl_frag[TL_MAXFRAGS]; 66 }; 67 68 /* 69 * This is a special case of an RX list. By setting the One_Frag 70 * bit in the NETCONFIG register, the driver can force the ThunderLAN 71 * chip to use only one fragment when DMAing RX frames. 72 */ 73 74 struct tl_list_onefrag { 75 u_int32_t tlist_fptr; 76 u_int16_t tlist_cstat; 77 u_int16_t tlist_frsize; 78 struct tl_frag tl_frag; 79 }; 80 81 struct tl_list_data { 82 struct tl_list_onefrag tl_rx_list[TL_RX_LIST_CNT]; 83 struct tl_list tl_tx_list[TL_TX_LIST_CNT]; 84 unsigned char tl_pad[TL_MIN_FRAMELEN]; 85 }; 86 87 struct tl_chain { 88 struct tl_list *tl_ptr; 89 struct mbuf *tl_mbuf; 90 struct tl_chain *tl_next; 91 }; 92 93 struct tl_chain_onefrag { 94 struct tl_list_onefrag *tl_ptr; 95 struct mbuf *tl_mbuf; 96 struct tl_chain_onefrag *tl_next; 97 }; 98 99 struct tl_chain_data { 100 struct tl_chain_onefrag tl_rx_chain[TL_RX_LIST_CNT]; 101 struct tl_chain tl_tx_chain[TL_TX_LIST_CNT]; 102 103 struct tl_chain_onefrag *tl_rx_head; 104 struct tl_chain_onefrag *tl_rx_tail; 105 106 struct tl_chain *tl_tx_head; 107 struct tl_chain *tl_tx_tail; 108 struct tl_chain *tl_tx_free; 109 }; 110 111 struct tl_softc { 112 struct arpcom arpcom; /* interface info */ 113 struct ifmedia ifmedia; /* media info */ 114 bus_space_handle_t tl_bhandle; 115 bus_space_tag_t tl_btag; 116 struct tl_type *tl_dinfo; /* ThunderLAN adapter info */ 117 struct tl_type *tl_pinfo; /* PHY info struct */ 118 u_int8_t tl_ctlr; /* chip number */ 119 u_int8_t tl_unit; /* interface number */ 120 u_int8_t tl_eeaddr; 121 u_int8_t tl_phy_addr; /* PHY address */ 122 u_int8_t tl_tx_pend; /* TX pending */ 123 u_int8_t tl_want_auto; /* autoneg scheduled */ 124 u_int8_t tl_autoneg; /* autoneg in progress */ 125 u_int16_t tl_phy_sts; /* PHY status */ 126 u_int16_t tl_phy_vid; /* PHY vendor ID */ 127 u_int16_t tl_phy_did; /* PHY device ID */ 128 caddr_t tl_ldata_ptr; 129 struct tl_list_data *tl_ldata; /* TX/RX lists and mbufs */ 130 struct tl_chain_data tl_cdata; 131 u_int8_t tl_txeoc; 132 u_int8_t tl_bitrate; 133 struct callout_handle tl_stat_ch; 134 }; 135 136 /* 137 * Transmit interrupt threshold. 138 */ 139 #define TX_THR 0x00000004 140 141 #define TL_FLAG_FORCEDELAY 1 142 #define TL_FLAG_SCHEDDELAY 2 143 #define TL_FLAG_DELAYTIMEO 3 144 145 /* 146 * The ThunderLAN supports up to 32 PHYs. 147 */ 148 #define TL_PHYADDR_MIN 0x00 149 #define TL_PHYADDR_MAX 0x1F 150 151 #define PHY_UNKNOWN 6 152 153 #define TL_PHYS_IDLE -1 154 155 /* 156 * General constants that are fun to know. 157 * 158 * The ThunderLAN controller is made by Texas Instruments. The 159 * manual indicates that if the EEPROM checksum fails, the PCI 160 * vendor and device ID registers will be loaded with TI-specific 161 * values. 162 */ 163 #define TI_VENDORID 0x104C 164 #define TI_DEVICEID_THUNDERLAN 0x0500 165 166 /* 167 * Known PHY Ids. According to the Level 1 documentation (which is 168 * very nice, incidentally), here's how they work: 169 * 170 * The PHY identifier register #1 is composed of bits 3 through 18 171 * of the OUI. (First 16-bit word.) 172 * The PHY identifier register #2 is composed of bits 19 through 24 173 * if the OUI. 174 * This is followed by 6 bits containing the manufacturer's model 175 * number. 176 * Lastly, there are 4 bits for the manufacturer's revision number. 177 * 178 * Honestly, there are a lot of these that don't make any sense; the 179 * only way to be really sure is to look at the data sheets. 180 */ 181 182 /* 183 * Texas Instruments PHY identifiers 184 * 185 * The ThunderLAN manual has a curious and confusing error in it. 186 * In chapter 7, which describes PHYs, it says that TI PHYs have 187 * the following ID codes, where xx denotes a revision: 188 * 189 * 0x4000501xx internal 10baseT PHY 190 * 0x4000502xx TNETE211 100VG-AnyLan PMI 191 * 192 * The problem here is that these are not valid 32-bit hex numbers: 193 * there's one digit too many. My guess is that they mean the internal 194 * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these 195 * are the only numbers that make sense. 196 */ 197 #define TI_PHY_VENDORID 0x4000 198 #define TI_PHY_10BT 0x501F 199 #define TI_PHY_100VGPMI 0x502F 200 201 /* 202 * These ID values are for the NS DP83840A 10/100 PHY 203 */ 204 #define NS_PHY_VENDORID 0x2000 205 #define NS_PHY_83840A 0x5C0F 206 207 /* 208 * Level 1 10/100 PHY 209 */ 210 #define LEVEL1_PHY_VENDORID 0x7810 211 #define LEVEL1_PHY_LXT970 0x000F 212 213 /* 214 * Intel 82555 10/100 PHY 215 */ 216 #define INTEL_PHY_VENDORID 0x0A28 217 #define INTEL_PHY_82555 0x015F 218 219 /* 220 * SEEQ 80220 10/100 PHY 221 */ 222 #define SEEQ_PHY_VENDORID 0x0016 223 #define SEEQ_PHY_80220 0xF83F 224 225 /* 226 * These are the PCI vendor and device IDs for Compaq ethernet 227 * adapters based on the ThunderLAN controller. 228 */ 229 #define COMPAQ_VENDORID 0x0E11 230 #define COMPAQ_DEVICEID_NETEL_10_100 0xAE32 231 #define COMPAQ_DEVICEID_NETEL_UNKNOWN 0xAE33 232 #define COMPAQ_DEVICEID_NETEL_10 0xAE34 233 #define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED 0xAE35 234 #define COMPAQ_DEVICEID_NETEL_10_100_DUAL 0xAE40 235 #define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT 0xAE43 236 #define COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED 0xB011 237 #define COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX 0xB012 238 #define COMPAQ_DEVICEID_NETEL_10_100_TX_UTP 0xB030 239 #define COMPAQ_DEVICEID_NETFLEX_3P 0xF130 240 #define COMPAQ_DEVICEID_NETFLEX_3P_BNC 0xF150 241 242 /* 243 * These are the PCI vendor and device IDs for Olicom 244 * adapters based on the ThunderLAN controller. 245 */ 246 #define OLICOM_VENDORID 0x108D 247 #define OLICOM_DEVICEID_OC2183 0x0013 248 #define OLICOM_DEVICEID_OC2325 0x0012 249 #define OLICOM_DEVICEID_OC2326 0x0014 250 251 /* 252 * PCI low memory base and low I/O base 253 */ 254 #define TL_PCI_LOIO 0x10 255 #define TL_PCI_LOMEM 0x14 256 257 /* 258 * PCI latency timer (it's actually 0x0D, but we want a value 259 * that's longword aligned). 260 */ 261 #define TL_PCI_LATENCY_TIMER 0x0C 262 263 #define TL_DIO_ADDR_INC 0x8000 /* Increment addr on each read */ 264 #define TL_DIO_RAM_SEL 0x4000 /* RAM address select */ 265 #define TL_DIO_ADDR_MASK 0x3FFF /* address bits mask */ 266 267 /* 268 * Interrupt types 269 */ 270 #define TL_INTR_INVALID 0x0 271 #define TL_INTR_TXEOF 0x1 272 #define TL_INTR_STATOFLOW 0x2 273 #define TL_INTR_RXEOF 0x3 274 #define TL_INTR_DUMMY 0x4 275 #define TL_INTR_TXEOC 0x5 276 #define TL_INTR_ADCHK 0x6 277 #define TL_INTR_RXEOC 0x7 278 279 #define TL_INT_MASK 0x001C 280 #define TL_VEC_MASK 0x1FE0 281 /* 282 * Host command register bits 283 */ 284 #define TL_CMD_GO 0x80000000 285 #define TL_CMD_STOP 0x40000000 286 #define TL_CMD_ACK 0x20000000 287 #define TL_CMD_CHSEL7 0x10000000 288 #define TL_CMD_CHSEL6 0x08000000 289 #define TL_CMD_CHSEL5 0x04000000 290 #define TL_CMD_CHSEL4 0x02000000 291 #define TL_CMD_CHSEL3 0x01000000 292 #define TL_CMD_CHSEL2 0x00800000 293 #define TL_CMD_CHSEL1 0x00400000 294 #define TL_CMD_CHSEL0 0x00200000 295 #define TL_CMD_EOC 0x00100000 296 #define TL_CMD_RT 0x00080000 297 #define TL_CMD_NES 0x00040000 298 #define TL_CMD_ZERO0 0x00020000 299 #define TL_CMD_ZERO1 0x00010000 300 #define TL_CMD_ADRST 0x00008000 301 #define TL_CMD_LDTMR 0x00004000 302 #define TL_CMD_LDTHR 0x00002000 303 #define TL_CMD_REQINT 0x00001000 304 #define TL_CMD_INTSOFF 0x00000800 305 #define TL_CMD_INTSON 0x00000400 306 #define TL_CMD_RSVD0 0x00000200 307 #define TL_CMD_RSVD1 0x00000100 308 #define TL_CMD_ACK7 0x00000080 309 #define TL_CMD_ACK6 0x00000040 310 #define TL_CMD_ACK5 0x00000020 311 #define TL_CMD_ACK4 0x00000010 312 #define TL_CMD_ACK3 0x00000008 313 #define TL_CMD_ACK2 0x00000004 314 #define TL_CMD_ACK1 0x00000002 315 #define TL_CMD_ACK0 0x00000001 316 317 #define TL_CMD_CHSEL_MASK 0x01FE0000 318 #define TL_CMD_ACK_MASK 0xFF 319 320 /* 321 * EEPROM address where station address resides. 322 */ 323 #define TL_EEPROM_EADDR 0x83 324 #define TL_EEPROM_EADDR2 0x99 325 #define TL_EEPROM_EADDR3 0xAF 326 #define TL_EEPROM_EADDR_OC 0xF8 /* Olicom cards use a different 327 address than Compaqs. */ 328 /* 329 * ThunderLAN host command register offsets. 330 * (Can be accessed either by IO ports or memory map.) 331 */ 332 #define TL_HOSTCMD 0x00 333 #define TL_CH_PARM 0x04 334 #define TL_DIO_ADDR 0x08 335 #define TL_HOST_INT 0x0A 336 #define TL_DIO_DATA 0x0C 337 338 /* 339 * ThunderLAN internal registers 340 */ 341 #define TL_NETCMD 0x00 342 #define TL_NETSIO 0x01 343 #define TL_NETSTS 0x02 344 #define TL_NETMASK 0x03 345 346 #define TL_NETCONFIG 0x04 347 #define TL_MANTEST 0x06 348 349 #define TL_VENID_LSB 0x08 350 #define TL_VENID_MSB 0x09 351 #define TL_DEVID_LSB 0x0A 352 #define TL_DEVID_MSB 0x0B 353 354 #define TL_REVISION 0x0C 355 #define TL_SUBCLASS 0x0D 356 #define TL_MINLAT 0x0E 357 #define TL_MAXLAT 0x0F 358 359 #define TL_AREG0_B5 0x10 360 #define TL_AREG0_B4 0x11 361 #define TL_AREG0_B3 0x12 362 #define TL_AREG0_B2 0x13 363 364 #define TL_AREG0_B1 0x14 365 #define TL_AREG0_B0 0x15 366 #define TL_AREG1_B5 0x16 367 #define TL_AREG1_B4 0x17 368 369 #define TL_AREG1_B3 0x18 370 #define TL_AREG1_B2 0x19 371 #define TL_AREG1_B1 0x1A 372 #define TL_AREG1_B0 0x1B 373 374 #define TL_AREG2_B5 0x1C 375 #define TL_AREG2_B4 0x1D 376 #define TL_AREG2_B3 0x1E 377 #define TL_AREG2_B2 0x1F 378 379 #define TL_AREG2_B1 0x20 380 #define TL_AREG2_B0 0x21 381 #define TL_AREG3_B5 0x22 382 #define TL_AREG3_B4 0x23 383 384 #define TL_AREG3_B3 0x24 385 #define TL_AREG3_B2 0x25 386 #define TL_AREG3_B1 0x26 387 #define TL_AREG3_B0 0x27 388 389 #define TL_HASH1 0x28 390 #define TL_HASH2 0x2C 391 #define TL_TXGOODFRAMES 0x30 392 #define TL_TXUNDERRUN 0x33 393 #define TL_RXGOODFRAMES 0x34 394 #define TL_RXOVERRUN 0x37 395 #define TL_DEFEREDTX 0x38 396 #define TL_CRCERROR 0x3A 397 #define TL_CODEERROR 0x3B 398 #define TL_MULTICOLTX 0x3C 399 #define TL_SINGLECOLTX 0x3E 400 #define TL_EXCESSIVECOL 0x40 401 #define TL_LATECOL 0x41 402 #define TL_CARRIERLOSS 0x42 403 #define TL_ACOMMIT 0x43 404 #define TL_LDREG 0x44 405 #define TL_BSIZEREG 0x45 406 #define TL_MAXRX 0x46 407 408 /* 409 * ThunderLAN SIO register bits 410 */ 411 #define TL_SIO_MINTEN 0x80 412 #define TL_SIO_ECLOK 0x40 413 #define TL_SIO_ETXEN 0x20 414 #define TL_SIO_EDATA 0x10 415 #define TL_SIO_NMRST 0x08 416 #define TL_SIO_MCLK 0x04 417 #define TL_SIO_MTXEN 0x02 418 #define TL_SIO_MDATA 0x01 419 420 /* 421 * Thunderlan NETCONFIG bits 422 */ 423 #define TL_CFG_RCLKTEST 0x8000 424 #define TL_CFG_TCLKTEST 0x4000 425 #define TL_CFG_BITRATE 0x2000 426 #define TL_CFG_RXCRC 0x1000 427 #define TL_CFG_PEF 0x0800 428 #define TL_CFG_ONEFRAG 0x0400 429 #define TL_CFG_ONECHAN 0x0200 430 #define TL_CFG_MTEST 0x0100 431 #define TL_CFG_PHYEN 0x0080 432 #define TL_CFG_MACSEL6 0x0040 433 #define TL_CFG_MACSEL5 0x0020 434 #define TL_CFG_MACSEL4 0x0010 435 #define TL_CFG_MACSEL3 0x0008 436 #define TL_CFG_MACSEL2 0x0004 437 #define TL_CFG_MACSEL1 0x0002 438 #define TL_CFG_MACSEL0 0x0001 439 440 /* 441 * ThunderLAN NETSTS bits 442 */ 443 #define TL_STS_MIRQ 0x80 444 #define TL_STS_HBEAT 0x40 445 #define TL_STS_TXSTOP 0x20 446 #define TL_STS_RXSTOP 0x10 447 448 /* 449 * ThunderLAN NETCMD bits 450 */ 451 #define TL_CMD_NRESET 0x80 452 #define TL_CMD_NWRAP 0x40 453 #define TL_CMD_CSF 0x20 454 #define TL_CMD_CAF 0x10 455 #define TL_CMD_NOBRX 0x08 456 #define TL_CMD_DUPLEX 0x04 457 #define TL_CMD_TRFRAM 0x02 458 #define TL_CMD_TXPACE 0x01 459 460 /* 461 * ThunderLAN NETMASK bits 462 */ 463 #define TL_MASK_MASK7 0x80 464 #define TL_MASK_MASK6 0x40 465 #define TL_MASK_MASK5 0x20 466 #define TL_MASK_MASK4 0x10 467 468 /* 469 * MII frame format 470 */ 471 #ifdef ANSI_DOESNT_ALLOW_BITFIELDS 472 struct tl_mii_frame { 473 u_int16_t mii_stdelim:2, 474 mii_opcode:2, 475 mii_phyaddr:5, 476 mii_regaddr:5, 477 mii_turnaround:2; 478 u_int16_t mii_data; 479 }; 480 #else 481 struct tl_mii_frame { 482 u_int8_t mii_stdelim; 483 u_int8_t mii_opcode; 484 u_int8_t mii_phyaddr; 485 u_int8_t mii_regaddr; 486 u_int8_t mii_turnaround; 487 u_int16_t mii_data; 488 }; 489 #endif 490 /* 491 * MII constants 492 */ 493 #define TL_MII_STARTDELIM 0x01 494 #define TL_MII_READOP 0x02 495 #define TL_MII_WRITEOP 0x01 496 #define TL_MII_TURNAROUND 0x02 497 498 #define TL_LAST_FRAG 0x80000000 499 #define TL_CSTAT_UNUSED 0x8000 500 #define TL_CSTAT_FRAMECMP 0x4000 501 #define TL_CSTAT_READY 0x3000 502 #define TL_CSTAT_UNUSED13 0x2000 503 #define TL_CSTAT_UNUSED12 0x1000 504 #define TL_CSTAT_EOC 0x0800 505 #define TL_CSTAT_RXERROR 0x0400 506 #define TL_CSTAT_PASSCRC 0x0200 507 #define TL_CSTAT_DPRIO 0x0100 508 509 #define TL_FRAME_MASK 0x00FFFFFF 510 #define tl_tx_goodframes(x) (x.tl_txstat & TL_FRAME_MASK) 511 #define tl_tx_underrun(x) ((x.tl_txstat & ~TL_FRAME_MASK) >> 24) 512 #define tl_rx_goodframes(x) (x.tl_rxstat & TL_FRAME_MASK) 513 #define tl_rx_overrun(x) ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24) 514 515 struct tl_stats { 516 u_int32_t tl_txstat; 517 u_int32_t tl_rxstat; 518 u_int16_t tl_deferred; 519 u_int8_t tl_crc_errors; 520 u_int8_t tl_code_errors; 521 u_int16_t tl_tx_multi_collision; 522 u_int16_t tl_tx_single_collision; 523 u_int8_t tl_excessive_collision; 524 u_int8_t tl_late_collision; 525 u_int8_t tl_carrier_loss; 526 u_int8_t acommit; 527 }; 528 529 /* 530 * ACOMMIT register bits. These are used only when a bitrate 531 * PHY is selected ('bitrate' bit in netconfig register is set). 532 */ 533 #define TL_AC_MTXER 0x01 /* reserved */ 534 #define TL_AC_MTXD1 0x02 /* 0 == 10baseT 1 == AUI */ 535 #define TL_AC_MTXD2 0x04 /* loopback disable */ 536 #define TL_AC_MTXD3 0x08 /* full duplex disable */ 537 538 /* 539 * register space access macros 540 */ 541 #define CSR_WRITE_4(sc, reg, val) \ 542 bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val) 543 #define CSR_WRITE_2(sc, reg, val) \ 544 bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val) 545 #define CSR_WRITE_1(sc, reg, val) \ 546 bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val) 547 548 #define CSR_READ_4(sc, reg) \ 549 bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg) 550 #define CSR_READ_2(sc, reg) \ 551 bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg) 552 #define CSR_READ_1(sc, reg) \ 553 bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg) 554 555 #define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x) 556 #define CMD_SET(sc, x) \ 557 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x)) 558 #define CMD_CLR(sc, x) \ 559 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x)) 560 561 /* 562 * ThunderLAN adapters typically have a serial EEPROM containing 563 * configuration information. The main reason we're interested in 564 * it is because it also contains the adapters's station address. 565 * 566 * Access to the EEPROM is a bit goofy since it is a serial device: 567 * you have to do reads and writes one bit at a time. The state of 568 * the DATA bit can only change while the CLOCK line is held low. 569 * Transactions work basically like this: 570 * 571 * 1) Send the EEPROM_START sequence to prepare the EEPROM for 572 * accepting commands. This pulls the clock high, sets 573 * the data bit to 0, enables transmission to the EEPROM, 574 * pulls the data bit up to 1, then pulls the clock low. 575 * The idea is to do a 0 to 1 transition of the data bit 576 * while the clock pin is held high. 577 * 578 * 2) To write a bit to the EEPROM, set the TXENABLE bit, then 579 * set the EDATA bit to send a 1 or clear it to send a 0. 580 * Finally, set and then clear ECLOK. Strobing the clock 581 * transmits the bit. After 8 bits have been written, the 582 * EEPROM should respond with an ACK, which should be read. 583 * 584 * 3) To read a bit from the EEPROM, clear the TXENABLE bit, 585 * then set ECLOK. The bit can then be read by reading EDATA. 586 * ECLOCK should then be cleared again. This can be repeated 587 * 8 times to read a whole byte, after which the 588 * 589 * 4) We need to send the address byte to the EEPROM. For this 590 * we have to send the write control byte to the EEPROM to 591 * tell it to accept data. The byte is 0xA0. The EEPROM should 592 * ack this. The address byte can be send after that. 593 * 594 * 5) Now we have to tell the EEPROM to send us data. For that we 595 * have to transmit the read control byte, which is 0xA1. This 596 * byte should also be acked. We can then read the data bits 597 * from the EEPROM. 598 * 599 * 6) When we're all finished, send the EEPROM_STOP sequence. 600 * 601 * Note that we use the ThunderLAN's NetSio register to access the 602 * EEPROM, however there is an alternate method. There is a PCI NVRAM 603 * register at PCI offset 0xB4 which can also be used with minor changes. 604 * The difference is that access to PCI registers via pci_conf_read() 605 * and pci_conf_write() is done using programmed I/O, which we want to 606 * avoid. 607 */ 608 609 /* 610 * Note that EEPROM_START leaves transmission enabled. 611 */ 612 #define EEPROM_START \ 613 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\ 614 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */ \ 615 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\ 616 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\ 617 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 618 619 /* 620 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 621 * that no further data can be written to the EEPROM I/O pin. 622 */ 623 #define EEPROM_STOP \ 624 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */ \ 625 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */ \ 626 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */ \ 627 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */ \ 628 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */ \ 629 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */ \ 630 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 631 632 633 /* 634 * These are the register definitions for the PHY (physical layer 635 * interface chip). 636 * The ThunderLAN chip has a built-in 10Mb/sec PHY which may be used 637 * in some configurations. The Compaq 10/100 cards based on the ThunderLAN 638 * use a National Semiconductor DP83840A PHY. The generic BMCR and BMSR 639 * layouts for both PHYs are identical, however some of the bits are not 640 * used by the ThunderLAN's internal PHY (most notably those dealing with 641 * switching between 10 and 100Mb/sec speeds). Since Both PHYs use the 642 * same bits, we #define them with generic names here. 643 */ 644 /* 645 * PHY BMCR Basic Mode Control Register 646 */ 647 #define PHY_BMCR 0x00 648 #define PHY_BMCR_RESET 0x8000 649 #define PHY_BMCR_LOOPBK 0x4000 650 #define PHY_BMCR_SPEEDSEL 0x2000 651 #define PHY_BMCR_AUTONEGENBL 0x1000 652 #define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 653 #define PHY_BMCR_PWRDOWN 0x0800 /* tlan internal PHY only */ 654 #define PHY_BMCR_ISOLATE 0x0400 655 #define PHY_BMCR_AUTONEGRSTR 0x0200 656 #define PHY_BMCR_DUPLEX 0x0100 657 #define PHY_BMCR_COLLTEST 0x0080 658 #define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 659 #define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 660 #define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 661 #define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 662 #define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 663 #define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 664 #define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 665 /* 666 * RESET: 1 == software reset, 0 == normal operation 667 * Resets status and control registers to default values. 668 * Relatches all hardware config values. 669 * 670 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 671 * 672 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 673 * Link speed is selected byt his bit or if auto-negotiation if bit 674 * 12 (AUTONEGENBL) is set (in which case the value of this register 675 * is ignored). 676 * 677 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 678 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 679 * determine speed and mode. Should be cleared and then set if PHY configured 680 * for no autoneg on startup. 681 * 682 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 683 * 684 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 685 * 686 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 687 * 688 * COLLTEST: 1 == collision test enabled, 0 == normal operation 689 */ 690 691 /* 692 * PHY, BMSR Basic Mode Status Register 693 */ 694 #define PHY_BMSR 0x01 695 #define PHY_BMSR_100BT4 0x8000 696 #define PHY_BMSR_100BTXFULL 0x4000 697 #define PHY_BMSR_100BTXHALF 0x2000 698 #define PHY_BMSR_10BTFULL 0x1000 699 #define PHY_BMSR_10BTHALF 0x0800 700 #define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 701 #define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 702 #define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 703 #define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 704 #define PHY_BMSR_MFPRESUP 0x0040 705 #define PHY_BMSR_AUTONEGCOMP 0x0020 706 #define PHY_BMSR_REMFAULT 0x0010 707 #define PHY_BMSR_CANAUTONEG 0x0008 708 #define PHY_BMSR_LINKSTAT 0x0004 709 #define PHY_BMSR_JABBER 0x0002 710 #define PHY_BMSR_EXTENDED 0x0001 711 712 #define PHY_CTL_IGLINK 0x8000 713 #define PHY_CTL_SWAPOL 0x4000 714 #define PHY_CTL_AUISEL 0x2000 715 #define PHY_CTL_SQEEN 0x1000 716 #define PHY_CTL_MTEST 0x0800 717 #define PHY_CTL_NFEW 0x0004 718 #define PHY_CTL_INTEN 0x0002 719 #define PHY_CTL_TINT 0x0001 720 721 #define TL_PHY_GENCTL 0x00 722 #define TL_PHY_GENSTS 0x01 723 724 /* 725 * PHY Generic Identifier Register, hi bits 726 */ 727 #define TL_PHY_VENID 0x02 728 729 /* 730 * PHY Generic Identifier Register, lo bits 731 */ 732 #define TL_PHY_DEVID 0x03 733 734 #define TL_PHY_ANAR 0x04 735 #define TL_PHY_LPAR 0x05 736 #define TL_PHY_ANEXP 0x06 737 738 #define TL_PHY_PHYID 0x10 739 #define TL_PHY_CTL 0x11 740 #define TL_PHY_STS 0x12 741 742 #define TL_LPAR_RMFLT 0x2000 743 #define TL_LPAR_RSVD0 0x1000 744 #define TL_LPAR_RSVD1 0x0800 745 #define TL_LPAR_100BT4 0x0400 746 #define TL_LPAR_100BTXFULL 0x0200 747 #define TL_LPAR_100BTXHALF 0x0100 748 #define TL_LPAR_10BTFULL 0x0080 749 #define TL_LPAR_10BTHALF 0x0040 750 751 /* 752 * PHY Antoneg advertisement register. 753 */ 754 #define PHY_ANAR TL_PHY_ANAR 755 #define PHY_ANAR_NEXTPAGE 0x8000 756 #define PHY_ANAR_RSVD0 0x4000 757 #define PHY_ANAR_TLRFLT 0x2000 758 #define PHY_ANAR_RSVD1 0x1000 759 #define PHY_RSVD_RSDV2 0x0800 760 #define PHY_RSVD_RSVD3 0x0400 761 #define PHY_ANAR_100BT4 0x0200 762 #define PHY_ANAR_100BTXFULL 0x0100 763 #define PHY_ANAR_100BTXHALF 0x0080 764 #define PHY_ANAR_10BTFULL 0x0040 765 #define PHY_ANAR_10BTHALF 0x0020 766 #define PHY_ANAR_PROTO4 0x0010 767 #define PHY_ANAR_PROTO3 0x0008 768 #define PHY_ANAR_PROTO2 0x0004 769 #define PHY_AHAR_PROTO1 0x0002 770 #define PHY_AHAR_PROTO0 0x0001 771 772 /* 773 * DP83840 PHY, PCS Confifguration Register 774 */ 775 #define TL_DP83840_PCS 0x17 776 #define TL_DP83840_PCS_LED4_MODE 0x0002 777 #define TL_DP83840_PCS_F_CONNECT 0x0020 778 #define TL_DP83840_PCS_BIT8 0x0100 779 #define TL_DP83840_PCS_BIT10 0x0400 780 781 /* 782 * DP83840 PHY, PAR register 783 */ 784 #define TL_DP83840_PAR 0x19 785 786 #define PAR_RSVD0 0x8000 787 #define PAR_RSVD1 0x4000 788 #define PAR_RSVD2 0x2000 789 #define PAR_RSVD3 0x1000 790 #define PAR_DIS_CRS_JAB 0x0800 791 #define PAR_AN_EN_STAT 0x0400 792 #define PAR_RSVD4 0x0200 793 #define PAR_FEFI_EN 0x0100 794 #define PAR_DUPLEX_STAT 0x0080 795 #define PAR_SPEED_10 0x0040 796 #define PAR_CIM_STATUS 0x0020 797 #define PAR_PHYADDR4 0x0010 798 #define PAR_PHYADDR3 0x0008 799 #define PAR_PHYADDR2 0x0004 800 #define PAR_PHYADDR1 0x0002 801 #define PAR_PHYADDR0 0x0001 802 803 804 /* 805 * Microchip Technology 24Cxx EEPROM control bytes 806 */ 807 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 808 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 809 810 #ifdef __alpha__ 811 #undef vtophys 812 #define vtophys(va) (pmap_kextract(((vm_offset_t) (va))) \ 813 + 1*1024*1024*1024) 814 #endif
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