The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/pci/if_tlreg.h

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 1997, 1998
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/5.4/sys/pci/if_tlreg.h 141090 2005-01-31 23:27:04Z imp $
   33  */
   34 
   35 
   36 struct tl_type {
   37         u_int16_t               tl_vid;
   38         u_int16_t               tl_did;
   39         char                    *tl_name;
   40 };
   41 
   42 /*
   43  * ThunderLAN TX/RX list format. The TX and RX lists are pretty much
   44  * identical: the list begins with a 32-bit forward pointer which points
   45  * at the next list in the chain, followed by 16 bits for the total
   46  * frame size, and a 16 bit status field. This is followed by a series
   47  * of 10 32-bit data count/data address pairs that point to the fragments
   48  * that make up the complete frame.
   49  */
   50 
   51 #define TL_MAXFRAGS             10
   52 #define TL_RX_LIST_CNT          64
   53 #define TL_TX_LIST_CNT          128
   54 #define TL_MIN_FRAMELEN         64
   55 
   56 struct tl_frag {
   57         u_int32_t               tlist_dcnt;
   58         u_int32_t               tlist_dadr;
   59 };
   60 
   61 struct tl_list {
   62         u_int32_t               tlist_fptr;     /* phys address of next list */
   63         u_int16_t               tlist_cstat;    /* status word */
   64         u_int16_t               tlist_frsize;   /* size of data in frame */
   65         struct tl_frag          tl_frag[TL_MAXFRAGS];
   66 };
   67 
   68 /*
   69  * This is a special case of an RX list. By setting the One_Frag
   70  * bit in the NETCONFIG register, the driver can force the ThunderLAN
   71  * chip to use only one fragment when DMAing RX frames.
   72  */
   73 
   74 struct tl_list_onefrag {
   75         u_int32_t               tlist_fptr;
   76         u_int16_t               tlist_cstat;
   77         u_int16_t               tlist_frsize;
   78         struct tl_frag          tl_frag;
   79 };
   80 
   81 struct tl_list_data {
   82         struct tl_list_onefrag  tl_rx_list[TL_RX_LIST_CNT];
   83         struct tl_list          tl_tx_list[TL_TX_LIST_CNT];
   84         unsigned char           tl_pad[TL_MIN_FRAMELEN];
   85 };
   86 
   87 struct tl_chain {
   88         struct tl_list          *tl_ptr;
   89         struct mbuf             *tl_mbuf;
   90         struct tl_chain         *tl_next;
   91 };
   92 
   93 struct tl_chain_onefrag {
   94         struct tl_list_onefrag  *tl_ptr;
   95         struct mbuf             *tl_mbuf;
   96         struct tl_chain_onefrag *tl_next;
   97 };
   98 
   99 struct tl_chain_data {
  100         struct tl_chain_onefrag tl_rx_chain[TL_RX_LIST_CNT];
  101         struct tl_chain         tl_tx_chain[TL_TX_LIST_CNT];
  102 
  103         struct tl_chain_onefrag *tl_rx_head;
  104         struct tl_chain_onefrag *tl_rx_tail;
  105 
  106         struct tl_chain         *tl_tx_head;
  107         struct tl_chain         *tl_tx_tail;
  108         struct tl_chain         *tl_tx_free;
  109 };
  110 
  111 struct tl_softc {
  112         struct arpcom           arpcom;         /* interface info */
  113         struct ifmedia          ifmedia;        /* media info */
  114         bus_space_handle_t      tl_bhandle;
  115         bus_space_tag_t         tl_btag;
  116         void                    *tl_intrhand;
  117         struct resource         *tl_irq;
  118         struct resource         *tl_res;
  119         device_t                tl_miibus;
  120         struct tl_type          *tl_dinfo;      /* ThunderLAN adapter info */
  121         u_int8_t                tl_eeaddr;
  122         struct tl_list_data     *tl_ldata;      /* TX/RX lists and mbufs */
  123         struct tl_chain_data    tl_cdata;
  124         u_int8_t                tl_txeoc;
  125         u_int8_t                tl_bitrate;
  126         int                     tl_if_flags;
  127         struct callout_handle   tl_stat_ch;
  128         struct mtx              tl_mtx;
  129 };
  130 
  131 #define TL_LOCK(_sc)            mtx_lock(&(_sc)->tl_mtx)
  132 #define TL_UNLOCK(_sc)          mtx_unlock(&(_sc)->tl_mtx)
  133 #define TL_LOCK_ASSERT(_sc)     mtx_assert(&(_sc)->tl_mtx, MA_OWNED)
  134 
  135 /*
  136  * Transmit interrupt threshold.
  137  */
  138 #define TX_THR          0x00000004
  139 
  140 /*
  141  * General constants that are fun to know.
  142  *
  143  * The ThunderLAN controller is made by Texas Instruments. The
  144  * manual indicates that if the EEPROM checksum fails, the PCI
  145  * vendor and device ID registers will be loaded with TI-specific
  146  * values.
  147  */
  148 #define TI_VENDORID             0x104C
  149 #define TI_DEVICEID_THUNDERLAN  0x0500
  150 
  151 /*
  152  * These are the PCI vendor and device IDs for Compaq ethernet
  153  * adapters based on the ThunderLAN controller.
  154  */
  155 #define COMPAQ_VENDORID                         0x0E11
  156 #define COMPAQ_DEVICEID_NETEL_10_100            0xAE32
  157 #define COMPAQ_DEVICEID_NETEL_UNKNOWN           0xAE33
  158 #define COMPAQ_DEVICEID_NETEL_10                0xAE34
  159 #define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED   0xAE35
  160 #define COMPAQ_DEVICEID_NETEL_10_100_DUAL       0xAE40
  161 #define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT   0xAE43
  162 #define COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED   0xB011
  163 #define COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX    0xB012
  164 #define COMPAQ_DEVICEID_NETEL_10_100_TX_UTP     0xB030
  165 #define COMPAQ_DEVICEID_NETFLEX_3P              0xF130
  166 #define COMPAQ_DEVICEID_NETFLEX_3P_BNC          0xF150
  167 
  168 /*
  169  * These are the PCI vendor and device IDs for Olicom
  170  * adapters based on the ThunderLAN controller.
  171  */
  172 #define OLICOM_VENDORID                         0x108D
  173 #define OLICOM_DEVICEID_OC2183                  0x0013
  174 #define OLICOM_DEVICEID_OC2325                  0x0012
  175 #define OLICOM_DEVICEID_OC2326                  0x0014
  176 
  177 /*
  178  * PCI low memory base and low I/O base
  179  */
  180 #define TL_PCI_LOIO             0x10
  181 #define TL_PCI_LOMEM            0x14
  182 
  183 /*
  184  * PCI latency timer (it's actually 0x0D, but we want a value
  185  * that's longword aligned).
  186  */
  187 #define TL_PCI_LATENCY_TIMER    0x0C
  188 
  189 #define TL_DIO_ADDR_INC         0x8000  /* Increment addr on each read */
  190 #define TL_DIO_RAM_SEL          0x4000  /* RAM address select */
  191 #define TL_DIO_ADDR_MASK        0x3FFF  /* address bits mask */
  192 
  193 /*
  194  * Interrupt types
  195  */
  196 #define TL_INTR_INVALID         0x0
  197 #define TL_INTR_TXEOF           0x1
  198 #define TL_INTR_STATOFLOW       0x2
  199 #define TL_INTR_RXEOF           0x3
  200 #define TL_INTR_DUMMY           0x4
  201 #define TL_INTR_TXEOC           0x5
  202 #define TL_INTR_ADCHK           0x6
  203 #define TL_INTR_RXEOC           0x7
  204 
  205 #define TL_INT_MASK             0x001C
  206 #define TL_VEC_MASK             0x1FE0
  207 /*
  208  * Host command register bits
  209  */
  210 #define TL_CMD_GO               0x80000000
  211 #define TL_CMD_STOP             0x40000000
  212 #define TL_CMD_ACK              0x20000000
  213 #define TL_CMD_CHSEL7           0x10000000
  214 #define TL_CMD_CHSEL6           0x08000000
  215 #define TL_CMD_CHSEL5           0x04000000
  216 #define TL_CMD_CHSEL4           0x02000000
  217 #define TL_CMD_CHSEL3           0x01000000
  218 #define TL_CMD_CHSEL2           0x00800000
  219 #define TL_CMD_CHSEL1           0x00400000
  220 #define TL_CMD_CHSEL0           0x00200000
  221 #define TL_CMD_EOC              0x00100000
  222 #define TL_CMD_RT               0x00080000
  223 #define TL_CMD_NES              0x00040000
  224 #define TL_CMD_ZERO0            0x00020000
  225 #define TL_CMD_ZERO1            0x00010000
  226 #define TL_CMD_ADRST            0x00008000
  227 #define TL_CMD_LDTMR            0x00004000
  228 #define TL_CMD_LDTHR            0x00002000
  229 #define TL_CMD_REQINT           0x00001000
  230 #define TL_CMD_INTSOFF          0x00000800
  231 #define TL_CMD_INTSON           0x00000400
  232 #define TL_CMD_RSVD0            0x00000200
  233 #define TL_CMD_RSVD1            0x00000100
  234 #define TL_CMD_ACK7             0x00000080
  235 #define TL_CMD_ACK6             0x00000040
  236 #define TL_CMD_ACK5             0x00000020
  237 #define TL_CMD_ACK4             0x00000010
  238 #define TL_CMD_ACK3             0x00000008
  239 #define TL_CMD_ACK2             0x00000004
  240 #define TL_CMD_ACK1             0x00000002
  241 #define TL_CMD_ACK0             0x00000001
  242 
  243 #define TL_CMD_CHSEL_MASK       0x01FE0000
  244 #define TL_CMD_ACK_MASK         0xFF
  245 
  246 /*
  247  * EEPROM address where station address resides.
  248  */
  249 #define TL_EEPROM_EADDR         0x83
  250 #define TL_EEPROM_EADDR2        0x99
  251 #define TL_EEPROM_EADDR3        0xAF
  252 #define TL_EEPROM_EADDR_OC      0xF8    /* Olicom cards use a different
  253                                            address than Compaqs. */
  254 /*
  255  * ThunderLAN host command register offsets.
  256  * (Can be accessed either by IO ports or memory map.)
  257  */
  258 #define TL_HOSTCMD              0x00
  259 #define TL_CH_PARM              0x04
  260 #define TL_DIO_ADDR             0x08
  261 #define TL_HOST_INT             0x0A
  262 #define TL_DIO_DATA             0x0C
  263 
  264 /*
  265  * ThunderLAN internal registers
  266  */
  267 #define TL_NETCMD               0x00
  268 #define TL_NETSIO               0x01
  269 #define TL_NETSTS               0x02
  270 #define TL_NETMASK              0x03
  271 
  272 #define TL_NETCONFIG            0x04
  273 #define TL_MANTEST              0x06
  274 
  275 #define TL_VENID_LSB            0x08
  276 #define TL_VENID_MSB            0x09
  277 #define TL_DEVID_LSB            0x0A
  278 #define TL_DEVID_MSB            0x0B
  279 
  280 #define TL_REVISION             0x0C
  281 #define TL_SUBCLASS             0x0D
  282 #define TL_MINLAT               0x0E
  283 #define TL_MAXLAT               0x0F
  284 
  285 #define TL_AREG0_B5             0x10
  286 #define TL_AREG0_B4             0x11
  287 #define TL_AREG0_B3             0x12
  288 #define TL_AREG0_B2             0x13
  289 
  290 #define TL_AREG0_B1             0x14
  291 #define TL_AREG0_B0             0x15
  292 #define TL_AREG1_B5             0x16
  293 #define TL_AREG1_B4             0x17
  294 
  295 #define TL_AREG1_B3             0x18
  296 #define TL_AREG1_B2             0x19
  297 #define TL_AREG1_B1             0x1A
  298 #define TL_AREG1_B0             0x1B
  299 
  300 #define TL_AREG2_B5             0x1C
  301 #define TL_AREG2_B4             0x1D
  302 #define TL_AREG2_B3             0x1E
  303 #define TL_AREG2_B2             0x1F
  304 
  305 #define TL_AREG2_B1             0x20
  306 #define TL_AREG2_B0             0x21
  307 #define TL_AREG3_B5             0x22
  308 #define TL_AREG3_B4             0x23
  309 
  310 #define TL_AREG3_B3             0x24
  311 #define TL_AREG3_B2             0x25
  312 #define TL_AREG3_B1             0x26
  313 #define TL_AREG3_B0             0x27
  314 
  315 #define TL_HASH1                0x28
  316 #define TL_HASH2                0x2C
  317 #define TL_TXGOODFRAMES         0x30
  318 #define TL_TXUNDERRUN           0x33
  319 #define TL_RXGOODFRAMES         0x34
  320 #define TL_RXOVERRUN            0x37
  321 #define TL_DEFEREDTX            0x38
  322 #define TL_CRCERROR             0x3A
  323 #define TL_CODEERROR            0x3B
  324 #define TL_MULTICOLTX           0x3C
  325 #define TL_SINGLECOLTX          0x3E
  326 #define TL_EXCESSIVECOL         0x40
  327 #define TL_LATECOL              0x41
  328 #define TL_CARRIERLOSS          0x42
  329 #define TL_ACOMMIT              0x43
  330 #define TL_LDREG                0x44
  331 #define TL_BSIZEREG             0x45
  332 #define TL_MAXRX                0x46
  333 
  334 /*
  335  * ThunderLAN SIO register bits
  336  */
  337 #define TL_SIO_MINTEN           0x80
  338 #define TL_SIO_ECLOK            0x40
  339 #define TL_SIO_ETXEN            0x20
  340 #define TL_SIO_EDATA            0x10
  341 #define TL_SIO_NMRST            0x08
  342 #define TL_SIO_MCLK             0x04
  343 #define TL_SIO_MTXEN            0x02
  344 #define TL_SIO_MDATA            0x01
  345 
  346 /*
  347  * Thunderlan NETCONFIG bits
  348  */
  349 #define TL_CFG_RCLKTEST         0x8000
  350 #define TL_CFG_TCLKTEST         0x4000
  351 #define TL_CFG_BITRATE          0x2000
  352 #define TL_CFG_RXCRC            0x1000
  353 #define TL_CFG_PEF              0x0800
  354 #define TL_CFG_ONEFRAG          0x0400
  355 #define TL_CFG_ONECHAN          0x0200
  356 #define TL_CFG_MTEST            0x0100
  357 #define TL_CFG_PHYEN            0x0080
  358 #define TL_CFG_MACSEL6          0x0040
  359 #define TL_CFG_MACSEL5          0x0020
  360 #define TL_CFG_MACSEL4          0x0010
  361 #define TL_CFG_MACSEL3          0x0008
  362 #define TL_CFG_MACSEL2          0x0004
  363 #define TL_CFG_MACSEL1          0x0002
  364 #define TL_CFG_MACSEL0          0x0001
  365 
  366 /*
  367  * ThunderLAN NETSTS bits
  368  */
  369 #define TL_STS_MIRQ             0x80
  370 #define TL_STS_HBEAT            0x40
  371 #define TL_STS_TXSTOP           0x20
  372 #define TL_STS_RXSTOP           0x10
  373 
  374 /*
  375  * ThunderLAN NETCMD bits
  376  */
  377 #define TL_CMD_NRESET           0x80
  378 #define TL_CMD_NWRAP            0x40
  379 #define TL_CMD_CSF              0x20
  380 #define TL_CMD_CAF              0x10
  381 #define TL_CMD_NOBRX            0x08
  382 #define TL_CMD_DUPLEX           0x04
  383 #define TL_CMD_TRFRAM           0x02
  384 #define TL_CMD_TXPACE           0x01
  385 
  386 /*
  387  * ThunderLAN NETMASK bits
  388  */
  389 #define TL_MASK_MASK7           0x80
  390 #define TL_MASK_MASK6           0x40
  391 #define TL_MASK_MASK5           0x20
  392 #define TL_MASK_MASK4           0x10
  393 
  394 /*
  395  * MII frame format
  396  */
  397 #ifdef ANSI_DOESNT_ALLOW_BITFIELDS
  398 struct tl_mii_frame {
  399         u_int16_t               mii_stdelim:2,
  400                                 mii_opcode:2,
  401                                 mii_phyaddr:5,
  402                                 mii_regaddr:5,
  403                                 mii_turnaround:2;
  404         u_int16_t               mii_data;
  405 };
  406 #else
  407 struct tl_mii_frame {
  408         u_int8_t                mii_stdelim;
  409         u_int8_t                mii_opcode;
  410         u_int8_t                mii_phyaddr;
  411         u_int8_t                mii_regaddr;
  412         u_int8_t                mii_turnaround;
  413         u_int16_t               mii_data;
  414 };
  415 #endif
  416 /*
  417  * MII constants
  418  */
  419 #define TL_MII_STARTDELIM       0x01
  420 #define TL_MII_READOP           0x02
  421 #define TL_MII_WRITEOP          0x01
  422 #define TL_MII_TURNAROUND       0x02
  423 
  424 #define TL_LAST_FRAG            0x80000000
  425 #define TL_CSTAT_UNUSED         0x8000
  426 #define TL_CSTAT_FRAMECMP       0x4000
  427 #define TL_CSTAT_READY          0x3000
  428 #define TL_CSTAT_UNUSED13       0x2000
  429 #define TL_CSTAT_UNUSED12       0x1000
  430 #define TL_CSTAT_EOC            0x0800
  431 #define TL_CSTAT_RXERROR        0x0400
  432 #define TL_CSTAT_PASSCRC        0x0200
  433 #define TL_CSTAT_DPRIO          0x0100
  434 
  435 #define TL_FRAME_MASK           0x00FFFFFF
  436 #define tl_tx_goodframes(x)     (x.tl_txstat & TL_FRAME_MASK)
  437 #define tl_tx_underrun(x)       ((x.tl_txstat & ~TL_FRAME_MASK) >> 24)
  438 #define tl_rx_goodframes(x)     (x.tl_rxstat & TL_FRAME_MASK)
  439 #define tl_rx_overrun(x)        ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24)
  440 
  441 struct tl_stats {
  442         u_int32_t               tl_txstat;
  443         u_int32_t               tl_rxstat;
  444         u_int16_t               tl_deferred;
  445         u_int8_t                tl_crc_errors;
  446         u_int8_t                tl_code_errors;
  447         u_int16_t               tl_tx_multi_collision;
  448         u_int16_t               tl_tx_single_collision;
  449         u_int8_t                tl_excessive_collision;
  450         u_int8_t                tl_late_collision;
  451         u_int8_t                tl_carrier_loss;
  452         u_int8_t                acommit;
  453 };
  454 
  455 /*
  456  * ACOMMIT register bits. These are used only when a bitrate
  457  * PHY is selected ('bitrate' bit in netconfig register is set).
  458  */
  459 #define TL_AC_MTXER             0x01    /* reserved */
  460 #define TL_AC_MTXD1             0x02    /* 0 == 10baseT 1 == AUI */
  461 #define TL_AC_MTXD2             0x04    /* loopback disable */
  462 #define TL_AC_MTXD3             0x08    /* full duplex disable */
  463 
  464 #define TL_AC_TXTHRESH          0xF0
  465 #define TL_AC_TXTHRESH_16LONG   0x00
  466 #define TL_AC_TXTHRESH_32LONG   0x10
  467 #define TL_AC_TXTHRESH_64LONG   0x20
  468 #define TL_AC_TXTHRESH_128LONG  0x30
  469 #define TL_AC_TXTHRESH_256LONG  0x40
  470 #define TL_AC_TXTHRESH_WHOLEPKT 0x50
  471 
  472 /*
  473  * PCI burst size register (TL_BSIZEREG).
  474  */
  475 #define TL_RXBURST              0x0F
  476 #define TL_TXBURST              0xF0
  477 
  478 #define TL_RXBURST_4LONG        0x00
  479 #define TL_RXBURST_8LONG        0x01
  480 #define TL_RXBURST_16LONG       0x02
  481 #define TL_RXBURST_32LONG       0x03
  482 #define TL_RXBURST_64LONG       0x04
  483 #define TL_RXBURST_128LONG      0x05
  484 
  485 #define TL_TXBURST_4LONG        0x00
  486 #define TL_TXBURST_8LONG        0x10
  487 #define TL_TXBURST_16LONG       0x20
  488 #define TL_TXBURST_32LONG       0x30
  489 #define TL_TXBURST_64LONG       0x40
  490 #define TL_TXBURST_128LONG      0x50
  491 
  492 /*
  493  * register space access macros
  494  */
  495 #define CSR_WRITE_4(sc, reg, val)       \
  496         bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val)
  497 #define CSR_WRITE_2(sc, reg, val)       \
  498         bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val)
  499 #define CSR_WRITE_1(sc, reg, val)       \
  500         bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val)
  501 
  502 #define CSR_READ_4(sc, reg)             \
  503         bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg)
  504 #define CSR_READ_2(sc, reg)             \
  505         bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg)
  506 #define CSR_READ_1(sc, reg)             \
  507         bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg)
  508 
  509 #define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x)
  510 #define CMD_SET(sc, x)  \
  511         CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x))
  512 #define CMD_CLR(sc, x)  \
  513         CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x))
  514 
  515 /*
  516  * ThunderLAN adapters typically have a serial EEPROM containing
  517  * configuration information. The main reason we're interested in
  518  * it is because it also contains the adapters's station address.
  519  *
  520  * Access to the EEPROM is a bit goofy since it is a serial device:
  521  * you have to do reads and writes one bit at a time. The state of
  522  * the DATA bit can only change while the CLOCK line is held low.
  523  * Transactions work basically like this:
  524  *
  525  * 1) Send the EEPROM_START sequence to prepare the EEPROM for
  526  *    accepting commands. This pulls the clock high, sets
  527  *    the data bit to 0, enables transmission to the EEPROM,
  528  *    pulls the data bit up to 1, then pulls the clock low.
  529  *    The idea is to do a 0 to 1 transition of the data bit
  530  *    while the clock pin is held high.
  531  *
  532  * 2) To write a bit to the EEPROM, set the TXENABLE bit, then
  533  *    set the EDATA bit to send a 1 or clear it to send a 0.
  534  *    Finally, set and then clear ECLOK. Strobing the clock
  535  *    transmits the bit. After 8 bits have been written, the
  536  *    EEPROM should respond with an ACK, which should be read.
  537  *
  538  * 3) To read a bit from the EEPROM, clear the TXENABLE bit,
  539  *    then set ECLOK. The bit can then be read by reading EDATA.
  540  *    ECLOCK should then be cleared again. This can be repeated
  541  *    8 times to read a whole byte, after which the 
  542  *
  543  * 4) We need to send the address byte to the EEPROM. For this
  544  *    we have to send the write control byte to the EEPROM to
  545  *    tell it to accept data. The byte is 0xA0. The EEPROM should
  546  *    ack this. The address byte can be send after that.
  547  *
  548  * 5) Now we have to tell the EEPROM to send us data. For that we
  549  *    have to transmit the read control byte, which is 0xA1. This
  550  *    byte should also be acked. We can then read the data bits
  551  *    from the EEPROM.
  552  *
  553  * 6) When we're all finished, send the EEPROM_STOP sequence.
  554  *
  555  * Note that we use the ThunderLAN's NetSio register to access the
  556  * EEPROM, however there is an alternate method. There is a PCI NVRAM
  557  * register at PCI offset 0xB4 which can also be used with minor changes.
  558  * The difference is that access to PCI registers via pci_conf_read()
  559  * and pci_conf_write() is done using programmed I/O, which we want to
  560  * avoid.
  561  */
  562 
  563 /*
  564  * Note that EEPROM_START leaves transmission enabled.
  565  */
  566 #define EEPROM_START                                                    \
  567         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\
  568         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */     \
  569         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\
  570         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\
  571         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */
  572 
  573 /*
  574  * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so
  575  * that no further data can be written to the EEPROM I/O pin.
  576  */
  577 #define EEPROM_STOP                                                     \
  578         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */  \
  579         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */        \
  580         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */       \
  581         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */   \
  582         tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */      \
  583         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */ \
  584         tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */
  585 
  586 
  587 /*
  588  * Microchip Technology 24Cxx EEPROM control bytes
  589  */
  590 #define EEPROM_CTL_READ                 0xA1    /* 0101 0001 */
  591 #define EEPROM_CTL_WRITE                0xA0    /* 0101 0000 */
  592 
  593 #ifdef __alpha__
  594 #undef vtophys
  595 #define vtophys(va)             alpha_XXX_dmamap((vm_offset_t)va)
  596 #endif

Cache object: 4d93daa12ac2c3221d3b18dea62f2e7f


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.