Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_txvar.h
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1 /* $OpenBSD: if_txvar.h,v 1.3 1998/10/10 04:30:09 jason Exp $ */ 2 /* $FreeBSD$ */ 3 4 /*- 5 * Copyright (c) 1997 Semen Ustimenko 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * 30 */ 31 32 /* 33 * Configuration 34 */ 35 #ifndef ETHER_MAX_LEN 36 #define ETHER_MAX_LEN 1518 37 #endif 38 #ifndef ETHER_MIN_LEN 39 #define ETHER_MIN_LEN 64 40 #endif 41 #ifndef ETHER_CRC_LEN 42 #define ETHER_CRC_LEN 4 43 #endif 44 #define TX_RING_SIZE 16 /* Leave this a power of 2 */ 45 #define RX_RING_SIZE 16 /* And this too, to do not */ 46 /* confuse RX(TX)_RING_MASK */ 47 #define TX_RING_MASK (TX_RING_SIZE - 1) 48 #define RX_RING_MASK (RX_RING_SIZE - 1) 49 #define EPIC_FULL_DUPLEX 1 50 #define EPIC_HALF_DUPLEX 0 51 #define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN) 52 #define EPIC_LINK_DOWN 0x00000001 53 54 /* PCI identification */ 55 #define SMC_VENDORID 0x10B8 56 #define CHIPID_83C170 0x0005 57 #define PCI_VENDORID(x) ((x) & 0xFFFF) 58 #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF) 59 60 /* PCI configuration */ 61 #define PCI_CFID 0x00 /* Configuration ID */ 62 #define PCI_CFCS 0x04 /* Configurtion Command/Status */ 63 #define PCI_CFRV 0x08 /* Configuration Revision */ 64 #define PCI_CFLT 0x0c /* Configuration Latency Timer */ 65 #define PCI_CBIO 0x10 /* Configuration Base IO Address */ 66 #define PCI_CBMA 0x14 /* Configuration Base Memory Address */ 67 #define PCI_CFIT 0x3c /* Configuration Interrupt */ 68 #define PCI_CFDA 0x40 /* Configuration Driver Area */ 69 70 #define PCI_CONF_WRITE(r, v) pci_conf_write(config_id, (r), (v)) 71 #define PCI_CONF_READ(r) pci_conf_read(config_id, (r)) 72 73 /* EPIC's registers */ 74 #define COMMAND 0x0000 75 #define INTSTAT 0x0004 /* Interrupt status. See below */ 76 #define INTMASK 0x0008 /* Interrupt mask. See below */ 77 #define GENCTL 0x000C 78 #define NVCTL 0x0010 79 #define EECTL 0x0014 /* EEPROM control **/ 80 #define TEST1 0x001C /* XXXXX */ 81 #define CRCCNT 0x0020 /* CRC error counter */ 82 #define ALICNT 0x0024 /* FrameTooLang error counter */ 83 #define MPCNT 0x0028 /* MissedFrames error counters */ 84 #define MIICTL 0x0030 85 #define MIIDATA 0x0034 86 #define MIICFG 0x0038 87 #define IPG 0x003C 88 #define LAN0 0x0040 /* MAC address */ 89 #define LAN1 0x0044 /* MAC address */ 90 #define LAN2 0x0048 /* MAC address */ 91 #define ID_CHK 0x004C 92 #define MC0 0x0050 /* Multicast filter table */ 93 #define MC1 0x0054 /* Multicast filter table */ 94 #define MC2 0x0058 /* Multicast filter table */ 95 #define MC3 0x005C /* Multicast filter table */ 96 #define RXCON 0x0060 /* Rx control register */ 97 #define TXCON 0x0070 /* Tx control register */ 98 #define TXSTAT 0x0074 99 #define PRCDAR 0x0084 /* RxRing bus address */ 100 #define PRSTAT 0x00A4 101 #define PRCPTHR 0x00B0 102 #define PTCDAR 0x00C4 /* TxRing bus address */ 103 #define ETXTHR 0x00DC 104 105 #define COMMAND_STOP_RX 0x01 106 #define COMMAND_START_RX 0x02 107 #define COMMAND_TXQUEUED 0x04 108 #define COMMAND_RXQUEUED 0x08 109 #define COMMAND_NEXTFRAME 0x10 110 #define COMMAND_STOP_TDMA 0x20 111 #define COMMAND_STOP_RDMA 0x40 112 #define COMMAND_TXUGO 0x80 113 114 /* Tx threshold */ 115 #define TX_FIFO_THRESH 0x80 /* 0x40 or 0x10 */ 116 117 /* Interrupt register bits */ 118 #define INTSTAT_RCC 0x00000001 119 #define INTSTAT_HCC 0x00000002 120 #define INTSTAT_RQE 0x00000004 121 #define INTSTAT_OVW 0x00000008 122 #define INTSTAT_RXE 0x00000010 123 #define INTSTAT_TXC 0x00000020 124 #define INTSTAT_TCC 0x00000040 125 #define INTSTAT_TQE 0x00000080 126 #define INTSTAT_TXU 0x00000100 127 #define INTSTAT_CNT 0x00000200 128 #define INTSTAT_PREI 0x00000400 129 #define INTSTAT_RCT 0x00000800 130 #define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */ 131 #define INTSTAT_UNUSED1 0x00002000 132 #define INTSTAT_UNUSED2 0x00004000 133 #define INTSTAT_GP2 0x00008000 /* PHY Event */ 134 #define INTSTAT_INT_ACTV 0x00010000 135 #define INTSTAT_RXIDLE 0x00020000 136 #define INTSTAT_TXIDLE 0x00040000 137 #define INTSTAT_RCIP 0x00080000 138 #define INTSTAT_TCIP 0x00100000 139 #define INTSTAT_RBE 0x00200000 140 #define INTSTAT_RCTS 0x00400000 141 #define INTSTAT_RSV 0x00800000 142 #define INTSTAT_DPE 0x01000000 /* PCI Fatal error */ 143 #define INTSTAT_APE 0x02000000 /* PCI Fatal error */ 144 #define INTSTAT_PMA 0x04000000 /* PCI Fatal error */ 145 #define INTSTAT_PTA 0x08000000 /* PCI Fatal error */ 146 147 #define GENCTL_SOFT_RESET 0x00000001 148 #define GENCTL_ENABLE_INTERRUPT 0x00000002 149 #define GENCTL_SOFTWARE_INTERRUPT 0x00000004 150 #define GENCTL_POWER_DOWN 0x00000008 151 #define GENCTL_ONECOPY 0x00000010 152 #define GENCTL_BIG_ENDIAN 0x00000020 153 #define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040 154 #define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080 155 #define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300 156 #define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200 157 #define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100 158 #define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000 159 #define GENCTL_MEMORY_READ_LINE 0x00000400 160 #define GENCTL_MEMORY_READ_MULTIPLE 0x00000800 161 #define GENCTL_SOFTWARE1 0x00001000 162 #define GENCTL_SOFTWARE2 0x00002000 163 #define GENCTL_RESET_PHY 0x00004000 164 165 #define NVCTL_ENABLE_MEMORY_MAP 0x00000001 166 #define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002 167 #define NVCTL_GP1_OUTPUT_ENABLE 0x00000004 168 #define NVCTL_GP2_OUTPUT_ENABLE 0x00000008 169 #define NVCTL_GP1 0x00000010 170 #define NVCTL_GP2 0x00000020 171 #define NVCTL_CARDBUS_MODE 0x00000040 172 #define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) 173 174 #define RXCON_SAVE_ERRORED_PACKETS 0x00000001 175 #define RXCON_RECEIVE_RUNT_FRAMES 0x00000002 176 #define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004 177 #define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008 178 #define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010 179 #define RXCON_PROMISCUOUS_MODE 0x00000020 180 #define RXCON_MONITOR_MODE 0x00000040 181 #define RXCON_EARLY_RECEIVE_ENABLE 0x00000080 182 #define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000 183 #define RXCON_EXTERNAL_BUFFER_16K 0x00000100 184 #define RXCON_EXTERNAL_BUFFER_32K 0x00000200 185 #define RXCON_EXTERNAL_BUFFER_128K 0x00000300 186 187 #define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001 188 #define TXCON_LOOPBACK_DISABLE 0x00000000 189 #define TXCON_LOOPBACK_MODE_INT 0x00000002 190 #define TXCON_LOOPBACK_MODE_PHY 0x00000004 191 #define TXCON_LOOPBACK_MODE 0x00000006 192 #define TXCON_FULL_DUPLEX 0x00000006 193 #define TXCON_SLOT_TIME 0x00000078 194 195 #define MIICFG_SMI_ENABLE 0x00000010 196 197 #define TEST1_CLOCK_TEST 0x00000008 198 199 #define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE) 200 #define TRANSMIT_THRESHOLD 0x80 201 202 #if defined(EARLY_RX) 203 #define RXCON_DEFAULT (RXCON_EARLY_RECEIVE_ENABLE | RXCON_SAVE_ERRORED_PACKETS) 204 #else 205 #define RXCON_DEFAULT (0) 206 #endif 207 /* 208 * National Semiconductor's DP83840A Registers and bits 209 */ 210 #define DP83840_OUI 0x080017 211 #define DP83840_BMCR 0x00 /* Control register */ 212 #define DP83840_BMSR 0x01 /* Status rgister */ 213 #define DP83840_ANAR 0x04 /* Autonegotiation advertising register */ 214 #define DP83840_LPAR 0x05 /* Link Partner Ability register */ 215 #define DP83840_ANER 0x06 /* Auto-Negotiation Expansion Register */ 216 #define DP83840_PAR 0x19 /* PHY Address Register */ 217 #define DP83840_PHYIDR1 0x02 218 #define DP83840_PHYIDR2 0x03 219 220 #define BMCR_RESET 0x8000 221 #define BMCR_LOOPBACK 0x4000 222 #define BMCR_100MBPS 0x2000 /* 10/100 Mbps */ 223 #define BMCR_AUTONEGOTIATION 0x1000 /* ON/OFF */ 224 #define BMCR_POWERDOWN 0x0800 225 #define BMCR_ISOLATE 0x0400 226 #define BMCR_RESTART_AUTONEG 0x0200 227 #define BMCR_FULL_DUPLEX 0x0100 228 #define BMCR_COL_TEST 0x0080 229 230 #define BMSR_100BASE_T4 0x8000 231 #define BMSR_100BASE_TX_FD 0x4000 232 #define BMSR_100BASE_TX 0x2000 233 #define BMSR_10BASE_T_FD 0x1000 234 #define BMSR_10BASE_T 0x0800 235 #define BMSR_AUTONEG_COMPLETE 0x0020 236 #define BMSR_AUTONEG_ABLE 0x0008 237 #define BMSR_LINK_STATUS 0x0004 238 239 #define PAR_FULL_DUPLEX 0x0400 240 241 #define ANER_MULTIPLE_LINK_FAULT 0x10 242 243 /* ANAR and LPAR have the same bits, define them only once */ 244 #define ANAR_10 0x0020 245 #define ANAR_10_FD 0x0040 246 #define ANAR_100_TX 0x0080 247 #define ANAR_100_TX_FD 0x0100 248 #define ANAR_100_T4 0x0200 249 250 /* 251 * Quality Semiconductor's QS6612 registers and bits 252 */ 253 #define QS6612_OUI 0x006051 254 #define QS6612_MCTL 17 255 #define QS6612_INTSTAT 29 256 #define QS6612_INTMASK 30 257 #define QS6612_BPCR 31 258 259 #define MCTL_T4_PRESENT 0x1000 /* External T4 Enabled, ignored */ 260 /* if AutoNeg is enabled */ 261 #define MCTL_BTEXT 0x0800 /* Reduces 10baset squelch level */ 262 /* for extended cable length */ 263 264 #define INTSTAT_AN_COMPLETE 0x40 /* Autonegotiation complete */ 265 #define INTSTAT_RF_DETECTED 0x20 /* Remote Fault detected */ 266 #define INTSTAT_LINK_STATUS 0x10 /* Link status changed */ 267 #define INTSTAT_AN_LP_ACK 0x08 /* Autoneg. LP Acknoledge */ 268 #define INTSTAT_PD_FAULT 0x04 /* Parallel Detection Fault */ 269 #define INTSTAT_AN_PAGE 0x04 /* Autoneg. Page Received */ 270 #define INTSTAT_RE_CNT_FULL 0x01 /* Receive Error Counter Full */ 271 272 #define INTMASK_THUNDERLAN 0x8000 /* Enable interrupts */ 273 274 /* 275 * Structures definition and Functions prototypes 276 */ 277 278 /* EPIC's hardware descriptors, must be aligned on dword in memory */ 279 /* NB: to make driver happy, this two structures MUST have thier sizes */ 280 /* be divisor of PAGE_SIZE */ 281 struct epic_tx_desc { 282 volatile u_int16_t status; 283 volatile u_int16_t txlength; 284 volatile u_int32_t bufaddr; 285 volatile u_int16_t buflength; 286 volatile u_int16_t control; 287 volatile u_int32_t next; 288 }; 289 struct epic_rx_desc { 290 volatile u_int16_t status; 291 volatile u_int16_t rxlength; 292 volatile u_int32_t bufaddr; 293 volatile u_int32_t buflength; 294 volatile u_int32_t next; 295 }; 296 297 /* This structure defines EPIC's fragment list, maximum number of frags */ 298 /* is 63. Let use maximum, becouse size of struct MUST be divisor of */ 299 /* PAGE_SIZE, and sometimes come mbufs with more then 30 frags */ 300 #define EPIC_MAX_FRAGS 63 301 struct epic_frag_list { 302 volatile u_int32_t numfrags; 303 struct { 304 volatile u_int32_t fragaddr; 305 volatile u_int32_t fraglen; 306 } frag[EPIC_MAX_FRAGS]; 307 volatile u_int32_t pad; /* align on 256 bytes */ 308 }; 309 310 /* This is driver's structure to define EPIC descriptors */ 311 struct epic_rx_buffer { 312 struct mbuf * mbuf; /* mbuf receiving packet */ 313 }; 314 315 struct epic_tx_buffer { 316 struct mbuf * mbuf; /* mbuf contained packet */ 317 }; 318 319 /* 320 * NB: ALIGN OF ABOVE STRUCTURES 321 * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword 322 */ 323 324 /* Driver status structure */ 325 typedef struct { 326 struct arpcom arpcom; 327 #if defined(__OpenBSD__) 328 struct device sc_dev; 329 void *sc_ih; 330 bus_space_tag_t sc_st; 331 bus_space_handle_t sc_sh; 332 #else /* __FreeBSD__ */ 333 #if defined(EPIC_USEIOSPACE) 334 u_int32_t iobase; 335 #else 336 caddr_t csr; 337 #endif 338 #endif 339 #if !defined(EPIC_NOIFMEDIA) 340 struct ifmedia ifmedia; 341 #endif 342 u_int32_t unit; 343 struct epic_rx_buffer rx_buffer[RX_RING_SIZE]; 344 struct epic_tx_buffer tx_buffer[TX_RING_SIZE]; 345 346 /* Each element of array MUST be aligned on dword */ 347 /* and bounded on PAGE_SIZE */ 348 struct epic_rx_desc *rx_desc; 349 struct epic_tx_desc *tx_desc; 350 struct epic_frag_list *tx_flist; 351 u_int32_t flags; 352 u_int32_t tx_threshold; 353 u_int32_t txcon; 354 u_int32_t phyid; 355 u_int32_t cur_tx; 356 u_int32_t cur_rx; 357 u_int32_t dirty_tx; 358 u_int32_t pending_txs; 359 void *pool; 360 } epic_softc_t; 361 362 #if defined(__FreeBSD__) 363 #define EPIC_FORMAT "tx%d" 364 #define EPIC_ARGS(sc) (sc->unit) 365 #define sc_if arpcom.ac_if 366 #define sc_macaddr arpcom.ac_enaddr 367 #if defined(EPIC_USEIOSPACE) 368 #define CSR_WRITE_4(sc,reg,val) \ 369 outl( (sc)->iobase + (u_int32_t)(reg), (val) ) 370 #define CSR_WRITE_2(sc,reg,val) \ 371 outw( (sc)->iobase + (u_int32_t)(reg), (val) ) 372 #define CSR_WRITE_1(sc,reg,val) \ 373 outb( (sc)->iobase + (u_int32_t)(reg), (val) ) 374 #define CSR_READ_4(sc,reg) \ 375 inl( (sc)->iobase + (u_int32_t)(reg) ) 376 #define CSR_READ_2(sc,reg) \ 377 inw( (sc)->iobase + (u_int32_t)(reg) ) 378 #define CSR_READ_1(sc,reg) \ 379 inb( (sc)->iobase + (u_int32_t)(reg) ) 380 #else 381 #define CSR_WRITE_1(sc,reg,val) \ 382 ((*(volatile u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val)) 383 #define CSR_WRITE_2(sc,reg,val) \ 384 ((*(volatile u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val)) 385 #define CSR_WRITE_4(sc,reg,val) \ 386 ((*(volatile u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val)) 387 #define CSR_READ_1(sc,reg) \ 388 (*(volatile u_int8_t*)((sc)->csr + (u_int32_t)(reg))) 389 #define CSR_READ_2(sc,reg) \ 390 (*(volatile u_int16_t*)((sc)->csr + (u_int32_t)(reg))) 391 #define CSR_READ_4(sc,reg) \ 392 (*(volatile u_int32_t*)((sc)->csr + (u_int32_t)(reg))) 393 #endif 394 #else /* __OpenBSD__ */ 395 #define EPIC_FORMAT "%s" 396 #define EPIC_ARGS(sc) (sc->sc_dev.dv_xname) 397 #define sc_if arpcom.ac_if 398 #define sc_macaddr arpcom.ac_enaddr 399 #define CSR_WRITE_4(sc,reg,val) \ 400 bus_space_write_4( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 401 #define CSR_WRITE_2(sc,reg,val) \ 402 bus_space_write_2( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 403 #define CSR_WRITE_1(sc,reg,val) \ 404 bus_space_write_1( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 405 #define CSR_READ_4(sc,reg) \ 406 bus_space_read_4( (sc)->sc_st, (sc)->sc_sh, (reg) ) 407 #define CSR_READ_2(sc,reg) \ 408 bus_space_read_2( (sc)->sc_st, (sc)->sc_sh, (reg) ) 409 #define CSR_READ_1(sc,reg) \ 410 bus_space_read_1( (sc)->sc_st, (sc)->sc_sh, (reg) ) 411 #endif 412 413 #define PHY_READ_2(sc,reg) epic_read_phy_register(sc,reg) 414 #define PHY_WRITE_2(sc,reg,val) epic_write_phy_register(sc,reg,val) 415
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