FreeBSD/Linux Kernel Cross Reference
sys/pci/if_txvar.h
1 /* $OpenBSD: if_txvar.h,v 1.3 1998/10/10 04:30:09 jason Exp $ */
2 /* $FreeBSD: src/sys/pci/if_txvar.h,v 1.1.2.2 1999/09/05 08:21:14 peter Exp $ */
3
4 /*-
5 * Copyright (c) 1997 Semen Ustimenko
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 *
30 */
31
32 /*
33 * Configuration
34 */
35 #ifndef ETHER_MAX_LEN
36 #define ETHER_MAX_LEN 1518
37 #endif
38 #ifndef ETHER_MIN_LEN
39 #define ETHER_MIN_LEN 64
40 #endif
41 #ifndef ETHER_CRC_LEN
42 #define ETHER_CRC_LEN 4
43 #endif
44 #define TX_RING_SIZE 16 /* Leave this a power of 2 */
45 #define RX_RING_SIZE 16 /* And this too, to do not */
46 /* confuse RX(TX)_RING_MASK */
47 #define TX_RING_MASK (TX_RING_SIZE - 1)
48 #define RX_RING_MASK (RX_RING_SIZE - 1)
49 #define EPIC_FULL_DUPLEX 1
50 #define EPIC_HALF_DUPLEX 0
51 #define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN)
52 #define EPIC_LINK_DOWN 0x00000001
53
54 /* PCI identification */
55 #define SMC_VENDORID 0x10B8
56 #define CHIPID_83C170 0x0005
57 #define PCI_VENDORID(x) ((x) & 0xFFFF)
58 #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF)
59
60 /* PCI configuration */
61 #define PCI_CFID 0x00 /* Configuration ID */
62 #define PCI_CFCS 0x04 /* Configurtion Command/Status */
63 #define PCI_CFRV 0x08 /* Configuration Revision */
64 #define PCI_CFLT 0x0c /* Configuration Latency Timer */
65 #define PCI_CBIO 0x10 /* Configuration Base IO Address */
66 #define PCI_CBMA 0x14 /* Configuration Base Memory Address */
67 #define PCI_CFIT 0x3c /* Configuration Interrupt */
68 #define PCI_CFDA 0x40 /* Configuration Driver Area */
69
70 #define PCI_CONF_WRITE(r, v) pci_conf_write(config_id, (r), (v))
71 #define PCI_CONF_READ(r) pci_conf_read(config_id, (r))
72
73 /* EPIC's registers */
74 #define COMMAND 0x0000
75 #define INTSTAT 0x0004 /* Interrupt status. See below */
76 #define INTMASK 0x0008 /* Interrupt mask. See below */
77 #define GENCTL 0x000C
78 #define NVCTL 0x0010
79 #define EECTL 0x0014 /* EEPROM control **/
80 #define TEST1 0x001C /* XXXXX */
81 #define CRCCNT 0x0020 /* CRC error counter */
82 #define ALICNT 0x0024 /* FrameTooLang error counter */
83 #define MPCNT 0x0028 /* MissedFrames error counters */
84 #define MIICTL 0x0030
85 #define MIIDATA 0x0034
86 #define MIICFG 0x0038
87 #define IPG 0x003C
88 #define LAN0 0x0040 /* MAC address */
89 #define LAN1 0x0044 /* MAC address */
90 #define LAN2 0x0048 /* MAC address */
91 #define ID_CHK 0x004C
92 #define MC0 0x0050 /* Multicast filter table */
93 #define MC1 0x0054 /* Multicast filter table */
94 #define MC2 0x0058 /* Multicast filter table */
95 #define MC3 0x005C /* Multicast filter table */
96 #define RXCON 0x0060 /* Rx control register */
97 #define TXCON 0x0070 /* Tx control register */
98 #define TXSTAT 0x0074
99 #define PRCDAR 0x0084 /* RxRing bus address */
100 #define PRSTAT 0x00A4
101 #define PRCPTHR 0x00B0
102 #define PTCDAR 0x00C4 /* TxRing bus address */
103 #define ETXTHR 0x00DC
104
105 #define COMMAND_STOP_RX 0x01
106 #define COMMAND_START_RX 0x02
107 #define COMMAND_TXQUEUED 0x04
108 #define COMMAND_RXQUEUED 0x08
109 #define COMMAND_NEXTFRAME 0x10
110 #define COMMAND_STOP_TDMA 0x20
111 #define COMMAND_STOP_RDMA 0x40
112 #define COMMAND_TXUGO 0x80
113
114 /* Tx threshold */
115 #define TX_FIFO_THRESH 0x80 /* 0x40 or 0x10 */
116
117 /* Interrupt register bits */
118 #define INTSTAT_RCC 0x00000001
119 #define INTSTAT_HCC 0x00000002
120 #define INTSTAT_RQE 0x00000004
121 #define INTSTAT_OVW 0x00000008
122 #define INTSTAT_RXE 0x00000010
123 #define INTSTAT_TXC 0x00000020
124 #define INTSTAT_TCC 0x00000040
125 #define INTSTAT_TQE 0x00000080
126 #define INTSTAT_TXU 0x00000100
127 #define INTSTAT_CNT 0x00000200
128 #define INTSTAT_PREI 0x00000400
129 #define INTSTAT_RCT 0x00000800
130 #define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */
131 #define INTSTAT_UNUSED1 0x00002000
132 #define INTSTAT_UNUSED2 0x00004000
133 #define INTSTAT_GP2 0x00008000 /* PHY Event */
134 #define INTSTAT_INT_ACTV 0x00010000
135 #define INTSTAT_RXIDLE 0x00020000
136 #define INTSTAT_TXIDLE 0x00040000
137 #define INTSTAT_RCIP 0x00080000
138 #define INTSTAT_TCIP 0x00100000
139 #define INTSTAT_RBE 0x00200000
140 #define INTSTAT_RCTS 0x00400000
141 #define INTSTAT_RSV 0x00800000
142 #define INTSTAT_DPE 0x01000000 /* PCI Fatal error */
143 #define INTSTAT_APE 0x02000000 /* PCI Fatal error */
144 #define INTSTAT_PMA 0x04000000 /* PCI Fatal error */
145 #define INTSTAT_PTA 0x08000000 /* PCI Fatal error */
146
147 #define GENCTL_SOFT_RESET 0x00000001
148 #define GENCTL_ENABLE_INTERRUPT 0x00000002
149 #define GENCTL_SOFTWARE_INTERRUPT 0x00000004
150 #define GENCTL_POWER_DOWN 0x00000008
151 #define GENCTL_ONECOPY 0x00000010
152 #define GENCTL_BIG_ENDIAN 0x00000020
153 #define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040
154 #define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080
155 #define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300
156 #define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200
157 #define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100
158 #define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000
159 #define GENCTL_MEMORY_READ_LINE 0x00000400
160 #define GENCTL_MEMORY_READ_MULTIPLE 0x00000800
161 #define GENCTL_SOFTWARE1 0x00001000
162 #define GENCTL_SOFTWARE2 0x00002000
163 #define GENCTL_RESET_PHY 0x00004000
164
165 #define NVCTL_ENABLE_MEMORY_MAP 0x00000001
166 #define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002
167 #define NVCTL_GP1_OUTPUT_ENABLE 0x00000004
168 #define NVCTL_GP2_OUTPUT_ENABLE 0x00000008
169 #define NVCTL_GP1 0x00000010
170 #define NVCTL_GP2 0x00000020
171 #define NVCTL_CARDBUS_MODE 0x00000040
172 #define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7)
173
174 #define RXCON_SAVE_ERRORED_PACKETS 0x00000001
175 #define RXCON_RECEIVE_RUNT_FRAMES 0x00000002
176 #define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004
177 #define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008
178 #define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010
179 #define RXCON_PROMISCUOUS_MODE 0x00000020
180 #define RXCON_MONITOR_MODE 0x00000040
181 #define RXCON_EARLY_RECEIVE_ENABLE 0x00000080
182 #define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000
183 #define RXCON_EXTERNAL_BUFFER_16K 0x00000100
184 #define RXCON_EXTERNAL_BUFFER_32K 0x00000200
185 #define RXCON_EXTERNAL_BUFFER_128K 0x00000300
186
187 #define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001
188 #define TXCON_LOOPBACK_DISABLE 0x00000000
189 #define TXCON_LOOPBACK_MODE_INT 0x00000002
190 #define TXCON_LOOPBACK_MODE_PHY 0x00000004
191 #define TXCON_LOOPBACK_MODE 0x00000006
192 #define TXCON_FULL_DUPLEX 0x00000006
193 #define TXCON_SLOT_TIME 0x00000078
194
195 #define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE)
196 #define TRANSMIT_THRESHOLD 0x80
197
198 #if defined(EARLY_RX)
199 #define RXCON_DEFAULT (RXCON_EARLY_RECEIVE_ENABLE | RXCON_SAVE_ERRORED_PACKETS)
200 #else
201 #define RXCON_DEFAULT (0)
202 #endif
203 /*
204 * National Semiconductor's DP83840A Registers and bits
205 */
206 #define DP83840_OUI 0x080017
207 #define DP83840_BMCR 0x00 /* Control register */
208 #define DP83840_BMSR 0x01 /* Status rgister */
209 #define DP83840_ANAR 0x04 /* Autonegotiation advertising register */
210 #define DP83840_LPAR 0x05 /* Link Partner Ability register */
211 #define DP83840_ANER 0x06 /* Auto-Negotiation Expansion Register */
212 #define DP83840_PAR 0x19 /* PHY Address Register */
213 #define DP83840_PHYIDR1 0x02
214 #define DP83840_PHYIDR2 0x03
215
216 #define BMCR_RESET 0x8000
217 #define BMCR_100MBPS 0x2000 /* 10/100 Mbps */
218 #define BMCR_AUTONEGOTIATION 0x1000 /* ON/OFF */
219 #define BMCR_RESTART_AUTONEG 0x0200
220 #define BMCR_FULL_DUPLEX 0x0100
221
222 #define BMSR_100BASE_T4 0x8000
223 #define BMSR_100BASE_TX_FD 0x4000
224 #define BMSR_100BASE_TX 0x2000
225 #define BMSR_10BASE_T_FD 0x1000
226 #define BMSR_10BASE_T 0x0800
227 #define BMSR_AUTONEG_COMPLETE 0x0020
228 #define BMSR_AUTONEG_ABLE 0x0008
229 #define BMSR_LINK_STATUS 0x0004
230
231 #define PAR_FULL_DUPLEX 0x0400
232
233 #define ANER_MULTIPLE_LINK_FAULT 0x10
234
235 /* ANAR and LPAR have the same bits, define them only once */
236 #define ANAR_10 0x0020
237 #define ANAR_10_FD 0x0040
238 #define ANAR_100_TX 0x0080
239 #define ANAR_100_TX_FD 0x0100
240 #define ANAR_100_T4 0x0200
241
242 /*
243 * Quality Semiconductor's QS6612 registers and bits
244 */
245 #define QS6612_OUI 0x006051
246 #define QS6612_MCTL 17
247 #define QS6612_INTSTAT 29
248 #define QS6612_INTMASK 30
249
250 #define MCTL_T4_PRESENT 0x1000 /* External T4 Enabled, ignored */
251 /* if AutoNeg is enabled */
252 #define MCTL_BTEXT 0x0800 /* Reduces 10baset squelch level */
253 /* for extended cable length */
254
255 #define INTSTAT_AN_COMPLETE 0x40 /* Autonegotiation complete */
256 #define INTSTAT_RF_DETECTED 0x20 /* Remote Fault detected */
257 #define INTSTAT_LINK_STATUS 0x10 /* Link status changed */
258 #define INTSTAT_AN_LP_ACK 0x08 /* Autoneg. LP Acknoledge */
259 #define INTSTAT_PD_FAULT 0x04 /* Parallel Detection Fault */
260 #define INTSTAT_AN_PAGE 0x04 /* Autoneg. Page Received */
261 #define INTSTAT_RE_CNT_FULL 0x01 /* Receive Error Counter Full */
262
263 #define INTMASK_THUNDERLAN 0x8000 /* Enable interrupts */
264
265 /*
266 * Structures definition and Functions prototypes
267 */
268
269 /* EPIC's hardware descriptors, must be aligned on dword in memory */
270 /* NB: to make driver happy, this two structures MUST have thier sizes */
271 /* be divisor of PAGE_SIZE */
272 struct epic_tx_desc {
273 volatile u_int16_t status;
274 volatile u_int16_t txlength;
275 volatile u_int32_t bufaddr;
276 volatile u_int16_t buflength;
277 volatile u_int16_t control;
278 volatile u_int32_t next;
279 };
280 struct epic_rx_desc {
281 volatile u_int16_t status;
282 volatile u_int16_t rxlength;
283 volatile u_int32_t bufaddr;
284 volatile u_int32_t buflength;
285 volatile u_int32_t next;
286 };
287
288 /* This structure defines EPIC's fragment list, maximum number of frags */
289 /* is 63. Let use maximum, becouse size of struct MUST be divisor of */
290 /* PAGE_SIZE, and sometimes come mbufs with more then 30 frags */
291 #define EPIC_MAX_FRAGS 63
292 struct epic_frag_list {
293 volatile u_int32_t numfrags;
294 struct {
295 volatile u_int32_t fragaddr;
296 volatile u_int32_t fraglen;
297 } frag[EPIC_MAX_FRAGS];
298 volatile u_int32_t pad; /* align on 256 bytes */
299 };
300
301 /* This is driver's structure to define EPIC descriptors */
302 struct epic_rx_buffer {
303 struct mbuf * mbuf; /* mbuf receiving packet */
304 };
305
306 struct epic_tx_buffer {
307 struct mbuf * mbuf; /* mbuf contained packet */
308 };
309
310 /*
311 * NB: ALIGN OF ABOVE STRUCTURES
312 * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword
313 */
314
315 /* Driver status structure */
316 typedef struct {
317 #if defined(__OpenBSD__)
318 struct device sc_dev;
319 void *sc_ih;
320 bus_space_tag_t sc_st;
321 bus_space_handle_t sc_sh;
322 #else /* __FreeBSD__ */
323 #if defined(EPIC_USEIOSPACE)
324 u_int32_t iobase;
325 #else
326 caddr_t csr;
327 #endif
328 #endif
329 #if !defined(EPIC_NOIFMEDIA)
330 struct ifmedia ifmedia;
331 #endif
332 struct arpcom arpcom;
333 u_int32_t unit;
334 struct epic_rx_buffer rx_buffer[RX_RING_SIZE];
335 struct epic_tx_buffer tx_buffer[TX_RING_SIZE];
336
337 /* Each element of array MUST be aligned on dword */
338 /* and bounded on PAGE_SIZE */
339 struct epic_rx_desc *rx_desc;
340 struct epic_tx_desc *tx_desc;
341 struct epic_frag_list *tx_flist;
342 u_int32_t flags;
343 u_int32_t tx_threshold;
344 u_int32_t txcon;
345 u_int32_t phyid;
346 u_int32_t cur_tx;
347 u_int32_t cur_rx;
348 u_int32_t dirty_tx;
349 u_int32_t pending_txs;
350 void *pool;
351 } epic_softc_t;
352
353 #if defined(__FreeBSD__)
354 #define EPIC_FORMAT "tx%d"
355 #define EPIC_ARGS(sc) (sc->unit)
356 #define sc_if arpcom.ac_if
357 #define sc_macaddr arpcom.ac_enaddr
358 #if defined(EPIC_USEIOSPACE)
359 #define CSR_WRITE_4(sc,reg,val) \
360 outl( (sc)->iobase + (u_int32_t)(reg), (val) )
361 #define CSR_WRITE_2(sc,reg,val) \
362 outw( (sc)->iobase + (u_int32_t)(reg), (val) )
363 #define CSR_WRITE_1(sc,reg,val) \
364 outb( (sc)->iobase + (u_int32_t)(reg), (val) )
365 #define CSR_READ_4(sc,reg) \
366 inl( (sc)->iobase + (u_int32_t)(reg) )
367 #define CSR_READ_2(sc,reg) \
368 inw( (sc)->iobase + (u_int32_t)(reg) )
369 #define CSR_READ_1(sc,reg) \
370 inb( (sc)->iobase + (u_int32_t)(reg) )
371 #else
372 #define CSR_WRITE_1(sc,reg,val) \
373 ((*(u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val))
374 #define CSR_WRITE_2(sc,reg,val) \
375 ((*(u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val))
376 #define CSR_WRITE_4(sc,reg,val) \
377 ((*(u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val))
378 #define CSR_READ_1(sc,reg) \
379 (*(u_int8_t*)((sc)->csr + (u_int32_t)(reg)))
380 #define CSR_READ_2(sc,reg) \
381 (*(u_int16_t*)((sc)->csr + (u_int32_t)(reg)))
382 #define CSR_READ_4(sc,reg) \
383 (*(u_int32_t*)((sc)->csr + (u_int32_t)(reg)))
384 #endif
385 #else /* __OpenBSD__ */
386 #define EPIC_FORMAT "%s"
387 #define EPIC_ARGS(sc) (sc->sc_dev.dv_xname)
388 #define sc_if arpcom.ac_if
389 #define sc_macaddr arpcom.ac_enaddr
390 #define CSR_WRITE_4(sc,reg,val) \
391 bus_space_write_4( (sc)->sc_st, (sc)->sc_sh, (reg), (val) )
392 #define CSR_WRITE_2(sc,reg,val) \
393 bus_space_write_2( (sc)->sc_st, (sc)->sc_sh, (reg), (val) )
394 #define CSR_WRITE_1(sc,reg,val) \
395 bus_space_write_1( (sc)->sc_st, (sc)->sc_sh, (reg), (val) )
396 #define CSR_READ_4(sc,reg) \
397 bus_space_read_4( (sc)->sc_st, (sc)->sc_sh, (reg) )
398 #define CSR_READ_2(sc,reg) \
399 bus_space_read_2( (sc)->sc_st, (sc)->sc_sh, (reg) )
400 #define CSR_READ_1(sc,reg) \
401 bus_space_read_1( (sc)->sc_st, (sc)->sc_sh, (reg) )
402 #endif
403
404 #define PHY_READ_2(sc,reg) epic_read_phy_register(sc,reg)
405 #define PHY_WRITE_2(sc,reg,val) epic_write_phy_register(sc,reg,val)
406
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