Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_vr.c
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1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * VIA Rhine fast ethernet PCI NIC driver 37 * 38 * Supports various network adapters based on the VIA Rhine 39 * and Rhine II PCI controllers, including the D-Link DFE530TX. 40 * Datasheets are available at http://www.via.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/sockio.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 70 #include <net/if.h> 71 #include <net/if_arp.h> 72 #include <net/ethernet.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/bpf.h> 77 78 #include <vm/vm.h> /* for vtophys */ 79 #include <vm/pmap.h> /* for vtophys */ 80 #include <machine/clock.h> /* for DELAY */ 81 #include <machine/bus_pio.h> 82 #include <machine/bus_memio.h> 83 #include <machine/bus.h> 84 #include <machine/resource.h> 85 #include <sys/bus.h> 86 #include <sys/rman.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 91 #include <pci/pcireg.h> 92 #include <pci/pcivar.h> 93 94 #define VR_USEIOSPACE 95 96 #include <pci/if_vrreg.h> 97 98 /* "controller miibus0" required. See GENERIC if you get errors here. */ 99 #include "miibus_if.h" 100 101 #ifndef lint 102 static const char rcsid[] = 103 "$FreeBSD$"; 104 #endif 105 106 #undef VR_USESWSHIFT 107 108 /* 109 * Various supported device vendors/types and their names. 110 */ 111 static struct vr_type vr_devs[] = { 112 { VIA_VENDORID, VIA_DEVICEID_RHINE, 113 "VIA VT3043 Rhine I 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 115 "VIA VT86C100A Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 117 "VIA VT6102 Rhine II 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 119 "VIA VT6105 Rhine III 10/100BaseTX" }, 120 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 121 "VIA VT6105M Rhine III 10/100BaseTX" }, 122 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 123 "Delta Electronics Rhine II 10/100BaseTX" }, 124 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 125 "Addtron Technology Rhine II 10/100BaseTX" }, 126 { 0, 0, NULL } 127 }; 128 129 static int vr_probe __P((device_t)); 130 static int vr_attach __P((device_t)); 131 static int vr_detach __P((device_t)); 132 133 static int vr_newbuf __P((struct vr_softc *, 134 struct vr_chain_onefrag *, 135 struct mbuf *)); 136 static int vr_encap __P((struct vr_softc *, struct vr_chain *, 137 struct mbuf * )); 138 139 static void vr_rxeof __P((struct vr_softc *)); 140 static void vr_rxeoc __P((struct vr_softc *)); 141 static void vr_txeof __P((struct vr_softc *)); 142 static void vr_tick __P((void *)); 143 static void vr_intr __P((void *)); 144 static void vr_start __P((struct ifnet *)); 145 static int vr_ioctl __P((struct ifnet *, u_long, caddr_t)); 146 static void vr_init __P((void *)); 147 static void vr_stop __P((struct vr_softc *)); 148 static void vr_watchdog __P((struct ifnet *)); 149 static void vr_shutdown __P((device_t)); 150 static int vr_ifmedia_upd __P((struct ifnet *)); 151 static void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 152 153 #ifdef VR_USESWSHIFT 154 static void vr_mii_sync __P((struct vr_softc *)); 155 static void vr_mii_send __P((struct vr_softc *, u_int32_t, int)); 156 #endif 157 static int vr_mii_readreg __P((struct vr_softc *, struct vr_mii_frame *)); 158 static int vr_mii_writereg __P((struct vr_softc *, struct vr_mii_frame *)); 159 static int vr_miibus_readreg __P((device_t, int, int)); 160 static int vr_miibus_writereg __P((device_t, int, int, int)); 161 static void vr_miibus_statchg __P((device_t)); 162 163 static void vr_setcfg __P((struct vr_softc *, int)); 164 static u_int8_t vr_calchash __P((u_int8_t *)); 165 static void vr_setmulti __P((struct vr_softc *)); 166 static void vr_reset __P((struct vr_softc *)); 167 static int vr_list_rx_init __P((struct vr_softc *)); 168 static int vr_list_tx_init __P((struct vr_softc *)); 169 170 #ifdef VR_USEIOSPACE 171 #define VR_RES SYS_RES_IOPORT 172 #define VR_RID VR_PCI_LOIO 173 #else 174 #define VR_RES SYS_RES_MEMORY 175 #define VR_RID VR_PCI_LOMEM 176 #endif 177 178 static device_method_t vr_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, vr_probe), 181 DEVMETHOD(device_attach, vr_attach), 182 DEVMETHOD(device_detach, vr_detach), 183 DEVMETHOD(device_shutdown, vr_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 191 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 192 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 193 194 { 0, 0 } 195 }; 196 197 static driver_t vr_driver = { 198 "vr", 199 vr_methods, 200 sizeof(struct vr_softc) 201 }; 202 203 static devclass_t vr_devclass; 204 205 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 206 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 207 208 #define VR_SETBIT(sc, reg, x) \ 209 CSR_WRITE_1(sc, reg, \ 210 CSR_READ_1(sc, reg) | x) 211 212 #define VR_CLRBIT(sc, reg, x) \ 213 CSR_WRITE_1(sc, reg, \ 214 CSR_READ_1(sc, reg) & ~x) 215 216 #define VR_SETBIT16(sc, reg, x) \ 217 CSR_WRITE_2(sc, reg, \ 218 CSR_READ_2(sc, reg) | x) 219 220 #define VR_CLRBIT16(sc, reg, x) \ 221 CSR_WRITE_2(sc, reg, \ 222 CSR_READ_2(sc, reg) & ~x) 223 224 #define VR_SETBIT32(sc, reg, x) \ 225 CSR_WRITE_4(sc, reg, \ 226 CSR_READ_4(sc, reg) | x) 227 228 #define VR_CLRBIT32(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, \ 230 CSR_READ_4(sc, reg) & ~x) 231 232 #define SIO_SET(x) \ 233 CSR_WRITE_1(sc, VR_MIICMD, \ 234 CSR_READ_1(sc, VR_MIICMD) | x) 235 236 #define SIO_CLR(x) \ 237 CSR_WRITE_1(sc, VR_MIICMD, \ 238 CSR_READ_1(sc, VR_MIICMD) & ~x) 239 240 #ifdef VR_USESWSHIFT 241 /* 242 * Sync the PHYs by setting data bit and strobing the clock 32 times. 243 */ 244 static void vr_mii_sync(sc) 245 struct vr_softc *sc; 246 { 247 register int i; 248 249 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 250 251 for (i = 0; i < 32; i++) { 252 SIO_SET(VR_MIICMD_CLK); 253 DELAY(1); 254 SIO_CLR(VR_MIICMD_CLK); 255 DELAY(1); 256 } 257 258 return; 259 } 260 261 /* 262 * Clock a series of bits through the MII. 263 */ 264 static void vr_mii_send(sc, bits, cnt) 265 struct vr_softc *sc; 266 u_int32_t bits; 267 int cnt; 268 { 269 int i; 270 271 SIO_CLR(VR_MIICMD_CLK); 272 273 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 274 if (bits & i) { 275 SIO_SET(VR_MIICMD_DATAIN); 276 } else { 277 SIO_CLR(VR_MIICMD_DATAIN); 278 } 279 DELAY(1); 280 SIO_CLR(VR_MIICMD_CLK); 281 DELAY(1); 282 SIO_SET(VR_MIICMD_CLK); 283 } 284 } 285 #endif 286 287 /* 288 * Read an PHY register through the MII. 289 */ 290 static int vr_mii_readreg(sc, frame) 291 struct vr_softc *sc; 292 struct vr_mii_frame *frame; 293 294 #ifdef VR_USESWSHIFT 295 { 296 int i, ack, s; 297 298 s = splimp(); 299 300 /* 301 * Set up frame for RX. 302 */ 303 frame->mii_stdelim = VR_MII_STARTDELIM; 304 frame->mii_opcode = VR_MII_READOP; 305 frame->mii_turnaround = 0; 306 frame->mii_data = 0; 307 308 CSR_WRITE_1(sc, VR_MIICMD, 0); 309 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 310 311 /* 312 * Turn on data xmit. 313 */ 314 SIO_SET(VR_MIICMD_DIR); 315 316 vr_mii_sync(sc); 317 318 /* 319 * Send command/address info. 320 */ 321 vr_mii_send(sc, frame->mii_stdelim, 2); 322 vr_mii_send(sc, frame->mii_opcode, 2); 323 vr_mii_send(sc, frame->mii_phyaddr, 5); 324 vr_mii_send(sc, frame->mii_regaddr, 5); 325 326 /* Idle bit */ 327 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 328 DELAY(1); 329 SIO_SET(VR_MIICMD_CLK); 330 DELAY(1); 331 332 /* Turn off xmit. */ 333 SIO_CLR(VR_MIICMD_DIR); 334 335 /* Check for ack */ 336 SIO_CLR(VR_MIICMD_CLK); 337 DELAY(1); 338 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 339 SIO_SET(VR_MIICMD_CLK); 340 DELAY(1); 341 342 /* 343 * Now try reading data bits. If the ack failed, we still 344 * need to clock through 16 cycles to keep the PHY(s) in sync. 345 */ 346 if (ack) { 347 for(i = 0; i < 16; i++) { 348 SIO_CLR(VR_MIICMD_CLK); 349 DELAY(1); 350 SIO_SET(VR_MIICMD_CLK); 351 DELAY(1); 352 } 353 goto fail; 354 } 355 356 for (i = 0x8000; i; i >>= 1) { 357 SIO_CLR(VR_MIICMD_CLK); 358 DELAY(1); 359 if (!ack) { 360 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 361 frame->mii_data |= i; 362 DELAY(1); 363 } 364 SIO_SET(VR_MIICMD_CLK); 365 DELAY(1); 366 } 367 368 fail: 369 370 SIO_CLR(VR_MIICMD_CLK); 371 DELAY(1); 372 SIO_SET(VR_MIICMD_CLK); 373 DELAY(1); 374 375 splx(s); 376 377 if (ack) 378 return(1); 379 return(0); 380 } 381 #else 382 { 383 int s, i; 384 385 s = splimp(); 386 387 /* Set the PHY-adress */ 388 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 389 frame->mii_phyaddr); 390 391 /* Set the register-adress */ 392 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 393 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 394 395 for (i = 0; i < 10000; i++) { 396 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 397 break; 398 DELAY(1); 399 } 400 401 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 402 403 (void)splx(s); 404 405 return(0); 406 } 407 #endif 408 409 410 /* 411 * Write to a PHY register through the MII. 412 */ 413 static int vr_mii_writereg(sc, frame) 414 struct vr_softc *sc; 415 struct vr_mii_frame *frame; 416 417 #ifdef VR_USESWSHIFT 418 { 419 int s; 420 421 s = splimp(); 422 423 CSR_WRITE_1(sc, VR_MIICMD, 0); 424 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 425 426 /* 427 * Set up frame for TX. 428 */ 429 430 frame->mii_stdelim = VR_MII_STARTDELIM; 431 frame->mii_opcode = VR_MII_WRITEOP; 432 frame->mii_turnaround = VR_MII_TURNAROUND; 433 434 /* 435 * Turn on data output. 436 */ 437 SIO_SET(VR_MIICMD_DIR); 438 439 vr_mii_sync(sc); 440 441 vr_mii_send(sc, frame->mii_stdelim, 2); 442 vr_mii_send(sc, frame->mii_opcode, 2); 443 vr_mii_send(sc, frame->mii_phyaddr, 5); 444 vr_mii_send(sc, frame->mii_regaddr, 5); 445 vr_mii_send(sc, frame->mii_turnaround, 2); 446 vr_mii_send(sc, frame->mii_data, 16); 447 448 /* Idle bit. */ 449 SIO_SET(VR_MIICMD_CLK); 450 DELAY(1); 451 SIO_CLR(VR_MIICMD_CLK); 452 DELAY(1); 453 454 /* 455 * Turn off xmit. 456 */ 457 SIO_CLR(VR_MIICMD_DIR); 458 459 splx(s); 460 461 return(0); 462 } 463 #else 464 { 465 int s, i; 466 467 s = splimp(); 468 469 /* Set the PHY-adress */ 470 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 471 frame->mii_phyaddr); 472 473 /* Set the register-adress and data to write */ 474 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 475 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 476 477 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 478 479 for (i = 0; i < 10000; i++) { 480 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 481 break; 482 DELAY(1); 483 } 484 485 (void)splx(s); 486 487 return(0); 488 } 489 #endif 490 491 static int vr_miibus_readreg(dev, phy, reg) 492 device_t dev; 493 int phy, reg; 494 { 495 struct vr_softc *sc; 496 struct vr_mii_frame frame; 497 498 sc = device_get_softc(dev); 499 500 switch (sc->vr_revid) { 501 case REV_ID_VT6102_APOLLO: 502 if (phy != 1) 503 return 0; 504 default: 505 break; 506 } 507 508 bzero((char *)&frame, sizeof(frame)); 509 510 frame.mii_phyaddr = phy; 511 frame.mii_regaddr = reg; 512 vr_mii_readreg(sc, &frame); 513 514 return(frame.mii_data); 515 } 516 517 static int vr_miibus_writereg(dev, phy, reg, data) 518 device_t dev; 519 u_int16_t phy, reg, data; 520 { 521 struct vr_softc *sc; 522 struct vr_mii_frame frame; 523 524 sc = device_get_softc(dev); 525 526 switch (sc->vr_revid) { 527 case REV_ID_VT6102_APOLLO: 528 if (phy != 1) 529 return 0; 530 default: 531 break; 532 } 533 534 bzero((char *)&frame, sizeof(frame)); 535 536 frame.mii_phyaddr = phy; 537 frame.mii_regaddr = reg; 538 frame.mii_data = data; 539 540 vr_mii_writereg(sc, &frame); 541 542 return(0); 543 } 544 545 static void vr_miibus_statchg(dev) 546 device_t dev; 547 { 548 struct vr_softc *sc; 549 struct mii_data *mii; 550 551 sc = device_get_softc(dev); 552 mii = device_get_softc(sc->vr_miibus); 553 vr_setcfg(sc, mii->mii_media_active); 554 555 return; 556 } 557 558 /* 559 * Calculate CRC of a multicast group address, return the lower 6 bits. 560 */ 561 static u_int8_t vr_calchash(addr) 562 u_int8_t *addr; 563 { 564 u_int32_t crc, carry; 565 int i, j; 566 u_int8_t c; 567 568 /* Compute CRC for the address value. */ 569 crc = 0xFFFFFFFF; /* initial value */ 570 571 for (i = 0; i < 6; i++) { 572 c = *(addr + i); 573 for (j = 0; j < 8; j++) { 574 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 575 crc <<= 1; 576 c >>= 1; 577 if (carry) 578 crc = (crc ^ 0x04c11db6) | carry; 579 } 580 } 581 582 /* return the filter bit position */ 583 return((crc >> 26) & 0x0000003F); 584 } 585 586 /* 587 * Program the 64-bit multicast hash filter. 588 */ 589 static void vr_setmulti(sc) 590 struct vr_softc *sc; 591 { 592 struct ifnet *ifp; 593 int h = 0; 594 u_int32_t hashes[2] = { 0, 0 }; 595 struct ifmultiaddr *ifma; 596 u_int8_t rxfilt; 597 int mcnt = 0; 598 599 ifp = &sc->arpcom.ac_if; 600 601 rxfilt = CSR_READ_1(sc, VR_RXCFG); 602 603 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 604 rxfilt |= VR_RXCFG_RX_MULTI; 605 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 606 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 607 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 608 return; 609 } 610 611 /* first, zot all the existing hash bits */ 612 CSR_WRITE_4(sc, VR_MAR0, 0); 613 CSR_WRITE_4(sc, VR_MAR1, 0); 614 615 /* now program new ones */ 616 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 617 ifma = ifma->ifma_link.le_next) { 618 if (ifma->ifma_addr->sa_family != AF_LINK) 619 continue; 620 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 621 if (h < 32) 622 hashes[0] |= (1 << h); 623 else 624 hashes[1] |= (1 << (h - 32)); 625 mcnt++; 626 } 627 628 if (mcnt) 629 rxfilt |= VR_RXCFG_RX_MULTI; 630 else 631 rxfilt &= ~VR_RXCFG_RX_MULTI; 632 633 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 634 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 635 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 636 637 return; 638 } 639 640 /* 641 * In order to fiddle with the 642 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 643 * first have to put the transmit and/or receive logic in the idle state. 644 */ 645 static void vr_setcfg(sc, media) 646 struct vr_softc *sc; 647 int media; 648 { 649 int restart = 0; 650 651 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 652 restart = 1; 653 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 654 } 655 656 if ((media & IFM_GMASK) == IFM_FDX) 657 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 658 else 659 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 660 661 if (restart) 662 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 663 664 return; 665 } 666 667 static void vr_reset(sc) 668 struct vr_softc *sc; 669 { 670 register int i; 671 672 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 673 674 for (i = 0; i < VR_TIMEOUT; i++) { 675 DELAY(10); 676 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 677 break; 678 } 679 if (i == VR_TIMEOUT) { 680 if (sc->vr_revid < REV_ID_VT3065_A) 681 printf("vr%d: reset never completed!\n", sc->vr_unit); 682 else { 683 /* Use newer force reset command */ 684 printf("vr%d: Using force reset command.\n", sc->vr_unit); 685 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 686 } 687 } 688 689 /* Wait a little while for the chip to get its brains in order. */ 690 DELAY(1000); 691 692 return; 693 } 694 695 /* 696 * Probe for a VIA Rhine chip. Check the PCI vendor and device 697 * IDs against our list and return a device name if we find a match. 698 */ 699 static int vr_probe(dev) 700 device_t dev; 701 { 702 struct vr_type *t; 703 704 t = vr_devs; 705 706 while(t->vr_name != NULL) { 707 if ((pci_get_vendor(dev) == t->vr_vid) && 708 (pci_get_device(dev) == t->vr_did)) { 709 device_set_desc(dev, t->vr_name); 710 return(0); 711 } 712 t++; 713 } 714 715 return(ENXIO); 716 } 717 718 /* 719 * Attach the interface. Allocate softc structures, do ifmedia 720 * setup and ethernet/BPF attach. 721 */ 722 static int vr_attach(dev) 723 device_t dev; 724 { 725 int i, s; 726 u_char eaddr[ETHER_ADDR_LEN]; 727 u_int32_t command; 728 struct vr_softc *sc; 729 struct ifnet *ifp; 730 int unit, error = 0, rid; 731 732 s = splimp(); 733 734 sc = device_get_softc(dev); 735 unit = device_get_unit(dev); 736 bzero(sc, sizeof(struct vr_softc *)); 737 738 /* 739 * Handle power management nonsense. 740 */ 741 742 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 743 if (command == 0x01) { 744 745 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 746 if (command & VR_PSTATE_MASK) { 747 u_int32_t iobase, membase, irq; 748 749 /* Save important PCI config data. */ 750 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 751 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 752 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 753 754 /* Reset the power state. */ 755 printf("vr%d: chip is in D%d power mode " 756 "-- setting to D0\n", unit, command & VR_PSTATE_MASK); 757 command &= 0xFFFFFFFC; 758 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 759 760 /* Restore PCI config data. */ 761 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 762 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 763 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 764 } 765 } 766 767 /* 768 * Map control/status registers. 769 */ 770 command = pci_read_config(dev, PCIR_COMMAND, 4); 771 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 772 pci_write_config(dev, PCIR_COMMAND, command, 4); 773 command = pci_read_config(dev, PCIR_COMMAND, 4); 774 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 775 776 #ifdef VR_USEIOSPACE 777 if (!(command & PCIM_CMD_PORTEN)) { 778 printf("vr%d: failed to enable I/O ports!\n", unit); 779 free(sc, M_DEVBUF); 780 goto fail; 781 } 782 #else 783 if (!(command & PCIM_CMD_MEMEN)) { 784 printf("vr%d: failed to enable memory mapping!\n", unit); 785 goto fail; 786 } 787 #endif 788 789 rid = VR_RID; 790 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 791 0, ~0, 1, RF_ACTIVE); 792 793 if (sc->vr_res == NULL) { 794 printf("vr%d: couldn't map ports/memory\n", unit); 795 error = ENXIO; 796 goto fail; 797 } 798 799 sc->vr_btag = rman_get_bustag(sc->vr_res); 800 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 801 802 /* Allocate interrupt */ 803 rid = 0; 804 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 805 RF_SHAREABLE | RF_ACTIVE); 806 807 if (sc->vr_irq == NULL) { 808 printf("vr%d: couldn't map interrupt\n", unit); 809 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 810 error = ENXIO; 811 goto fail; 812 } 813 814 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 815 vr_intr, sc, &sc->vr_intrhand); 816 817 if (error) { 818 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 819 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 820 printf("vr%d: couldn't set up irq\n", unit); 821 goto fail; 822 } 823 824 /* 825 * Windows may put the chip in suspend mode when it 826 * shuts down. Be sure to kick it in the head to wake it 827 * up again. 828 */ 829 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 830 831 /* Reset the adapter. */ 832 vr_reset(sc); 833 834 /* 835 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 836 * initialization and disable AUTOPOLL. 837 */ 838 pci_write_config(dev, VR_PCI_MODE, 839 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 840 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 841 842 /* 843 * Get station address. The way the Rhine chips work, 844 * you're not allowed to directly access the EEPROM once 845 * they've been programmed a special way. Consequently, 846 * we need to read the node address from the PAR0 and PAR1 847 * registers. 848 */ 849 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 850 DELAY(200); 851 for (i = 0; i < ETHER_ADDR_LEN; i++) 852 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 853 854 /* 855 * A Rhine chip was detected. Inform the world. 856 */ 857 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 858 859 sc->vr_unit = unit; 860 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 861 862 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 863 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 864 865 if (sc->vr_ldata == NULL) { 866 printf("vr%d: no memory for list buffers!\n", unit); 867 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 868 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 869 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 870 error = ENXIO; 871 goto fail; 872 } 873 874 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 875 876 ifp = &sc->arpcom.ac_if; 877 ifp->if_softc = sc; 878 ifp->if_unit = unit; 879 ifp->if_name = "vr"; 880 ifp->if_mtu = ETHERMTU; 881 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 882 ifp->if_ioctl = vr_ioctl; 883 ifp->if_output = ether_output; 884 ifp->if_start = vr_start; 885 ifp->if_watchdog = vr_watchdog; 886 ifp->if_init = vr_init; 887 ifp->if_baudrate = 10000000; 888 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 889 #ifdef DEVICE_POLLING 890 ifp->if_capabilities |= IFCAP_POLLING; 891 #endif 892 ifp->if_capenable = ifp->if_capabilities; 893 894 /* 895 * Do MII setup. 896 */ 897 if (mii_phy_probe(dev, &sc->vr_miibus, 898 vr_ifmedia_upd, vr_ifmedia_sts)) { 899 printf("vr%d: MII without any phy!\n", sc->vr_unit); 900 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 901 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 902 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 903 contigfree(sc->vr_ldata, 904 sizeof(struct vr_list_data), M_DEVBUF); 905 error = ENXIO; 906 goto fail; 907 } 908 909 callout_handle_init(&sc->vr_stat_ch); 910 911 /* 912 * Call MI attach routine. 913 */ 914 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 915 916 fail: 917 splx(s); 918 return(error); 919 } 920 921 static int vr_detach(dev) 922 device_t dev; 923 { 924 struct vr_softc *sc; 925 struct ifnet *ifp; 926 int s; 927 928 s = splimp(); 929 930 sc = device_get_softc(dev); 931 ifp = &sc->arpcom.ac_if; 932 933 vr_stop(sc); 934 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 935 936 bus_generic_detach(dev); 937 device_delete_child(dev, sc->vr_miibus); 938 939 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 940 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 941 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 942 943 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 944 945 splx(s); 946 947 return(0); 948 } 949 950 /* 951 * Initialize the transmit descriptors. 952 */ 953 static int vr_list_tx_init(sc) 954 struct vr_softc *sc; 955 { 956 struct vr_chain_data *cd; 957 struct vr_list_data *ld; 958 int i; 959 960 cd = &sc->vr_cdata; 961 ld = sc->vr_ldata; 962 for (i = 0; i < VR_TX_LIST_CNT; i++) { 963 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 964 if (i == (VR_TX_LIST_CNT - 1)) 965 cd->vr_tx_chain[i].vr_nextdesc = 966 &cd->vr_tx_chain[0]; 967 else 968 cd->vr_tx_chain[i].vr_nextdesc = 969 &cd->vr_tx_chain[i + 1]; 970 } 971 972 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 973 974 return(0); 975 } 976 977 978 /* 979 * Initialize the RX descriptors and allocate mbufs for them. Note that 980 * we arrange the descriptors in a closed ring, so that the last descriptor 981 * points back to the first. 982 */ 983 static int vr_list_rx_init(sc) 984 struct vr_softc *sc; 985 { 986 struct vr_chain_data *cd; 987 struct vr_list_data *ld; 988 int i; 989 990 cd = &sc->vr_cdata; 991 ld = sc->vr_ldata; 992 993 for (i = 0; i < VR_RX_LIST_CNT; i++) { 994 cd->vr_rx_chain[i].vr_ptr = 995 (struct vr_desc *)&ld->vr_rx_list[i]; 996 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 997 return(ENOBUFS); 998 if (i == (VR_RX_LIST_CNT - 1)) { 999 cd->vr_rx_chain[i].vr_nextdesc = 1000 &cd->vr_rx_chain[0]; 1001 ld->vr_rx_list[i].vr_next = 1002 vtophys(&ld->vr_rx_list[0]); 1003 } else { 1004 cd->vr_rx_chain[i].vr_nextdesc = 1005 &cd->vr_rx_chain[i + 1]; 1006 ld->vr_rx_list[i].vr_next = 1007 vtophys(&ld->vr_rx_list[i + 1]); 1008 } 1009 } 1010 1011 cd->vr_rx_head = &cd->vr_rx_chain[0]; 1012 1013 return(0); 1014 } 1015 1016 /* 1017 * Initialize an RX descriptor and attach an MBUF cluster. 1018 * Note: the length fields are only 11 bits wide, which means the 1019 * largest size we can specify is 2047. This is important because 1020 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1021 * overflow the field and make a mess. 1022 */ 1023 static int vr_newbuf(sc, c, m) 1024 struct vr_softc *sc; 1025 struct vr_chain_onefrag *c; 1026 struct mbuf *m; 1027 { 1028 struct mbuf *m_new = NULL; 1029 1030 if (m == NULL) { 1031 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1032 if (m_new == NULL) 1033 return(ENOBUFS); 1034 1035 MCLGET(m_new, M_DONTWAIT); 1036 if (!(m_new->m_flags & M_EXT)) { 1037 m_freem(m_new); 1038 return(ENOBUFS); 1039 } 1040 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1041 } else { 1042 m_new = m; 1043 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1044 m_new->m_data = m_new->m_ext.ext_buf; 1045 } 1046 1047 m_adj(m_new, sizeof(u_int64_t)); 1048 1049 c->vr_mbuf = m_new; 1050 c->vr_ptr->vr_status = VR_RXSTAT; 1051 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1052 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1053 1054 return(0); 1055 } 1056 1057 /* 1058 * A frame has been uploaded: pass the resulting mbuf chain up to 1059 * the higher level protocols. 1060 */ 1061 static void vr_rxeof(sc) 1062 struct vr_softc *sc; 1063 { 1064 struct ether_header *eh; 1065 struct mbuf *m, *m0; 1066 struct ifnet *ifp; 1067 struct vr_chain_onefrag *cur_rx; 1068 int total_len = 0; 1069 u_int32_t rxstat; 1070 1071 ifp = &sc->arpcom.ac_if; 1072 1073 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1074 VR_RXSTAT_OWN)) { 1075 #ifdef DEVICE_POLLING 1076 if (ifp->if_ipending & IFF_POLLING) { 1077 if (sc->rxcycles <= 0) 1078 break; 1079 sc->rxcycles--; 1080 } 1081 #endif /* DEVICE_POLLING */ 1082 m0 = NULL; 1083 cur_rx = sc->vr_cdata.vr_rx_head; 1084 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1085 m = cur_rx->vr_mbuf; 1086 1087 /* 1088 * If an error occurs, update stats, clear the 1089 * status word and leave the mbuf cluster in place: 1090 * it should simply get re-used next time this descriptor 1091 * comes up in the ring. 1092 */ 1093 if (rxstat & VR_RXSTAT_RXERR) { 1094 ifp->if_ierrors++; 1095 printf("vr%d: rx error (%02x):", 1096 sc->vr_unit, rxstat & 0x000000ff); 1097 if (rxstat & VR_RXSTAT_CRCERR) 1098 printf(" crc error"); 1099 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1100 printf(" frame alignment error\n"); 1101 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1102 printf(" FIFO overflow"); 1103 if (rxstat & VR_RXSTAT_GIANT) 1104 printf(" received giant packet"); 1105 if (rxstat & VR_RXSTAT_RUNT) 1106 printf(" received runt packet"); 1107 if (rxstat & VR_RXSTAT_BUSERR) 1108 printf(" system bus error"); 1109 if (rxstat & VR_RXSTAT_BUFFERR) 1110 printf("rx buffer error"); 1111 printf("\n"); 1112 vr_newbuf(sc, cur_rx, m); 1113 continue; 1114 } 1115 1116 /* No errors; receive the packet. */ 1117 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1118 1119 /* 1120 * XXX The VIA Rhine chip includes the CRC with every 1121 * received frame, and there's no way to turn this 1122 * behavior off (at least, I can't find anything in 1123 * the manual that explains how to do it) so we have 1124 * to trim off the CRC manually. 1125 */ 1126 total_len -= ETHER_CRC_LEN; 1127 1128 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1129 total_len + ETHER_ALIGN, 0, ifp, NULL); 1130 vr_newbuf(sc, cur_rx, m); 1131 if (m0 == NULL) { 1132 ifp->if_ierrors++; 1133 continue; 1134 } 1135 m_adj(m0, ETHER_ALIGN); 1136 m = m0; 1137 1138 ifp->if_ipackets++; 1139 eh = mtod(m, struct ether_header *); 1140 1141 /* Remove header from mbuf and pass it on. */ 1142 m_adj(m, sizeof(struct ether_header)); 1143 ether_input(ifp, eh, m); 1144 } 1145 1146 return; 1147 } 1148 1149 void vr_rxeoc(sc) 1150 struct vr_softc *sc; 1151 { 1152 struct ifnet *ifp; 1153 int i; 1154 1155 ifp = &sc->arpcom.ac_if; 1156 1157 ifp->if_ierrors++; 1158 1159 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1160 DELAY(10000); 1161 1162 for (i = 0x400; 1163 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1164 i--) 1165 ; /* Wait for receiver to stop */ 1166 1167 if (!i) { 1168 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1169 sc->vr_flags |= VR_F_RESTART; 1170 return; 1171 } 1172 1173 vr_rxeof(sc); 1174 1175 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1176 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1177 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1178 1179 return; 1180 } 1181 1182 /* 1183 * A frame was downloaded to the chip. It's safe for us to clean up 1184 * the list buffers. 1185 */ 1186 1187 static void vr_txeof(sc) 1188 struct vr_softc *sc; 1189 { 1190 struct vr_chain *cur_tx; 1191 struct ifnet *ifp; 1192 1193 ifp = &sc->arpcom.ac_if; 1194 1195 /* 1196 * Go through our tx list and free mbufs for those 1197 * frames that have been transmitted. 1198 */ 1199 cur_tx = sc->vr_cdata.vr_tx_cons; 1200 while (cur_tx->vr_mbuf != NULL) { 1201 u_int32_t txstat; 1202 int i; 1203 1204 txstat = cur_tx->vr_ptr->vr_status; 1205 1206 if ((txstat & VR_TXSTAT_ABRT) || 1207 (txstat & VR_TXSTAT_UDF)) { 1208 for (i = 0x400; 1209 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1210 i--) 1211 ; /* Wait for chip to shutdown */ 1212 if (!i) { 1213 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1214 sc->vr_flags |= VR_F_RESTART; 1215 break; 1216 } 1217 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1218 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1219 break; 1220 } 1221 1222 if (txstat & VR_TXSTAT_OWN) 1223 break; 1224 1225 if (txstat & VR_TXSTAT_ERRSUM) { 1226 ifp->if_oerrors++; 1227 if (txstat & VR_TXSTAT_DEFER) 1228 ifp->if_collisions++; 1229 if (txstat & VR_TXSTAT_LATECOLL) 1230 ifp->if_collisions++; 1231 } 1232 1233 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1234 1235 ifp->if_opackets++; 1236 m_freem(cur_tx->vr_mbuf); 1237 cur_tx->vr_mbuf = NULL; 1238 ifp->if_flags &= ~IFF_OACTIVE; 1239 1240 cur_tx = cur_tx->vr_nextdesc; 1241 } 1242 sc->vr_cdata.vr_tx_cons = cur_tx; 1243 if (cur_tx->vr_mbuf == NULL) 1244 ifp->if_timer = 0; 1245 } 1246 1247 static void vr_tick(xsc) 1248 void *xsc; 1249 { 1250 struct vr_softc *sc; 1251 struct mii_data *mii; 1252 int s; 1253 1254 s = splimp(); 1255 1256 sc = xsc; 1257 if (sc->vr_flags & VR_F_RESTART) { 1258 printf("vr%d: restarting\n", sc->vr_unit); 1259 vr_stop(sc); 1260 vr_reset(sc); 1261 vr_init(sc); 1262 sc->vr_flags &= ~VR_F_RESTART; 1263 } 1264 1265 mii = device_get_softc(sc->vr_miibus); 1266 mii_tick(mii); 1267 1268 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1269 1270 splx(s); 1271 1272 return; 1273 } 1274 1275 #ifdef DEVICE_POLLING 1276 static poll_handler_t vr_poll; 1277 1278 static void 1279 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1280 { 1281 struct vr_softc *sc = ifp->if_softc; 1282 1283 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1284 ether_poll_deregister(ifp); 1285 cmd = POLL_DEREGISTER; 1286 } 1287 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1288 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1289 return; 1290 } 1291 1292 sc->rxcycles = count; 1293 vr_rxeof(sc); 1294 vr_txeof(sc); 1295 if (ifp->if_snd.ifq_head != NULL) 1296 vr_start(ifp); 1297 1298 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1299 u_int16_t status; 1300 1301 status = CSR_READ_2(sc, VR_ISR); 1302 if (status) 1303 CSR_WRITE_2(sc, VR_ISR, status); 1304 1305 if ((status & VR_INTRS) == 0) 1306 return; 1307 1308 if (status & VR_ISR_RX_DROPPED) { 1309 printf("vr%d: rx packet lost\n", sc->vr_unit); 1310 ifp->if_ierrors++; 1311 } 1312 1313 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1314 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1315 printf("vr%d: receive error (%04x)", 1316 sc->vr_unit, status); 1317 if (status & VR_ISR_RX_NOBUF) 1318 printf(" no buffers"); 1319 if (status & VR_ISR_RX_OFLOW) 1320 printf(" overflow"); 1321 if (status & VR_ISR_RX_DROPPED) 1322 printf(" packet lost"); 1323 printf("\n"); 1324 vr_rxeoc(sc); 1325 } 1326 1327 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1328 vr_reset(sc); 1329 vr_init(sc); 1330 return; 1331 } 1332 1333 if ((status & VR_ISR_UDFI) || 1334 (status & VR_ISR_TX_ABRT2) || 1335 (status & VR_ISR_TX_ABRT)) { 1336 ifp->if_oerrors++; 1337 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1338 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1339 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1340 } 1341 } 1342 } 1343 } 1344 #endif /* DEVICE_POLLING */ 1345 1346 static void vr_intr(arg) 1347 void *arg; 1348 { 1349 struct vr_softc *sc; 1350 struct ifnet *ifp; 1351 u_int16_t status; 1352 1353 sc = arg; 1354 ifp = &sc->arpcom.ac_if; 1355 1356 #ifdef DEVICE_POLLING 1357 if (ifp->if_ipending & IFF_POLLING) 1358 return; 1359 if ((ifp->if_capenable & IFCAP_POLLING) && 1360 ether_poll_register(vr_poll, ifp)) { /* ok, disable interrupts */ 1361 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1362 vr_poll(ifp, 0, 1); 1363 return; 1364 } 1365 #endif /* DEVICE_POLLING */ 1366 1367 /* Supress unwanted interrupts. */ 1368 if (!(ifp->if_flags & IFF_UP)) { 1369 vr_stop(sc); 1370 return; 1371 } 1372 1373 /* Disable interrupts. */ 1374 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1375 1376 for (;;) { 1377 1378 status = CSR_READ_2(sc, VR_ISR); 1379 if (status) 1380 CSR_WRITE_2(sc, VR_ISR, status); 1381 1382 if ((status & VR_INTRS) == 0) 1383 break; 1384 1385 if (status & VR_ISR_RX_OK) 1386 vr_rxeof(sc); 1387 1388 if (status & VR_ISR_RX_DROPPED) { 1389 printf("vr%d: rx packet lost\n", sc->vr_unit); 1390 ifp->if_ierrors++; 1391 } 1392 1393 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1394 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1395 printf("vr%d: receive error (%04x)", 1396 sc->vr_unit, status); 1397 if (status & VR_ISR_RX_NOBUF) 1398 printf(" no buffers"); 1399 if (status & VR_ISR_RX_OFLOW) 1400 printf(" overflow"); 1401 if (status & VR_ISR_RX_DROPPED) 1402 printf(" packet lost"); 1403 printf("\n"); 1404 vr_rxeoc(sc); 1405 } 1406 1407 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1408 vr_reset(sc); 1409 vr_init(sc); 1410 break; 1411 } 1412 1413 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1414 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1415 vr_txeof(sc); 1416 if ((status & VR_ISR_UDFI) || 1417 (status & VR_ISR_TX_ABRT2) || 1418 (status & VR_ISR_TX_ABRT)) { 1419 ifp->if_oerrors++; 1420 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1421 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1422 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1423 } 1424 } 1425 } 1426 1427 } 1428 1429 /* Re-enable interrupts. */ 1430 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1431 1432 if (ifp->if_snd.ifq_head != NULL) { 1433 vr_start(ifp); 1434 } 1435 1436 return; 1437 } 1438 1439 /* 1440 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1441 * pointers to the fragment pointers. 1442 */ 1443 static int vr_encap(sc, c, m_head) 1444 struct vr_softc *sc; 1445 struct vr_chain *c; 1446 struct mbuf *m_head; 1447 { 1448 struct vr_desc *f = NULL; 1449 struct mbuf *m; 1450 1451 /* 1452 * The VIA Rhine wants packet buffers to be longword 1453 * aligned, but very often our mbufs aren't. Rather than 1454 * waste time trying to decide when to copy and when not 1455 * to copy, just do it all the time. 1456 */ 1457 m = m_defrag(m_head, M_DONTWAIT); 1458 if (m == NULL) { 1459 return(1); 1460 } 1461 1462 /* 1463 * The Rhine chip doesn't auto-pad, so we have to make 1464 * sure to pad short frames out to the minimum frame length 1465 * ourselves. 1466 */ 1467 if (m->m_len < VR_MIN_FRAMELEN) { 1468 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1469 m->m_len = m->m_pkthdr.len; 1470 } 1471 1472 c->vr_mbuf = m; 1473 f = c->vr_ptr; 1474 f->vr_data = vtophys(mtod(m, caddr_t)); 1475 f->vr_ctl = m->m_len; 1476 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1477 f->vr_status = 0; 1478 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1479 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1480 1481 return(0); 1482 } 1483 1484 /* 1485 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1486 * to the mbuf data regions directly in the transmit lists. We also save a 1487 * copy of the pointers since the transmit list fragment pointers are 1488 * physical addresses. 1489 */ 1490 static void vr_start(ifp) 1491 struct ifnet *ifp; 1492 { 1493 struct vr_softc *sc; 1494 struct mbuf *m_head; 1495 struct vr_chain *cur_tx; 1496 1497 if (ifp->if_flags & IFF_OACTIVE) 1498 return; 1499 1500 sc = ifp->if_softc; 1501 1502 cur_tx = sc->vr_cdata.vr_tx_prod; 1503 while (cur_tx->vr_mbuf == NULL) { 1504 IF_DEQUEUE(&ifp->if_snd, m_head); 1505 if (m_head == NULL) 1506 break; 1507 1508 /* Pack the data into the descriptor. */ 1509 if (vr_encap(sc, cur_tx, m_head)) { 1510 /* Rollback, send what we were able to encap. */ 1511 IF_PREPEND(&ifp->if_snd, m_head); 1512 break; 1513 } 1514 1515 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1516 1517 /* 1518 * If there's a BPF listener, bounce a copy of this frame 1519 * to him. 1520 */ 1521 if (ifp->if_bpf) 1522 bpf_mtap(ifp, cur_tx->vr_mbuf); 1523 1524 cur_tx = cur_tx->vr_nextdesc; 1525 } 1526 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1527 sc->vr_cdata.vr_tx_prod = cur_tx; 1528 1529 /* Tell the chip to start transmitting. */ 1530 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1531 1532 /* Set a timeout in case the chip goes out to lunch. */ 1533 ifp->if_timer = 5; 1534 1535 if (cur_tx->vr_mbuf != NULL) 1536 ifp->if_flags |= IFF_OACTIVE; 1537 } 1538 1539 return; 1540 } 1541 1542 static void vr_init(xsc) 1543 void *xsc; 1544 { 1545 struct vr_softc *sc = xsc; 1546 struct ifnet *ifp = &sc->arpcom.ac_if; 1547 struct mii_data *mii; 1548 int s, i; 1549 1550 s = splimp(); 1551 1552 mii = device_get_softc(sc->vr_miibus); 1553 1554 /* 1555 * Cancel pending I/O and free all RX/TX buffers. 1556 */ 1557 vr_stop(sc); 1558 vr_reset(sc); 1559 1560 /* 1561 * Set our station address. 1562 */ 1563 for (i = 0; i < ETHER_ADDR_LEN; i++) 1564 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1565 1566 /* Set DMA size */ 1567 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1568 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1569 1570 /* 1571 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1572 * so we must set both. 1573 */ 1574 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1575 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1576 1577 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1578 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1579 1580 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1581 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1582 1583 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1584 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1585 1586 /* Init circular RX list. */ 1587 if (vr_list_rx_init(sc) == ENOBUFS) { 1588 printf("vr%d: initialization failed: no " 1589 "memory for rx buffers\n", sc->vr_unit); 1590 vr_stop(sc); 1591 (void)splx(s); 1592 return; 1593 } 1594 1595 /* 1596 * Init tx descriptors. 1597 */ 1598 vr_list_tx_init(sc); 1599 1600 /* If we want promiscuous mode, set the allframes bit. */ 1601 if (ifp->if_flags & IFF_PROMISC) 1602 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1603 else 1604 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1605 1606 /* Set capture broadcast bit to capture broadcast frames. */ 1607 if (ifp->if_flags & IFF_BROADCAST) 1608 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1609 else 1610 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1611 1612 /* 1613 * Program the multicast filter, if necessary. 1614 */ 1615 vr_setmulti(sc); 1616 1617 /* 1618 * Load the address of the RX list. 1619 */ 1620 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1621 1622 /* Enable receiver and transmitter. */ 1623 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1624 VR_CMD_TX_ON|VR_CMD_RX_ON| 1625 VR_CMD_RX_GO); 1626 1627 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1628 1629 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1630 #ifdef DEVICE_POLLING 1631 /* 1632 * Disable interrupts if we are polling. 1633 */ 1634 if (ifp->if_ipending & IFF_POLLING) 1635 CSR_WRITE_2(sc, VR_IMR, 0); 1636 else 1637 #endif /* DEVICE_POLLING */ 1638 /* 1639 * Enable interrupts. 1640 */ 1641 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1642 1643 mii_mediachg(mii); 1644 1645 ifp->if_flags |= IFF_RUNNING; 1646 ifp->if_flags &= ~IFF_OACTIVE; 1647 1648 (void)splx(s); 1649 1650 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1651 1652 return; 1653 } 1654 1655 /* 1656 * Set media options. 1657 */ 1658 static int vr_ifmedia_upd(ifp) 1659 struct ifnet *ifp; 1660 { 1661 struct vr_softc *sc; 1662 1663 sc = ifp->if_softc; 1664 1665 if (ifp->if_flags & IFF_UP) 1666 vr_init(sc); 1667 1668 return(0); 1669 } 1670 1671 /* 1672 * Report current media status. 1673 */ 1674 static void vr_ifmedia_sts(ifp, ifmr) 1675 struct ifnet *ifp; 1676 struct ifmediareq *ifmr; 1677 { 1678 struct vr_softc *sc; 1679 struct mii_data *mii; 1680 1681 sc = ifp->if_softc; 1682 mii = device_get_softc(sc->vr_miibus); 1683 mii_pollstat(mii); 1684 ifmr->ifm_active = mii->mii_media_active; 1685 ifmr->ifm_status = mii->mii_media_status; 1686 1687 return; 1688 } 1689 1690 static int vr_ioctl(ifp, command, data) 1691 struct ifnet *ifp; 1692 u_long command; 1693 caddr_t data; 1694 { 1695 struct vr_softc *sc = ifp->if_softc; 1696 struct ifreq *ifr = (struct ifreq *) data; 1697 struct mii_data *mii; 1698 int s, error = 0; 1699 1700 s = splimp(); 1701 1702 switch(command) { 1703 case SIOCSIFADDR: 1704 case SIOCGIFADDR: 1705 case SIOCSIFMTU: 1706 error = ether_ioctl(ifp, command, data); 1707 break; 1708 case SIOCSIFFLAGS: 1709 if (ifp->if_flags & IFF_UP) { 1710 vr_init(sc); 1711 } else { 1712 if (ifp->if_flags & IFF_RUNNING) 1713 vr_stop(sc); 1714 } 1715 error = 0; 1716 break; 1717 case SIOCADDMULTI: 1718 case SIOCDELMULTI: 1719 vr_setmulti(sc); 1720 error = 0; 1721 break; 1722 case SIOCGIFMEDIA: 1723 case SIOCSIFMEDIA: 1724 mii = device_get_softc(sc->vr_miibus); 1725 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1726 break; 1727 case SIOCSIFCAP: 1728 ifp->if_capenable = ifr->ifr_reqcap; 1729 break; 1730 default: 1731 error = EINVAL; 1732 break; 1733 } 1734 1735 (void)splx(s); 1736 1737 return(error); 1738 } 1739 1740 static void vr_watchdog(ifp) 1741 struct ifnet *ifp; 1742 { 1743 struct vr_softc *sc; 1744 1745 sc = ifp->if_softc; 1746 1747 ifp->if_oerrors++; 1748 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1749 1750 vr_stop(sc); 1751 vr_reset(sc); 1752 vr_init(sc); 1753 1754 if (ifp->if_snd.ifq_head != NULL) 1755 vr_start(ifp); 1756 1757 return; 1758 } 1759 1760 /* 1761 * Stop the adapter and free any mbufs allocated to the 1762 * RX and TX lists. 1763 */ 1764 static void vr_stop(sc) 1765 struct vr_softc *sc; 1766 { 1767 register int i; 1768 struct ifnet *ifp; 1769 1770 ifp = &sc->arpcom.ac_if; 1771 ifp->if_timer = 0; 1772 1773 untimeout(vr_tick, sc, sc->vr_stat_ch); 1774 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1775 #ifdef DEVICE_POLLING 1776 ether_poll_deregister(ifp); 1777 #endif /* DEVICE_POLLING */ 1778 1779 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1780 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1781 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1782 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1783 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1784 1785 /* 1786 * Free data in the RX lists. 1787 */ 1788 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1789 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1790 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1791 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1792 } 1793 } 1794 bzero((char *)&sc->vr_ldata->vr_rx_list, 1795 sizeof(sc->vr_ldata->vr_rx_list)); 1796 1797 /* 1798 * Free the TX list buffers. 1799 */ 1800 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1801 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1802 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1803 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1804 } 1805 } 1806 1807 bzero((char *)&sc->vr_ldata->vr_tx_list, 1808 sizeof(sc->vr_ldata->vr_tx_list)); 1809 1810 return; 1811 } 1812 1813 /* 1814 * Stop all chip I/O so that the kernel's probe routines don't 1815 * get confused by errant DMAs when rebooting. 1816 */ 1817 static void vr_shutdown(dev) 1818 device_t dev; 1819 { 1820 struct vr_softc *sc; 1821 1822 sc = device_get_softc(dev); 1823 1824 vr_stop(sc); 1825 1826 return; 1827 }
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