FreeBSD/Linux Kernel Cross Reference
sys/pci/if_vr.c
1 /*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/5.2/sys/pci/if_vr.c 122689 2003-11-14 19:00:32Z sam $");
35
36 /*
37 * VIA Rhine fast ethernet PCI NIC driver
38 *
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47 /*
48 * The VIA Rhine controllers are similar in some respects to the
49 * the DEC tulip chips, except less complicated. The controller
50 * uses an MII bus and an external physical layer interface. The
51 * receiver has a one entry perfect filter and a 64-bit hash table
52 * multicast filter. Transmit and receive descriptors are similar
53 * to the tulip.
54 *
55 * The Rhine has a serious flaw in its transmit DMA mechanism:
56 * transmit buffers must be longword aligned. Unfortunately,
57 * FreeBSD doesn't guarantee that mbufs will be filled in starting
58 * at longword boundaries, so we have to do a buffer copy before
59 * transmission.
60 */
61
62 #include <sys/param.h>
63 #include <sys/systm.h>
64 #include <sys/sockio.h>
65 #include <sys/mbuf.h>
66 #include <sys/malloc.h>
67 #include <sys/kernel.h>
68 #include <sys/socket.h>
69
70 #include <net/if.h>
71 #include <net/if_arp.h>
72 #include <net/ethernet.h>
73 #include <net/if_dl.h>
74 #include <net/if_media.h>
75
76 #include <net/bpf.h>
77
78 #include <vm/vm.h> /* for vtophys */
79 #include <vm/pmap.h> /* for vtophys */
80 #include <machine/bus_pio.h>
81 #include <machine/bus_memio.h>
82 #include <machine/bus.h>
83 #include <machine/resource.h>
84 #include <sys/bus.h>
85 #include <sys/rman.h>
86
87 #include <dev/mii/mii.h>
88 #include <dev/mii/miivar.h>
89
90 #include <dev/pci/pcireg.h>
91 #include <dev/pci/pcivar.h>
92
93 #define VR_USEIOSPACE
94
95 #include <pci/if_vrreg.h>
96
97 MODULE_DEPEND(vr, pci, 1, 1, 1);
98 MODULE_DEPEND(vr, ether, 1, 1, 1);
99 MODULE_DEPEND(vr, miibus, 1, 1, 1);
100
101 /* "controller miibus0" required. See GENERIC if you get errors here. */
102 #include "miibus_if.h"
103
104 #undef VR_USESWSHIFT
105
106 /*
107 * Various supported device vendors/types and their names.
108 */
109 static struct vr_type vr_devs[] = {
110 { VIA_VENDORID, VIA_DEVICEID_RHINE,
111 "VIA VT3043 Rhine I 10/100BaseTX" },
112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
113 "VIA VT86C100A Rhine II 10/100BaseTX" },
114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
115 "VIA VT6102 Rhine II 10/100BaseTX" },
116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
117 "VIA VT6105 Rhine III 10/100BaseTX" },
118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
119 "VIA VT6105M Rhine III 10/100BaseTX" },
120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
121 "Delta Electronics Rhine II 10/100BaseTX" },
122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
123 "Addtron Technology Rhine II 10/100BaseTX" },
124 { 0, 0, NULL }
125 };
126
127 static int vr_probe (device_t);
128 static int vr_attach (device_t);
129 static int vr_detach (device_t);
130
131 static int vr_newbuf (struct vr_softc *,
132 struct vr_chain_onefrag *,
133 struct mbuf *);
134 static int vr_encap (struct vr_softc *, struct vr_chain *,
135 struct mbuf * );
136
137 static void vr_rxeof (struct vr_softc *);
138 static void vr_rxeoc (struct vr_softc *);
139 static void vr_txeof (struct vr_softc *);
140 static void vr_txeoc (struct vr_softc *);
141 static void vr_tick (void *);
142 static void vr_intr (void *);
143 static void vr_start (struct ifnet *);
144 static int vr_ioctl (struct ifnet *, u_long, caddr_t);
145 static void vr_init (void *);
146 static void vr_stop (struct vr_softc *);
147 static void vr_watchdog (struct ifnet *);
148 static void vr_shutdown (device_t);
149 static int vr_ifmedia_upd (struct ifnet *);
150 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *);
151
152 #ifdef VR_USESWSHIFT
153 static void vr_mii_sync (struct vr_softc *);
154 static void vr_mii_send (struct vr_softc *, u_int32_t, int);
155 #endif
156 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *);
157 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *);
158 static int vr_miibus_readreg (device_t, int, int);
159 static int vr_miibus_writereg (device_t, int, int, int);
160 static void vr_miibus_statchg (device_t);
161
162 static void vr_setcfg (struct vr_softc *, int);
163 static u_int32_t vr_mchash (caddr_t);
164 static void vr_setmulti (struct vr_softc *);
165 static void vr_reset (struct vr_softc *);
166 static int vr_list_rx_init (struct vr_softc *);
167 static int vr_list_tx_init (struct vr_softc *);
168
169 #ifdef VR_USEIOSPACE
170 #define VR_RES SYS_RES_IOPORT
171 #define VR_RID VR_PCI_LOIO
172 #else
173 #define VR_RES SYS_RES_MEMORY
174 #define VR_RID VR_PCI_LOMEM
175 #endif
176
177 static device_method_t vr_methods[] = {
178 /* Device interface */
179 DEVMETHOD(device_probe, vr_probe),
180 DEVMETHOD(device_attach, vr_attach),
181 DEVMETHOD(device_detach, vr_detach),
182 DEVMETHOD(device_shutdown, vr_shutdown),
183
184 /* bus interface */
185 DEVMETHOD(bus_print_child, bus_generic_print_child),
186 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
187
188 /* MII interface */
189 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
190 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
191 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
192
193 { 0, 0 }
194 };
195
196 static driver_t vr_driver = {
197 "vr",
198 vr_methods,
199 sizeof(struct vr_softc)
200 };
201
202 static devclass_t vr_devclass;
203
204 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0);
205 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
206
207 #define VR_SETBIT(sc, reg, x) \
208 CSR_WRITE_1(sc, reg, \
209 CSR_READ_1(sc, reg) | (x))
210
211 #define VR_CLRBIT(sc, reg, x) \
212 CSR_WRITE_1(sc, reg, \
213 CSR_READ_1(sc, reg) & ~(x))
214
215 #define VR_SETBIT16(sc, reg, x) \
216 CSR_WRITE_2(sc, reg, \
217 CSR_READ_2(sc, reg) | (x))
218
219 #define VR_CLRBIT16(sc, reg, x) \
220 CSR_WRITE_2(sc, reg, \
221 CSR_READ_2(sc, reg) & ~(x))
222
223 #define VR_SETBIT32(sc, reg, x) \
224 CSR_WRITE_4(sc, reg, \
225 CSR_READ_4(sc, reg) | (x))
226
227 #define VR_CLRBIT32(sc, reg, x) \
228 CSR_WRITE_4(sc, reg, \
229 CSR_READ_4(sc, reg) & ~(x))
230
231 #define SIO_SET(x) \
232 CSR_WRITE_1(sc, VR_MIICMD, \
233 CSR_READ_1(sc, VR_MIICMD) | (x))
234
235 #define SIO_CLR(x) \
236 CSR_WRITE_1(sc, VR_MIICMD, \
237 CSR_READ_1(sc, VR_MIICMD) & ~(x))
238
239 #ifdef VR_USESWSHIFT
240 /*
241 * Sync the PHYs by setting data bit and strobing the clock 32 times.
242 */
243 static void
244 vr_mii_sync(sc)
245 struct vr_softc *sc;
246 {
247 register int i;
248
249 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
250
251 for (i = 0; i < 32; i++) {
252 SIO_SET(VR_MIICMD_CLK);
253 DELAY(1);
254 SIO_CLR(VR_MIICMD_CLK);
255 DELAY(1);
256 }
257
258 return;
259 }
260
261 /*
262 * Clock a series of bits through the MII.
263 */
264 static void
265 vr_mii_send(sc, bits, cnt)
266 struct vr_softc *sc;
267 u_int32_t bits;
268 int cnt;
269 {
270 int i;
271
272 SIO_CLR(VR_MIICMD_CLK);
273
274 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
275 if (bits & i) {
276 SIO_SET(VR_MIICMD_DATAIN);
277 } else {
278 SIO_CLR(VR_MIICMD_DATAIN);
279 }
280 DELAY(1);
281 SIO_CLR(VR_MIICMD_CLK);
282 DELAY(1);
283 SIO_SET(VR_MIICMD_CLK);
284 }
285 }
286 #endif
287
288 /*
289 * Read an PHY register through the MII.
290 */
291 static int
292 vr_mii_readreg(sc, frame)
293 struct vr_softc *sc;
294 struct vr_mii_frame *frame;
295
296 #ifdef VR_USESWSHIFT
297 {
298 int i, ack;
299
300 VR_LOCK(sc);
301
302 /*
303 * Set up frame for RX.
304 */
305 frame->mii_stdelim = VR_MII_STARTDELIM;
306 frame->mii_opcode = VR_MII_READOP;
307 frame->mii_turnaround = 0;
308 frame->mii_data = 0;
309
310 CSR_WRITE_1(sc, VR_MIICMD, 0);
311 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
312
313 /*
314 * Turn on data xmit.
315 */
316 SIO_SET(VR_MIICMD_DIR);
317
318 vr_mii_sync(sc);
319
320 /*
321 * Send command/address info.
322 */
323 vr_mii_send(sc, frame->mii_stdelim, 2);
324 vr_mii_send(sc, frame->mii_opcode, 2);
325 vr_mii_send(sc, frame->mii_phyaddr, 5);
326 vr_mii_send(sc, frame->mii_regaddr, 5);
327
328 /* Idle bit */
329 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
330 DELAY(1);
331 SIO_SET(VR_MIICMD_CLK);
332 DELAY(1);
333
334 /* Turn off xmit. */
335 SIO_CLR(VR_MIICMD_DIR);
336
337 /* Check for ack */
338 SIO_CLR(VR_MIICMD_CLK);
339 DELAY(1);
340 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
341 SIO_SET(VR_MIICMD_CLK);
342 DELAY(1);
343
344 /*
345 * Now try reading data bits. If the ack failed, we still
346 * need to clock through 16 cycles to keep the PHY(s) in sync.
347 */
348 if (ack) {
349 for(i = 0; i < 16; i++) {
350 SIO_CLR(VR_MIICMD_CLK);
351 DELAY(1);
352 SIO_SET(VR_MIICMD_CLK);
353 DELAY(1);
354 }
355 goto fail;
356 }
357
358 for (i = 0x8000; i; i >>= 1) {
359 SIO_CLR(VR_MIICMD_CLK);
360 DELAY(1);
361 if (!ack) {
362 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
363 frame->mii_data |= i;
364 DELAY(1);
365 }
366 SIO_SET(VR_MIICMD_CLK);
367 DELAY(1);
368 }
369
370 fail:
371
372 SIO_CLR(VR_MIICMD_CLK);
373 DELAY(1);
374 SIO_SET(VR_MIICMD_CLK);
375 DELAY(1);
376
377 VR_UNLOCK(sc);
378
379 if (ack)
380 return(1);
381 return(0);
382 }
383 #else
384 {
385 int s, i;
386
387 s = splimp();
388
389 /* Set the PHY-adress */
390 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
391 frame->mii_phyaddr);
392
393 /* Set the register-adress */
394 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
395 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
396
397 for (i = 0; i < 10000; i++) {
398 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
399 break;
400 DELAY(1);
401 }
402
403 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
404
405 (void)splx(s);
406
407 return(0);
408 }
409 #endif
410
411
412 /*
413 * Write to a PHY register through the MII.
414 */
415 static int
416 vr_mii_writereg(sc, frame)
417 struct vr_softc *sc;
418 struct vr_mii_frame *frame;
419
420 #ifdef VR_USESWSHIFT
421 {
422 VR_LOCK(sc);
423
424 CSR_WRITE_1(sc, VR_MIICMD, 0);
425 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
426
427 /*
428 * Set up frame for TX.
429 */
430
431 frame->mii_stdelim = VR_MII_STARTDELIM;
432 frame->mii_opcode = VR_MII_WRITEOP;
433 frame->mii_turnaround = VR_MII_TURNAROUND;
434
435 /*
436 * Turn on data output.
437 */
438 SIO_SET(VR_MIICMD_DIR);
439
440 vr_mii_sync(sc);
441
442 vr_mii_send(sc, frame->mii_stdelim, 2);
443 vr_mii_send(sc, frame->mii_opcode, 2);
444 vr_mii_send(sc, frame->mii_phyaddr, 5);
445 vr_mii_send(sc, frame->mii_regaddr, 5);
446 vr_mii_send(sc, frame->mii_turnaround, 2);
447 vr_mii_send(sc, frame->mii_data, 16);
448
449 /* Idle bit. */
450 SIO_SET(VR_MIICMD_CLK);
451 DELAY(1);
452 SIO_CLR(VR_MIICMD_CLK);
453 DELAY(1);
454
455 /*
456 * Turn off xmit.
457 */
458 SIO_CLR(VR_MIICMD_DIR);
459
460 VR_UNLOCK(sc);
461
462 return(0);
463 }
464 #else
465 {
466 int s, i;
467
468 s = splimp();
469
470 /* Set the PHY-adress */
471 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
472 frame->mii_phyaddr);
473
474 /* Set the register-adress and data to write */
475 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
476 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
477
478 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
479
480 for (i = 0; i < 10000; i++) {
481 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
482 break;
483 DELAY(1);
484 }
485
486 (void)splx(s);
487
488 return(0);
489 }
490 #endif
491
492 static int
493 vr_miibus_readreg(dev, phy, reg)
494 device_t dev;
495 int phy, reg;
496 {
497 struct vr_softc *sc;
498 struct vr_mii_frame frame;
499
500 sc = device_get_softc(dev);
501
502 switch (sc->vr_revid) {
503 case REV_ID_VT6102_APOLLO:
504 if (phy != 1)
505 return 0;
506 default:
507 break;
508 }
509
510 bzero((char *)&frame, sizeof(frame));
511
512 frame.mii_phyaddr = phy;
513 frame.mii_regaddr = reg;
514 vr_mii_readreg(sc, &frame);
515
516 return(frame.mii_data);
517 }
518
519 static int
520 vr_miibus_writereg(dev, phy, reg, data)
521 device_t dev;
522 u_int16_t phy, reg, data;
523 {
524 struct vr_softc *sc;
525 struct vr_mii_frame frame;
526
527 sc = device_get_softc(dev);
528
529 switch (sc->vr_revid) {
530 case REV_ID_VT6102_APOLLO:
531 if (phy != 1)
532 return 0;
533 default:
534 break;
535 }
536
537 bzero((char *)&frame, sizeof(frame));
538
539 frame.mii_phyaddr = phy;
540 frame.mii_regaddr = reg;
541 frame.mii_data = data;
542
543 vr_mii_writereg(sc, &frame);
544
545 return(0);
546 }
547
548 static void
549 vr_miibus_statchg(dev)
550 device_t dev;
551 {
552 struct vr_softc *sc;
553 struct mii_data *mii;
554
555 sc = device_get_softc(dev);
556 VR_LOCK(sc);
557 mii = device_get_softc(sc->vr_miibus);
558 vr_setcfg(sc, mii->mii_media_active);
559 VR_UNLOCK(sc);
560
561 return;
562 }
563
564 /*
565 * Calculate CRC of a multicast group address, return the lower 6 bits.
566 */
567 static u_int32_t
568 vr_mchash(addr)
569 caddr_t addr;
570 {
571 u_int32_t crc, carry;
572 int idx, bit;
573 u_int8_t data;
574
575 /* Compute CRC for the address value. */
576 crc = 0xFFFFFFFF; /* initial value */
577
578 for (idx = 0; idx < 6; idx++) {
579 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) {
580 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
581 crc <<= 1;
582 if (carry)
583 crc = (crc ^ 0x04c11db6) | carry;
584 }
585 }
586
587 /* return the filter bit position */
588 return((crc >> 26) & 0x0000003F);
589 }
590
591 /*
592 * Program the 64-bit multicast hash filter.
593 */
594 static void
595 vr_setmulti(sc)
596 struct vr_softc *sc;
597 {
598 struct ifnet *ifp;
599 int h = 0;
600 u_int32_t hashes[2] = { 0, 0 };
601 struct ifmultiaddr *ifma;
602 u_int8_t rxfilt;
603 int mcnt = 0;
604
605 ifp = &sc->arpcom.ac_if;
606
607 rxfilt = CSR_READ_1(sc, VR_RXCFG);
608
609 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
610 rxfilt |= VR_RXCFG_RX_MULTI;
611 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
612 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
613 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
614 return;
615 }
616
617 /* first, zot all the existing hash bits */
618 CSR_WRITE_4(sc, VR_MAR0, 0);
619 CSR_WRITE_4(sc, VR_MAR1, 0);
620
621 /* now program new ones */
622 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
623 if (ifma->ifma_addr->sa_family != AF_LINK)
624 continue;
625 h = vr_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
626 if (h < 32)
627 hashes[0] |= (1 << h);
628 else
629 hashes[1] |= (1 << (h - 32));
630 mcnt++;
631 }
632
633 if (mcnt)
634 rxfilt |= VR_RXCFG_RX_MULTI;
635 else
636 rxfilt &= ~VR_RXCFG_RX_MULTI;
637
638 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
639 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
640 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
641
642 return;
643 }
644
645 /*
646 * In order to fiddle with the
647 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
648 * first have to put the transmit and/or receive logic in the idle state.
649 */
650 static void
651 vr_setcfg(sc, media)
652 struct vr_softc *sc;
653 int media;
654 {
655 int restart = 0;
656
657 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
658 restart = 1;
659 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
660 }
661
662 if ((media & IFM_GMASK) == IFM_FDX)
663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
664 else
665 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
666
667 if (restart)
668 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
669
670 return;
671 }
672
673 static void
674 vr_reset(sc)
675 struct vr_softc *sc;
676 {
677 register int i;
678
679 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
680
681 for (i = 0; i < VR_TIMEOUT; i++) {
682 DELAY(10);
683 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
684 break;
685 }
686 if (i == VR_TIMEOUT) {
687 if (sc->vr_revid < REV_ID_VT3065_A)
688 printf("vr%d: reset never completed!\n", sc->vr_unit);
689 else {
690 /* Use newer force reset command */
691 printf("vr%d: Using force reset command.\n", sc->vr_unit);
692 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
693 }
694 }
695
696 /* Wait a little while for the chip to get its brains in order. */
697 DELAY(1000);
698
699 return;
700 }
701
702 /*
703 * Probe for a VIA Rhine chip. Check the PCI vendor and device
704 * IDs against our list and return a device name if we find a match.
705 */
706 static int
707 vr_probe(dev)
708 device_t dev;
709 {
710 struct vr_type *t;
711
712 t = vr_devs;
713
714 while(t->vr_name != NULL) {
715 if ((pci_get_vendor(dev) == t->vr_vid) &&
716 (pci_get_device(dev) == t->vr_did)) {
717 device_set_desc(dev, t->vr_name);
718 return(0);
719 }
720 t++;
721 }
722
723 return(ENXIO);
724 }
725
726 /*
727 * Attach the interface. Allocate softc structures, do ifmedia
728 * setup and ethernet/BPF attach.
729 */
730 static int
731 vr_attach(dev)
732 device_t dev;
733 {
734 int i;
735 u_char eaddr[ETHER_ADDR_LEN];
736 struct vr_softc *sc;
737 struct ifnet *ifp;
738 int unit, error = 0, rid;
739
740 sc = device_get_softc(dev);
741 unit = device_get_unit(dev);
742
743 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
744 MTX_DEF | MTX_RECURSE);
745 #ifndef BURN_BRIDGES
746 /*
747 * Handle power management nonsense.
748 */
749 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
750 u_int32_t iobase, membase, irq;
751
752 /* Save important PCI config data. */
753 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
754 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
755 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
756
757 /* Reset the power state. */
758 printf("vr%d: chip is in D%d power mode "
759 "-- setting to D0\n", unit,
760 pci_get_powerstate(dev));
761 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
762
763 /* Restore PCI config data. */
764 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
765 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
766 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
767 }
768 #endif
769 /*
770 * Map control/status registers.
771 */
772 pci_enable_busmaster(dev);
773 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF;
774
775 rid = VR_RID;
776 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid,
777 0, ~0, 1, RF_ACTIVE);
778
779 if (sc->vr_res == NULL) {
780 printf("vr%d: couldn't map ports/memory\n", unit);
781 error = ENXIO;
782 goto fail;
783 }
784
785 sc->vr_btag = rman_get_bustag(sc->vr_res);
786 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
787
788 /* Allocate interrupt */
789 rid = 0;
790 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
791 RF_SHAREABLE | RF_ACTIVE);
792
793 if (sc->vr_irq == NULL) {
794 printf("vr%d: couldn't map interrupt\n", unit);
795 error = ENXIO;
796 goto fail;
797 }
798
799 /*
800 * Windows may put the chip in suspend mode when it
801 * shuts down. Be sure to kick it in the head to wake it
802 * up again.
803 */
804 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
805
806 /* Reset the adapter. */
807 vr_reset(sc);
808
809 /*
810 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
811 * initialization and disable AUTOPOLL.
812 */
813 pci_write_config(dev, VR_PCI_MODE,
814 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4);
815 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
816
817 /*
818 * Get station address. The way the Rhine chips work,
819 * you're not allowed to directly access the EEPROM once
820 * they've been programmed a special way. Consequently,
821 * we need to read the node address from the PAR0 and PAR1
822 * registers.
823 */
824 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
825 DELAY(200);
826 for (i = 0; i < ETHER_ADDR_LEN; i++)
827 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
828
829 /*
830 * A Rhine chip was detected. Inform the world.
831 */
832 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":");
833
834 sc->vr_unit = unit;
835 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
836
837 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
838 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
839
840 if (sc->vr_ldata == NULL) {
841 printf("vr%d: no memory for list buffers!\n", unit);
842 error = ENXIO;
843 goto fail;
844 }
845
846 bzero(sc->vr_ldata, sizeof(struct vr_list_data));
847
848 ifp = &sc->arpcom.ac_if;
849 ifp->if_softc = sc;
850 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
851 ifp->if_mtu = ETHERMTU;
852 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
853 ifp->if_ioctl = vr_ioctl;
854 ifp->if_output = ether_output;
855 ifp->if_start = vr_start;
856 ifp->if_watchdog = vr_watchdog;
857 ifp->if_init = vr_init;
858 ifp->if_baudrate = 10000000;
859 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1;
860
861 /*
862 * Do MII setup.
863 */
864 if (mii_phy_probe(dev, &sc->vr_miibus,
865 vr_ifmedia_upd, vr_ifmedia_sts)) {
866 printf("vr%d: MII without any phy!\n", sc->vr_unit);
867 error = ENXIO;
868 goto fail;
869 }
870
871 callout_handle_init(&sc->vr_stat_ch);
872
873 /*
874 * Call MI attach routine.
875 */
876 ether_ifattach(ifp, eaddr);
877
878 /* Hook interrupt last to avoid having to lock softc */
879 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET,
880 vr_intr, sc, &sc->vr_intrhand);
881
882 if (error) {
883 printf("vr%d: couldn't set up irq\n", unit);
884 ether_ifdetach(ifp);
885 goto fail;
886 }
887
888 fail:
889 if (error)
890 vr_detach(dev);
891
892 return(error);
893 }
894
895 /*
896 * Shutdown hardware and free up resources. This can be called any
897 * time after the mutex has been initialized. It is called in both
898 * the error case in attach and the normal detach case so it needs
899 * to be careful about only freeing resources that have actually been
900 * allocated.
901 */
902 static int
903 vr_detach(dev)
904 device_t dev;
905 {
906 struct vr_softc *sc;
907 struct ifnet *ifp;
908
909 sc = device_get_softc(dev);
910 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized"));
911 VR_LOCK(sc);
912 ifp = &sc->arpcom.ac_if;
913
914 /* These should only be active if attach succeeded */
915 if (device_is_attached(dev)) {
916 vr_stop(sc);
917 ether_ifdetach(ifp);
918 }
919 if (sc->vr_miibus)
920 device_delete_child(dev, sc->vr_miibus);
921 bus_generic_detach(dev);
922
923 if (sc->vr_intrhand)
924 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
925 if (sc->vr_irq)
926 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
927 if (sc->vr_res)
928 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
929
930 if (sc->vr_ldata)
931 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
932
933 VR_UNLOCK(sc);
934 mtx_destroy(&sc->vr_mtx);
935
936 return(0);
937 }
938
939 /*
940 * Initialize the transmit descriptors.
941 */
942 static int
943 vr_list_tx_init(sc)
944 struct vr_softc *sc;
945 {
946 struct vr_chain_data *cd;
947 struct vr_list_data *ld;
948 int i;
949
950 cd = &sc->vr_cdata;
951 ld = sc->vr_ldata;
952 for (i = 0; i < VR_TX_LIST_CNT; i++) {
953 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
954 if (i == (VR_TX_LIST_CNT - 1))
955 cd->vr_tx_chain[i].vr_nextdesc =
956 &cd->vr_tx_chain[0];
957 else
958 cd->vr_tx_chain[i].vr_nextdesc =
959 &cd->vr_tx_chain[i + 1];
960 }
961
962 cd->vr_tx_free = &cd->vr_tx_chain[0];
963 cd->vr_tx_tail = cd->vr_tx_head = NULL;
964
965 return(0);
966 }
967
968
969 /*
970 * Initialize the RX descriptors and allocate mbufs for them. Note that
971 * we arrange the descriptors in a closed ring, so that the last descriptor
972 * points back to the first.
973 */
974 static int
975 vr_list_rx_init(sc)
976 struct vr_softc *sc;
977 {
978 struct vr_chain_data *cd;
979 struct vr_list_data *ld;
980 int i;
981
982 cd = &sc->vr_cdata;
983 ld = sc->vr_ldata;
984
985 for (i = 0; i < VR_RX_LIST_CNT; i++) {
986 cd->vr_rx_chain[i].vr_ptr =
987 (struct vr_desc *)&ld->vr_rx_list[i];
988 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
989 return(ENOBUFS);
990 if (i == (VR_RX_LIST_CNT - 1)) {
991 cd->vr_rx_chain[i].vr_nextdesc =
992 &cd->vr_rx_chain[0];
993 ld->vr_rx_list[i].vr_next =
994 vtophys(&ld->vr_rx_list[0]);
995 } else {
996 cd->vr_rx_chain[i].vr_nextdesc =
997 &cd->vr_rx_chain[i + 1];
998 ld->vr_rx_list[i].vr_next =
999 vtophys(&ld->vr_rx_list[i + 1]);
1000 }
1001 }
1002
1003 cd->vr_rx_head = &cd->vr_rx_chain[0];
1004
1005 return(0);
1006 }
1007
1008 /*
1009 * Initialize an RX descriptor and attach an MBUF cluster.
1010 * Note: the length fields are only 11 bits wide, which means the
1011 * largest size we can specify is 2047. This is important because
1012 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
1013 * overflow the field and make a mess.
1014 */
1015 static int
1016 vr_newbuf(sc, c, m)
1017 struct vr_softc *sc;
1018 struct vr_chain_onefrag *c;
1019 struct mbuf *m;
1020 {
1021 struct mbuf *m_new = NULL;
1022
1023 if (m == NULL) {
1024 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1025 if (m_new == NULL)
1026 return(ENOBUFS);
1027
1028 MCLGET(m_new, M_DONTWAIT);
1029 if (!(m_new->m_flags & M_EXT)) {
1030 m_freem(m_new);
1031 return(ENOBUFS);
1032 }
1033 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1034 } else {
1035 m_new = m;
1036 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1037 m_new->m_data = m_new->m_ext.ext_buf;
1038 }
1039
1040 m_adj(m_new, sizeof(u_int64_t));
1041
1042 c->vr_mbuf = m_new;
1043 c->vr_ptr->vr_status = VR_RXSTAT;
1044 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
1045 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
1046
1047 return(0);
1048 }
1049
1050 /*
1051 * A frame has been uploaded: pass the resulting mbuf chain up to
1052 * the higher level protocols.
1053 */
1054 static void
1055 vr_rxeof(sc)
1056 struct vr_softc *sc;
1057 {
1058 struct mbuf *m;
1059 struct ifnet *ifp;
1060 struct vr_chain_onefrag *cur_rx;
1061 int total_len = 0;
1062 u_int32_t rxstat;
1063
1064 VR_LOCK_ASSERT(sc);
1065
1066 ifp = &sc->arpcom.ac_if;
1067
1068 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
1069 VR_RXSTAT_OWN)) {
1070 struct mbuf *m0 = NULL;
1071
1072 cur_rx = sc->vr_cdata.vr_rx_head;
1073 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
1074 m = cur_rx->vr_mbuf;
1075
1076 /*
1077 * If an error occurs, update stats, clear the
1078 * status word and leave the mbuf cluster in place:
1079 * it should simply get re-used next time this descriptor
1080 * comes up in the ring.
1081 */
1082 if (rxstat & VR_RXSTAT_RXERR) {
1083 ifp->if_ierrors++;
1084 printf("vr%d: rx error (%02x):",
1085 sc->vr_unit, rxstat & 0x000000ff);
1086 if (rxstat & VR_RXSTAT_CRCERR)
1087 printf(" crc error");
1088 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1089 printf(" frame alignment error\n");
1090 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1091 printf(" FIFO overflow");
1092 if (rxstat & VR_RXSTAT_GIANT)
1093 printf(" received giant packet");
1094 if (rxstat & VR_RXSTAT_RUNT)
1095 printf(" received runt packet");
1096 if (rxstat & VR_RXSTAT_BUSERR)
1097 printf(" system bus error");
1098 if (rxstat & VR_RXSTAT_BUFFERR)
1099 printf("rx buffer error");
1100 printf("\n");
1101 vr_newbuf(sc, cur_rx, m);
1102 continue;
1103 }
1104
1105 /* No errors; receive the packet. */
1106 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
1107
1108 /*
1109 * XXX The VIA Rhine chip includes the CRC with every
1110 * received frame, and there's no way to turn this
1111 * behavior off (at least, I can't find anything in
1112 * the manual that explains how to do it) so we have
1113 * to trim off the CRC manually.
1114 */
1115 total_len -= ETHER_CRC_LEN;
1116
1117 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
1118 NULL);
1119 vr_newbuf(sc, cur_rx, m);
1120 if (m0 == NULL) {
1121 ifp->if_ierrors++;
1122 continue;
1123 }
1124 m = m0;
1125
1126 ifp->if_ipackets++;
1127 VR_UNLOCK(sc);
1128 (*ifp->if_input)(ifp, m);
1129 VR_LOCK(sc);
1130 }
1131
1132 return;
1133 }
1134
1135 static void
1136 vr_rxeoc(sc)
1137 struct vr_softc *sc;
1138 {
1139 struct ifnet *ifp;
1140 int i;
1141
1142 ifp = &sc->arpcom.ac_if;
1143
1144 ifp->if_ierrors++;
1145
1146 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1147 DELAY(10000);
1148
1149 for (i = 0x400;
1150 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1151 i--)
1152 ; /* Wait for receiver to stop */
1153
1154 if (!i) {
1155 printf("vr%d: rx shutdown error!\n", sc->vr_unit);
1156 sc->vr_flags |= VR_F_RESTART;
1157 return;
1158 }
1159
1160 vr_rxeof(sc);
1161
1162 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1163 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1164 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1165
1166 return;
1167 }
1168
1169 /*
1170 * A frame was downloaded to the chip. It's safe for us to clean up
1171 * the list buffers.
1172 */
1173
1174 static void
1175 vr_txeof(sc)
1176 struct vr_softc *sc;
1177 {
1178 struct vr_chain *cur_tx;
1179 struct ifnet *ifp;
1180
1181 ifp = &sc->arpcom.ac_if;
1182
1183 /* Reset the timeout timer; if_txeoc will clear it. */
1184 ifp->if_timer = 5;
1185
1186 /* Sanity check. */
1187 if (sc->vr_cdata.vr_tx_head == NULL)
1188 return;
1189
1190 /*
1191 * Go through our tx list and free mbufs for those
1192 * frames that have been transmitted.
1193 */
1194 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) {
1195 u_int32_t txstat;
1196 int i;
1197
1198 cur_tx = sc->vr_cdata.vr_tx_head;
1199 txstat = cur_tx->vr_ptr->vr_status;
1200
1201 if ((txstat & VR_TXSTAT_ABRT) ||
1202 (txstat & VR_TXSTAT_UDF)) {
1203 for (i = 0x400;
1204 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1205 i--)
1206 ; /* Wait for chip to shutdown */
1207 if (!i) {
1208 printf("vr%d: tx shutdown timeout\n", sc->vr_unit);
1209 sc->vr_flags |= VR_F_RESTART;
1210 break;
1211 }
1212 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1213 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr));
1214 break;
1215 }
1216
1217 if (txstat & VR_TXSTAT_OWN)
1218 break;
1219
1220 if (txstat & VR_TXSTAT_ERRSUM) {
1221 ifp->if_oerrors++;
1222 if (txstat & VR_TXSTAT_DEFER)
1223 ifp->if_collisions++;
1224 if (txstat & VR_TXSTAT_LATECOLL)
1225 ifp->if_collisions++;
1226 }
1227
1228 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3;
1229
1230 ifp->if_opackets++;
1231 if (cur_tx->vr_mbuf != NULL) {
1232 m_freem(cur_tx->vr_mbuf);
1233 cur_tx->vr_mbuf = NULL;
1234 }
1235
1236 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) {
1237 sc->vr_cdata.vr_tx_head = NULL;
1238 sc->vr_cdata.vr_tx_tail = NULL;
1239 break;
1240 }
1241
1242 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc;
1243 }
1244
1245 return;
1246 }
1247
1248 /*
1249 * TX 'end of channel' interrupt handler.
1250 */
1251 static void
1252 vr_txeoc(sc)
1253 struct vr_softc *sc;
1254 {
1255 struct ifnet *ifp;
1256
1257 ifp = &sc->arpcom.ac_if;
1258
1259 if (sc->vr_cdata.vr_tx_head == NULL) {
1260 ifp->if_flags &= ~IFF_OACTIVE;
1261 sc->vr_cdata.vr_tx_tail = NULL;
1262 ifp->if_timer = 0;
1263 }
1264
1265 return;
1266 }
1267
1268 static void
1269 vr_tick(xsc)
1270 void *xsc;
1271 {
1272 struct vr_softc *sc;
1273 struct mii_data *mii;
1274
1275 sc = xsc;
1276 VR_LOCK(sc);
1277 if (sc->vr_flags & VR_F_RESTART) {
1278 printf("vr%d: restarting\n", sc->vr_unit);
1279 vr_stop(sc);
1280 vr_reset(sc);
1281 vr_init(sc);
1282 sc->vr_flags &= ~VR_F_RESTART;
1283 }
1284
1285 mii = device_get_softc(sc->vr_miibus);
1286 mii_tick(mii);
1287
1288 sc->vr_stat_ch = timeout(vr_tick, sc, hz);
1289
1290 VR_UNLOCK(sc);
1291
1292 return;
1293 }
1294
1295 static void
1296 vr_intr(arg)
1297 void *arg;
1298 {
1299 struct vr_softc *sc;
1300 struct ifnet *ifp;
1301 u_int16_t status;
1302
1303 sc = arg;
1304 VR_LOCK(sc);
1305 ifp = &sc->arpcom.ac_if;
1306
1307 /* Supress unwanted interrupts. */
1308 if (!(ifp->if_flags & IFF_UP)) {
1309 vr_stop(sc);
1310 VR_UNLOCK(sc);
1311 return;
1312 }
1313
1314 /* Disable interrupts. */
1315 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1316
1317 for (;;) {
1318
1319 status = CSR_READ_2(sc, VR_ISR);
1320 if (status)
1321 CSR_WRITE_2(sc, VR_ISR, status);
1322
1323 if ((status & VR_INTRS) == 0)
1324 break;
1325
1326 if (status & VR_ISR_RX_OK)
1327 vr_rxeof(sc);
1328
1329 if (status & VR_ISR_RX_DROPPED) {
1330 printf("vr%d: rx packet lost\n", sc->vr_unit);
1331 ifp->if_ierrors++;
1332 }
1333
1334 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1335 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
1336 printf("vr%d: receive error (%04x)",
1337 sc->vr_unit, status);
1338 if (status & VR_ISR_RX_NOBUF)
1339 printf(" no buffers");
1340 if (status & VR_ISR_RX_OFLOW)
1341 printf(" overflow");
1342 if (status & VR_ISR_RX_DROPPED)
1343 printf(" packet lost");
1344 printf("\n");
1345 vr_rxeoc(sc);
1346 }
1347
1348 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1349 vr_reset(sc);
1350 vr_init(sc);
1351 break;
1352 }
1353
1354 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1355 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1356 vr_txeof(sc);
1357 if ((status & VR_ISR_UDFI) ||
1358 (status & VR_ISR_TX_ABRT2) ||
1359 (status & VR_ISR_TX_ABRT)) {
1360 ifp->if_oerrors++;
1361 if (sc->vr_cdata.vr_tx_head != NULL) {
1362 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
1363 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
1364 }
1365 } else
1366 vr_txeoc(sc);
1367 }
1368
1369 }
1370
1371 /* Re-enable interrupts. */
1372 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1373
1374 if (ifp->if_snd.ifq_head != NULL) {
1375 vr_start(ifp);
1376 }
1377
1378 VR_UNLOCK(sc);
1379
1380 return;
1381 }
1382
1383 /*
1384 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1385 * pointers to the fragment pointers.
1386 */
1387 static int
1388 vr_encap(sc, c, m_head)
1389 struct vr_softc *sc;
1390 struct vr_chain *c;
1391 struct mbuf *m_head;
1392 {
1393 int frag = 0;
1394 struct vr_desc *f = NULL;
1395 int total_len;
1396 struct mbuf *m;
1397
1398 m = m_head;
1399 total_len = 0;
1400
1401 /*
1402 * The VIA Rhine wants packet buffers to be longword
1403 * aligned, but very often our mbufs aren't. Rather than
1404 * waste time trying to decide when to copy and when not
1405 * to copy, just do it all the time.
1406 */
1407 if (m != NULL) {
1408 struct mbuf *m_new = NULL;
1409
1410 m_new = m_defrag(m_head, M_DONTWAIT);
1411 if (m_new == NULL) {
1412 return(1);
1413 }
1414
1415 m_head = m_new;
1416 /*
1417 * The Rhine chip doesn't auto-pad, so we have to make
1418 * sure to pad short frames out to the minimum frame length
1419 * ourselves.
1420 */
1421 if (m_head->m_len < VR_MIN_FRAMELEN) {
1422 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len;
1423 m_new->m_len = m_new->m_pkthdr.len;
1424 }
1425 f = c->vr_ptr;
1426 f->vr_data = vtophys(mtod(m_new, caddr_t));
1427 f->vr_ctl = total_len = m_new->m_len;
1428 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG;
1429 f->vr_status = 0;
1430 frag = 1;
1431 }
1432
1433 c->vr_mbuf = m_head;
1434 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT;
1435 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr);
1436
1437 return(0);
1438 }
1439
1440 /*
1441 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1442 * to the mbuf data regions directly in the transmit lists. We also save a
1443 * copy of the pointers since the transmit list fragment pointers are
1444 * physical addresses.
1445 */
1446
1447 static void
1448 vr_start(ifp)
1449 struct ifnet *ifp;
1450 {
1451 struct vr_softc *sc;
1452 struct mbuf *m_head = NULL;
1453 struct vr_chain *cur_tx = NULL, *start_tx, *prev_tx;
1454
1455 sc = ifp->if_softc;
1456
1457 VR_LOCK(sc);
1458
1459 /*
1460 * Check for an available queue slot. If there are none,
1461 * punt.
1462 */
1463 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) {
1464 VR_UNLOCK(sc);
1465 return;
1466 }
1467
1468 start_tx = sc->vr_cdata.vr_tx_free;
1469
1470 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) {
1471 IF_DEQUEUE(&ifp->if_snd, m_head);
1472 if (m_head == NULL)
1473 break;
1474
1475 /* Pick a descriptor off the free list. */
1476 prev_tx = cur_tx;
1477 cur_tx = sc->vr_cdata.vr_tx_free;
1478 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc;
1479
1480 /* Pack the data into the descriptor. */
1481 if (vr_encap(sc, cur_tx, m_head)) {
1482 /* Rollback, send what we were able to encap. */
1483 IF_PREPEND(&ifp->if_snd, m_head);
1484 sc->vr_cdata.vr_tx_free = cur_tx;
1485 cur_tx = prev_tx;
1486 break;
1487 }
1488
1489 if (cur_tx != start_tx)
1490 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1491
1492 /*
1493 * If there's a BPF listener, bounce a copy of this frame
1494 * to him.
1495 */
1496 BPF_MTAP(ifp, cur_tx->vr_mbuf);
1497
1498 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1499 }
1500
1501 /*
1502 * If there are no frames queued, bail.
1503 */
1504 if (cur_tx == NULL) {
1505 VR_UNLOCK(sc);
1506 return;
1507 }
1508
1509 sc->vr_cdata.vr_tx_tail = cur_tx;
1510
1511 if (sc->vr_cdata.vr_tx_head == NULL)
1512 sc->vr_cdata.vr_tx_head = start_tx;
1513
1514 /* Tell the chip to start transmitting. */
1515 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1516
1517 /*
1518 * Set a timeout in case the chip goes out to lunch.
1519 */
1520 ifp->if_timer = 5;
1521 VR_UNLOCK(sc);
1522
1523 return;
1524 }
1525
1526 static void
1527 vr_init(xsc)
1528 void *xsc;
1529 {
1530 struct vr_softc *sc = xsc;
1531 struct ifnet *ifp = &sc->arpcom.ac_if;
1532 struct mii_data *mii;
1533 int i;
1534
1535 VR_LOCK(sc);
1536
1537 mii = device_get_softc(sc->vr_miibus);
1538
1539 /*
1540 * Cancel pending I/O and free all RX/TX buffers.
1541 */
1542 vr_stop(sc);
1543 vr_reset(sc);
1544
1545 /*
1546 * Set our station address.
1547 */
1548 for (i = 0; i < ETHER_ADDR_LEN; i++)
1549 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1550
1551 /* Set DMA size */
1552 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1553 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1554
1555 /*
1556 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1557 * so we must set both.
1558 */
1559 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1560 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1561
1562 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1563 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1564
1565 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1566 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1567
1568 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1569 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1570
1571 /* Init circular RX list. */
1572 if (vr_list_rx_init(sc) == ENOBUFS) {
1573 printf("vr%d: initialization failed: no "
1574 "memory for rx buffers\n", sc->vr_unit);
1575 vr_stop(sc);
1576 VR_UNLOCK(sc);
1577 return;
1578 }
1579
1580 /*
1581 * Init tx descriptors.
1582 */
1583 vr_list_tx_init(sc);
1584
1585 /* If we want promiscuous mode, set the allframes bit. */
1586 if (ifp->if_flags & IFF_PROMISC)
1587 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1588 else
1589 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1590
1591 /* Set capture broadcast bit to capture broadcast frames. */
1592 if (ifp->if_flags & IFF_BROADCAST)
1593 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1594 else
1595 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1596
1597 /*
1598 * Program the multicast filter, if necessary.
1599 */
1600 vr_setmulti(sc);
1601
1602 /*
1603 * Load the address of the RX list.
1604 */
1605 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1606
1607 /* Enable receiver and transmitter. */
1608 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1609 VR_CMD_TX_ON|VR_CMD_RX_ON|
1610 VR_CMD_RX_GO);
1611
1612 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1613
1614 /*
1615 * Enable interrupts.
1616 */
1617 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1618 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1619
1620 mii_mediachg(mii);
1621
1622 ifp->if_flags |= IFF_RUNNING;
1623 ifp->if_flags &= ~IFF_OACTIVE;
1624
1625 sc->vr_stat_ch = timeout(vr_tick, sc, hz);
1626
1627 VR_UNLOCK(sc);
1628
1629 return;
1630 }
1631
1632 /*
1633 * Set media options.
1634 */
1635 static int
1636 vr_ifmedia_upd(ifp)
1637 struct ifnet *ifp;
1638 {
1639 struct vr_softc *sc;
1640
1641 sc = ifp->if_softc;
1642
1643 if (ifp->if_flags & IFF_UP)
1644 vr_init(sc);
1645
1646 return(0);
1647 }
1648
1649 /*
1650 * Report current media status.
1651 */
1652 static void
1653 vr_ifmedia_sts(ifp, ifmr)
1654 struct ifnet *ifp;
1655 struct ifmediareq *ifmr;
1656 {
1657 struct vr_softc *sc;
1658 struct mii_data *mii;
1659
1660 sc = ifp->if_softc;
1661 mii = device_get_softc(sc->vr_miibus);
1662 mii_pollstat(mii);
1663 ifmr->ifm_active = mii->mii_media_active;
1664 ifmr->ifm_status = mii->mii_media_status;
1665
1666 return;
1667 }
1668
1669 static int
1670 vr_ioctl(ifp, command, data)
1671 struct ifnet *ifp;
1672 u_long command;
1673 caddr_t data;
1674 {
1675 struct vr_softc *sc = ifp->if_softc;
1676 struct ifreq *ifr = (struct ifreq *) data;
1677 struct mii_data *mii;
1678 int error = 0;
1679
1680 VR_LOCK(sc);
1681
1682 switch(command) {
1683 case SIOCSIFFLAGS:
1684 if (ifp->if_flags & IFF_UP) {
1685 vr_init(sc);
1686 } else {
1687 if (ifp->if_flags & IFF_RUNNING)
1688 vr_stop(sc);
1689 }
1690 error = 0;
1691 break;
1692 case SIOCADDMULTI:
1693 case SIOCDELMULTI:
1694 vr_setmulti(sc);
1695 error = 0;
1696 break;
1697 case SIOCGIFMEDIA:
1698 case SIOCSIFMEDIA:
1699 mii = device_get_softc(sc->vr_miibus);
1700 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1701 break;
1702 default:
1703 error = ether_ioctl(ifp, command, data);
1704 break;
1705 }
1706
1707 VR_UNLOCK(sc);
1708
1709 return(error);
1710 }
1711
1712 static void
1713 vr_watchdog(ifp)
1714 struct ifnet *ifp;
1715 {
1716 struct vr_softc *sc;
1717
1718 sc = ifp->if_softc;
1719
1720 VR_LOCK(sc);
1721 ifp->if_oerrors++;
1722 printf("vr%d: watchdog timeout\n", sc->vr_unit);
1723
1724 vr_stop(sc);
1725 vr_reset(sc);
1726 vr_init(sc);
1727
1728 if (ifp->if_snd.ifq_head != NULL)
1729 vr_start(ifp);
1730
1731 VR_UNLOCK(sc);
1732
1733 return;
1734 }
1735
1736 /*
1737 * Stop the adapter and free any mbufs allocated to the
1738 * RX and TX lists.
1739 */
1740 static void
1741 vr_stop(sc)
1742 struct vr_softc *sc;
1743 {
1744 register int i;
1745 struct ifnet *ifp;
1746
1747 VR_LOCK(sc);
1748
1749 ifp = &sc->arpcom.ac_if;
1750 ifp->if_timer = 0;
1751
1752 untimeout(vr_tick, sc, sc->vr_stat_ch);
1753
1754 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1755 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1756 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1757 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1758 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1759
1760 /*
1761 * Free data in the RX lists.
1762 */
1763 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1764 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1765 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1766 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1767 }
1768 }
1769 bzero((char *)&sc->vr_ldata->vr_rx_list,
1770 sizeof(sc->vr_ldata->vr_rx_list));
1771
1772 /*
1773 * Free the TX list buffers.
1774 */
1775 for (i = 0; i < VR_TX_LIST_CNT; i++) {
1776 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) {
1777 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf);
1778 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL;
1779 }
1780 }
1781
1782 bzero((char *)&sc->vr_ldata->vr_tx_list,
1783 sizeof(sc->vr_ldata->vr_tx_list));
1784
1785 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1786 VR_UNLOCK(sc);
1787
1788 return;
1789 }
1790
1791 /*
1792 * Stop all chip I/O so that the kernel's probe routines don't
1793 * get confused by errant DMAs when rebooting.
1794 */
1795 static void
1796 vr_shutdown(dev)
1797 device_t dev;
1798 {
1799 struct vr_softc *sc;
1800
1801 sc = device_get_softc(dev);
1802
1803 vr_stop(sc);
1804
1805 return;
1806 }
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